2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
4 * Author: Shlomi Gridish <gridish@freescale.com>
7 * UCC GETH Driver -- PHY handling
10 * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
11 * - Rearrange code and style fixes
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/slab.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/spinlock.h>
33 #include <linux/module.h>
34 #include <linux/version.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
37 #include <linux/ethtool.h>
41 #include <asm/uaccess.h>
44 #include "ucc_geth_phy.h"
45 #include <platforms/83xx/mpc8360e_pb.h>
47 #define ugphy_printk(level, format, arg...) \
48 printk(level format "\n", ## arg)
50 #define ugphy_dbg(format, arg...) \
51 ugphy_printk(KERN_DEBUG, format , ## arg)
52 #define ugphy_err(format, arg...) \
53 ugphy_printk(KERN_ERR, format , ## arg)
54 #define ugphy_info(format, arg...) \
55 ugphy_printk(KERN_INFO, format , ## arg)
56 #define ugphy_warn(format, arg...) \
57 ugphy_printk(KERN_WARNING, format , ## arg)
59 #ifdef UGETH_VERBOSE_DEBUG
60 #define ugphy_vdbg ugphy_dbg
62 #define ugphy_vdbg(fmt, args...) do { } while (0)
63 #endif /* UGETH_VERBOSE_DEBUG */
65 static void config_genmii_advert(struct ugeth_mii_info
*mii_info
);
66 static void genmii_setup_forced(struct ugeth_mii_info
*mii_info
);
67 static void genmii_restart_aneg(struct ugeth_mii_info
*mii_info
);
68 static int gbit_config_aneg(struct ugeth_mii_info
*mii_info
);
69 static int genmii_config_aneg(struct ugeth_mii_info
*mii_info
);
70 static int genmii_update_link(struct ugeth_mii_info
*mii_info
);
71 static int genmii_read_status(struct ugeth_mii_info
*mii_info
);
72 u16
phy_read(struct ugeth_mii_info
*mii_info
, u16 regnum
);
73 void phy_write(struct ugeth_mii_info
*mii_info
, u16 regnum
, u16 val
);
75 static u8
*bcsr_regs
= NULL
;
77 /* Write value to the PHY for this device to the register at regnum, */
78 /* waiting until the write is done before it returns. All PHY */
79 /* configuration has to be done through the TSEC1 MIIM regs */
80 void write_phy_reg(struct net_device
*dev
, int mii_id
, int regnum
, int value
)
82 ucc_geth_private_t
*ugeth
= netdev_priv(dev
);
83 ucc_mii_mng_t
*mii_regs
;
84 enet_tbi_mii_reg_e mii_reg
= (enet_tbi_mii_reg_e
) regnum
;
87 ugphy_vdbg("%s: IN", __FUNCTION__
);
89 spin_lock_irq(&ugeth
->lock
);
91 mii_regs
= ugeth
->mii_info
->mii_regs
;
93 /* Set this UCC to be the master of the MII managment */
94 ucc_set_qe_mux_mii_mng(ugeth
->ug_info
->uf_info
.ucc_num
);
96 /* Stop the MII management read cycle */
97 out_be32(&mii_regs
->miimcom
, 0);
98 /* Setting up the MII Mangement Address Register */
99 tmp_reg
= ((u32
) mii_id
<< MIIMADD_PHY_ADDRESS_SHIFT
) | mii_reg
;
100 out_be32(&mii_regs
->miimadd
, tmp_reg
);
102 /* Setting up the MII Mangement Control Register with the value */
103 out_be32(&mii_regs
->miimcon
, (u32
) value
);
105 /* Wait till MII management write is complete */
106 while ((in_be32(&mii_regs
->miimind
)) & MIIMIND_BUSY
)
109 spin_unlock_irq(&ugeth
->lock
);
114 /* Reads from register regnum in the PHY for device dev, */
115 /* returning the value. Clears miimcom first. All PHY */
116 /* configuration has to be done through the TSEC1 MIIM regs */
117 int read_phy_reg(struct net_device
*dev
, int mii_id
, int regnum
)
119 ucc_geth_private_t
*ugeth
= netdev_priv(dev
);
120 ucc_mii_mng_t
*mii_regs
;
121 enet_tbi_mii_reg_e mii_reg
= (enet_tbi_mii_reg_e
) regnum
;
125 ugphy_vdbg("%s: IN", __FUNCTION__
);
127 spin_lock_irq(&ugeth
->lock
);
129 mii_regs
= ugeth
->mii_info
->mii_regs
;
131 /* Setting up the MII Mangement Address Register */
132 tmp_reg
= ((u32
) mii_id
<< MIIMADD_PHY_ADDRESS_SHIFT
) | mii_reg
;
133 out_be32(&mii_regs
->miimadd
, tmp_reg
);
135 /* Perform an MII management read cycle */
136 out_be32(&mii_regs
->miimcom
, MIIMCOM_READ_CYCLE
);
138 /* Wait till MII management write is complete */
139 while ((in_be32(&mii_regs
->miimind
)) & MIIMIND_BUSY
)
144 /* Read MII management status */
145 value
= (u16
) in_be32(&mii_regs
->miimstat
);
146 out_be32(&mii_regs
->miimcom
, 0);
148 ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x",
149 mii_id
, mii_reg
, (u32
) & (mii_regs
->miimcfg
));
151 spin_unlock_irq(&ugeth
->lock
);
156 void mii_clear_phy_interrupt(struct ugeth_mii_info
*mii_info
)
158 ugphy_vdbg("%s: IN", __FUNCTION__
);
160 if (mii_info
->phyinfo
->ack_interrupt
)
161 mii_info
->phyinfo
->ack_interrupt(mii_info
);
164 void mii_configure_phy_interrupt(struct ugeth_mii_info
*mii_info
,
167 ugphy_vdbg("%s: IN", __FUNCTION__
);
169 mii_info
->interrupts
= interrupts
;
170 if (mii_info
->phyinfo
->config_intr
)
171 mii_info
->phyinfo
->config_intr(mii_info
);
174 /* Writes MII_ADVERTISE with the appropriate values, after
175 * sanitizing advertise to make sure only supported features
178 static void config_genmii_advert(struct ugeth_mii_info
*mii_info
)
183 ugphy_vdbg("%s: IN", __FUNCTION__
);
185 /* Only allow advertising what this PHY supports */
186 mii_info
->advertising
&= mii_info
->phyinfo
->features
;
187 advertise
= mii_info
->advertising
;
189 /* Setup standard advertisement */
190 adv
= phy_read(mii_info
, MII_ADVERTISE
);
191 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
192 if (advertise
& ADVERTISED_10baseT_Half
)
193 adv
|= ADVERTISE_10HALF
;
194 if (advertise
& ADVERTISED_10baseT_Full
)
195 adv
|= ADVERTISE_10FULL
;
196 if (advertise
& ADVERTISED_100baseT_Half
)
197 adv
|= ADVERTISE_100HALF
;
198 if (advertise
& ADVERTISED_100baseT_Full
)
199 adv
|= ADVERTISE_100FULL
;
200 phy_write(mii_info
, MII_ADVERTISE
, adv
);
203 static void genmii_setup_forced(struct ugeth_mii_info
*mii_info
)
206 u32 features
= mii_info
->phyinfo
->features
;
208 ugphy_vdbg("%s: IN", __FUNCTION__
);
210 ctrl
= phy_read(mii_info
, MII_BMCR
);
213 ~(BMCR_FULLDPLX
| BMCR_SPEED100
| BMCR_SPEED1000
| BMCR_ANENABLE
);
216 switch (mii_info
->speed
) {
218 if (features
& (SUPPORTED_1000baseT_Half
219 | SUPPORTED_1000baseT_Full
)) {
220 ctrl
|= BMCR_SPEED1000
;
223 mii_info
->speed
= SPEED_100
;
225 if (features
& (SUPPORTED_100baseT_Half
226 | SUPPORTED_100baseT_Full
)) {
227 ctrl
|= BMCR_SPEED100
;
230 mii_info
->speed
= SPEED_10
;
232 if (features
& (SUPPORTED_10baseT_Half
233 | SUPPORTED_10baseT_Full
))
235 default: /* Unsupported speed! */
236 ugphy_err("%s: Bad speed!", mii_info
->dev
->name
);
240 phy_write(mii_info
, MII_BMCR
, ctrl
);
243 /* Enable and Restart Autonegotiation */
244 static void genmii_restart_aneg(struct ugeth_mii_info
*mii_info
)
248 ugphy_vdbg("%s: IN", __FUNCTION__
);
250 ctl
= phy_read(mii_info
, MII_BMCR
);
251 ctl
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
252 phy_write(mii_info
, MII_BMCR
, ctl
);
255 static int gbit_config_aneg(struct ugeth_mii_info
*mii_info
)
260 ugphy_vdbg("%s: IN", __FUNCTION__
);
262 if (mii_info
->autoneg
) {
263 /* Configure the ADVERTISE register */
264 config_genmii_advert(mii_info
);
265 advertise
= mii_info
->advertising
;
267 adv
= phy_read(mii_info
, MII_1000BASETCONTROL
);
268 adv
&= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP
|
269 MII_1000BASETCONTROL_HALFDUPLEXCAP
);
270 if (advertise
& SUPPORTED_1000baseT_Half
)
271 adv
|= MII_1000BASETCONTROL_HALFDUPLEXCAP
;
272 if (advertise
& SUPPORTED_1000baseT_Full
)
273 adv
|= MII_1000BASETCONTROL_FULLDUPLEXCAP
;
274 phy_write(mii_info
, MII_1000BASETCONTROL
, adv
);
276 /* Start/Restart aneg */
277 genmii_restart_aneg(mii_info
);
279 genmii_setup_forced(mii_info
);
284 static int genmii_config_aneg(struct ugeth_mii_info
*mii_info
)
286 ugphy_vdbg("%s: IN", __FUNCTION__
);
288 if (mii_info
->autoneg
) {
289 config_genmii_advert(mii_info
);
290 genmii_restart_aneg(mii_info
);
292 genmii_setup_forced(mii_info
);
297 static int genmii_update_link(struct ugeth_mii_info
*mii_info
)
301 ugphy_vdbg("%s: IN", __FUNCTION__
);
304 phy_read(mii_info
, MII_BMSR
);
306 /* Read link and autonegotiation status */
307 status
= phy_read(mii_info
, MII_BMSR
);
308 if ((status
& BMSR_LSTATUS
) == 0)
313 /* If we are autonegotiating, and not done,
315 if (mii_info
->autoneg
&& !(status
& BMSR_ANEGCOMPLETE
))
321 static int genmii_read_status(struct ugeth_mii_info
*mii_info
)
326 ugphy_vdbg("%s: IN", __FUNCTION__
);
328 /* Update the link, but return if there
330 err
= genmii_update_link(mii_info
);
334 if (mii_info
->autoneg
) {
335 status
= phy_read(mii_info
, MII_LPA
);
337 if (status
& (LPA_10FULL
| LPA_100FULL
))
338 mii_info
->duplex
= DUPLEX_FULL
;
340 mii_info
->duplex
= DUPLEX_HALF
;
341 if (status
& (LPA_100FULL
| LPA_100HALF
))
342 mii_info
->speed
= SPEED_100
;
344 mii_info
->speed
= SPEED_10
;
347 /* On non-aneg, we assume what we put in BMCR is the speed,
348 * though magic-aneg shouldn't prevent this case from occurring
354 static int marvell_init(struct ugeth_mii_info
*mii_info
)
356 ugphy_vdbg("%s: IN", __FUNCTION__
);
358 phy_write(mii_info
, 0x14, 0x0cd2);
359 phy_write(mii_info
, MII_BMCR
,
360 phy_read(mii_info
, MII_BMCR
) | BMCR_RESET
);
366 static int marvell_config_aneg(struct ugeth_mii_info
*mii_info
)
368 ugphy_vdbg("%s: IN", __FUNCTION__
);
370 /* The Marvell PHY has an errata which requires
371 * that certain registers get written in order
372 * to restart autonegotiation */
373 phy_write(mii_info
, MII_BMCR
, BMCR_RESET
);
375 phy_write(mii_info
, 0x1d, 0x1f);
376 phy_write(mii_info
, 0x1e, 0x200c);
377 phy_write(mii_info
, 0x1d, 0x5);
378 phy_write(mii_info
, 0x1e, 0);
379 phy_write(mii_info
, 0x1e, 0x100);
381 gbit_config_aneg(mii_info
);
386 static int marvell_read_status(struct ugeth_mii_info
*mii_info
)
391 ugphy_vdbg("%s: IN", __FUNCTION__
);
393 /* Update the link, but return if there
395 err
= genmii_update_link(mii_info
);
399 /* If the link is up, read the speed and duplex */
400 /* If we aren't autonegotiating, assume speeds
402 if (mii_info
->autoneg
&& mii_info
->link
) {
404 status
= phy_read(mii_info
, MII_M1011_PHY_SPEC_STATUS
);
406 /* Get the duplexity */
407 if (status
& MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX
)
408 mii_info
->duplex
= DUPLEX_FULL
;
410 mii_info
->duplex
= DUPLEX_HALF
;
413 speed
= status
& MII_M1011_PHY_SPEC_STATUS_SPD_MASK
;
415 case MII_M1011_PHY_SPEC_STATUS_1000
:
416 mii_info
->speed
= SPEED_1000
;
418 case MII_M1011_PHY_SPEC_STATUS_100
:
419 mii_info
->speed
= SPEED_100
;
422 mii_info
->speed
= SPEED_10
;
431 static int marvell_ack_interrupt(struct ugeth_mii_info
*mii_info
)
433 ugphy_vdbg("%s: IN", __FUNCTION__
);
435 /* Clear the interrupts by reading the reg */
436 phy_read(mii_info
, MII_M1011_IEVENT
);
441 static int marvell_config_intr(struct ugeth_mii_info
*mii_info
)
443 ugphy_vdbg("%s: IN", __FUNCTION__
);
445 if (mii_info
->interrupts
== MII_INTERRUPT_ENABLED
)
446 phy_write(mii_info
, MII_M1011_IMASK
, MII_M1011_IMASK_INIT
);
448 phy_write(mii_info
, MII_M1011_IMASK
, MII_M1011_IMASK_CLEAR
);
453 static int cis820x_init(struct ugeth_mii_info
*mii_info
)
455 ugphy_vdbg("%s: IN", __FUNCTION__
);
457 phy_write(mii_info
, MII_CIS8201_AUX_CONSTAT
,
458 MII_CIS8201_AUXCONSTAT_INIT
);
459 phy_write(mii_info
, MII_CIS8201_EXT_CON1
, MII_CIS8201_EXTCON1_INIT
);
464 static int cis820x_read_status(struct ugeth_mii_info
*mii_info
)
469 ugphy_vdbg("%s: IN", __FUNCTION__
);
471 /* Update the link, but return if there
473 err
= genmii_update_link(mii_info
);
477 /* If the link is up, read the speed and duplex */
478 /* If we aren't autonegotiating, assume speeds
480 if (mii_info
->autoneg
&& mii_info
->link
) {
483 status
= phy_read(mii_info
, MII_CIS8201_AUX_CONSTAT
);
484 if (status
& MII_CIS8201_AUXCONSTAT_DUPLEX
)
485 mii_info
->duplex
= DUPLEX_FULL
;
487 mii_info
->duplex
= DUPLEX_HALF
;
489 speed
= status
& MII_CIS8201_AUXCONSTAT_SPEED
;
492 case MII_CIS8201_AUXCONSTAT_GBIT
:
493 mii_info
->speed
= SPEED_1000
;
495 case MII_CIS8201_AUXCONSTAT_100
:
496 mii_info
->speed
= SPEED_100
;
499 mii_info
->speed
= SPEED_10
;
507 static int cis820x_ack_interrupt(struct ugeth_mii_info
*mii_info
)
509 ugphy_vdbg("%s: IN", __FUNCTION__
);
511 phy_read(mii_info
, MII_CIS8201_ISTAT
);
516 static int cis820x_config_intr(struct ugeth_mii_info
*mii_info
)
518 ugphy_vdbg("%s: IN", __FUNCTION__
);
520 if (mii_info
->interrupts
== MII_INTERRUPT_ENABLED
)
521 phy_write(mii_info
, MII_CIS8201_IMASK
, MII_CIS8201_IMASK_MASK
);
523 phy_write(mii_info
, MII_CIS8201_IMASK
, 0);
528 #define DM9161_DELAY 10
530 static int dm9161_read_status(struct ugeth_mii_info
*mii_info
)
535 ugphy_vdbg("%s: IN", __FUNCTION__
);
537 /* Update the link, but return if there
539 err
= genmii_update_link(mii_info
);
543 /* If the link is up, read the speed and duplex */
544 /* If we aren't autonegotiating, assume speeds
546 if (mii_info
->autoneg
&& mii_info
->link
) {
547 status
= phy_read(mii_info
, MII_DM9161_SCSR
);
548 if (status
& (MII_DM9161_SCSR_100F
| MII_DM9161_SCSR_100H
))
549 mii_info
->speed
= SPEED_100
;
551 mii_info
->speed
= SPEED_10
;
553 if (status
& (MII_DM9161_SCSR_100F
| MII_DM9161_SCSR_10F
))
554 mii_info
->duplex
= DUPLEX_FULL
;
556 mii_info
->duplex
= DUPLEX_HALF
;
562 static int dm9161_config_aneg(struct ugeth_mii_info
*mii_info
)
564 struct dm9161_private
*priv
= mii_info
->priv
;
566 ugphy_vdbg("%s: IN", __FUNCTION__
);
568 if (0 == priv
->resetdone
)
574 static void dm9161_timer(unsigned long data
)
576 struct ugeth_mii_info
*mii_info
= (struct ugeth_mii_info
*)data
;
577 struct dm9161_private
*priv
= mii_info
->priv
;
578 u16 status
= phy_read(mii_info
, MII_BMSR
);
580 ugphy_vdbg("%s: IN", __FUNCTION__
);
582 if (status
& BMSR_ANEGCOMPLETE
) {
585 mod_timer(&priv
->timer
, jiffies
+ DM9161_DELAY
* HZ
);
588 static int dm9161_init(struct ugeth_mii_info
*mii_info
)
590 struct dm9161_private
*priv
;
592 ugphy_vdbg("%s: IN", __FUNCTION__
);
594 /* Allocate the private data structure */
595 priv
= kmalloc(sizeof(struct dm9161_private
), GFP_KERNEL
);
600 mii_info
->priv
= priv
;
602 /* Reset is not done yet */
605 phy_write(mii_info
, MII_BMCR
,
606 phy_read(mii_info
, MII_BMCR
) | BMCR_RESET
);
608 phy_write(mii_info
, MII_BMCR
,
609 phy_read(mii_info
, MII_BMCR
) & ~BMCR_ISOLATE
);
611 config_genmii_advert(mii_info
);
612 /* Start/Restart aneg */
613 genmii_config_aneg(mii_info
);
615 /* Start a timer for DM9161_DELAY seconds to wait
616 * for the PHY to be ready */
617 init_timer(&priv
->timer
);
618 priv
->timer
.function
= &dm9161_timer
;
619 priv
->timer
.data
= (unsigned long)mii_info
;
620 mod_timer(&priv
->timer
, jiffies
+ DM9161_DELAY
* HZ
);
625 static void dm9161_close(struct ugeth_mii_info
*mii_info
)
627 struct dm9161_private
*priv
= mii_info
->priv
;
629 ugphy_vdbg("%s: IN", __FUNCTION__
);
631 del_timer_sync(&priv
->timer
);
635 static int dm9161_ack_interrupt(struct ugeth_mii_info
*mii_info
)
637 /* FIXME: This lines are for BUG fixing in the mpc8325.
638 Remove this from here when it's fixed */
639 if (bcsr_regs
== NULL
)
640 bcsr_regs
= (u8
*) ioremap(BCSR_PHYS_ADDR
, BCSR_SIZE
);
641 bcsr_regs
[14] |= 0x40;
642 ugphy_vdbg("%s: IN", __FUNCTION__
);
644 /* Clear the interrupts by reading the reg */
645 phy_read(mii_info
, MII_DM9161_INTR
);
651 static int dm9161_config_intr(struct ugeth_mii_info
*mii_info
)
653 /* FIXME: This lines are for BUG fixing in the mpc8325.
654 Remove this from here when it's fixed */
655 if (bcsr_regs
== NULL
) {
656 bcsr_regs
= (u8
*) ioremap(BCSR_PHYS_ADDR
, BCSR_SIZE
);
657 bcsr_regs
[14] &= ~0x40;
659 ugphy_vdbg("%s: IN", __FUNCTION__
);
661 if (mii_info
->interrupts
== MII_INTERRUPT_ENABLED
)
662 phy_write(mii_info
, MII_DM9161_INTR
, MII_DM9161_INTR_INIT
);
664 phy_write(mii_info
, MII_DM9161_INTR
, MII_DM9161_INTR_STOP
);
670 static struct phy_info phy_info_cis820x
= {
671 .phy_id
= 0x000fc440,
672 .name
= "Cicada Cis8204",
673 .phy_id_mask
= 0x000fffc0,
674 .features
= MII_GBIT_FEATURES
,
675 .init
= &cis820x_init
,
676 .config_aneg
= &gbit_config_aneg
,
677 .read_status
= &cis820x_read_status
,
678 .ack_interrupt
= &cis820x_ack_interrupt
,
679 .config_intr
= &cis820x_config_intr
,
682 static struct phy_info phy_info_dm9161
= {
683 .phy_id
= 0x0181b880,
684 .phy_id_mask
= 0x0ffffff0,
685 .name
= "Davicom DM9161E",
687 .config_aneg
= dm9161_config_aneg
,
688 .read_status
= dm9161_read_status
,
689 .close
= dm9161_close
,
692 static struct phy_info phy_info_dm9161a
= {
693 .phy_id
= 0x0181b8a0,
694 .phy_id_mask
= 0x0ffffff0,
695 .name
= "Davicom DM9161A",
696 .features
= MII_BASIC_FEATURES
,
698 .config_aneg
= dm9161_config_aneg
,
699 .read_status
= dm9161_read_status
,
700 .ack_interrupt
= dm9161_ack_interrupt
,
701 .config_intr
= dm9161_config_intr
,
702 .close
= dm9161_close
,
705 static struct phy_info phy_info_marvell
= {
706 .phy_id
= 0x01410c00,
707 .phy_id_mask
= 0xffffff00,
708 .name
= "Marvell 88E11x1",
709 .features
= MII_GBIT_FEATURES
,
710 .init
= &marvell_init
,
711 .config_aneg
= &marvell_config_aneg
,
712 .read_status
= &marvell_read_status
,
713 .ack_interrupt
= &marvell_ack_interrupt
,
714 .config_intr
= &marvell_config_intr
,
717 static struct phy_info phy_info_genmii
= {
718 .phy_id
= 0x00000000,
719 .phy_id_mask
= 0x00000000,
720 .name
= "Generic MII",
721 .features
= MII_BASIC_FEATURES
,
722 .config_aneg
= genmii_config_aneg
,
723 .read_status
= genmii_read_status
,
726 static struct phy_info
*phy_info
[] = {
735 u16
phy_read(struct ugeth_mii_info
*mii_info
, u16 regnum
)
740 ugphy_vdbg("%s: IN", __FUNCTION__
);
742 spin_lock_irqsave(&mii_info
->mdio_lock
, flags
);
743 retval
= mii_info
->mdio_read(mii_info
->dev
, mii_info
->mii_id
, regnum
);
744 spin_unlock_irqrestore(&mii_info
->mdio_lock
, flags
);
749 void phy_write(struct ugeth_mii_info
*mii_info
, u16 regnum
, u16 val
)
753 ugphy_vdbg("%s: IN", __FUNCTION__
);
755 spin_lock_irqsave(&mii_info
->mdio_lock
, flags
);
756 mii_info
->mdio_write(mii_info
->dev
, mii_info
->mii_id
, regnum
, val
);
757 spin_unlock_irqrestore(&mii_info
->mdio_lock
, flags
);
760 /* Use the PHY ID registers to determine what type of PHY is attached
761 * to device dev. return a struct phy_info structure describing that PHY
763 struct phy_info
*get_phy_info(struct ugeth_mii_info
*mii_info
)
768 struct phy_info
*theInfo
= NULL
;
769 struct net_device
*dev
= mii_info
->dev
;
771 ugphy_vdbg("%s: IN", __FUNCTION__
);
773 /* Grab the bits from PHYIR1, and put them in the upper half */
774 phy_reg
= phy_read(mii_info
, MII_PHYSID1
);
775 phy_ID
= (phy_reg
& 0xffff) << 16;
777 /* Grab the bits from PHYIR2, and put them in the lower half */
778 phy_reg
= phy_read(mii_info
, MII_PHYSID2
);
779 phy_ID
|= (phy_reg
& 0xffff);
781 /* loop through all the known PHY types, and find one that */
782 /* matches the ID we read from the PHY. */
783 for (i
= 0; phy_info
[i
]; i
++)
784 if (phy_info
[i
]->phy_id
== (phy_ID
& phy_info
[i
]->phy_id_mask
)){
785 theInfo
= phy_info
[i
];
789 /* This shouldn't happen, as we have generic PHY support */
790 if (theInfo
== NULL
) {
791 ugphy_info("%s: PHY id %x is not supported!", dev
->name
,
795 ugphy_info("%s: PHY is %s (%x)", dev
->name
, theInfo
->name
,