drivers/ata/pata_hpt366.c

   1 /*
   2  * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
   3  *
   4  * This driver is heavily based upon:
   5  *
   6  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   7  *
   8  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   9  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  10  * Portions Copyright (C) 2003          Red Hat Inc
  11  *
  12  *
  13  * TODO
  14  *      Look into engine reset on timeout errors. Should not be required.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/init.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <scsi/scsi_host.h>
  25 #include <linux/libata.h>
  26
  27 #define DRV_NAME        "pata_hpt366"
  28 #define DRV_VERSION     "0.6.10"
  29
  30 struct hpt_clock {
  31         u8      xfer_mode;
  32         u32     timing;
  33 };
  34
  35 /* key for bus clock timings
  36  * bit
  37  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  38  *        cycles = value + 1
  39  * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  40  *        cycles = value + 1
  41  * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  42  *        register access.
  43  * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
  44  *        register access.
  45  * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
  46  * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
  47  * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
  48  *        register access.
  49  * 28     UDMA enable.
  50  * 29     DMA  enable.
  51  * 30     PIO_MST enable. If set, the chip is in bus master mode during
  52  *        PIO xfer.
  53  * 31     FIFO enable.
  54  */
  55
  56 static const struct hpt_clock hpt366_40[] = {
  57         {       XFER_UDMA_4,    0x900fd943      },
  58         {       XFER_UDMA_3,    0x900ad943      },
  59         {       XFER_UDMA_2,    0x900bd943      },
  60         {       XFER_UDMA_1,    0x9008d943      },
  61         {       XFER_UDMA_0,    0x9008d943      },
  62
  63         {       XFER_MW_DMA_2,  0xa008d943      },
  64         {       XFER_MW_DMA_1,  0xa010d955      },
  65         {       XFER_MW_DMA_0,  0xa010d9fc      },
  66
  67         {       XFER_PIO_4,     0xc008d963      },
  68         {       XFER_PIO_3,     0xc010d974      },
  69         {       XFER_PIO_2,     0xc010d997      },
  70         {       XFER_PIO_1,     0xc010d9c7      },
  71         {       XFER_PIO_0,     0xc018d9d9      },
  72         {       0,              0x0120d9d9      }
  73 };
  74
  75 static const struct hpt_clock hpt366_33[] = {
  76         {       XFER_UDMA_4,    0x90c9a731      },
  77         {       XFER_UDMA_3,    0x90cfa731      },
  78         {       XFER_UDMA_2,    0x90caa731      },
  79         {       XFER_UDMA_1,    0x90cba731      },
  80         {       XFER_UDMA_0,    0x90c8a731      },
  81
  82         {       XFER_MW_DMA_2,  0xa0c8a731      },
  83         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
  84         {       XFER_MW_DMA_0,  0xa0c8a797      },
  85
  86         {       XFER_PIO_4,     0xc0c8a731      },
  87         {       XFER_PIO_3,     0xc0c8a742      },
  88         {       XFER_PIO_2,     0xc0d0a753      },
  89         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
  90         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
  91         {       0,              0x0120a7a7      }
  92 };
  93
  94 static const struct hpt_clock hpt366_25[] = {
  95         {       XFER_UDMA_4,    0x90c98521      },
  96         {       XFER_UDMA_3,    0x90cf8521      },
  97         {       XFER_UDMA_2,    0x90cf8521      },
  98         {       XFER_UDMA_1,    0x90cb8521      },
  99         {       XFER_UDMA_0,    0x90cb8521      },
 100
 101         {       XFER_MW_DMA_2,  0xa0ca8521      },
 102         {       XFER_MW_DMA_1,  0xa0ca8532      },
 103         {       XFER_MW_DMA_0,  0xa0ca8575      },
 104
 105         {       XFER_PIO_4,     0xc0ca8521      },
 106         {       XFER_PIO_3,     0xc0ca8532      },
 107         {       XFER_PIO_2,     0xc0ca8542      },
 108         {       XFER_PIO_1,     0xc0d08572      },
 109         {       XFER_PIO_0,     0xc0d08585      },
 110         {       0,              0x01208585      }
 111 };
 112
 113 static const char * const bad_ata33[] = {
 114         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
 115         "Maxtor 90845U3", "Maxtor 90650U2",
 116         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
 117         "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 118         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
 119         "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 120         "Maxtor 90510D4",
 121         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 122         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
 123         "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 124         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
 125         "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 126         NULL
 127 };
 128
 129 static const char * const bad_ata66_4[] = {
 130         "IBM-DTLA-307075",
 131         "IBM-DTLA-307060",
 132         "IBM-DTLA-307045",
 133         "IBM-DTLA-307030",
 134         "IBM-DTLA-307020",
 135         "IBM-DTLA-307015",
 136         "IBM-DTLA-305040",
 137         "IBM-DTLA-305030",
 138         "IBM-DTLA-305020",
 139         "IC35L010AVER07-0",
 140         "IC35L020AVER07-0",
 141         "IC35L030AVER07-0",
 142         "IC35L040AVER07-0",
 143         "IC35L060AVER07-0",
 144         "WDC AC310200R",
 145         NULL
 146 };
 147
 148 static const char * const bad_ata66_3[] = {
 149         "WDC AC310200R",
 150         NULL
 151 };
 152
 153 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
 154                                const char * const list[])
 155 {
 156         unsigned char model_num[ATA_ID_PROD_LEN + 1];
 157         int i = 0;
 158
 159         ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 160
 161         while (list[i] != NULL) {
 162                 if (!strcmp(list[i], model_num)) {
 163                         pr_warning(DRV_NAME ": %s is not supported for %s.\n",
 164                                    modestr, list[i]);
 165                         return 1;
 166                 }
 167                 i++;
 168         }
 169         return 0;
 170 }
 171
 172 /**
 173  *      hpt366_filter   -       mode selection filter
 174  *      @adev: ATA device
 175  *
 176  *      Block UDMA on devices that cause trouble with this controller.
 177  */
 178
 179 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
 180 {
 181         if (adev->class == ATA_DEV_ATA) {
 182                 if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
 183                         mask &= ~ATA_MASK_UDMA;
 184                 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
 185                         mask &= ~(0xF8 << ATA_SHIFT_UDMA);
 186                 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
 187                         mask &= ~(0xF0 << ATA_SHIFT_UDMA);
 188         } else if (adev->class == ATA_DEV_ATAPI)
 189                 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 190
 191         return mask;
 192 }
 193
 194 static int hpt36x_cable_detect(struct ata_port *ap)
 195 {
 196         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 197         u8 ata66;
 198
 199         /*
 200          * Each channel of pata_hpt366 occupies separate PCI function
 201          * as the primary channel and bit1 indicates the cable type.
 202          */
 203         pci_read_config_byte(pdev, 0x5A, &ata66);
 204         if (ata66 & 2)
 205                 return ATA_CBL_PATA40;
 206         return ATA_CBL_PATA80;
 207 }
 208
 209 static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
 210                             u8 mode)
 211 {
 212         struct hpt_clock *clocks = ap->host->private_data;
 213         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 214         u32 addr = 0x40 + 4 * adev->devno;
 215         u32 mask, reg;
 216
 217         /* determine timing mask and find matching clock entry */
 218         if (mode < XFER_MW_DMA_0)
 219                 mask = 0xc1f8ffff;
 220         else if (mode < XFER_UDMA_0)
 221                 mask = 0x303800ff;
 222         else
 223                 mask = 0x30070000;
 224
 225         while (clocks->xfer_mode) {
 226                 if (clocks->xfer_mode == mode)
 227                         break;
 228                 clocks++;
 229         }
 230         if (!clocks->xfer_mode)
 231                 BUG();
 232
 233         /*
 234          * Combine new mode bits with old config bits and disable
 235          * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
 236          * problems handling I/O errors later.
 237          */
 238         pci_read_config_dword(pdev, addr, &reg);
 239         reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
 240         pci_write_config_dword(pdev, addr, reg);
 241 }
 242
 243 /**
 244  *      hpt366_set_piomode              -       PIO setup
 245  *      @ap: ATA interface
 246  *      @adev: device on the interface
 247  *
 248  *      Perform PIO mode setup.
 249  */
 250
 251 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
 252 {
 253         hpt366_set_mode(ap, adev, adev->pio_mode);
 254 }
 255
 256 /**
 257  *      hpt366_set_dmamode              -       DMA timing setup
 258  *      @ap: ATA interface
 259  *      @adev: Device being configured
 260  *
 261  *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 262  *      PIO, load the mode number and then set MWDMA or UDMA flag.
 263  */
 264
 265 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 266 {
 267         hpt366_set_mode(ap, adev, adev->dma_mode);
 268 }
 269
 270 static struct scsi_host_template hpt36x_sht = {
 271         ATA_BMDMA_SHT(DRV_NAME),
 272 };
 273
 274 /*
 275  *      Configuration for HPT366/68
 276  */
 277
 278 static struct ata_port_operations hpt366_port_ops = {
 279         .inherits       = &ata_bmdma_port_ops,
 280         .cable_detect   = hpt36x_cable_detect,
 281         .mode_filter    = hpt366_filter,
 282         .set_piomode    = hpt366_set_piomode,
 283         .set_dmamode    = hpt366_set_dmamode,
 284 };
 285
 286 /**
 287  *      hpt36x_init_chipset     -       common chip setup
 288  *      @dev: PCI device
 289  *
 290  *      Perform the chip setup work that must be done at both init and
 291  *      resume time
 292  */
 293
 294 static void hpt36x_init_chipset(struct pci_dev *dev)
 295 {
 296         u8 drive_fast;
 297
 298         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 299         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 300         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 301         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 302
 303         pci_read_config_byte(dev, 0x51, &drive_fast);
 304         if (drive_fast & 0x80)
 305                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 306 }
 307
 308 /**
 309  *      hpt36x_init_one         -       Initialise an HPT366/368
 310  *      @dev: PCI device
 311  *      @id: Entry in match table
 312  *
 313  *      Initialise an HPT36x device. There are some interesting complications
 314  *      here. Firstly the chip may report 366 and be one of several variants.
 315  *      Secondly all the timings depend on the clock for the chip which we must
 316  *      detect and look up
 317  *
 318  *      This is the known chip mappings. It may be missing a couple of later
 319  *      releases.
 320  *
 321  *      Chip version            PCI             Rev     Notes
 322  *      HPT366                  4 (HPT366)      0       UDMA66
 323  *      HPT366                  4 (HPT366)      1       UDMA66
 324  *      HPT368                  4 (HPT366)      2       UDMA66
 325  *      HPT37x/30x              4 (HPT366)      3+      Other driver
 326  *
 327  */
 328
 329 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 330 {
 331         static const struct ata_port_info info_hpt366 = {
 332                 .flags = ATA_FLAG_SLAVE_POSS,
 333                 .pio_mask = ATA_PIO4,
 334                 .mwdma_mask = ATA_MWDMA2,
 335                 .udma_mask = ATA_UDMA4,
 336                 .port_ops = &hpt366_port_ops
 337         };
 338         const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
 339
 340         void *hpriv = NULL;
 341         u32 reg1;
 342         int rc;
 343
 344         rc = pcim_enable_device(dev);
 345         if (rc)
 346                 return rc;
 347
 348         /* May be a later chip in disguise. Check */
 349         /* Newer chips are not in the HPT36x driver. Ignore them */
 350         if (dev->revision > 2)
 351                 return -ENODEV;
 352
 353         hpt36x_init_chipset(dev);
 354
 355         pci_read_config_dword(dev, 0x40,  &reg1);
 356
 357         /* PCI clocking determines the ATA timing values to use */
 358         /* info_hpt366 is safe against re-entry so we can scribble on it */
 359         switch ((reg1 & 0x700) >> 8) {
 360         case 9:
 361                 hpriv = &hpt366_40;
 362                 break;
 363         case 5:
 364                 hpriv = &hpt366_25;
 365                 break;
 366         default:
 367                 hpriv = &hpt366_33;
 368                 break;
 369         }
 370         /* Now kick off ATA set up */
 371         return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
 372 }
 373
 374 #ifdef CONFIG_PM
 375 static int hpt36x_reinit_one(struct pci_dev *dev)
 376 {
 377         struct ata_host *host = dev_get_drvdata(&dev->dev);
 378         int rc;
 379
 380         rc = ata_pci_device_do_resume(dev);
 381         if (rc)
 382                 return rc;
 383         hpt36x_init_chipset(dev);
 384         ata_host_resume(host);
 385         return 0;
 386 }
 387 #endif
 388
 389 static const struct pci_device_id hpt36x[] = {
 390         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 391         { },
 392 };
 393
 394 static struct pci_driver hpt36x_pci_driver = {
 395         .name           = DRV_NAME,
 396         .id_table       = hpt36x,
 397         .probe          = hpt36x_init_one,
 398         .remove         = ata_pci_remove_one,
 399 #ifdef CONFIG_PM
 400         .suspend        = ata_pci_device_suspend,
 401         .resume         = hpt36x_reinit_one,
 402 #endif
 403 };
 404
 405 static int __init hpt36x_init(void)
 406 {
 407         return pci_register_driver(&hpt36x_pci_driver);
 408 }
 409
 410 static void __exit hpt36x_exit(void)
 411 {
 412         pci_unregister_driver(&hpt36x_pci_driver);
 413 }
 414
 415 MODULE_AUTHOR("Alan Cox");
 416 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
 417 MODULE_LICENSE("GPL");
 418 MODULE_DEVICE_TABLE(pci, hpt36x);
 419 MODULE_VERSION(DRV_VERSION);
 420
 421 module_init(hpt36x_init);
 422 module_exit(hpt36x_exit);