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iwlagn: don't assign seqno to QoS Null frames
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
blob60a8eccb713310db966549dde74e92f3f781ed9d
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/bitops.h>
66 #include <linux/gfp.h>
67
68 #include "iwl-trans.h"
69 #include "iwl-trans-pcie-int.h"
70 #include "iwl-csr.h"
71 #include "iwl-prph.h"
72 #include "iwl-shared.h"
73 #include "iwl-eeprom.h"
74 #include "iwl-agn-hw.h"
75
76 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
77 {
78 struct iwl_trans_pcie *trans_pcie =
79 IWL_TRANS_GET_PCIE_TRANS(trans);
80 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
81 struct device *dev = bus(trans)->dev;
82
83 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
84
85 spin_lock_init(&rxq->lock);
86
87 if (WARN_ON(rxq->bd || rxq->rb_stts))
88 return -EINVAL;
89
90 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
91 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
92 &rxq->bd_dma, GFP_KERNEL);
93 if (!rxq->bd)
94 goto err_bd;
95 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
96
97 /*Allocate the driver's pointer to receive buffer status */
98 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
99 &rxq->rb_stts_dma, GFP_KERNEL);
100 if (!rxq->rb_stts)
101 goto err_rb_stts;
102 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
103
104 return 0;
105
106 err_rb_stts:
107 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
108 rxq->bd, rxq->bd_dma);
109 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
110 rxq->bd = NULL;
111 err_bd:
112 return -ENOMEM;
113 }
114
115 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
116 {
117 struct iwl_trans_pcie *trans_pcie =
118 IWL_TRANS_GET_PCIE_TRANS(trans);
119 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
120 int i;
121
122 /* Fill the rx_used queue with _all_ of the Rx buffers */
123 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
124 /* In the reset function, these buffers may have been allocated
125 * to an SKB, so we need to unmap and free potential storage */
126 if (rxq->pool[i].page != NULL) {
127 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
128 PAGE_SIZE << hw_params(trans).rx_page_order,
129 DMA_FROM_DEVICE);
130 __free_pages(rxq->pool[i].page,
131 hw_params(trans).rx_page_order);
132 rxq->pool[i].page = NULL;
133 }
134 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
135 }
136 }
137
138 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
139 struct iwl_rx_queue *rxq)
140 {
141 u32 rb_size;
142 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
143 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
144
145 if (iwlagn_mod_params.amsdu_size_8K)
146 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
147 else
148 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
149
150 /* Stop Rx DMA */
151 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
152
153 /* Reset driver's Rx queue write index */
154 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
155
156 /* Tell device where to find RBD circular buffer in DRAM */
157 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
158 (u32)(rxq->bd_dma >> 8));
159
160 /* Tell device where in DRAM to update its Rx status */
161 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
162 rxq->rb_stts_dma >> 4);
163
164 /* Enable Rx DMA
165 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
166 * the credit mechanism in 5000 HW RX FIFO
167 * Direct rx interrupts to hosts
168 * Rx buffer size 4 or 8k
169 * RB timeout 0x10
170 * 256 RBDs
171 */
172 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
173 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
174 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
175 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
176 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
177 rb_size|
178 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
179 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
180
181 /* Set interrupt coalescing timer to default (2048 usecs) */
182 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
183 }
184
185 static int iwl_rx_init(struct iwl_trans *trans)
186 {
187 struct iwl_trans_pcie *trans_pcie =
188 IWL_TRANS_GET_PCIE_TRANS(trans);
189 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
190
191 int i, err;
192 unsigned long flags;
193
194 if (!rxq->bd) {
195 err = iwl_trans_rx_alloc(trans);
196 if (err)
197 return err;
198 }
199
200 spin_lock_irqsave(&rxq->lock, flags);
201 INIT_LIST_HEAD(&rxq->rx_free);
202 INIT_LIST_HEAD(&rxq->rx_used);
203
204 iwl_trans_rxq_free_rx_bufs(trans);
205
206 for (i = 0; i < RX_QUEUE_SIZE; i++)
207 rxq->queue[i] = NULL;
208
209 /* Set us so that we have processed and used all buffers, but have
210 * not restocked the Rx queue with fresh buffers */
211 rxq->read = rxq->write = 0;
212 rxq->write_actual = 0;
213 rxq->free_count = 0;
214 spin_unlock_irqrestore(&rxq->lock, flags);
215
216 iwlagn_rx_replenish(trans);
217
218 iwl_trans_rx_hw_init(trans, rxq);
219
220 spin_lock_irqsave(&trans->shrd->lock, flags);
221 rxq->need_update = 1;
222 iwl_rx_queue_update_write_ptr(trans, rxq);
223 spin_unlock_irqrestore(&trans->shrd->lock, flags);
224
225 return 0;
226 }
227
228 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
229 {
230 struct iwl_trans_pcie *trans_pcie =
231 IWL_TRANS_GET_PCIE_TRANS(trans);
232 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
233
234 unsigned long flags;
235
236 /*if rxq->bd is NULL, it means that nothing has been allocated,
237 * exit now */
238 if (!rxq->bd) {
239 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
240 return;
241 }
242
243 spin_lock_irqsave(&rxq->lock, flags);
244 iwl_trans_rxq_free_rx_bufs(trans);
245 spin_unlock_irqrestore(&rxq->lock, flags);
246
247 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
248 rxq->bd, rxq->bd_dma);
249 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
250 rxq->bd = NULL;
251
252 if (rxq->rb_stts)
253 dma_free_coherent(bus(trans)->dev,
254 sizeof(struct iwl_rb_status),
255 rxq->rb_stts, rxq->rb_stts_dma);
256 else
257 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
258 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
259 rxq->rb_stts = NULL;
260 }
261
262 static int iwl_trans_rx_stop(struct iwl_trans *trans)
263 {
264
265 /* stop Rx DMA */
266 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
267 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
268 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
269 }
270
271 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
272 struct iwl_dma_ptr *ptr, size_t size)
273 {
274 if (WARN_ON(ptr->addr))
275 return -EINVAL;
276
277 ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
278 &ptr->dma, GFP_KERNEL);
279 if (!ptr->addr)
280 return -ENOMEM;
281 ptr->size = size;
282 return 0;
283 }
284
285 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
286 struct iwl_dma_ptr *ptr)
287 {
288 if (unlikely(!ptr->addr))
289 return;
290
291 dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
292 memset(ptr, 0, sizeof(*ptr));
293 }
294
295 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
296 struct iwl_tx_queue *txq, int slots_num,
297 u32 txq_id)
298 {
299 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
300 int i;
301
302 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
303 return -EINVAL;
304
305 txq->q.n_window = slots_num;
306
307 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
308 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
309
310 if (!txq->meta || !txq->cmd)
311 goto error;
312
313 if (txq_id == trans->shrd->cmd_queue)
314 for (i = 0; i < slots_num; i++) {
315 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
316 GFP_KERNEL);
317 if (!txq->cmd[i])
318 goto error;
319 }
320
321 /* Alloc driver data array and TFD circular buffer */
322 /* Driver private data, only for Tx (not command) queues,
323 * not shared with device. */
324 if (txq_id != trans->shrd->cmd_queue) {
325 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
326 GFP_KERNEL);
327 if (!txq->skbs) {
328 IWL_ERR(trans, "kmalloc for auxiliary BD "
329 "structures failed\n");
330 goto error;
331 }
332 } else {
333 txq->skbs = NULL;
334 }
335
336 /* Circular buffer of transmit frame descriptors (TFDs),
337 * shared with device */
338 txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
339 &txq->q.dma_addr, GFP_KERNEL);
340 if (!txq->tfds) {
341 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
342 goto error;
343 }
344 txq->q.id = txq_id;
345
346 return 0;
347 error:
348 kfree(txq->skbs);
349 txq->skbs = NULL;
350 /* since txq->cmd has been zeroed,
351 * all non allocated cmd[i] will be NULL */
352 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
353 for (i = 0; i < slots_num; i++)
354 kfree(txq->cmd[i]);
355 kfree(txq->meta);
356 kfree(txq->cmd);
357 txq->meta = NULL;
358 txq->cmd = NULL;
359
360 return -ENOMEM;
361
362 }
363
364 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
365 int slots_num, u32 txq_id)
366 {
367 int ret;
368
369 txq->need_update = 0;
370 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
371
372 /*
373 * For the default queues 0-3, set up the swq_id
374 * already -- all others need to get one later
375 * (if they need one at all).
376 */
377 if (txq_id < 4)
378 iwl_set_swq_id(txq, txq_id, txq_id);
379
380 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
381 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
382 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
383
384 /* Initialize queue's high/low-water marks, and head/tail indexes */
385 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
386 txq_id);
387 if (ret)
388 return ret;
389
390 /*
391 * Tell nic where to find circular buffer of Tx Frame Descriptors for
392 * given Tx queue, and enable the DMA channel used for that queue.
393 * Circular buffer (TFD queue in DRAM) physical base address */
394 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
395 txq->q.dma_addr >> 8);
396
397 return 0;
398 }
399
400 /**
401 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
402 */
403 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
404 {
405 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
406 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
407 struct iwl_queue *q = &txq->q;
408 enum dma_data_direction dma_dir;
409
410 if (!q->n_bd)
411 return;
412
413 /* In the command queue, all the TBs are mapped as BIDI
414 * so unmap them as such.
415 */
416 if (txq_id == trans->shrd->cmd_queue)
417 dma_dir = DMA_BIDIRECTIONAL;
418 else
419 dma_dir = DMA_TO_DEVICE;
420
421 while (q->write_ptr != q->read_ptr) {
422 /* The read_ptr needs to bound by q->n_window */
423 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
424 dma_dir);
425 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
426 }
427 }
428
429 /**
430 * iwl_tx_queue_free - Deallocate DMA queue.
431 * @txq: Transmit queue to deallocate.
432 *
433 * Empty queue by removing and destroying all BD's.
434 * Free all buffers.
435 * 0-fill, but do not free "txq" descriptor structure.
436 */
437 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
438 {
439 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
440 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
441 struct device *dev = bus(trans)->dev;
442 int i;
443 if (WARN_ON(!txq))
444 return;
445
446 iwl_tx_queue_unmap(trans, txq_id);
447
448 /* De-alloc array of command/tx buffers */
449
450 if (txq_id == trans->shrd->cmd_queue)
451 for (i = 0; i < txq->q.n_window; i++)
452 kfree(txq->cmd[i]);
453
454 /* De-alloc circular buffer of TFDs */
455 if (txq->q.n_bd) {
456 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
457 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
458 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
459 }
460
461 /* De-alloc array of per-TFD driver data */
462 kfree(txq->skbs);
463 txq->skbs = NULL;
464
465 /* deallocate arrays */
466 kfree(txq->cmd);
467 kfree(txq->meta);
468 txq->cmd = NULL;
469 txq->meta = NULL;
470
471 /* 0-fill queue descriptor structure */
472 memset(txq, 0, sizeof(*txq));
473 }
474
475 /**
476 * iwl_trans_tx_free - Free TXQ Context
477 *
478 * Destroy all TX DMA queues and structures
479 */
480 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
481 {
482 int txq_id;
483 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
484
485 /* Tx queues */
486 if (trans_pcie->txq) {
487 for (txq_id = 0;
488 txq_id < hw_params(trans).max_txq_num; txq_id++)
489 iwl_tx_queue_free(trans, txq_id);
490 }
491
492 kfree(trans_pcie->txq);
493 trans_pcie->txq = NULL;
494
495 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
496
497 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
498 }
499
500 /**
501 * iwl_trans_tx_alloc - allocate TX context
502 * Allocate all Tx DMA structures and initialize them
503 *
504 * @param priv
505 * @return error code
506 */
507 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
508 {
509 int ret;
510 int txq_id, slots_num;
511 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
512
513 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
514 sizeof(struct iwlagn_scd_bc_tbl);
515
516 /*It is not allowed to alloc twice, so warn when this happens.
517 * We cannot rely on the previous allocation, so free and fail */
518 if (WARN_ON(trans_pcie->txq)) {
519 ret = -EINVAL;
520 goto error;
521 }
522
523 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
524 scd_bc_tbls_size);
525 if (ret) {
526 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
527 goto error;
528 }
529
530 /* Alloc keep-warm buffer */
531 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
532 if (ret) {
533 IWL_ERR(trans, "Keep Warm allocation failed\n");
534 goto error;
535 }
536
537 trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
538 sizeof(struct iwl_tx_queue), GFP_KERNEL);
539 if (!trans_pcie->txq) {
540 IWL_ERR(trans, "Not enough memory for txq\n");
541 ret = ENOMEM;
542 goto error;
543 }
544
545 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
546 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
547 slots_num = (txq_id == trans->shrd->cmd_queue) ?
548 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
549 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
550 slots_num, txq_id);
551 if (ret) {
552 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
553 goto error;
554 }
555 }
556
557 return 0;
558
559 error:
560 iwl_trans_pcie_tx_free(trans);
561
562 return ret;
563 }
564 static int iwl_tx_init(struct iwl_trans *trans)
565 {
566 int ret;
567 int txq_id, slots_num;
568 unsigned long flags;
569 bool alloc = false;
570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
571
572 if (!trans_pcie->txq) {
573 ret = iwl_trans_tx_alloc(trans);
574 if (ret)
575 goto error;
576 alloc = true;
577 }
578
579 spin_lock_irqsave(&trans->shrd->lock, flags);
580
581 /* Turn off all Tx DMA fifos */
582 iwl_write_prph(bus(trans), SCD_TXFACT, 0);
583
584 /* Tell NIC where to find the "keep warm" buffer */
585 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
586 trans_pcie->kw.dma >> 4);
587
588 spin_unlock_irqrestore(&trans->shrd->lock, flags);
589
590 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
591 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
592 slots_num = (txq_id == trans->shrd->cmd_queue) ?
593 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
594 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
595 slots_num, txq_id);
596 if (ret) {
597 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
598 goto error;
599 }
600 }
601
602 return 0;
603 error:
604 /*Upon error, free only if we allocated something */
605 if (alloc)
606 iwl_trans_pcie_tx_free(trans);
607 return ret;
608 }
609
610 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
611 {
612 /*
613 * (for documentation purposes)
614 * to set power to V_AUX, do:
615
616 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
617 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
618 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
619 ~APMG_PS_CTRL_MSK_PWR_SRC);
620 */
621
622 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
623 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
624 ~APMG_PS_CTRL_MSK_PWR_SRC);
625 }
626
627 static int iwl_nic_init(struct iwl_trans *trans)
628 {
629 unsigned long flags;
630
631 /* nic_init */
632 spin_lock_irqsave(&trans->shrd->lock, flags);
633 iwl_apm_init(priv(trans));
634
635 /* Set interrupt coalescing calibration timer to default (512 usecs) */
636 iwl_write8(bus(trans), CSR_INT_COALESCING,
637 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
638
639 spin_unlock_irqrestore(&trans->shrd->lock, flags);
640
641 iwl_set_pwr_vmain(trans);
642
643 iwl_nic_config(priv(trans));
644
645 /* Allocate the RX queue, or reset if it is already allocated */
646 iwl_rx_init(trans);
647
648 /* Allocate or reset and init all Tx and Command queues */
649 if (iwl_tx_init(trans))
650 return -ENOMEM;
651
652 if (hw_params(trans).shadow_reg_enable) {
653 /* enable shadow regs in HW */
654 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
655 0x800FFFFF);
656 }
657
658 set_bit(STATUS_INIT, &trans->shrd->status);
659
660 return 0;
661 }
662
663 #define HW_READY_TIMEOUT (50)
664
665 /* Note: returns poll_bit return value, which is >= 0 if success */
666 static int iwl_set_hw_ready(struct iwl_trans *trans)
667 {
668 int ret;
669
670 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
671 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
672
673 /* See if we got it */
674 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
675 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
676 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
677 HW_READY_TIMEOUT);
678
679 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
680 return ret;
681 }
682
683 /* Note: returns standard 0/-ERROR code */
684 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
685 {
686 int ret;
687
688 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
689
690 ret = iwl_set_hw_ready(trans);
691 if (ret >= 0)
692 return 0;
693
694 /* If HW is not ready, prepare the conditions to check again */
695 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
696 CSR_HW_IF_CONFIG_REG_PREPARE);
697
698 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
699 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
700 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
701
702 if (ret < 0)
703 return ret;
704
705 /* HW should be ready by now, check again. */
706 ret = iwl_set_hw_ready(trans);
707 if (ret >= 0)
708 return 0;
709 return ret;
710 }
711
712 #define IWL_AC_UNSET -1
713
714 struct queue_to_fifo_ac {
715 s8 fifo, ac;
716 };
717
718 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
719 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
720 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
721 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
722 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
723 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
724 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
725 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
726 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
727 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
728 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
729 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
730 };
731
732 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
733 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
734 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
735 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
736 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
737 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
738 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
739 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
740 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
741 { IWL_TX_FIFO_BE_IPAN, 2, },
742 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
743 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
744 };
745
746 static const u8 iwlagn_bss_ac_to_fifo[] = {
747 IWL_TX_FIFO_VO,
748 IWL_TX_FIFO_VI,
749 IWL_TX_FIFO_BE,
750 IWL_TX_FIFO_BK,
751 };
752 static const u8 iwlagn_bss_ac_to_queue[] = {
753 0, 1, 2, 3,
754 };
755 static const u8 iwlagn_pan_ac_to_fifo[] = {
756 IWL_TX_FIFO_VO_IPAN,
757 IWL_TX_FIFO_VI_IPAN,
758 IWL_TX_FIFO_BE_IPAN,
759 IWL_TX_FIFO_BK_IPAN,
760 };
761 static const u8 iwlagn_pan_ac_to_queue[] = {
762 7, 6, 5, 4,
763 };
764
765 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
766 {
767 int ret;
768 struct iwl_trans_pcie *trans_pcie =
769 IWL_TRANS_GET_PCIE_TRANS(trans);
770
771 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
772 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
773 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
774
775 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
776 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
777
778 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
779 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
780
781 if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
782 iwl_trans_pcie_prepare_card_hw(trans)) {
783 IWL_WARN(trans, "Exit HW not ready\n");
784 return -EIO;
785 }
786
787 /* If platform's RF_KILL switch is NOT set to KILL */
788 if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
789 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
790 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
791 else
792 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
793
794 if (iwl_is_rfkill(trans->shrd)) {
795 iwl_set_hw_rfkill_state(priv(trans), true);
796 iwl_enable_interrupts(trans);
797 return -ERFKILL;
798 }
799
800 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
801
802 ret = iwl_nic_init(trans);
803 if (ret) {
804 IWL_ERR(trans, "Unable to init nic\n");
805 return ret;
806 }
807
808 /* make sure rfkill handshake bits are cleared */
809 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
810 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
811 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
812
813 /* clear (again), then enable host interrupts */
814 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
815 iwl_enable_interrupts(trans);
816
817 /* really make sure rfkill handshake bits are cleared */
818 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
819 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
820
821 return 0;
822 }
823
824 /*
825 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
826 * must be called under priv->shrd->lock and mac access
827 */
828 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
829 {
830 iwl_write_prph(bus(trans), SCD_TXFACT, mask);
831 }
832
833 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
834 {
835 const struct queue_to_fifo_ac *queue_to_fifo;
836 struct iwl_trans_pcie *trans_pcie =
837 IWL_TRANS_GET_PCIE_TRANS(trans);
838 u32 a;
839 unsigned long flags;
840 int i, chan;
841 u32 reg_val;
842
843 spin_lock_irqsave(&trans->shrd->lock, flags);
844
845 trans_pcie->scd_base_addr =
846 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
847 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
848 /* reset conext data memory */
849 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
850 a += 4)
851 iwl_write_targ_mem(bus(trans), a, 0);
852 /* reset tx status memory */
853 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
854 a += 4)
855 iwl_write_targ_mem(bus(trans), a, 0);
856 for (; a < trans_pcie->scd_base_addr +
857 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
858 a += 4)
859 iwl_write_targ_mem(bus(trans), a, 0);
860
861 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
862 trans_pcie->scd_bc_tbls.dma >> 10);
863
864 /* Enable DMA channel */
865 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
866 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
867 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
868 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
869
870 /* Update FH chicken bits */
871 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
872 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
873 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
874
875 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
876 SCD_QUEUECHAIN_SEL_ALL(trans));
877 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
878
879 /* initiate the queues */
880 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
881 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
882 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
883 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
884 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
885 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
886 SCD_CONTEXT_QUEUE_OFFSET(i) +
887 sizeof(u32),
888 ((SCD_WIN_SIZE <<
889 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
890 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
891 ((SCD_FRAME_LIMIT <<
892 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
893 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
894 }
895
896 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
897 IWL_MASK(0, hw_params(trans).max_txq_num));
898
899 /* Activate all Tx DMA/FIFO channels */
900 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
901
902 /* map queues to FIFOs */
903 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
904 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
905 else
906 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
907
908 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
909
910 /* make sure all queue are not stopped */
911 memset(&trans_pcie->queue_stopped[0], 0,
912 sizeof(trans_pcie->queue_stopped));
913 for (i = 0; i < 4; i++)
914 atomic_set(&trans_pcie->queue_stop_count[i], 0);
915
916 /* reset to 0 to enable all the queue first */
917 trans_pcie->txq_ctx_active_msk = 0;
918
919 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
920 IWLAGN_FIRST_AMPDU_QUEUE);
921 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
922 IWLAGN_FIRST_AMPDU_QUEUE);
923
924 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
925 int fifo = queue_to_fifo[i].fifo;
926 int ac = queue_to_fifo[i].ac;
927
928 iwl_txq_ctx_activate(trans_pcie, i);
929
930 if (fifo == IWL_TX_FIFO_UNUSED)
931 continue;
932
933 if (ac != IWL_AC_UNSET)
934 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
935 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
936 fifo, 0);
937 }
938
939 spin_unlock_irqrestore(&trans->shrd->lock, flags);
940
941 /* Enable L1-Active */
942 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
943 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
944 }
945
946 /**
947 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
948 */
949 static int iwl_trans_tx_stop(struct iwl_trans *trans)
950 {
951 int ch, txq_id;
952 unsigned long flags;
953 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
954
955 /* Turn off all Tx DMA fifos */
956 spin_lock_irqsave(&trans->shrd->lock, flags);
957
958 iwl_trans_txq_set_sched(trans, 0);
959
960 /* Stop each Tx DMA channel, and wait for it to be idle */
961 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
962 iwl_write_direct32(bus(trans),
963 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
964 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
965 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
966 1000))
967 IWL_ERR(trans, "Failing on timeout while stopping"
968 " DMA channel %d [0x%08x]", ch,
969 iwl_read_direct32(bus(trans),
970 FH_TSSR_TX_STATUS_REG));
971 }
972 spin_unlock_irqrestore(&trans->shrd->lock, flags);
973
974 if (!trans_pcie->txq) {
975 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
976 return 0;
977 }
978
979 /* Unmap DMA from host system and free skb's */
980 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
981 iwl_tx_queue_unmap(trans, txq_id);
982
983 return 0;
984 }
985
986 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
987 {
988 unsigned long flags;
989 struct iwl_trans_pcie *trans_pcie =
990 IWL_TRANS_GET_PCIE_TRANS(trans);
991
992 spin_lock_irqsave(&trans->shrd->lock, flags);
993 iwl_disable_interrupts(trans);
994 spin_unlock_irqrestore(&trans->shrd->lock, flags);
995
996 /* wait to make sure we flush pending tasklet*/
997 synchronize_irq(bus(trans)->irq);
998 tasklet_kill(&trans_pcie->irq_tasklet);
999 }
1000
1001 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1002 {
1003 /* stop and reset the on-board processor */
1004 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1005
1006 /* tell the device to stop sending interrupts */
1007 iwl_trans_pcie_disable_sync_irq(trans);
1008
1009 /* device going down, Stop using ICT table */
1010 iwl_disable_ict(trans);
1011
1012 /*
1013 * If a HW restart happens during firmware loading,
1014 * then the firmware loading might call this function
1015 * and later it might be called again due to the
1016 * restart. So don't process again if the device is
1017 * already dead.
1018 */
1019 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1020 iwl_trans_tx_stop(trans);
1021 iwl_trans_rx_stop(trans);
1022
1023 /* Power-down device's busmaster DMA clocks */
1024 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1025 APMG_CLK_VAL_DMA_CLK_RQT);
1026 udelay(5);
1027 }
1028
1029 /* Make sure (redundant) we've released our request to stay awake */
1030 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1031 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1032
1033 /* Stop the device, and put it in low power state */
1034 iwl_apm_stop(priv(trans));
1035 }
1036
1037 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1038 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1039 u8 sta_id)
1040 {
1041 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1042 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1043 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1044 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1045 struct iwl_cmd_meta *out_meta;
1046 struct iwl_tx_queue *txq;
1047 struct iwl_queue *q;
1048
1049 dma_addr_t phys_addr = 0;
1050 dma_addr_t txcmd_phys;
1051 dma_addr_t scratch_phys;
1052 u16 len, firstlen, secondlen;
1053 u16 seq_number = 0;
1054 u8 wait_write_ptr = 0;
1055 u8 txq_id;
1056 u8 tid = 0;
1057 bool is_agg = false;
1058 __le16 fc = hdr->frame_control;
1059 u8 hdr_len = ieee80211_hdrlen(fc);
1060
1061 /*
1062 * Send this frame after DTIM -- there's a special queue
1063 * reserved for this for contexts that support AP mode.
1064 */
1065 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1066 txq_id = trans_pcie->mcast_queue[ctx];
1067
1068 /*
1069 * The microcode will clear the more data
1070 * bit in the last frame it transmits.
1071 */
1072 hdr->frame_control |=
1073 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1074 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1075 txq_id = IWL_AUX_QUEUE;
1076 else
1077 txq_id =
1078 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1079
1080 if (ieee80211_is_data_qos(fc) && !ieee80211_is_qos_nullfunc(fc)) {
1081 u8 *qc = NULL;
1082 struct iwl_tid_data *tid_data;
1083 qc = ieee80211_get_qos_ctl(hdr);
1084 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1085 tid_data = &trans->shrd->tid_data[sta_id][tid];
1086
1087 if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
1088 return -1;
1089
1090 seq_number = tid_data->seq_number;
1091 seq_number &= IEEE80211_SCTL_SEQ;
1092 hdr->seq_ctrl = hdr->seq_ctrl &
1093 cpu_to_le16(IEEE80211_SCTL_FRAG);
1094 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1095 seq_number += 0x10;
1096 /* aggregation is on for this <sta,tid> */
1097 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1098 WARN_ON(tid_data->agg.state != IWL_AGG_ON);
1099 txq_id = tid_data->agg.txq_id;
1100 is_agg = true;
1101 }
1102 }
1103
1104 /* Copy MAC header from skb into command buffer */
1105 memcpy(tx_cmd->hdr, hdr, hdr_len);
1106
1107 txq = &trans_pcie->txq[txq_id];
1108 q = &txq->q;
1109
1110 /* Set up driver data for this TFD */
1111 txq->skbs[q->write_ptr] = skb;
1112 txq->cmd[q->write_ptr] = dev_cmd;
1113
1114 dev_cmd->hdr.cmd = REPLY_TX;
1115 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1116 INDEX_TO_SEQ(q->write_ptr)));
1117
1118 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1119 out_meta = &txq->meta[q->write_ptr];
1120
1121 /*
1122 * Use the first empty entry in this queue's command buffer array
1123 * to contain the Tx command and MAC header concatenated together
1124 * (payload data will be in another buffer).
1125 * Size of this varies, due to varying MAC header length.
1126 * If end is not dword aligned, we'll have 2 extra bytes at the end
1127 * of the MAC header (device reads on dword boundaries).
1128 * We'll tell device about this padding later.
1129 */
1130 len = sizeof(struct iwl_tx_cmd) +
1131 sizeof(struct iwl_cmd_header) + hdr_len;
1132 firstlen = (len + 3) & ~3;
1133
1134 /* Tell NIC about any 2-byte padding after MAC header */
1135 if (firstlen != len)
1136 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1137
1138 /* Physical address of this Tx command's header (not MAC header!),
1139 * within command buffer array. */
1140 txcmd_phys = dma_map_single(bus(trans)->dev,
1141 &dev_cmd->hdr, firstlen,
1142 DMA_BIDIRECTIONAL);
1143 if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1144 return -1;
1145 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1146 dma_unmap_len_set(out_meta, len, firstlen);
1147
1148 if (!ieee80211_has_morefrags(fc)) {
1149 txq->need_update = 1;
1150 } else {
1151 wait_write_ptr = 1;
1152 txq->need_update = 0;
1153 }
1154
1155 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1156 * if any (802.11 null frames have no payload). */
1157 secondlen = skb->len - hdr_len;
1158 if (secondlen > 0) {
1159 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1160 secondlen, DMA_TO_DEVICE);
1161 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1162 dma_unmap_single(bus(trans)->dev,
1163 dma_unmap_addr(out_meta, mapping),
1164 dma_unmap_len(out_meta, len),
1165 DMA_BIDIRECTIONAL);
1166 return -1;
1167 }
1168 }
1169
1170 /* Attach buffers to TFD */
1171 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1172 if (secondlen > 0)
1173 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1174 secondlen, 0);
1175
1176 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1177 offsetof(struct iwl_tx_cmd, scratch);
1178
1179 /* take back ownership of DMA buffer to enable update */
1180 dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1181 DMA_BIDIRECTIONAL);
1182 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1183 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1184
1185 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1186 le16_to_cpu(dev_cmd->hdr.sequence));
1187 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1188 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1189 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1190
1191 /* Set up entry for this TFD in Tx byte-count array */
1192 if (is_agg)
1193 iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
1194 le16_to_cpu(tx_cmd->len));
1195
1196 dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1197 DMA_BIDIRECTIONAL);
1198
1199 trace_iwlwifi_dev_tx(priv(trans),
1200 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1201 sizeof(struct iwl_tfd),
1202 &dev_cmd->hdr, firstlen,
1203 skb->data + hdr_len, secondlen);
1204
1205 /* Tell device the write index *just past* this latest filled TFD */
1206 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1207 iwl_txq_update_write_ptr(trans, txq);
1208
1209 if (ieee80211_is_data_qos(fc) && !ieee80211_is_qos_nullfunc(fc)) {
1210 trans->shrd->tid_data[sta_id][tid].tfds_in_queue++;
1211 if (!ieee80211_has_morefrags(fc))
1212 trans->shrd->tid_data[sta_id][tid].seq_number =
1213 seq_number;
1214 }
1215
1216 /*
1217 * At this point the frame is "transmitted" successfully
1218 * and we will get a TX status notification eventually,
1219 * regardless of the value of ret. "ret" only indicates
1220 * whether or not we should update the write pointer.
1221 */
1222 if (iwl_queue_space(q) < q->high_mark) {
1223 if (wait_write_ptr) {
1224 txq->need_update = 1;
1225 iwl_txq_update_write_ptr(trans, txq);
1226 } else {
1227 iwl_stop_queue(trans, txq);
1228 }
1229 }
1230 return 0;
1231 }
1232
1233 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1234 {
1235 /* Remove all resets to allow NIC to operate */
1236 iwl_write32(bus(trans), CSR_RESET, 0);
1237 }
1238
1239 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1240 {
1241 struct iwl_trans_pcie *trans_pcie =
1242 IWL_TRANS_GET_PCIE_TRANS(trans);
1243 int err;
1244
1245 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1246
1247 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1248 iwl_irq_tasklet, (unsigned long)trans);
1249
1250 iwl_alloc_isr_ict(trans);
1251
1252 err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1253 DRV_NAME, trans);
1254 if (err) {
1255 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1256 iwl_free_isr_ict(trans);
1257 return err;
1258 }
1259
1260 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1261 return 0;
1262 }
1263
1264 static int iwlagn_txq_check_empty(struct iwl_trans *trans,
1265 int sta_id, u8 tid, int txq_id)
1266 {
1267 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1268 struct iwl_queue *q = &trans_pcie->txq[txq_id].q;
1269 struct iwl_tid_data *tid_data = &trans->shrd->tid_data[sta_id][tid];
1270
1271 lockdep_assert_held(&trans->shrd->sta_lock);
1272
1273 switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
1274 case IWL_EMPTYING_HW_QUEUE_DELBA:
1275 /* We are reclaiming the last packet of the */
1276 /* aggregated HW queue */
1277 if ((txq_id == tid_data->agg.txq_id) &&
1278 (q->read_ptr == q->write_ptr)) {
1279 IWL_DEBUG_HT(trans,
1280 "HW queue empty: continue DELBA flow\n");
1281 iwl_trans_pcie_txq_agg_disable(trans, txq_id);
1282 tid_data->agg.state = IWL_AGG_OFF;
1283 iwl_stop_tx_ba_trans_ready(priv(trans),
1284 NUM_IWL_RXON_CTX,
1285 sta_id, tid);
1286 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1287 }
1288 break;
1289 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1290 /* We are reclaiming the last packet of the queue */
1291 if (tid_data->tfds_in_queue == 0) {
1292 IWL_DEBUG_HT(trans,
1293 "HW queue empty: continue ADDBA flow\n");
1294 tid_data->agg.state = IWL_AGG_ON;
1295 iwl_start_tx_ba_trans_ready(priv(trans),
1296 NUM_IWL_RXON_CTX,
1297 sta_id, tid);
1298 }
1299 break;
1300 default:
1301 break;
1302 }
1303
1304 return 0;
1305 }
1306
1307 static void iwl_free_tfds_in_queue(struct iwl_trans *trans,
1308 int sta_id, int tid, int freed)
1309 {
1310 lockdep_assert_held(&trans->shrd->sta_lock);
1311
1312 if (trans->shrd->tid_data[sta_id][tid].tfds_in_queue >= freed)
1313 trans->shrd->tid_data[sta_id][tid].tfds_in_queue -= freed;
1314 else {
1315 IWL_DEBUG_TX(trans, "free more than tfds_in_queue (%u:%d)\n",
1316 trans->shrd->tid_data[sta_id][tid].tfds_in_queue,
1317 freed);
1318 trans->shrd->tid_data[sta_id][tid].tfds_in_queue = 0;
1319 }
1320 }
1321
1322 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1323 int txq_id, int ssn, u32 status,
1324 struct sk_buff_head *skbs)
1325 {
1326 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1327 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1328 enum iwl_agg_state agg_state;
1329 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1330 int tfd_num = ssn & (txq->q.n_bd - 1);
1331 int freed = 0;
1332 bool cond;
1333
1334 txq->time_stamp = jiffies;
1335
1336 if (txq->sched_retry) {
1337 agg_state =
1338 trans->shrd->tid_data[txq->sta_id][txq->tid].agg.state;
1339 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1340 } else {
1341 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1342 }
1343
1344 if (txq->q.read_ptr != tfd_num) {
1345 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1346 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1347 ssn , tfd_num, txq_id, txq->swq_id);
1348 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1349 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1350 iwl_wake_queue(trans, txq);
1351 }
1352
1353 iwl_free_tfds_in_queue(trans, sta_id, tid, freed);
1354 iwlagn_txq_check_empty(trans, sta_id, tid, txq_id);
1355 }
1356
1357 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1358 {
1359 iwl_trans_pcie_tx_free(trans);
1360 iwl_trans_pcie_rx_free(trans);
1361 free_irq(bus(trans)->irq, trans);
1362 iwl_free_isr_ict(trans);
1363 trans->shrd->trans = NULL;
1364 kfree(trans);
1365 }
1366
1367 #ifdef CONFIG_PM_SLEEP
1368 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1369 {
1370 /*
1371 * This function is called when system goes into suspend state
1372 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1373 * first but since iwl_mac_stop() has no knowledge of who the caller is,
1374 * it will not call apm_ops.stop() to stop the DMA operation.
1375 * Calling apm_ops.stop here to make sure we stop the DMA.
1376 *
1377 * But of course ... if we have configured WoWLAN then we did other
1378 * things already :-)
1379 */
1380 if (!trans->shrd->wowlan)
1381 iwl_apm_stop(priv(trans));
1382
1383 return 0;
1384 }
1385
1386 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1387 {
1388 bool hw_rfkill = false;
1389
1390 iwl_enable_interrupts(trans);
1391
1392 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1393 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1394 hw_rfkill = true;
1395
1396 if (hw_rfkill)
1397 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1398 else
1399 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1400
1401 iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1402
1403 return 0;
1404 }
1405 #endif /* CONFIG_PM_SLEEP */
1406
1407 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1408 enum iwl_rxon_context_id ctx)
1409 {
1410 u8 ac, txq_id;
1411 struct iwl_trans_pcie *trans_pcie =
1412 IWL_TRANS_GET_PCIE_TRANS(trans);
1413
1414 for (ac = 0; ac < AC_NUM; ac++) {
1415 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1416 IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n",
1417 ac,
1418 (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1419 ? "stopped" : "awake");
1420 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1421 }
1422 }
1423
1424 const struct iwl_trans_ops trans_ops_pcie;
1425
1426 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1427 {
1428 struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1429 sizeof(struct iwl_trans_pcie),
1430 GFP_KERNEL);
1431 if (iwl_trans) {
1432 struct iwl_trans_pcie *trans_pcie =
1433 IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1434 iwl_trans->ops = &trans_ops_pcie;
1435 iwl_trans->shrd = shrd;
1436 trans_pcie->trans = iwl_trans;
1437 spin_lock_init(&iwl_trans->hcmd_lock);
1438 }
1439
1440 return iwl_trans;
1441 }
1442
1443 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id)
1444 {
1445 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1446
1447 iwl_stop_queue(trans, &trans_pcie->txq[txq_id]);
1448 }
1449
1450 #define IWL_FLUSH_WAIT_MS 2000
1451
1452 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1453 {
1454 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1455 struct iwl_tx_queue *txq;
1456 struct iwl_queue *q;
1457 int cnt;
1458 unsigned long now = jiffies;
1459 int ret = 0;
1460
1461 /* waiting for all the tx frames complete might take a while */
1462 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1463 if (cnt == trans->shrd->cmd_queue)
1464 continue;
1465 txq = &trans_pcie->txq[cnt];
1466 q = &txq->q;
1467 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1468 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1469 msleep(1);
1470
1471 if (q->read_ptr != q->write_ptr) {
1472 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1473 ret = -ETIMEDOUT;
1474 break;
1475 }
1476 }
1477 return ret;
1478 }
1479
1480 /*
1481 * On every watchdog tick we check (latest) time stamp. If it does not
1482 * change during timeout period and queue is not empty we reset firmware.
1483 */
1484 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1485 {
1486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1487 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1488 struct iwl_queue *q = &txq->q;
1489 unsigned long timeout;
1490
1491 if (q->read_ptr == q->write_ptr) {
1492 txq->time_stamp = jiffies;
1493 return 0;
1494 }
1495
1496 timeout = txq->time_stamp +
1497 msecs_to_jiffies(hw_params(trans).wd_timeout);
1498
1499 if (time_after(jiffies, timeout)) {
1500 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1501 hw_params(trans).wd_timeout);
1502 IWL_ERR(trans, "Current read_ptr %d write_ptr %d\n",
1503 q->read_ptr, q->write_ptr);
1504 return 1;
1505 }
1506
1507 return 0;
1508 }
1509
1510 static const char *get_fh_string(int cmd)
1511 {
1512 switch (cmd) {
1513 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1514 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1515 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1516 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1517 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1518 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1519 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1520 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1521 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1522 default:
1523 return "UNKNOWN";
1524 }
1525 }
1526
1527 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1528 {
1529 int i;
1530 #ifdef CONFIG_IWLWIFI_DEBUG
1531 int pos = 0;
1532 size_t bufsz = 0;
1533 #endif
1534 static const u32 fh_tbl[] = {
1535 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1536 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1537 FH_RSCSR_CHNL0_WPTR,
1538 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1539 FH_MEM_RSSR_SHARED_CTRL_REG,
1540 FH_MEM_RSSR_RX_STATUS_REG,
1541 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1542 FH_TSSR_TX_STATUS_REG,
1543 FH_TSSR_TX_ERROR_REG
1544 };
1545 #ifdef CONFIG_IWLWIFI_DEBUG
1546 if (display) {
1547 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1548 *buf = kmalloc(bufsz, GFP_KERNEL);
1549 if (!*buf)
1550 return -ENOMEM;
1551 pos += scnprintf(*buf + pos, bufsz - pos,
1552 "FH register values:\n");
1553 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1554 pos += scnprintf(*buf + pos, bufsz - pos,
1555 " %34s: 0X%08x\n",
1556 get_fh_string(fh_tbl[i]),
1557 iwl_read_direct32(bus(trans), fh_tbl[i]));
1558 }
1559 return pos;
1560 }
1561 #endif
1562 IWL_ERR(trans, "FH register values:\n");
1563 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1564 IWL_ERR(trans, " %34s: 0X%08x\n",
1565 get_fh_string(fh_tbl[i]),
1566 iwl_read_direct32(bus(trans), fh_tbl[i]));
1567 }
1568 return 0;
1569 }
1570
1571 static const char *get_csr_string(int cmd)
1572 {
1573 switch (cmd) {
1574 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1575 IWL_CMD(CSR_INT_COALESCING);
1576 IWL_CMD(CSR_INT);
1577 IWL_CMD(CSR_INT_MASK);
1578 IWL_CMD(CSR_FH_INT_STATUS);
1579 IWL_CMD(CSR_GPIO_IN);
1580 IWL_CMD(CSR_RESET);
1581 IWL_CMD(CSR_GP_CNTRL);
1582 IWL_CMD(CSR_HW_REV);
1583 IWL_CMD(CSR_EEPROM_REG);
1584 IWL_CMD(CSR_EEPROM_GP);
1585 IWL_CMD(CSR_OTP_GP_REG);
1586 IWL_CMD(CSR_GIO_REG);
1587 IWL_CMD(CSR_GP_UCODE_REG);
1588 IWL_CMD(CSR_GP_DRIVER_REG);
1589 IWL_CMD(CSR_UCODE_DRV_GP1);
1590 IWL_CMD(CSR_UCODE_DRV_GP2);
1591 IWL_CMD(CSR_LED_REG);
1592 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1593 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1594 IWL_CMD(CSR_ANA_PLL_CFG);
1595 IWL_CMD(CSR_HW_REV_WA_REG);
1596 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1597 default:
1598 return "UNKNOWN";
1599 }
1600 }
1601
1602 void iwl_dump_csr(struct iwl_trans *trans)
1603 {
1604 int i;
1605 static const u32 csr_tbl[] = {
1606 CSR_HW_IF_CONFIG_REG,
1607 CSR_INT_COALESCING,
1608 CSR_INT,
1609 CSR_INT_MASK,
1610 CSR_FH_INT_STATUS,
1611 CSR_GPIO_IN,
1612 CSR_RESET,
1613 CSR_GP_CNTRL,
1614 CSR_HW_REV,
1615 CSR_EEPROM_REG,
1616 CSR_EEPROM_GP,
1617 CSR_OTP_GP_REG,
1618 CSR_GIO_REG,
1619 CSR_GP_UCODE_REG,
1620 CSR_GP_DRIVER_REG,
1621 CSR_UCODE_DRV_GP1,
1622 CSR_UCODE_DRV_GP2,
1623 CSR_LED_REG,
1624 CSR_DRAM_INT_TBL_REG,
1625 CSR_GIO_CHICKEN_BITS,
1626 CSR_ANA_PLL_CFG,
1627 CSR_HW_REV_WA_REG,
1628 CSR_DBG_HPET_MEM_REG
1629 };
1630 IWL_ERR(trans, "CSR values:\n");
1631 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1632 "CSR_INT_PERIODIC_REG)\n");
1633 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1634 IWL_ERR(trans, " %25s: 0X%08x\n",
1635 get_csr_string(csr_tbl[i]),
1636 iwl_read32(bus(trans), csr_tbl[i]));
1637 }
1638 }
1639
1640 #ifdef CONFIG_IWLWIFI_DEBUGFS
1641 /* create and remove of files */
1642 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1643 if (!debugfs_create_file(#name, mode, parent, trans, \
1644 &iwl_dbgfs_##name##_ops)) \
1645 return -ENOMEM; \
1646 } while (0)
1647
1648 /* file operation */
1649 #define DEBUGFS_READ_FUNC(name) \
1650 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1651 char __user *user_buf, \
1652 size_t count, loff_t *ppos);
1653
1654 #define DEBUGFS_WRITE_FUNC(name) \
1655 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1656 const char __user *user_buf, \
1657 size_t count, loff_t *ppos);
1658
1659
1660 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1661 {
1662 file->private_data = inode->i_private;
1663 return 0;
1664 }
1665
1666 #define DEBUGFS_READ_FILE_OPS(name) \
1667 DEBUGFS_READ_FUNC(name); \
1668 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1669 .read = iwl_dbgfs_##name##_read, \
1670 .open = iwl_dbgfs_open_file_generic, \
1671 .llseek = generic_file_llseek, \
1672 };
1673
1674 #define DEBUGFS_WRITE_FILE_OPS(name) \
1675 DEBUGFS_WRITE_FUNC(name); \
1676 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1677 .write = iwl_dbgfs_##name##_write, \
1678 .open = iwl_dbgfs_open_file_generic, \
1679 .llseek = generic_file_llseek, \
1680 };
1681
1682 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1683 DEBUGFS_READ_FUNC(name); \
1684 DEBUGFS_WRITE_FUNC(name); \
1685 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1686 .write = iwl_dbgfs_##name##_write, \
1687 .read = iwl_dbgfs_##name##_read, \
1688 .open = iwl_dbgfs_open_file_generic, \
1689 .llseek = generic_file_llseek, \
1690 };
1691
1692 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1693 char __user *user_buf,
1694 size_t count, loff_t *ppos)
1695 {
1696 struct iwl_trans *trans = file->private_data;
1697 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1698 struct iwl_tx_queue *txq;
1699 struct iwl_queue *q;
1700 char *buf;
1701 int pos = 0;
1702 int cnt;
1703 int ret;
1704 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1705
1706 if (!trans_pcie->txq) {
1707 IWL_ERR(trans, "txq not ready\n");
1708 return -EAGAIN;
1709 }
1710 buf = kzalloc(bufsz, GFP_KERNEL);
1711 if (!buf)
1712 return -ENOMEM;
1713
1714 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1715 txq = &trans_pcie->txq[cnt];
1716 q = &txq->q;
1717 pos += scnprintf(buf + pos, bufsz - pos,
1718 "hwq %.2d: read=%u write=%u stop=%d"
1719 " swq_id=%#.2x (ac %d/hwq %d)\n",
1720 cnt, q->read_ptr, q->write_ptr,
1721 !!test_bit(cnt, trans_pcie->queue_stopped),
1722 txq->swq_id, txq->swq_id & 3,
1723 (txq->swq_id >> 2) & 0x1f);
1724 if (cnt >= 4)
1725 continue;
1726 /* for the ACs, display the stop count too */
1727 pos += scnprintf(buf + pos, bufsz - pos,
1728 " stop-count: %d\n",
1729 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1730 }
1731 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1732 kfree(buf);
1733 return ret;
1734 }
1735
1736 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1737 char __user *user_buf,
1738 size_t count, loff_t *ppos) {
1739 struct iwl_trans *trans = file->private_data;
1740 struct iwl_trans_pcie *trans_pcie =
1741 IWL_TRANS_GET_PCIE_TRANS(trans);
1742 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1743 char buf[256];
1744 int pos = 0;
1745 const size_t bufsz = sizeof(buf);
1746
1747 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1748 rxq->read);
1749 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1750 rxq->write);
1751 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1752 rxq->free_count);
1753 if (rxq->rb_stts) {
1754 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1755 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1756 } else {
1757 pos += scnprintf(buf + pos, bufsz - pos,
1758 "closed_rb_num: Not Allocated\n");
1759 }
1760 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1761 }
1762
1763 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1764 char __user *user_buf,
1765 size_t count, loff_t *ppos)
1766 {
1767 struct iwl_trans *trans = file->private_data;
1768 char *buf;
1769 int pos = 0;
1770 ssize_t ret = -ENOMEM;
1771
1772 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1773 if (buf) {
1774 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1775 kfree(buf);
1776 }
1777 return ret;
1778 }
1779
1780 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1781 const char __user *user_buf,
1782 size_t count, loff_t *ppos)
1783 {
1784 struct iwl_trans *trans = file->private_data;
1785 u32 event_log_flag;
1786 char buf[8];
1787 int buf_size;
1788
1789 memset(buf, 0, sizeof(buf));
1790 buf_size = min(count, sizeof(buf) - 1);
1791 if (copy_from_user(buf, user_buf, buf_size))
1792 return -EFAULT;
1793 if (sscanf(buf, "%d", &event_log_flag) != 1)
1794 return -EFAULT;
1795 if (event_log_flag == 1)
1796 iwl_dump_nic_event_log(trans, true, NULL, false);
1797
1798 return count;
1799 }
1800
1801 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1802 char __user *user_buf,
1803 size_t count, loff_t *ppos) {
1804
1805 struct iwl_trans *trans = file->private_data;
1806 struct iwl_trans_pcie *trans_pcie =
1807 IWL_TRANS_GET_PCIE_TRANS(trans);
1808 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1809
1810 int pos = 0;
1811 char *buf;
1812 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1813 ssize_t ret;
1814
1815 buf = kzalloc(bufsz, GFP_KERNEL);
1816 if (!buf) {
1817 IWL_ERR(trans, "Can not allocate Buffer\n");
1818 return -ENOMEM;
1819 }
1820
1821 pos += scnprintf(buf + pos, bufsz - pos,
1822 "Interrupt Statistics Report:\n");
1823
1824 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1825 isr_stats->hw);
1826 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1827 isr_stats->sw);
1828 if (isr_stats->sw || isr_stats->hw) {
1829 pos += scnprintf(buf + pos, bufsz - pos,
1830 "\tLast Restarting Code: 0x%X\n",
1831 isr_stats->err_code);
1832 }
1833 #ifdef CONFIG_IWLWIFI_DEBUG
1834 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1835 isr_stats->sch);
1836 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1837 isr_stats->alive);
1838 #endif
1839 pos += scnprintf(buf + pos, bufsz - pos,
1840 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1841
1842 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1843 isr_stats->ctkill);
1844
1845 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1846 isr_stats->wakeup);
1847
1848 pos += scnprintf(buf + pos, bufsz - pos,
1849 "Rx command responses:\t\t %u\n", isr_stats->rx);
1850
1851 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1852 isr_stats->tx);
1853
1854 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1855 isr_stats->unhandled);
1856
1857 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1858 kfree(buf);
1859 return ret;
1860 }
1861
1862 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1863 const char __user *user_buf,
1864 size_t count, loff_t *ppos)
1865 {
1866 struct iwl_trans *trans = file->private_data;
1867 struct iwl_trans_pcie *trans_pcie =
1868 IWL_TRANS_GET_PCIE_TRANS(trans);
1869 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1870
1871 char buf[8];
1872 int buf_size;
1873 u32 reset_flag;
1874
1875 memset(buf, 0, sizeof(buf));
1876 buf_size = min(count, sizeof(buf) - 1);
1877 if (copy_from_user(buf, user_buf, buf_size))
1878 return -EFAULT;
1879 if (sscanf(buf, "%x", &reset_flag) != 1)
1880 return -EFAULT;
1881 if (reset_flag == 0)
1882 memset(isr_stats, 0, sizeof(*isr_stats));
1883
1884 return count;
1885 }
1886
1887 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1888 const char __user *user_buf,
1889 size_t count, loff_t *ppos)
1890 {
1891 struct iwl_trans *trans = file->private_data;
1892 char buf[8];
1893 int buf_size;
1894 int csr;
1895
1896 memset(buf, 0, sizeof(buf));
1897 buf_size = min(count, sizeof(buf) - 1);
1898 if (copy_from_user(buf, user_buf, buf_size))
1899 return -EFAULT;
1900 if (sscanf(buf, "%d", &csr) != 1)
1901 return -EFAULT;
1902
1903 iwl_dump_csr(trans);
1904
1905 return count;
1906 }
1907
1908 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1909 char __user *user_buf,
1910 size_t count, loff_t *ppos)
1911 {
1912 struct iwl_trans *trans = file->private_data;
1913 char *buf;
1914 int pos = 0;
1915 ssize_t ret = -EFAULT;
1916
1917 ret = pos = iwl_dump_fh(trans, &buf, true);
1918 if (buf) {
1919 ret = simple_read_from_buffer(user_buf,
1920 count, ppos, buf, pos);
1921 kfree(buf);
1922 }
1923
1924 return ret;
1925 }
1926
1927 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1928 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1929 DEBUGFS_READ_FILE_OPS(fh_reg);
1930 DEBUGFS_READ_FILE_OPS(rx_queue);
1931 DEBUGFS_READ_FILE_OPS(tx_queue);
1932 DEBUGFS_WRITE_FILE_OPS(csr);
1933
1934 /*
1935 * Create the debugfs files and directories
1936 *
1937 */
1938 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1939 struct dentry *dir)
1940 {
1941 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1942 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1943 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1944 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1945 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1946 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1947 return 0;
1948 }
1949 #else
1950 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1951 struct dentry *dir)
1952 { return 0; }
1953
1954 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1955
1956 const struct iwl_trans_ops trans_ops_pcie = {
1957 .alloc = iwl_trans_pcie_alloc,
1958 .request_irq = iwl_trans_pcie_request_irq,
1959 .start_device = iwl_trans_pcie_start_device,
1960 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1961 .stop_device = iwl_trans_pcie_stop_device,
1962
1963 .tx_start = iwl_trans_pcie_tx_start,
1964 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1965
1966 .send_cmd = iwl_trans_pcie_send_cmd,
1967
1968 .tx = iwl_trans_pcie_tx,
1969 .reclaim = iwl_trans_pcie_reclaim,
1970
1971 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1972 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1973 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1974
1975 .kick_nic = iwl_trans_pcie_kick_nic,
1976
1977 .free = iwl_trans_pcie_free,
1978 .stop_queue = iwl_trans_pcie_stop_queue,
1979
1980 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1981
1982 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1983 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1984
1985 #ifdef CONFIG_PM_SLEEP
1986 .suspend = iwl_trans_pcie_suspend,
1987 .resume = iwl_trans_pcie_resume,
1988 #endif
1989 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree