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hmt: adjust for new pwm_backlight->notify prototype
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / sata_fsl.c
blobce4136eea08fa5f309855a621dd981a412fd6d9b
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21
22 #include <scsi/scsi_host.h>
23 #include <scsi/scsi_cmnd.h>
24 #include <linux/libata.h>
25 #include <asm/io.h>
26 #include <linux/of_platform.h>
27
28 /* Controller information */
29 enum {
30 SATA_FSL_QUEUE_DEPTH = 16,
31 SATA_FSL_MAX_PRD = 63,
32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
34
35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
37 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
38
39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
42
43 /*
44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
45 * chained indirect PRDEs upto a max count of 63.
46 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
47 * be setup as an indirect descriptor, pointing to it's next
48 * (contiguous) PRDE. Though chained indirect PRDE arrays are
49 * supported,it will be more efficient to use a direct PRDT and
50 * a single chain/link to indirect PRDE array/PRDT.
51 */
52
53 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
54 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
56 SATA_FSL_CMD_DESC_RSRVD = 16,
57
58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
59 SATA_FSL_CMD_DESC_SFIS_SZ +
60 SATA_FSL_CMD_DESC_ACMD_SZ +
61 SATA_FSL_CMD_DESC_RSRVD +
62 SATA_FSL_MAX_PRD * 16),
63
64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
65 (SATA_FSL_CMD_DESC_CFIS_SZ +
66 SATA_FSL_CMD_DESC_SFIS_SZ +
67 SATA_FSL_CMD_DESC_ACMD_SZ +
68 SATA_FSL_CMD_DESC_RSRVD),
69
70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
72 SATA_FSL_CMD_DESC_AR_SZ),
73
74 /*
75 * MPC8315 has two SATA controllers, SATA1 & SATA2
76 * (one port per controller)
77 * MPC837x has 2/4 controllers, one port per controller
78 */
79
80 SATA_FSL_MAX_PORTS = 1,
81
82 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
83 };
84
85 /*
86 * Host Controller command register set - per port
87 */
88 enum {
89 CQ = 0,
90 CA = 8,
91 CC = 0x10,
92 CE = 0x18,
93 DE = 0x20,
94 CHBA = 0x24,
95 HSTATUS = 0x28,
96 HCONTROL = 0x2C,
97 CQPMP = 0x30,
98 SIGNATURE = 0x34,
99 ICC = 0x38,
100
101 /*
102 * Host Status Register (HStatus) bitdefs
103 */
104 ONLINE = (1 << 31),
105 GOING_OFFLINE = (1 << 30),
106 BIST_ERR = (1 << 29),
107
108 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
109 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
110 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
111 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
112 FATAL_ERR_DATA_OVERRUN = (1 << 12),
113 FATAL_ERR_CRC_ERR_TX = (1 << 11),
114 FATAL_ERR_CRC_ERR_RX = (1 << 10),
115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
117
118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
119 FATAL_ERR_PARITY_ERR_TX |
120 FATAL_ERR_PARITY_ERR_RX |
121 FATAL_ERR_DATA_UNDERRUN |
122 FATAL_ERR_DATA_OVERRUN |
123 FATAL_ERR_CRC_ERR_TX |
124 FATAL_ERR_CRC_ERR_RX |
125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
126
127 INT_ON_FATAL_ERR = (1 << 5),
128 INT_ON_PHYRDY_CHG = (1 << 4),
129
130 INT_ON_SIGNATURE_UPDATE = (1 << 3),
131 INT_ON_SNOTIFY_UPDATE = (1 << 2),
132 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
133 INT_ON_CMD_COMPLETE = 1,
134
135 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
137
138 /*
139 * Host Control Register (HControl) bitdefs
140 */
141 HCONTROL_ONLINE_PHY_RST = (1 << 31),
142 HCONTROL_FORCE_OFFLINE = (1 << 30),
143 HCONTROL_PARITY_PROT_MOD = (1 << 14),
144 HCONTROL_DPATH_PARITY = (1 << 12),
145 HCONTROL_SNOOP_ENABLE = (1 << 10),
146 HCONTROL_PMP_ATTACHED = (1 << 9),
147 HCONTROL_COPYOUT_STATFIS = (1 << 8),
148 IE_ON_FATAL_ERR = (1 << 5),
149 IE_ON_PHYRDY_CHG = (1 << 4),
150 IE_ON_SIGNATURE_UPDATE = (1 << 3),
151 IE_ON_SNOTIFY_UPDATE = (1 << 2),
152 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
153 IE_ON_CMD_COMPLETE = 1,
154
155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
156 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
158
159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
160 DATA_SNOOP_ENABLE = (1 << 22),
161 };
162
163 /*
164 * SATA Superset Registers
165 */
166 enum {
167 SSTATUS = 0,
168 SERROR = 4,
169 SCONTROL = 8,
170 SNOTIFY = 0xC,
171 };
172
173 /*
174 * Control Status Register Set
175 */
176 enum {
177 TRANSCFG = 0,
178 TRANSSTATUS = 4,
179 LINKCFG = 8,
180 LINKCFG1 = 0xC,
181 LINKCFG2 = 0x10,
182 LINKSTATUS = 0x14,
183 LINKSTATUS1 = 0x18,
184 PHYCTRLCFG = 0x1C,
185 COMMANDSTAT = 0x20,
186 };
187
188 /* PHY (link-layer) configuration control */
189 enum {
190 PHY_BIST_ENABLE = 0x01,
191 };
192
193 /*
194 * Command Header Table entry, i.e, command slot
195 * 4 Dwords per command slot, command header size == 64 Dwords.
196 */
197 struct cmdhdr_tbl_entry {
198 u32 cda;
199 u32 prde_fis_len;
200 u32 ttl;
201 u32 desc_info;
202 };
203
204 /*
205 * Description information bitdefs
206 */
207 enum {
208 CMD_DESC_RES = (1 << 11),
209 VENDOR_SPECIFIC_BIST = (1 << 10),
210 CMD_DESC_SNOOP_ENABLE = (1 << 9),
211 FPDMA_QUEUED_CMD = (1 << 8),
212 SRST_CMD = (1 << 7),
213 BIST = (1 << 6),
214 ATAPI_CMD = (1 << 5),
215 };
216
217 /*
218 * Command Descriptor
219 */
220 struct command_desc {
221 u8 cfis[8 * 4];
222 u8 sfis[8 * 4];
223 u8 acmd[4 * 4];
224 u8 fill[4 * 4];
225 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
226 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
227 };
228
229 /*
230 * Physical region table descriptor(PRD)
231 */
232
233 struct prde {
234 u32 dba;
235 u8 fill[2 * 4];
236 u32 ddc_and_ext;
237 };
238
239 /*
240 * ata_port private data
241 * This is our per-port instance data.
242 */
243 struct sata_fsl_port_priv {
244 struct cmdhdr_tbl_entry *cmdslot;
245 dma_addr_t cmdslot_paddr;
246 struct command_desc *cmdentry;
247 dma_addr_t cmdentry_paddr;
248 };
249
250 /*
251 * ata_port->host_set private data
252 */
253 struct sata_fsl_host_priv {
254 void __iomem *hcr_base;
255 void __iomem *ssr_base;
256 void __iomem *csr_base;
257 int irq;
258 };
259
260 static inline unsigned int sata_fsl_tag(unsigned int tag,
261 void __iomem *hcr_base)
262 {
263 /* We let libATA core do actual (queue) tag allocation */
264
265 /* all non NCQ/queued commands should have tag#0 */
266 if (ata_tag_internal(tag)) {
267 DPRINTK("mapping internal cmds to tag#0\n");
268 return 0;
269 }
270
271 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
272 DPRINTK("tag %d invalid : out of range\n", tag);
273 return 0;
274 }
275
276 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
277 DPRINTK("tag %d invalid : in use!!\n", tag);
278 return 0;
279 }
280
281 return tag;
282 }
283
284 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
285 unsigned int tag, u32 desc_info,
286 u32 data_xfer_len, u8 num_prde,
287 u8 fis_len)
288 {
289 dma_addr_t cmd_descriptor_address;
290
291 cmd_descriptor_address = pp->cmdentry_paddr +
292 tag * SATA_FSL_CMD_DESC_SIZE;
293
294 /* NOTE: both data_xfer_len & fis_len are Dword counts */
295
296 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
297 pp->cmdslot[tag].prde_fis_len =
298 cpu_to_le32((num_prde << 16) | (fis_len << 2));
299 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
300 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
301
302 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
303 pp->cmdslot[tag].cda,
304 pp->cmdslot[tag].prde_fis_len,
305 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
306
307 }
308
309 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
310 u32 *ttl, dma_addr_t cmd_desc_paddr)
311 {
312 struct scatterlist *sg;
313 unsigned int num_prde = 0;
314 u32 ttl_dwords = 0;
315
316 /*
317 * NOTE : direct & indirect prdt's are contiguously allocated
318 */
319 struct prde *prd = (struct prde *)&((struct command_desc *)
320 cmd_desc)->prdt;
321
322 struct prde *prd_ptr_to_indirect_ext = NULL;
323 unsigned indirect_ext_segment_sz = 0;
324 dma_addr_t indirect_ext_segment_paddr;
325 unsigned int si;
326
327 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
328
329 indirect_ext_segment_paddr = cmd_desc_paddr +
330 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
331
332 for_each_sg(qc->sg, sg, qc->n_elem, si) {
333 dma_addr_t sg_addr = sg_dma_address(sg);
334 u32 sg_len = sg_dma_len(sg);
335
336 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
337 (unsigned long long)sg_addr, sg_len);
338
339 /* warn if each s/g element is not dword aligned */
340 if (sg_addr & 0x03)
341 ata_port_printk(qc->ap, KERN_ERR,
342 "s/g addr unaligned : 0x%llx\n",
343 (unsigned long long)sg_addr);
344 if (sg_len & 0x03)
345 ata_port_printk(qc->ap, KERN_ERR,
346 "s/g len unaligned : 0x%x\n", sg_len);
347
348 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
349 sg_next(sg) != NULL) {
350 VPRINTK("setting indirect prde\n");
351 prd_ptr_to_indirect_ext = prd;
352 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
353 indirect_ext_segment_sz = 0;
354 ++prd;
355 ++num_prde;
356 }
357
358 ttl_dwords += sg_len;
359 prd->dba = cpu_to_le32(sg_addr);
360 prd->ddc_and_ext =
361 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
362
363 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
364 ttl_dwords, prd->dba, prd->ddc_and_ext);
365
366 ++num_prde;
367 ++prd;
368 if (prd_ptr_to_indirect_ext)
369 indirect_ext_segment_sz += sg_len;
370 }
371
372 if (prd_ptr_to_indirect_ext) {
373 /* set indirect extension flag along with indirect ext. size */
374 prd_ptr_to_indirect_ext->ddc_and_ext =
375 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
376 DATA_SNOOP_ENABLE |
377 (indirect_ext_segment_sz & ~0x03)));
378 }
379
380 *ttl = ttl_dwords;
381 return num_prde;
382 }
383
384 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
385 {
386 struct ata_port *ap = qc->ap;
387 struct sata_fsl_port_priv *pp = ap->private_data;
388 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
389 void __iomem *hcr_base = host_priv->hcr_base;
390 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
391 struct command_desc *cd;
392 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
393 u32 num_prde = 0;
394 u32 ttl_dwords = 0;
395 dma_addr_t cd_paddr;
396
397 cd = (struct command_desc *)pp->cmdentry + tag;
398 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
399
400 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
401
402 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
403 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
404
405 if (qc->tf.protocol == ATA_PROT_NCQ) {
406 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
407 cd->cfis[3], cd->cfis[11]);
408 }
409
410 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
411 if (ata_is_atapi(qc->tf.protocol)) {
412 desc_info |= ATAPI_CMD;
413 memset((void *)&cd->acmd, 0, 32);
414 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
415 }
416
417 if (qc->flags & ATA_QCFLAG_DMAMAP)
418 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
419 &ttl_dwords, cd_paddr);
420
421 if (qc->tf.protocol == ATA_PROT_NCQ)
422 desc_info |= FPDMA_QUEUED_CMD;
423
424 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
425 num_prde, 5);
426
427 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
428 desc_info, ttl_dwords, num_prde);
429 }
430
431 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
432 {
433 struct ata_port *ap = qc->ap;
434 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
435 void __iomem *hcr_base = host_priv->hcr_base;
436 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
437
438 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
439 ioread32(CQ + hcr_base),
440 ioread32(CA + hcr_base),
441 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
442
443 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
444
445 /* Simply queue command to the controller/device */
446 iowrite32(1 << tag, CQ + hcr_base);
447
448 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
449 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
450
451 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
452 ioread32(CE + hcr_base),
453 ioread32(DE + hcr_base),
454 ioread32(CC + hcr_base),
455 ioread32(COMMANDSTAT + host_priv->csr_base));
456
457 return 0;
458 }
459
460 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
461 {
462 struct sata_fsl_port_priv *pp = qc->ap->private_data;
463 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
464 void __iomem *hcr_base = host_priv->hcr_base;
465 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
466 struct command_desc *cd;
467
468 cd = pp->cmdentry + tag;
469
470 ata_tf_from_fis(cd->sfis, &qc->result_tf);
471 return true;
472 }
473
474 static int sata_fsl_scr_write(struct ata_link *link,
475 unsigned int sc_reg_in, u32 val)
476 {
477 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
478 void __iomem *ssr_base = host_priv->ssr_base;
479 unsigned int sc_reg;
480
481 switch (sc_reg_in) {
482 case SCR_STATUS:
483 case SCR_ERROR:
484 case SCR_CONTROL:
485 case SCR_ACTIVE:
486 sc_reg = sc_reg_in;
487 break;
488 default:
489 return -EINVAL;
490 }
491
492 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
493
494 iowrite32(val, ssr_base + (sc_reg * 4));
495 return 0;
496 }
497
498 static int sata_fsl_scr_read(struct ata_link *link,
499 unsigned int sc_reg_in, u32 *val)
500 {
501 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
502 void __iomem *ssr_base = host_priv->ssr_base;
503 unsigned int sc_reg;
504
505 switch (sc_reg_in) {
506 case SCR_STATUS:
507 case SCR_ERROR:
508 case SCR_CONTROL:
509 case SCR_ACTIVE:
510 sc_reg = sc_reg_in;
511 break;
512 default:
513 return -EINVAL;
514 }
515
516 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
517
518 *val = ioread32(ssr_base + (sc_reg * 4));
519 return 0;
520 }
521
522 static void sata_fsl_freeze(struct ata_port *ap)
523 {
524 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
525 void __iomem *hcr_base = host_priv->hcr_base;
526 u32 temp;
527
528 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
529 ioread32(CQ + hcr_base),
530 ioread32(CA + hcr_base),
531 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
532 VPRINTK("CmdStat = 0x%x\n",
533 ioread32(host_priv->csr_base + COMMANDSTAT));
534
535 /* disable interrupts on the controller/port */
536 temp = ioread32(hcr_base + HCONTROL);
537 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
538
539 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
540 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
541 }
542
543 static void sata_fsl_thaw(struct ata_port *ap)
544 {
545 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
546 void __iomem *hcr_base = host_priv->hcr_base;
547 u32 temp;
548
549 /* ack. any pending IRQs for this controller/port */
550 temp = ioread32(hcr_base + HSTATUS);
551
552 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
553
554 if (temp & 0x3F)
555 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
556
557 /* enable interrupts on the controller/port */
558 temp = ioread32(hcr_base + HCONTROL);
559 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
560
561 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
562 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
563 }
564
565 static void sata_fsl_pmp_attach(struct ata_port *ap)
566 {
567 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
568 void __iomem *hcr_base = host_priv->hcr_base;
569 u32 temp;
570
571 temp = ioread32(hcr_base + HCONTROL);
572 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
573 }
574
575 static void sata_fsl_pmp_detach(struct ata_port *ap)
576 {
577 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
578 void __iomem *hcr_base = host_priv->hcr_base;
579 u32 temp;
580
581 temp = ioread32(hcr_base + HCONTROL);
582 temp &= ~HCONTROL_PMP_ATTACHED;
583 iowrite32(temp, hcr_base + HCONTROL);
584
585 /* enable interrupts on the controller/port */
586 temp = ioread32(hcr_base + HCONTROL);
587 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
588
589 }
590
591 static int sata_fsl_port_start(struct ata_port *ap)
592 {
593 struct device *dev = ap->host->dev;
594 struct sata_fsl_port_priv *pp;
595 void *mem;
596 dma_addr_t mem_dma;
597 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
598 void __iomem *hcr_base = host_priv->hcr_base;
599 u32 temp;
600
601 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
602 if (!pp)
603 return -ENOMEM;
604
605 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
606 GFP_KERNEL);
607 if (!mem) {
608 kfree(pp);
609 return -ENOMEM;
610 }
611 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
612
613 pp->cmdslot = mem;
614 pp->cmdslot_paddr = mem_dma;
615
616 mem += SATA_FSL_CMD_SLOT_SIZE;
617 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
618
619 pp->cmdentry = mem;
620 pp->cmdentry_paddr = mem_dma;
621
622 ap->private_data = pp;
623
624 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
625 pp->cmdslot_paddr, pp->cmdentry_paddr);
626
627 /* Now, update the CHBA register in host controller cmd register set */
628 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
629
630 /*
631 * Now, we can bring the controller on-line & also initiate
632 * the COMINIT sequence, we simply return here and the boot-probing
633 * & device discovery process is re-initiated by libATA using a
634 * Softreset EH (dummy) session. Hence, boot probing and device
635 * discovey will be part of sata_fsl_softreset() callback.
636 */
637
638 temp = ioread32(hcr_base + HCONTROL);
639 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
640
641 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
642 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
643 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
644
645 #ifdef CONFIG_MPC8315_DS
646 /*
647 * Workaround for 8315DS board 3gbps link-up issue,
648 * currently limit SATA port to GEN1 speed
649 */
650 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
651 temp &= ~(0xF << 4);
652 temp |= (0x1 << 4);
653 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
654
655 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
656 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
657 temp);
658 #endif
659
660 return 0;
661 }
662
663 static void sata_fsl_port_stop(struct ata_port *ap)
664 {
665 struct device *dev = ap->host->dev;
666 struct sata_fsl_port_priv *pp = ap->private_data;
667 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
668 void __iomem *hcr_base = host_priv->hcr_base;
669 u32 temp;
670
671 /*
672 * Force host controller to go off-line, aborting current operations
673 */
674 temp = ioread32(hcr_base + HCONTROL);
675 temp &= ~HCONTROL_ONLINE_PHY_RST;
676 temp |= HCONTROL_FORCE_OFFLINE;
677 iowrite32(temp, hcr_base + HCONTROL);
678
679 /* Poll for controller to go offline - should happen immediately */
680 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
681
682 ap->private_data = NULL;
683 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
684 pp->cmdslot, pp->cmdslot_paddr);
685
686 kfree(pp);
687 }
688
689 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
690 {
691 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
692 void __iomem *hcr_base = host_priv->hcr_base;
693 struct ata_taskfile tf;
694 u32 temp;
695
696 temp = ioread32(hcr_base + SIGNATURE);
697
698 VPRINTK("raw sig = 0x%x\n", temp);
699 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
700 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
701
702 tf.lbah = (temp >> 24) & 0xff;
703 tf.lbam = (temp >> 16) & 0xff;
704 tf.lbal = (temp >> 8) & 0xff;
705 tf.nsect = temp & 0xff;
706
707 return ata_dev_classify(&tf);
708 }
709
710 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
711 unsigned long deadline)
712 {
713 struct ata_port *ap = link->ap;
714 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
715 void __iomem *hcr_base = host_priv->hcr_base;
716 u32 temp;
717 int i = 0;
718 unsigned long start_jiffies;
719
720 DPRINTK("in xx_hardreset\n");
721
722 try_offline_again:
723 /*
724 * Force host controller to go off-line, aborting current operations
725 */
726 temp = ioread32(hcr_base + HCONTROL);
727 temp &= ~HCONTROL_ONLINE_PHY_RST;
728 iowrite32(temp, hcr_base + HCONTROL);
729
730 /* Poll for controller to go offline */
731 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
732
733 if (temp & ONLINE) {
734 ata_port_printk(ap, KERN_ERR,
735 "Hardreset failed, not off-lined %d\n", i);
736
737 /*
738 * Try to offline controller atleast twice
739 */
740 i++;
741 if (i == 2)
742 goto err;
743 else
744 goto try_offline_again;
745 }
746
747 DPRINTK("hardreset, controller off-lined\n");
748 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
749 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
750
751 /*
752 * PHY reset should remain asserted for atleast 1ms
753 */
754 msleep(1);
755
756 /*
757 * Now, bring the host controller online again, this can take time
758 * as PHY reset and communication establishment, 1st D2H FIS and
759 * device signature update is done, on safe side assume 500ms
760 * NOTE : Host online status may be indicated immediately!!
761 */
762
763 temp = ioread32(hcr_base + HCONTROL);
764 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
765 temp |= HCONTROL_PMP_ATTACHED;
766 iowrite32(temp, hcr_base + HCONTROL);
767
768 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
769
770 if (!(temp & ONLINE)) {
771 ata_port_printk(ap, KERN_ERR,
772 "Hardreset failed, not on-lined\n");
773 goto err;
774 }
775
776 DPRINTK("hardreset, controller off-lined & on-lined\n");
777 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
778 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
779
780 /*
781 * First, wait for the PHYRDY change to occur before waiting for
782 * the signature, and also verify if SStatus indicates device
783 * presence
784 */
785
786 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
787 if ((!(temp & 0x10)) || ata_link_offline(link)) {
788 ata_port_printk(ap, KERN_WARNING,
789 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
790 ioread32(hcr_base + HSTATUS));
791 *class = ATA_DEV_NONE;
792 return 0;
793 }
794
795 /*
796 * Wait for the first D2H from device,i.e,signature update notification
797 */
798 start_jiffies = jiffies;
799 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
800 500, jiffies_to_msecs(deadline - start_jiffies));
801
802 if ((temp & 0xFF) != 0x18) {
803 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
804 *class = ATA_DEV_NONE;
805 goto do_followup_srst;
806 } else {
807 ata_port_printk(ap, KERN_INFO,
808 "Signature Update detected @ %d msecs\n",
809 jiffies_to_msecs(jiffies - start_jiffies));
810 *class = sata_fsl_dev_classify(ap);
811 return 0;
812 }
813
814 do_followup_srst:
815 /*
816 * request libATA to perform follow-up softreset
817 */
818 return -EAGAIN;
819
820 err:
821 return -EIO;
822 }
823
824 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
825 unsigned long deadline)
826 {
827 struct ata_port *ap = link->ap;
828 struct sata_fsl_port_priv *pp = ap->private_data;
829 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
830 void __iomem *hcr_base = host_priv->hcr_base;
831 int pmp = sata_srst_pmp(link);
832 u32 temp;
833 struct ata_taskfile tf;
834 u8 *cfis;
835 u32 Serror;
836
837 DPRINTK("in xx_softreset\n");
838
839 if (ata_link_offline(link)) {
840 DPRINTK("PHY reports no device\n");
841 *class = ATA_DEV_NONE;
842 return 0;
843 }
844
845 /*
846 * Send a device reset (SRST) explicitly on command slot #0
847 * Check : will the command queue (reg) be cleared during offlining ??
848 * Also we will be online only if Phy commn. has been established
849 * and device presence has been detected, therefore if we have
850 * reached here, we can send a command to the target device
851 */
852
853 DPRINTK("Sending SRST/device reset\n");
854
855 ata_tf_init(link->device, &tf);
856 cfis = (u8 *) &pp->cmdentry->cfis;
857
858 /* device reset/SRST is a control register update FIS, uses tag0 */
859 sata_fsl_setup_cmd_hdr_entry(pp, 0,
860 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
861
862 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
863 ata_tf_to_fis(&tf, pmp, 0, cfis);
864
865 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
866 cfis[0], cfis[1], cfis[2], cfis[3]);
867
868 /*
869 * Queue SRST command to the controller/device, ensure that no
870 * other commands are active on the controller/device
871 */
872
873 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
874 ioread32(CQ + hcr_base),
875 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
876
877 iowrite32(0xFFFF, CC + hcr_base);
878 if (pmp != SATA_PMP_CTRL_PORT)
879 iowrite32(pmp, CQPMP + hcr_base);
880 iowrite32(1, CQ + hcr_base);
881
882 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
883 if (temp & 0x1) {
884 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
885
886 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
887 ioread32(CQ + hcr_base),
888 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
889
890 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
891
892 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
893 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
894 DPRINTK("Serror = 0x%x\n", Serror);
895 goto err;
896 }
897
898 msleep(1);
899
900 /*
901 * SATA device enters reset state after receving a Control register
902 * FIS with SRST bit asserted and it awaits another H2D Control reg.
903 * FIS with SRST bit cleared, then the device does internal diags &
904 * initialization, followed by indicating it's initialization status
905 * using ATA signature D2H register FIS to the host controller.
906 */
907
908 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
909 0, 0, 5);
910
911 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
912 ata_tf_to_fis(&tf, pmp, 0, cfis);
913
914 if (pmp != SATA_PMP_CTRL_PORT)
915 iowrite32(pmp, CQPMP + hcr_base);
916 iowrite32(1, CQ + hcr_base);
917 msleep(150); /* ?? */
918
919 /*
920 * The above command would have signalled an interrupt on command
921 * complete, which needs special handling, by clearing the Nth
922 * command bit of the CCreg
923 */
924 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
925
926 DPRINTK("SATA FSL : Now checking device signature\n");
927
928 *class = ATA_DEV_NONE;
929
930 /* Verify if SStatus indicates device presence */
931 if (ata_link_online(link)) {
932 /*
933 * if we are here, device presence has been detected,
934 * 1st D2H FIS would have been received, but sfis in
935 * command desc. is not updated, but signature register
936 * would have been updated
937 */
938
939 *class = sata_fsl_dev_classify(ap);
940
941 DPRINTK("class = %d\n", *class);
942 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
943 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
944 }
945
946 return 0;
947
948 err:
949 return -EIO;
950 }
951
952 static void sata_fsl_error_handler(struct ata_port *ap)
953 {
954
955 DPRINTK("in xx_error_handler\n");
956 sata_pmp_error_handler(ap);
957
958 }
959
960 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
961 {
962 if (qc->flags & ATA_QCFLAG_FAILED)
963 qc->err_mask |= AC_ERR_OTHER;
964
965 if (qc->err_mask) {
966 /* make DMA engine forget about the failed command */
967
968 }
969 }
970
971 static void sata_fsl_error_intr(struct ata_port *ap)
972 {
973 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
974 void __iomem *hcr_base = host_priv->hcr_base;
975 u32 hstatus, dereg=0, cereg = 0, SError = 0;
976 unsigned int err_mask = 0, action = 0;
977 int freeze = 0, abort=0;
978 struct ata_link *link = NULL;
979 struct ata_queued_cmd *qc = NULL;
980 struct ata_eh_info *ehi;
981
982 hstatus = ioread32(hcr_base + HSTATUS);
983 cereg = ioread32(hcr_base + CE);
984
985 /* first, analyze and record host port events */
986 link = &ap->link;
987 ehi = &link->eh_info;
988 ata_ehi_clear_desc(ehi);
989
990 /*
991 * Handle & Clear SError
992 */
993
994 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
995 if (unlikely(SError & 0xFFFF0000))
996 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
997
998 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
999 hstatus, cereg, ioread32(hcr_base + DE), SError);
1000
1001 /* handle fatal errors */
1002 if (hstatus & FATAL_ERROR_DECODE) {
1003 ehi->err_mask |= AC_ERR_ATA_BUS;
1004 ehi->action |= ATA_EH_SOFTRESET;
1005
1006 freeze = 1;
1007 }
1008
1009 /* Handle SDB FIS receive & notify update */
1010 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1011 sata_async_notification(ap);
1012
1013 /* Handle PHYRDY change notification */
1014 if (hstatus & INT_ON_PHYRDY_CHG) {
1015 DPRINTK("SATA FSL: PHYRDY change indication\n");
1016
1017 /* Setup a soft-reset EH action */
1018 ata_ehi_hotplugged(ehi);
1019 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1020 freeze = 1;
1021 }
1022
1023 /* handle single device errors */
1024 if (cereg) {
1025 /*
1026 * clear the command error, also clears queue to the device
1027 * in error, and we can (re)issue commands to this device.
1028 * When a device is in error all commands queued into the
1029 * host controller and at the device are considered aborted
1030 * and the queue for that device is stopped. Now, after
1031 * clearing the device error, we can issue commands to the
1032 * device to interrogate it to find the source of the error.
1033 */
1034 abort = 1;
1035
1036 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1037 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1038
1039 /* find out the offending link and qc */
1040 if (ap->nr_pmp_links) {
1041 dereg = ioread32(hcr_base + DE);
1042 iowrite32(dereg, hcr_base + DE);
1043 iowrite32(cereg, hcr_base + CE);
1044
1045 if (dereg < ap->nr_pmp_links) {
1046 link = &ap->pmp_link[dereg];
1047 ehi = &link->eh_info;
1048 qc = ata_qc_from_tag(ap, link->active_tag);
1049 /*
1050 * We should consider this as non fatal error,
1051 * and TF must be updated as done below.
1052 */
1053
1054 err_mask |= AC_ERR_DEV;
1055
1056 } else {
1057 err_mask |= AC_ERR_HSM;
1058 action |= ATA_EH_HARDRESET;
1059 freeze = 1;
1060 }
1061 } else {
1062 dereg = ioread32(hcr_base + DE);
1063 iowrite32(dereg, hcr_base + DE);
1064 iowrite32(cereg, hcr_base + CE);
1065
1066 qc = ata_qc_from_tag(ap, link->active_tag);
1067 /*
1068 * We should consider this as non fatal error,
1069 * and TF must be updated as done below.
1070 */
1071 err_mask |= AC_ERR_DEV;
1072 }
1073 }
1074
1075 /* record error info */
1076 if (qc)
1077 qc->err_mask |= err_mask;
1078 else
1079 ehi->err_mask |= err_mask;
1080
1081 ehi->action |= action;
1082
1083 /* freeze or abort */
1084 if (freeze)
1085 ata_port_freeze(ap);
1086 else if (abort) {
1087 if (qc)
1088 ata_link_abort(qc->dev->link);
1089 else
1090 ata_port_abort(ap);
1091 }
1092 }
1093
1094 static void sata_fsl_host_intr(struct ata_port *ap)
1095 {
1096 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1097 void __iomem *hcr_base = host_priv->hcr_base;
1098 u32 hstatus, qc_active = 0;
1099 struct ata_queued_cmd *qc;
1100 u32 SError;
1101
1102 hstatus = ioread32(hcr_base + HSTATUS);
1103
1104 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1105
1106 if (unlikely(SError & 0xFFFF0000)) {
1107 DPRINTK("serror @host_intr : 0x%x\n", SError);
1108 sata_fsl_error_intr(ap);
1109 }
1110
1111 if (unlikely(hstatus & INT_ON_ERROR)) {
1112 DPRINTK("error interrupt!!\n");
1113 sata_fsl_error_intr(ap);
1114 return;
1115 }
1116
1117 /* Read command completed register */
1118 qc_active = ioread32(hcr_base + CC);
1119
1120 VPRINTK("Status of all queues :\n");
1121 VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1122 qc_active,
1123 ioread32(hcr_base + CA),
1124 ioread32(hcr_base + CE),
1125 ioread32(hcr_base + CQ),
1126 ap->qc_active);
1127
1128 if (qc_active & ap->qc_active) {
1129 int i;
1130 /* clear CC bit, this will also complete the interrupt */
1131 iowrite32(qc_active, hcr_base + CC);
1132
1133 DPRINTK("Status of all queues :\n");
1134 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1135 qc_active, ioread32(hcr_base + CA),
1136 ioread32(hcr_base + CE));
1137
1138 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1139 if (qc_active & (1 << i)) {
1140 qc = ata_qc_from_tag(ap, i);
1141 if (qc) {
1142 ata_qc_complete(qc);
1143 }
1144 DPRINTK
1145 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1146 i, ioread32(hcr_base + CC),
1147 ioread32(hcr_base + CA));
1148 }
1149 }
1150 return;
1151
1152 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1153 iowrite32(1, hcr_base + CC);
1154 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1155
1156 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1157 ioread32(hcr_base + CC));
1158
1159 if (qc) {
1160 ata_qc_complete(qc);
1161 }
1162 } else {
1163 /* Spurious Interrupt!! */
1164 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1165 ioread32(hcr_base + CC));
1166 iowrite32(qc_active, hcr_base + CC);
1167 return;
1168 }
1169 }
1170
1171 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1172 {
1173 struct ata_host *host = dev_instance;
1174 struct sata_fsl_host_priv *host_priv = host->private_data;
1175 void __iomem *hcr_base = host_priv->hcr_base;
1176 u32 interrupt_enables;
1177 unsigned handled = 0;
1178 struct ata_port *ap;
1179
1180 /* ack. any pending IRQs for this controller/port */
1181 interrupt_enables = ioread32(hcr_base + HSTATUS);
1182 interrupt_enables &= 0x3F;
1183
1184 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1185
1186 if (!interrupt_enables)
1187 return IRQ_NONE;
1188
1189 spin_lock(&host->lock);
1190
1191 /* Assuming one port per host controller */
1192
1193 ap = host->ports[0];
1194 if (ap) {
1195 sata_fsl_host_intr(ap);
1196 } else {
1197 dev_printk(KERN_WARNING, host->dev,
1198 "interrupt on disabled port 0\n");
1199 }
1200
1201 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1202 handled = 1;
1203
1204 spin_unlock(&host->lock);
1205
1206 return IRQ_RETVAL(handled);
1207 }
1208
1209 /*
1210 * Multiple ports are represented by multiple SATA controllers with
1211 * one port per controller
1212 */
1213 static int sata_fsl_init_controller(struct ata_host *host)
1214 {
1215 struct sata_fsl_host_priv *host_priv = host->private_data;
1216 void __iomem *hcr_base = host_priv->hcr_base;
1217 u32 temp;
1218
1219 /*
1220 * NOTE : We cannot bring the controller online before setting
1221 * the CHBA, hence main controller initialization is done as
1222 * part of the port_start() callback
1223 */
1224
1225 /* ack. any pending IRQs for this controller/port */
1226 temp = ioread32(hcr_base + HSTATUS);
1227 if (temp & 0x3F)
1228 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1229
1230 /* Keep interrupts disabled on the controller */
1231 temp = ioread32(hcr_base + HCONTROL);
1232 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1233
1234 /* Disable interrupt coalescing control(icc), for the moment */
1235 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1236 iowrite32(0x01000000, hcr_base + ICC);
1237
1238 /* clear error registers, SError is cleared by libATA */
1239 iowrite32(0x00000FFFF, hcr_base + CE);
1240 iowrite32(0x00000FFFF, hcr_base + DE);
1241
1242 /*
1243 * host controller will be brought on-line, during xx_port_start()
1244 * callback, that should also initiate the OOB, COMINIT sequence
1245 */
1246
1247 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1248 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1249
1250 return 0;
1251 }
1252
1253 /*
1254 * scsi mid-layer and libata interface structures
1255 */
1256 static struct scsi_host_template sata_fsl_sht = {
1257 ATA_NCQ_SHT("sata_fsl"),
1258 .can_queue = SATA_FSL_QUEUE_DEPTH,
1259 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1260 .dma_boundary = ATA_DMA_BOUNDARY,
1261 };
1262
1263 static struct ata_port_operations sata_fsl_ops = {
1264 .inherits = &sata_pmp_port_ops,
1265
1266 .qc_defer = ata_std_qc_defer,
1267 .qc_prep = sata_fsl_qc_prep,
1268 .qc_issue = sata_fsl_qc_issue,
1269 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1270
1271 .scr_read = sata_fsl_scr_read,
1272 .scr_write = sata_fsl_scr_write,
1273
1274 .freeze = sata_fsl_freeze,
1275 .thaw = sata_fsl_thaw,
1276 .softreset = sata_fsl_softreset,
1277 .hardreset = sata_fsl_hardreset,
1278 .pmp_softreset = sata_fsl_softreset,
1279 .error_handler = sata_fsl_error_handler,
1280 .post_internal_cmd = sata_fsl_post_internal_cmd,
1281
1282 .port_start = sata_fsl_port_start,
1283 .port_stop = sata_fsl_port_stop,
1284
1285 .pmp_attach = sata_fsl_pmp_attach,
1286 .pmp_detach = sata_fsl_pmp_detach,
1287 };
1288
1289 static const struct ata_port_info sata_fsl_port_info[] = {
1290 {
1291 .flags = SATA_FSL_HOST_FLAGS,
1292 .pio_mask = ATA_PIO4,
1293 .udma_mask = ATA_UDMA6,
1294 .port_ops = &sata_fsl_ops,
1295 },
1296 };
1297
1298 static int sata_fsl_probe(struct of_device *ofdev,
1299 const struct of_device_id *match)
1300 {
1301 int retval = -ENXIO;
1302 void __iomem *hcr_base = NULL;
1303 void __iomem *ssr_base = NULL;
1304 void __iomem *csr_base = NULL;
1305 struct sata_fsl_host_priv *host_priv = NULL;
1306 int irq;
1307 struct ata_host *host;
1308
1309 struct ata_port_info pi = sata_fsl_port_info[0];
1310 const struct ata_port_info *ppi[] = { &pi, NULL };
1311
1312 dev_printk(KERN_INFO, &ofdev->dev,
1313 "Sata FSL Platform/CSB Driver init\n");
1314
1315 hcr_base = of_iomap(ofdev->node, 0);
1316 if (!hcr_base)
1317 goto error_exit_with_cleanup;
1318
1319 ssr_base = hcr_base + 0x100;
1320 csr_base = hcr_base + 0x140;
1321
1322 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1323 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1324 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1325
1326 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1327 if (!host_priv)
1328 goto error_exit_with_cleanup;
1329
1330 host_priv->hcr_base = hcr_base;
1331 host_priv->ssr_base = ssr_base;
1332 host_priv->csr_base = csr_base;
1333
1334 irq = irq_of_parse_and_map(ofdev->node, 0);
1335 if (irq < 0) {
1336 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1337 goto error_exit_with_cleanup;
1338 }
1339 host_priv->irq = irq;
1340
1341 /* allocate host structure */
1342 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1343
1344 /* host->iomap is not used currently */
1345 host->private_data = host_priv;
1346
1347 /* initialize host controller */
1348 sata_fsl_init_controller(host);
1349
1350 /*
1351 * Now, register with libATA core, this will also initiate the
1352 * device discovery process, invoking our port_start() handler &
1353 * error_handler() to execute a dummy Softreset EH session
1354 */
1355 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1356 &sata_fsl_sht);
1357
1358 dev_set_drvdata(&ofdev->dev, host);
1359
1360 return 0;
1361
1362 error_exit_with_cleanup:
1363
1364 if (hcr_base)
1365 iounmap(hcr_base);
1366 if (host_priv)
1367 kfree(host_priv);
1368
1369 return retval;
1370 }
1371
1372 static int sata_fsl_remove(struct of_device *ofdev)
1373 {
1374 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1375 struct sata_fsl_host_priv *host_priv = host->private_data;
1376
1377 ata_host_detach(host);
1378
1379 dev_set_drvdata(&ofdev->dev, NULL);
1380
1381 irq_dispose_mapping(host_priv->irq);
1382 iounmap(host_priv->hcr_base);
1383 kfree(host_priv);
1384
1385 return 0;
1386 }
1387
1388 #ifdef CONFIG_PM
1389 static int sata_fsl_suspend(struct of_device *op, pm_message_t state)
1390 {
1391 struct ata_host *host = dev_get_drvdata(&op->dev);
1392 return ata_host_suspend(host, state);
1393 }
1394
1395 static int sata_fsl_resume(struct of_device *op)
1396 {
1397 struct ata_host *host = dev_get_drvdata(&op->dev);
1398 struct sata_fsl_host_priv *host_priv = host->private_data;
1399 int ret;
1400 void __iomem *hcr_base = host_priv->hcr_base;
1401 struct ata_port *ap = host->ports[0];
1402 struct sata_fsl_port_priv *pp = ap->private_data;
1403
1404 ret = sata_fsl_init_controller(host);
1405 if (ret) {
1406 dev_printk(KERN_ERR, &op->dev,
1407 "Error initialize hardware\n");
1408 return ret;
1409 }
1410
1411 /* Recovery the CHBA register in host controller cmd register set */
1412 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1413
1414 ata_host_resume(host);
1415 return 0;
1416 }
1417 #endif
1418
1419 static struct of_device_id fsl_sata_match[] = {
1420 {
1421 .compatible = "fsl,pq-sata",
1422 },
1423 {},
1424 };
1425
1426 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1427
1428 static struct of_platform_driver fsl_sata_driver = {
1429 .name = "fsl-sata",
1430 .match_table = fsl_sata_match,
1431 .probe = sata_fsl_probe,
1432 .remove = sata_fsl_remove,
1433 #ifdef CONFIG_PM
1434 .suspend = sata_fsl_suspend,
1435 .resume = sata_fsl_resume,
1436 #endif
1437 };
1438
1439 static int __init sata_fsl_init(void)
1440 {
1441 of_register_platform_driver(&fsl_sata_driver);
1442 return 0;
1443 }
1444
1445 static void __exit sata_fsl_exit(void)
1446 {
1447 of_unregister_platform_driver(&fsl_sata_driver);
1448 }
1449
1450 MODULE_LICENSE("GPL");
1451 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1452 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1453 MODULE_VERSION("1.10");
1454
1455 module_init(sata_fsl_init);
1456 module_exit(sata_fsl_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree