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bnx2: Fix register test on 5709.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / bnx2.c
blob0fcea85907779a908b64dcc01540f7bb84efe0a7
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2008 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50
51 #include "bnx2.h"
52 #include "bnx2_fw.h"
53 #include "bnx2_fw2.h"
54
55 #define FW_BUF_SIZE 0x10000
56
57 #define DRV_MODULE_NAME "bnx2"
58 #define PFX DRV_MODULE_NAME ": "
59 #define DRV_MODULE_VERSION "1.7.4"
60 #define DRV_MODULE_RELDATE "February 18, 2008"
61
62 #define RUN_AT(x) (jiffies + (x))
63
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (5*HZ)
66
67 static char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
74
75 static int disable_msi = 0;
76
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80 typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
86 BCM5708,
87 BCM5708S,
88 BCM5709,
89 BCM5709S,
90 } board_t;
91
92 /* indexed by board_t, above */
93 static struct {
94 char *name;
95 } board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
105 };
106
107 static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
126 { 0, }
127 };
128
129 static struct flash_spec flash_table[] =
130 {
131 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
133 /* Slow EEPROM */
134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137 "EEPROM - slow"},
138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142 "Entry 0001"},
143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0100"},
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
176 /* Fast EEPROM */
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180 "EEPROM - fast"},
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185 "Entry 1001"},
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1010"},
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1100"},
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1101"},
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
216 };
217
218 static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
225 };
226
227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
229 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
230 {
231 u32 diff;
232
233 smp_mb();
234
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
237 */
238 diff = bp->tx_prod - bnapi->tx_cons;
239 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff;
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
243 }
244 return (bp->tx_ring_size - diff);
245 }
246
247 static u32
248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249 {
250 u32 val;
251
252 spin_lock_bh(&bp->indirect_lock);
253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
256 return val;
257 }
258
259 static void
260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261 {
262 spin_lock_bh(&bp->indirect_lock);
263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
265 spin_unlock_bh(&bp->indirect_lock);
266 }
267
268 static void
269 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
270 {
271 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
272 }
273
274 static u32
275 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
276 {
277 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
278 }
279
280 static void
281 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
282 {
283 offset += cid_addr;
284 spin_lock_bh(&bp->indirect_lock);
285 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
286 int i;
287
288 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
289 REG_WR(bp, BNX2_CTX_CTX_CTRL,
290 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
291 for (i = 0; i < 5; i++) {
292 u32 val;
293 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
294 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
295 break;
296 udelay(5);
297 }
298 } else {
299 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
300 REG_WR(bp, BNX2_CTX_DATA, val);
301 }
302 spin_unlock_bh(&bp->indirect_lock);
303 }
304
305 static int
306 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
307 {
308 u32 val1;
309 int i, ret;
310
311 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
312 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
313 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
314
315 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
316 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317
318 udelay(40);
319 }
320
321 val1 = (bp->phy_addr << 21) | (reg << 16) |
322 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
323 BNX2_EMAC_MDIO_COMM_START_BUSY;
324 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
325
326 for (i = 0; i < 50; i++) {
327 udelay(10);
328
329 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
330 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
331 udelay(5);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
335
336 break;
337 }
338 }
339
340 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
341 *val = 0x0;
342 ret = -EBUSY;
343 }
344 else {
345 *val = val1;
346 ret = 0;
347 }
348
349 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
350 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
352
353 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
354 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355
356 udelay(40);
357 }
358
359 return ret;
360 }
361
362 static int
363 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
364 {
365 u32 val1;
366 int i, ret;
367
368 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
369 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
370 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
371
372 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
373 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374
375 udelay(40);
376 }
377
378 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
379 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
380 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
381 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
382
383 for (i = 0; i < 50; i++) {
384 udelay(10);
385
386 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
387 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
388 udelay(5);
389 break;
390 }
391 }
392
393 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
394 ret = -EBUSY;
395 else
396 ret = 0;
397
398 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
401
402 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
403 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404
405 udelay(40);
406 }
407
408 return ret;
409 }
410
411 static void
412 bnx2_disable_int(struct bnx2 *bp)
413 {
414 int i;
415 struct bnx2_napi *bnapi;
416
417 for (i = 0; i < bp->irq_nvecs; i++) {
418 bnapi = &bp->bnx2_napi[i];
419 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
420 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
421 }
422 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
423 }
424
425 static void
426 bnx2_enable_int(struct bnx2 *bp)
427 {
428 int i;
429 struct bnx2_napi *bnapi;
430
431 for (i = 0; i < bp->irq_nvecs; i++) {
432 bnapi = &bp->bnx2_napi[i];
433
434 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
435 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
436 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
437 bnapi->last_status_idx);
438
439 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
440 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
441 bnapi->last_status_idx);
442 }
443 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
444 }
445
446 static void
447 bnx2_disable_int_sync(struct bnx2 *bp)
448 {
449 int i;
450
451 atomic_inc(&bp->intr_sem);
452 bnx2_disable_int(bp);
453 for (i = 0; i < bp->irq_nvecs; i++)
454 synchronize_irq(bp->irq_tbl[i].vector);
455 }
456
457 static void
458 bnx2_napi_disable(struct bnx2 *bp)
459 {
460 int i;
461
462 for (i = 0; i < bp->irq_nvecs; i++)
463 napi_disable(&bp->bnx2_napi[i].napi);
464 }
465
466 static void
467 bnx2_napi_enable(struct bnx2 *bp)
468 {
469 int i;
470
471 for (i = 0; i < bp->irq_nvecs; i++)
472 napi_enable(&bp->bnx2_napi[i].napi);
473 }
474
475 static void
476 bnx2_netif_stop(struct bnx2 *bp)
477 {
478 bnx2_disable_int_sync(bp);
479 if (netif_running(bp->dev)) {
480 bnx2_napi_disable(bp);
481 netif_tx_disable(bp->dev);
482 bp->dev->trans_start = jiffies; /* prevent tx timeout */
483 }
484 }
485
486 static void
487 bnx2_netif_start(struct bnx2 *bp)
488 {
489 if (atomic_dec_and_test(&bp->intr_sem)) {
490 if (netif_running(bp->dev)) {
491 netif_wake_queue(bp->dev);
492 bnx2_napi_enable(bp);
493 bnx2_enable_int(bp);
494 }
495 }
496 }
497
498 static void
499 bnx2_free_mem(struct bnx2 *bp)
500 {
501 int i;
502
503 for (i = 0; i < bp->ctx_pages; i++) {
504 if (bp->ctx_blk[i]) {
505 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
506 bp->ctx_blk[i],
507 bp->ctx_blk_mapping[i]);
508 bp->ctx_blk[i] = NULL;
509 }
510 }
511 if (bp->status_blk) {
512 pci_free_consistent(bp->pdev, bp->status_stats_size,
513 bp->status_blk, bp->status_blk_mapping);
514 bp->status_blk = NULL;
515 bp->stats_blk = NULL;
516 }
517 if (bp->tx_desc_ring) {
518 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
519 bp->tx_desc_ring, bp->tx_desc_mapping);
520 bp->tx_desc_ring = NULL;
521 }
522 kfree(bp->tx_buf_ring);
523 bp->tx_buf_ring = NULL;
524 for (i = 0; i < bp->rx_max_ring; i++) {
525 if (bp->rx_desc_ring[i])
526 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
527 bp->rx_desc_ring[i],
528 bp->rx_desc_mapping[i]);
529 bp->rx_desc_ring[i] = NULL;
530 }
531 vfree(bp->rx_buf_ring);
532 bp->rx_buf_ring = NULL;
533 for (i = 0; i < bp->rx_max_pg_ring; i++) {
534 if (bp->rx_pg_desc_ring[i])
535 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
536 bp->rx_pg_desc_ring[i],
537 bp->rx_pg_desc_mapping[i]);
538 bp->rx_pg_desc_ring[i] = NULL;
539 }
540 if (bp->rx_pg_ring)
541 vfree(bp->rx_pg_ring);
542 bp->rx_pg_ring = NULL;
543 }
544
545 static int
546 bnx2_alloc_mem(struct bnx2 *bp)
547 {
548 int i, status_blk_size;
549
550 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
551 if (bp->tx_buf_ring == NULL)
552 return -ENOMEM;
553
554 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
555 &bp->tx_desc_mapping);
556 if (bp->tx_desc_ring == NULL)
557 goto alloc_mem_err;
558
559 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
560 if (bp->rx_buf_ring == NULL)
561 goto alloc_mem_err;
562
563 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
564
565 for (i = 0; i < bp->rx_max_ring; i++) {
566 bp->rx_desc_ring[i] =
567 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
568 &bp->rx_desc_mapping[i]);
569 if (bp->rx_desc_ring[i] == NULL)
570 goto alloc_mem_err;
571
572 }
573
574 if (bp->rx_pg_ring_size) {
575 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
576 bp->rx_max_pg_ring);
577 if (bp->rx_pg_ring == NULL)
578 goto alloc_mem_err;
579
580 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
581 bp->rx_max_pg_ring);
582 }
583
584 for (i = 0; i < bp->rx_max_pg_ring; i++) {
585 bp->rx_pg_desc_ring[i] =
586 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
587 &bp->rx_pg_desc_mapping[i]);
588 if (bp->rx_pg_desc_ring[i] == NULL)
589 goto alloc_mem_err;
590
591 }
592
593 /* Combine status and statistics blocks into one allocation. */
594 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
595 if (bp->flags & BNX2_FLAG_MSIX_CAP)
596 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
597 BNX2_SBLK_MSIX_ALIGN_SIZE);
598 bp->status_stats_size = status_blk_size +
599 sizeof(struct statistics_block);
600
601 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
602 &bp->status_blk_mapping);
603 if (bp->status_blk == NULL)
604 goto alloc_mem_err;
605
606 memset(bp->status_blk, 0, bp->status_stats_size);
607
608 bp->bnx2_napi[0].status_blk = bp->status_blk;
609 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
610 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
611 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
612
613 bnapi->status_blk_msix = (void *)
614 ((unsigned long) bp->status_blk +
615 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
616 bnapi->int_num = i << 24;
617 }
618 }
619
620 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
621 status_blk_size);
622
623 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
624
625 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
626 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
627 if (bp->ctx_pages == 0)
628 bp->ctx_pages = 1;
629 for (i = 0; i < bp->ctx_pages; i++) {
630 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
631 BCM_PAGE_SIZE,
632 &bp->ctx_blk_mapping[i]);
633 if (bp->ctx_blk[i] == NULL)
634 goto alloc_mem_err;
635 }
636 }
637 return 0;
638
639 alloc_mem_err:
640 bnx2_free_mem(bp);
641 return -ENOMEM;
642 }
643
644 static void
645 bnx2_report_fw_link(struct bnx2 *bp)
646 {
647 u32 fw_link_status = 0;
648
649 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
650 return;
651
652 if (bp->link_up) {
653 u32 bmsr;
654
655 switch (bp->line_speed) {
656 case SPEED_10:
657 if (bp->duplex == DUPLEX_HALF)
658 fw_link_status = BNX2_LINK_STATUS_10HALF;
659 else
660 fw_link_status = BNX2_LINK_STATUS_10FULL;
661 break;
662 case SPEED_100:
663 if (bp->duplex == DUPLEX_HALF)
664 fw_link_status = BNX2_LINK_STATUS_100HALF;
665 else
666 fw_link_status = BNX2_LINK_STATUS_100FULL;
667 break;
668 case SPEED_1000:
669 if (bp->duplex == DUPLEX_HALF)
670 fw_link_status = BNX2_LINK_STATUS_1000HALF;
671 else
672 fw_link_status = BNX2_LINK_STATUS_1000FULL;
673 break;
674 case SPEED_2500:
675 if (bp->duplex == DUPLEX_HALF)
676 fw_link_status = BNX2_LINK_STATUS_2500HALF;
677 else
678 fw_link_status = BNX2_LINK_STATUS_2500FULL;
679 break;
680 }
681
682 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
683
684 if (bp->autoneg) {
685 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
686
687 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
688 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
689
690 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
691 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
692 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
693 else
694 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
695 }
696 }
697 else
698 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
699
700 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
701 }
702
703 static char *
704 bnx2_xceiver_str(struct bnx2 *bp)
705 {
706 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
707 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
708 "Copper"));
709 }
710
711 static void
712 bnx2_report_link(struct bnx2 *bp)
713 {
714 if (bp->link_up) {
715 netif_carrier_on(bp->dev);
716 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
717 bnx2_xceiver_str(bp));
718
719 printk("%d Mbps ", bp->line_speed);
720
721 if (bp->duplex == DUPLEX_FULL)
722 printk("full duplex");
723 else
724 printk("half duplex");
725
726 if (bp->flow_ctrl) {
727 if (bp->flow_ctrl & FLOW_CTRL_RX) {
728 printk(", receive ");
729 if (bp->flow_ctrl & FLOW_CTRL_TX)
730 printk("& transmit ");
731 }
732 else {
733 printk(", transmit ");
734 }
735 printk("flow control ON");
736 }
737 printk("\n");
738 }
739 else {
740 netif_carrier_off(bp->dev);
741 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
742 bnx2_xceiver_str(bp));
743 }
744
745 bnx2_report_fw_link(bp);
746 }
747
748 static void
749 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
750 {
751 u32 local_adv, remote_adv;
752
753 bp->flow_ctrl = 0;
754 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
755 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
756
757 if (bp->duplex == DUPLEX_FULL) {
758 bp->flow_ctrl = bp->req_flow_ctrl;
759 }
760 return;
761 }
762
763 if (bp->duplex != DUPLEX_FULL) {
764 return;
765 }
766
767 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
768 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
769 u32 val;
770
771 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
772 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
773 bp->flow_ctrl |= FLOW_CTRL_TX;
774 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
775 bp->flow_ctrl |= FLOW_CTRL_RX;
776 return;
777 }
778
779 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
780 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
781
782 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
783 u32 new_local_adv = 0;
784 u32 new_remote_adv = 0;
785
786 if (local_adv & ADVERTISE_1000XPAUSE)
787 new_local_adv |= ADVERTISE_PAUSE_CAP;
788 if (local_adv & ADVERTISE_1000XPSE_ASYM)
789 new_local_adv |= ADVERTISE_PAUSE_ASYM;
790 if (remote_adv & ADVERTISE_1000XPAUSE)
791 new_remote_adv |= ADVERTISE_PAUSE_CAP;
792 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
793 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
794
795 local_adv = new_local_adv;
796 remote_adv = new_remote_adv;
797 }
798
799 /* See Table 28B-3 of 802.3ab-1999 spec. */
800 if (local_adv & ADVERTISE_PAUSE_CAP) {
801 if(local_adv & ADVERTISE_PAUSE_ASYM) {
802 if (remote_adv & ADVERTISE_PAUSE_CAP) {
803 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
804 }
805 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
806 bp->flow_ctrl = FLOW_CTRL_RX;
807 }
808 }
809 else {
810 if (remote_adv & ADVERTISE_PAUSE_CAP) {
811 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
812 }
813 }
814 }
815 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
816 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
817 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
818
819 bp->flow_ctrl = FLOW_CTRL_TX;
820 }
821 }
822 }
823
824 static int
825 bnx2_5709s_linkup(struct bnx2 *bp)
826 {
827 u32 val, speed;
828
829 bp->link_up = 1;
830
831 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
832 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
833 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
834
835 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
836 bp->line_speed = bp->req_line_speed;
837 bp->duplex = bp->req_duplex;
838 return 0;
839 }
840 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
841 switch (speed) {
842 case MII_BNX2_GP_TOP_AN_SPEED_10:
843 bp->line_speed = SPEED_10;
844 break;
845 case MII_BNX2_GP_TOP_AN_SPEED_100:
846 bp->line_speed = SPEED_100;
847 break;
848 case MII_BNX2_GP_TOP_AN_SPEED_1G:
849 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
850 bp->line_speed = SPEED_1000;
851 break;
852 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
853 bp->line_speed = SPEED_2500;
854 break;
855 }
856 if (val & MII_BNX2_GP_TOP_AN_FD)
857 bp->duplex = DUPLEX_FULL;
858 else
859 bp->duplex = DUPLEX_HALF;
860 return 0;
861 }
862
863 static int
864 bnx2_5708s_linkup(struct bnx2 *bp)
865 {
866 u32 val;
867
868 bp->link_up = 1;
869 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
870 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
871 case BCM5708S_1000X_STAT1_SPEED_10:
872 bp->line_speed = SPEED_10;
873 break;
874 case BCM5708S_1000X_STAT1_SPEED_100:
875 bp->line_speed = SPEED_100;
876 break;
877 case BCM5708S_1000X_STAT1_SPEED_1G:
878 bp->line_speed = SPEED_1000;
879 break;
880 case BCM5708S_1000X_STAT1_SPEED_2G5:
881 bp->line_speed = SPEED_2500;
882 break;
883 }
884 if (val & BCM5708S_1000X_STAT1_FD)
885 bp->duplex = DUPLEX_FULL;
886 else
887 bp->duplex = DUPLEX_HALF;
888
889 return 0;
890 }
891
892 static int
893 bnx2_5706s_linkup(struct bnx2 *bp)
894 {
895 u32 bmcr, local_adv, remote_adv, common;
896
897 bp->link_up = 1;
898 bp->line_speed = SPEED_1000;
899
900 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
901 if (bmcr & BMCR_FULLDPLX) {
902 bp->duplex = DUPLEX_FULL;
903 }
904 else {
905 bp->duplex = DUPLEX_HALF;
906 }
907
908 if (!(bmcr & BMCR_ANENABLE)) {
909 return 0;
910 }
911
912 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
913 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
914
915 common = local_adv & remote_adv;
916 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
917
918 if (common & ADVERTISE_1000XFULL) {
919 bp->duplex = DUPLEX_FULL;
920 }
921 else {
922 bp->duplex = DUPLEX_HALF;
923 }
924 }
925
926 return 0;
927 }
928
929 static int
930 bnx2_copper_linkup(struct bnx2 *bp)
931 {
932 u32 bmcr;
933
934 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
935 if (bmcr & BMCR_ANENABLE) {
936 u32 local_adv, remote_adv, common;
937
938 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
939 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
940
941 common = local_adv & (remote_adv >> 2);
942 if (common & ADVERTISE_1000FULL) {
943 bp->line_speed = SPEED_1000;
944 bp->duplex = DUPLEX_FULL;
945 }
946 else if (common & ADVERTISE_1000HALF) {
947 bp->line_speed = SPEED_1000;
948 bp->duplex = DUPLEX_HALF;
949 }
950 else {
951 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
952 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
953
954 common = local_adv & remote_adv;
955 if (common & ADVERTISE_100FULL) {
956 bp->line_speed = SPEED_100;
957 bp->duplex = DUPLEX_FULL;
958 }
959 else if (common & ADVERTISE_100HALF) {
960 bp->line_speed = SPEED_100;
961 bp->duplex = DUPLEX_HALF;
962 }
963 else if (common & ADVERTISE_10FULL) {
964 bp->line_speed = SPEED_10;
965 bp->duplex = DUPLEX_FULL;
966 }
967 else if (common & ADVERTISE_10HALF) {
968 bp->line_speed = SPEED_10;
969 bp->duplex = DUPLEX_HALF;
970 }
971 else {
972 bp->line_speed = 0;
973 bp->link_up = 0;
974 }
975 }
976 }
977 else {
978 if (bmcr & BMCR_SPEED100) {
979 bp->line_speed = SPEED_100;
980 }
981 else {
982 bp->line_speed = SPEED_10;
983 }
984 if (bmcr & BMCR_FULLDPLX) {
985 bp->duplex = DUPLEX_FULL;
986 }
987 else {
988 bp->duplex = DUPLEX_HALF;
989 }
990 }
991
992 return 0;
993 }
994
995 static void
996 bnx2_init_rx_context0(struct bnx2 *bp)
997 {
998 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
999
1000 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1002 val |= 0x02 << 8;
1003
1004 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005 u32 lo_water, hi_water;
1006
1007 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1009 else
1010 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011 if (lo_water >= bp->rx_ring_size)
1012 lo_water = 0;
1013
1014 hi_water = bp->rx_ring_size / 4;
1015
1016 if (hi_water <= lo_water)
1017 lo_water = 0;
1018
1019 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1021
1022 if (hi_water > 0xf)
1023 hi_water = 0xf;
1024 else if (hi_water == 0)
1025 lo_water = 0;
1026 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1027 }
1028 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029 }
1030
1031 static int
1032 bnx2_set_mac_link(struct bnx2 *bp)
1033 {
1034 u32 val;
1035
1036 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038 (bp->duplex == DUPLEX_HALF)) {
1039 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1040 }
1041
1042 /* Configure the EMAC mode register. */
1043 val = REG_RD(bp, BNX2_EMAC_MODE);
1044
1045 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1046 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1047 BNX2_EMAC_MODE_25G_MODE);
1048
1049 if (bp->link_up) {
1050 switch (bp->line_speed) {
1051 case SPEED_10:
1052 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1054 break;
1055 }
1056 /* fall through */
1057 case SPEED_100:
1058 val |= BNX2_EMAC_MODE_PORT_MII;
1059 break;
1060 case SPEED_2500:
1061 val |= BNX2_EMAC_MODE_25G_MODE;
1062 /* fall through */
1063 case SPEED_1000:
1064 val |= BNX2_EMAC_MODE_PORT_GMII;
1065 break;
1066 }
1067 }
1068 else {
1069 val |= BNX2_EMAC_MODE_PORT_GMII;
1070 }
1071
1072 /* Set the MAC to operate in the appropriate duplex mode. */
1073 if (bp->duplex == DUPLEX_HALF)
1074 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075 REG_WR(bp, BNX2_EMAC_MODE, val);
1076
1077 /* Enable/disable rx PAUSE. */
1078 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1079
1080 if (bp->flow_ctrl & FLOW_CTRL_RX)
1081 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1083
1084 /* Enable/disable tx PAUSE. */
1085 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1087
1088 if (bp->flow_ctrl & FLOW_CTRL_TX)
1089 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1091
1092 /* Acknowledge the interrupt. */
1093 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094
1095 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096 bnx2_init_rx_context0(bp);
1097
1098 return 0;
1099 }
1100
1101 static void
1102 bnx2_enable_bmsr1(struct bnx2 *bp)
1103 {
1104 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1105 (CHIP_NUM(bp) == CHIP_NUM_5709))
1106 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107 MII_BNX2_BLK_ADDR_GP_STATUS);
1108 }
1109
1110 static void
1111 bnx2_disable_bmsr1(struct bnx2 *bp)
1112 {
1113 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1114 (CHIP_NUM(bp) == CHIP_NUM_5709))
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117 }
1118
1119 static int
1120 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1121 {
1122 u32 up1;
1123 int ret = 1;
1124
1125 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1126 return 0;
1127
1128 if (bp->autoneg & AUTONEG_SPEED)
1129 bp->advertising |= ADVERTISED_2500baseX_Full;
1130
1131 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1133
1134 bnx2_read_phy(bp, bp->mii_up1, &up1);
1135 if (!(up1 & BCM5708S_UP1_2G5)) {
1136 up1 |= BCM5708S_UP1_2G5;
1137 bnx2_write_phy(bp, bp->mii_up1, up1);
1138 ret = 0;
1139 }
1140
1141 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1144
1145 return ret;
1146 }
1147
1148 static int
1149 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1150 {
1151 u32 up1;
1152 int ret = 0;
1153
1154 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1155 return 0;
1156
1157 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1159
1160 bnx2_read_phy(bp, bp->mii_up1, &up1);
1161 if (up1 & BCM5708S_UP1_2G5) {
1162 up1 &= ~BCM5708S_UP1_2G5;
1163 bnx2_write_phy(bp, bp->mii_up1, up1);
1164 ret = 1;
1165 }
1166
1167 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1170
1171 return ret;
1172 }
1173
1174 static void
1175 bnx2_enable_forced_2g5(struct bnx2 *bp)
1176 {
1177 u32 bmcr;
1178
1179 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1180 return;
1181
1182 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1183 u32 val;
1184
1185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186 MII_BNX2_BLK_ADDR_SERDES_DIG);
1187 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1191
1192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195
1196 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1197 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198 bmcr |= BCM5708S_BMCR_FORCE_2500;
1199 }
1200
1201 if (bp->autoneg & AUTONEG_SPEED) {
1202 bmcr &= ~BMCR_ANENABLE;
1203 if (bp->req_duplex == DUPLEX_FULL)
1204 bmcr |= BMCR_FULLDPLX;
1205 }
1206 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1207 }
1208
1209 static void
1210 bnx2_disable_forced_2g5(struct bnx2 *bp)
1211 {
1212 u32 bmcr;
1213
1214 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1215 return;
1216
1217 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1218 u32 val;
1219
1220 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221 MII_BNX2_BLK_ADDR_SERDES_DIG);
1222 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1225
1226 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1229
1230 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1231 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1233 }
1234
1235 if (bp->autoneg & AUTONEG_SPEED)
1236 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1238 }
1239
1240 static void
1241 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1242 {
1243 u32 val;
1244
1245 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1247 if (start)
1248 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1249 else
1250 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1251 }
1252
1253 static int
1254 bnx2_set_link(struct bnx2 *bp)
1255 {
1256 u32 bmsr;
1257 u8 link_up;
1258
1259 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1260 bp->link_up = 1;
1261 return 0;
1262 }
1263
1264 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1265 return 0;
1266
1267 link_up = bp->link_up;
1268
1269 bnx2_enable_bmsr1(bp);
1270 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272 bnx2_disable_bmsr1(bp);
1273
1274 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1275 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1276 u32 val, an_dbg;
1277
1278 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1279 bnx2_5706s_force_link_dn(bp, 0);
1280 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1281 }
1282 val = REG_RD(bp, BNX2_EMAC_STATUS);
1283
1284 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1287
1288 if ((val & BNX2_EMAC_STATUS_LINK) &&
1289 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1290 bmsr |= BMSR_LSTATUS;
1291 else
1292 bmsr &= ~BMSR_LSTATUS;
1293 }
1294
1295 if (bmsr & BMSR_LSTATUS) {
1296 bp->link_up = 1;
1297
1298 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1299 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1300 bnx2_5706s_linkup(bp);
1301 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1302 bnx2_5708s_linkup(bp);
1303 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1304 bnx2_5709s_linkup(bp);
1305 }
1306 else {
1307 bnx2_copper_linkup(bp);
1308 }
1309 bnx2_resolve_flow_ctrl(bp);
1310 }
1311 else {
1312 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1313 (bp->autoneg & AUTONEG_SPEED))
1314 bnx2_disable_forced_2g5(bp);
1315
1316 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1317 u32 bmcr;
1318
1319 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1320 bmcr |= BMCR_ANENABLE;
1321 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1322
1323 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1324 }
1325 bp->link_up = 0;
1326 }
1327
1328 if (bp->link_up != link_up) {
1329 bnx2_report_link(bp);
1330 }
1331
1332 bnx2_set_mac_link(bp);
1333
1334 return 0;
1335 }
1336
1337 static int
1338 bnx2_reset_phy(struct bnx2 *bp)
1339 {
1340 int i;
1341 u32 reg;
1342
1343 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1344
1345 #define PHY_RESET_MAX_WAIT 100
1346 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1347 udelay(10);
1348
1349 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1350 if (!(reg & BMCR_RESET)) {
1351 udelay(20);
1352 break;
1353 }
1354 }
1355 if (i == PHY_RESET_MAX_WAIT) {
1356 return -EBUSY;
1357 }
1358 return 0;
1359 }
1360
1361 static u32
1362 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1363 {
1364 u32 adv = 0;
1365
1366 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1367 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1368
1369 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1370 adv = ADVERTISE_1000XPAUSE;
1371 }
1372 else {
1373 adv = ADVERTISE_PAUSE_CAP;
1374 }
1375 }
1376 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1378 adv = ADVERTISE_1000XPSE_ASYM;
1379 }
1380 else {
1381 adv = ADVERTISE_PAUSE_ASYM;
1382 }
1383 }
1384 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1385 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1386 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1387 }
1388 else {
1389 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1390 }
1391 }
1392 return adv;
1393 }
1394
1395 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1396
1397 static int
1398 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1399 {
1400 u32 speed_arg = 0, pause_adv;
1401
1402 pause_adv = bnx2_phy_get_pause_adv(bp);
1403
1404 if (bp->autoneg & AUTONEG_SPEED) {
1405 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1406 if (bp->advertising & ADVERTISED_10baseT_Half)
1407 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1408 if (bp->advertising & ADVERTISED_10baseT_Full)
1409 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1410 if (bp->advertising & ADVERTISED_100baseT_Half)
1411 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1412 if (bp->advertising & ADVERTISED_100baseT_Full)
1413 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1414 if (bp->advertising & ADVERTISED_1000baseT_Full)
1415 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1416 if (bp->advertising & ADVERTISED_2500baseX_Full)
1417 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1418 } else {
1419 if (bp->req_line_speed == SPEED_2500)
1420 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1421 else if (bp->req_line_speed == SPEED_1000)
1422 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1423 else if (bp->req_line_speed == SPEED_100) {
1424 if (bp->req_duplex == DUPLEX_FULL)
1425 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1426 else
1427 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1428 } else if (bp->req_line_speed == SPEED_10) {
1429 if (bp->req_duplex == DUPLEX_FULL)
1430 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1431 else
1432 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1433 }
1434 }
1435
1436 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1437 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1438 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1439 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1440
1441 if (port == PORT_TP)
1442 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1443 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1444
1445 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1446
1447 spin_unlock_bh(&bp->phy_lock);
1448 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1449 spin_lock_bh(&bp->phy_lock);
1450
1451 return 0;
1452 }
1453
1454 static int
1455 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1456 {
1457 u32 adv, bmcr;
1458 u32 new_adv = 0;
1459
1460 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1461 return (bnx2_setup_remote_phy(bp, port));
1462
1463 if (!(bp->autoneg & AUTONEG_SPEED)) {
1464 u32 new_bmcr;
1465 int force_link_down = 0;
1466
1467 if (bp->req_line_speed == SPEED_2500) {
1468 if (!bnx2_test_and_enable_2g5(bp))
1469 force_link_down = 1;
1470 } else if (bp->req_line_speed == SPEED_1000) {
1471 if (bnx2_test_and_disable_2g5(bp))
1472 force_link_down = 1;
1473 }
1474 bnx2_read_phy(bp, bp->mii_adv, &adv);
1475 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1476
1477 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1478 new_bmcr = bmcr & ~BMCR_ANENABLE;
1479 new_bmcr |= BMCR_SPEED1000;
1480
1481 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1482 if (bp->req_line_speed == SPEED_2500)
1483 bnx2_enable_forced_2g5(bp);
1484 else if (bp->req_line_speed == SPEED_1000) {
1485 bnx2_disable_forced_2g5(bp);
1486 new_bmcr &= ~0x2000;
1487 }
1488
1489 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1490 if (bp->req_line_speed == SPEED_2500)
1491 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1492 else
1493 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1494 }
1495
1496 if (bp->req_duplex == DUPLEX_FULL) {
1497 adv |= ADVERTISE_1000XFULL;
1498 new_bmcr |= BMCR_FULLDPLX;
1499 }
1500 else {
1501 adv |= ADVERTISE_1000XHALF;
1502 new_bmcr &= ~BMCR_FULLDPLX;
1503 }
1504 if ((new_bmcr != bmcr) || (force_link_down)) {
1505 /* Force a link down visible on the other side */
1506 if (bp->link_up) {
1507 bnx2_write_phy(bp, bp->mii_adv, adv &
1508 ~(ADVERTISE_1000XFULL |
1509 ADVERTISE_1000XHALF));
1510 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1511 BMCR_ANRESTART | BMCR_ANENABLE);
1512
1513 bp->link_up = 0;
1514 netif_carrier_off(bp->dev);
1515 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1516 bnx2_report_link(bp);
1517 }
1518 bnx2_write_phy(bp, bp->mii_adv, adv);
1519 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1520 } else {
1521 bnx2_resolve_flow_ctrl(bp);
1522 bnx2_set_mac_link(bp);
1523 }
1524 return 0;
1525 }
1526
1527 bnx2_test_and_enable_2g5(bp);
1528
1529 if (bp->advertising & ADVERTISED_1000baseT_Full)
1530 new_adv |= ADVERTISE_1000XFULL;
1531
1532 new_adv |= bnx2_phy_get_pause_adv(bp);
1533
1534 bnx2_read_phy(bp, bp->mii_adv, &adv);
1535 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1536
1537 bp->serdes_an_pending = 0;
1538 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1539 /* Force a link down visible on the other side */
1540 if (bp->link_up) {
1541 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1542 spin_unlock_bh(&bp->phy_lock);
1543 msleep(20);
1544 spin_lock_bh(&bp->phy_lock);
1545 }
1546
1547 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1548 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1549 BMCR_ANENABLE);
1550 /* Speed up link-up time when the link partner
1551 * does not autonegotiate which is very common
1552 * in blade servers. Some blade servers use
1553 * IPMI for kerboard input and it's important
1554 * to minimize link disruptions. Autoneg. involves
1555 * exchanging base pages plus 3 next pages and
1556 * normally completes in about 120 msec.
1557 */
1558 bp->current_interval = SERDES_AN_TIMEOUT;
1559 bp->serdes_an_pending = 1;
1560 mod_timer(&bp->timer, jiffies + bp->current_interval);
1561 } else {
1562 bnx2_resolve_flow_ctrl(bp);
1563 bnx2_set_mac_link(bp);
1564 }
1565
1566 return 0;
1567 }
1568
1569 #define ETHTOOL_ALL_FIBRE_SPEED \
1570 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1571 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1572 (ADVERTISED_1000baseT_Full)
1573
1574 #define ETHTOOL_ALL_COPPER_SPEED \
1575 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1576 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1577 ADVERTISED_1000baseT_Full)
1578
1579 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1580 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1581
1582 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1583
1584 static void
1585 bnx2_set_default_remote_link(struct bnx2 *bp)
1586 {
1587 u32 link;
1588
1589 if (bp->phy_port == PORT_TP)
1590 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1591 else
1592 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1593
1594 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1595 bp->req_line_speed = 0;
1596 bp->autoneg |= AUTONEG_SPEED;
1597 bp->advertising = ADVERTISED_Autoneg;
1598 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1599 bp->advertising |= ADVERTISED_10baseT_Half;
1600 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1601 bp->advertising |= ADVERTISED_10baseT_Full;
1602 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1603 bp->advertising |= ADVERTISED_100baseT_Half;
1604 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1605 bp->advertising |= ADVERTISED_100baseT_Full;
1606 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1607 bp->advertising |= ADVERTISED_1000baseT_Full;
1608 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1609 bp->advertising |= ADVERTISED_2500baseX_Full;
1610 } else {
1611 bp->autoneg = 0;
1612 bp->advertising = 0;
1613 bp->req_duplex = DUPLEX_FULL;
1614 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1615 bp->req_line_speed = SPEED_10;
1616 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1617 bp->req_duplex = DUPLEX_HALF;
1618 }
1619 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1620 bp->req_line_speed = SPEED_100;
1621 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1622 bp->req_duplex = DUPLEX_HALF;
1623 }
1624 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1625 bp->req_line_speed = SPEED_1000;
1626 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1627 bp->req_line_speed = SPEED_2500;
1628 }
1629 }
1630
1631 static void
1632 bnx2_set_default_link(struct bnx2 *bp)
1633 {
1634 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1635 bnx2_set_default_remote_link(bp);
1636 return;
1637 }
1638
1639 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1640 bp->req_line_speed = 0;
1641 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1642 u32 reg;
1643
1644 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1645
1646 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1647 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1648 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1649 bp->autoneg = 0;
1650 bp->req_line_speed = bp->line_speed = SPEED_1000;
1651 bp->req_duplex = DUPLEX_FULL;
1652 }
1653 } else
1654 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1655 }
1656
1657 static void
1658 bnx2_send_heart_beat(struct bnx2 *bp)
1659 {
1660 u32 msg;
1661 u32 addr;
1662
1663 spin_lock(&bp->indirect_lock);
1664 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1665 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1666 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1667 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1668 spin_unlock(&bp->indirect_lock);
1669 }
1670
1671 static void
1672 bnx2_remote_phy_event(struct bnx2 *bp)
1673 {
1674 u32 msg;
1675 u8 link_up = bp->link_up;
1676 u8 old_port;
1677
1678 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1679
1680 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1681 bnx2_send_heart_beat(bp);
1682
1683 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1684
1685 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1686 bp->link_up = 0;
1687 else {
1688 u32 speed;
1689
1690 bp->link_up = 1;
1691 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1692 bp->duplex = DUPLEX_FULL;
1693 switch (speed) {
1694 case BNX2_LINK_STATUS_10HALF:
1695 bp->duplex = DUPLEX_HALF;
1696 case BNX2_LINK_STATUS_10FULL:
1697 bp->line_speed = SPEED_10;
1698 break;
1699 case BNX2_LINK_STATUS_100HALF:
1700 bp->duplex = DUPLEX_HALF;
1701 case BNX2_LINK_STATUS_100BASE_T4:
1702 case BNX2_LINK_STATUS_100FULL:
1703 bp->line_speed = SPEED_100;
1704 break;
1705 case BNX2_LINK_STATUS_1000HALF:
1706 bp->duplex = DUPLEX_HALF;
1707 case BNX2_LINK_STATUS_1000FULL:
1708 bp->line_speed = SPEED_1000;
1709 break;
1710 case BNX2_LINK_STATUS_2500HALF:
1711 bp->duplex = DUPLEX_HALF;
1712 case BNX2_LINK_STATUS_2500FULL:
1713 bp->line_speed = SPEED_2500;
1714 break;
1715 default:
1716 bp->line_speed = 0;
1717 break;
1718 }
1719
1720 bp->flow_ctrl = 0;
1721 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1722 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1723 if (bp->duplex == DUPLEX_FULL)
1724 bp->flow_ctrl = bp->req_flow_ctrl;
1725 } else {
1726 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1727 bp->flow_ctrl |= FLOW_CTRL_TX;
1728 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1729 bp->flow_ctrl |= FLOW_CTRL_RX;
1730 }
1731
1732 old_port = bp->phy_port;
1733 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1734 bp->phy_port = PORT_FIBRE;
1735 else
1736 bp->phy_port = PORT_TP;
1737
1738 if (old_port != bp->phy_port)
1739 bnx2_set_default_link(bp);
1740
1741 }
1742 if (bp->link_up != link_up)
1743 bnx2_report_link(bp);
1744
1745 bnx2_set_mac_link(bp);
1746 }
1747
1748 static int
1749 bnx2_set_remote_link(struct bnx2 *bp)
1750 {
1751 u32 evt_code;
1752
1753 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1754 switch (evt_code) {
1755 case BNX2_FW_EVT_CODE_LINK_EVENT:
1756 bnx2_remote_phy_event(bp);
1757 break;
1758 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1759 default:
1760 bnx2_send_heart_beat(bp);
1761 break;
1762 }
1763 return 0;
1764 }
1765
1766 static int
1767 bnx2_setup_copper_phy(struct bnx2 *bp)
1768 {
1769 u32 bmcr;
1770 u32 new_bmcr;
1771
1772 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1773
1774 if (bp->autoneg & AUTONEG_SPEED) {
1775 u32 adv_reg, adv1000_reg;
1776 u32 new_adv_reg = 0;
1777 u32 new_adv1000_reg = 0;
1778
1779 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1780 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1781 ADVERTISE_PAUSE_ASYM);
1782
1783 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1784 adv1000_reg &= PHY_ALL_1000_SPEED;
1785
1786 if (bp->advertising & ADVERTISED_10baseT_Half)
1787 new_adv_reg |= ADVERTISE_10HALF;
1788 if (bp->advertising & ADVERTISED_10baseT_Full)
1789 new_adv_reg |= ADVERTISE_10FULL;
1790 if (bp->advertising & ADVERTISED_100baseT_Half)
1791 new_adv_reg |= ADVERTISE_100HALF;
1792 if (bp->advertising & ADVERTISED_100baseT_Full)
1793 new_adv_reg |= ADVERTISE_100FULL;
1794 if (bp->advertising & ADVERTISED_1000baseT_Full)
1795 new_adv1000_reg |= ADVERTISE_1000FULL;
1796
1797 new_adv_reg |= ADVERTISE_CSMA;
1798
1799 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1800
1801 if ((adv1000_reg != new_adv1000_reg) ||
1802 (adv_reg != new_adv_reg) ||
1803 ((bmcr & BMCR_ANENABLE) == 0)) {
1804
1805 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1806 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1807 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1808 BMCR_ANENABLE);
1809 }
1810 else if (bp->link_up) {
1811 /* Flow ctrl may have changed from auto to forced */
1812 /* or vice-versa. */
1813
1814 bnx2_resolve_flow_ctrl(bp);
1815 bnx2_set_mac_link(bp);
1816 }
1817 return 0;
1818 }
1819
1820 new_bmcr = 0;
1821 if (bp->req_line_speed == SPEED_100) {
1822 new_bmcr |= BMCR_SPEED100;
1823 }
1824 if (bp->req_duplex == DUPLEX_FULL) {
1825 new_bmcr |= BMCR_FULLDPLX;
1826 }
1827 if (new_bmcr != bmcr) {
1828 u32 bmsr;
1829
1830 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1831 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1832
1833 if (bmsr & BMSR_LSTATUS) {
1834 /* Force link down */
1835 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1836 spin_unlock_bh(&bp->phy_lock);
1837 msleep(50);
1838 spin_lock_bh(&bp->phy_lock);
1839
1840 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1841 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1842 }
1843
1844 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1845
1846 /* Normally, the new speed is setup after the link has
1847 * gone down and up again. In some cases, link will not go
1848 * down so we need to set up the new speed here.
1849 */
1850 if (bmsr & BMSR_LSTATUS) {
1851 bp->line_speed = bp->req_line_speed;
1852 bp->duplex = bp->req_duplex;
1853 bnx2_resolve_flow_ctrl(bp);
1854 bnx2_set_mac_link(bp);
1855 }
1856 } else {
1857 bnx2_resolve_flow_ctrl(bp);
1858 bnx2_set_mac_link(bp);
1859 }
1860 return 0;
1861 }
1862
1863 static int
1864 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1865 {
1866 if (bp->loopback == MAC_LOOPBACK)
1867 return 0;
1868
1869 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1870 return (bnx2_setup_serdes_phy(bp, port));
1871 }
1872 else {
1873 return (bnx2_setup_copper_phy(bp));
1874 }
1875 }
1876
1877 static int
1878 bnx2_init_5709s_phy(struct bnx2 *bp)
1879 {
1880 u32 val;
1881
1882 bp->mii_bmcr = MII_BMCR + 0x10;
1883 bp->mii_bmsr = MII_BMSR + 0x10;
1884 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1885 bp->mii_adv = MII_ADVERTISE + 0x10;
1886 bp->mii_lpa = MII_LPA + 0x10;
1887 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1888
1889 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891
1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1893 bnx2_reset_phy(bp);
1894
1895 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1896
1897 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1898 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1899 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1900 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1901
1902 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1903 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1904 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
1905 val |= BCM5708S_UP1_2G5;
1906 else
1907 val &= ~BCM5708S_UP1_2G5;
1908 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1909
1910 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1911 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1912 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1913 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1914
1915 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1916
1917 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1918 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1919 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1920
1921 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1922
1923 return 0;
1924 }
1925
1926 static int
1927 bnx2_init_5708s_phy(struct bnx2 *bp)
1928 {
1929 u32 val;
1930
1931 bnx2_reset_phy(bp);
1932
1933 bp->mii_up1 = BCM5708S_UP1;
1934
1935 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1936 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1937 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1938
1939 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1940 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1941 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1942
1943 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1944 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1945 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1946
1947 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
1948 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1949 val |= BCM5708S_UP1_2G5;
1950 bnx2_write_phy(bp, BCM5708S_UP1, val);
1951 }
1952
1953 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1954 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1955 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1956 /* increase tx signal amplitude */
1957 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1958 BCM5708S_BLK_ADDR_TX_MISC);
1959 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1960 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1961 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1962 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1963 }
1964
1965 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
1966 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1967
1968 if (val) {
1969 u32 is_backplane;
1970
1971 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
1972 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1973 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1974 BCM5708S_BLK_ADDR_TX_MISC);
1975 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1976 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1977 BCM5708S_BLK_ADDR_DIG);
1978 }
1979 }
1980 return 0;
1981 }
1982
1983 static int
1984 bnx2_init_5706s_phy(struct bnx2 *bp)
1985 {
1986 bnx2_reset_phy(bp);
1987
1988 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1989
1990 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1991 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1992
1993 if (bp->dev->mtu > 1500) {
1994 u32 val;
1995
1996 /* Set extended packet length bit */
1997 bnx2_write_phy(bp, 0x18, 0x7);
1998 bnx2_read_phy(bp, 0x18, &val);
1999 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2000
2001 bnx2_write_phy(bp, 0x1c, 0x6c00);
2002 bnx2_read_phy(bp, 0x1c, &val);
2003 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2004 }
2005 else {
2006 u32 val;
2007
2008 bnx2_write_phy(bp, 0x18, 0x7);
2009 bnx2_read_phy(bp, 0x18, &val);
2010 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2011
2012 bnx2_write_phy(bp, 0x1c, 0x6c00);
2013 bnx2_read_phy(bp, 0x1c, &val);
2014 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2015 }
2016
2017 return 0;
2018 }
2019
2020 static int
2021 bnx2_init_copper_phy(struct bnx2 *bp)
2022 {
2023 u32 val;
2024
2025 bnx2_reset_phy(bp);
2026
2027 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2028 bnx2_write_phy(bp, 0x18, 0x0c00);
2029 bnx2_write_phy(bp, 0x17, 0x000a);
2030 bnx2_write_phy(bp, 0x15, 0x310b);
2031 bnx2_write_phy(bp, 0x17, 0x201f);
2032 bnx2_write_phy(bp, 0x15, 0x9506);
2033 bnx2_write_phy(bp, 0x17, 0x401f);
2034 bnx2_write_phy(bp, 0x15, 0x14e2);
2035 bnx2_write_phy(bp, 0x18, 0x0400);
2036 }
2037
2038 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2039 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2040 MII_BNX2_DSP_EXPAND_REG | 0x8);
2041 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2042 val &= ~(1 << 8);
2043 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2044 }
2045
2046 if (bp->dev->mtu > 1500) {
2047 /* Set extended packet length bit */
2048 bnx2_write_phy(bp, 0x18, 0x7);
2049 bnx2_read_phy(bp, 0x18, &val);
2050 bnx2_write_phy(bp, 0x18, val | 0x4000);
2051
2052 bnx2_read_phy(bp, 0x10, &val);
2053 bnx2_write_phy(bp, 0x10, val | 0x1);
2054 }
2055 else {
2056 bnx2_write_phy(bp, 0x18, 0x7);
2057 bnx2_read_phy(bp, 0x18, &val);
2058 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2059
2060 bnx2_read_phy(bp, 0x10, &val);
2061 bnx2_write_phy(bp, 0x10, val & ~0x1);
2062 }
2063
2064 /* ethernet@wirespeed */
2065 bnx2_write_phy(bp, 0x18, 0x7007);
2066 bnx2_read_phy(bp, 0x18, &val);
2067 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2068 return 0;
2069 }
2070
2071
2072 static int
2073 bnx2_init_phy(struct bnx2 *bp)
2074 {
2075 u32 val;
2076 int rc = 0;
2077
2078 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2079 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2080
2081 bp->mii_bmcr = MII_BMCR;
2082 bp->mii_bmsr = MII_BMSR;
2083 bp->mii_bmsr1 = MII_BMSR;
2084 bp->mii_adv = MII_ADVERTISE;
2085 bp->mii_lpa = MII_LPA;
2086
2087 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2088
2089 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2090 goto setup_phy;
2091
2092 bnx2_read_phy(bp, MII_PHYSID1, &val);
2093 bp->phy_id = val << 16;
2094 bnx2_read_phy(bp, MII_PHYSID2, &val);
2095 bp->phy_id |= val & 0xffff;
2096
2097 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2098 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2099 rc = bnx2_init_5706s_phy(bp);
2100 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2101 rc = bnx2_init_5708s_phy(bp);
2102 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2103 rc = bnx2_init_5709s_phy(bp);
2104 }
2105 else {
2106 rc = bnx2_init_copper_phy(bp);
2107 }
2108
2109 setup_phy:
2110 if (!rc)
2111 rc = bnx2_setup_phy(bp, bp->phy_port);
2112
2113 return rc;
2114 }
2115
2116 static int
2117 bnx2_set_mac_loopback(struct bnx2 *bp)
2118 {
2119 u32 mac_mode;
2120
2121 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2122 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2123 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2124 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2125 bp->link_up = 1;
2126 return 0;
2127 }
2128
2129 static int bnx2_test_link(struct bnx2 *);
2130
2131 static int
2132 bnx2_set_phy_loopback(struct bnx2 *bp)
2133 {
2134 u32 mac_mode;
2135 int rc, i;
2136
2137 spin_lock_bh(&bp->phy_lock);
2138 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2139 BMCR_SPEED1000);
2140 spin_unlock_bh(&bp->phy_lock);
2141 if (rc)
2142 return rc;
2143
2144 for (i = 0; i < 10; i++) {
2145 if (bnx2_test_link(bp) == 0)
2146 break;
2147 msleep(100);
2148 }
2149
2150 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2151 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2152 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2153 BNX2_EMAC_MODE_25G_MODE);
2154
2155 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2156 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2157 bp->link_up = 1;
2158 return 0;
2159 }
2160
2161 static int
2162 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2163 {
2164 int i;
2165 u32 val;
2166
2167 bp->fw_wr_seq++;
2168 msg_data |= bp->fw_wr_seq;
2169
2170 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2171
2172 /* wait for an acknowledgement. */
2173 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2174 msleep(10);
2175
2176 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2177
2178 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2179 break;
2180 }
2181 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2182 return 0;
2183
2184 /* If we timed out, inform the firmware that this is the case. */
2185 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2186 if (!silent)
2187 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2188 "%x\n", msg_data);
2189
2190 msg_data &= ~BNX2_DRV_MSG_CODE;
2191 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2192
2193 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2194
2195 return -EBUSY;
2196 }
2197
2198 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2199 return -EIO;
2200
2201 return 0;
2202 }
2203
2204 static int
2205 bnx2_init_5709_context(struct bnx2 *bp)
2206 {
2207 int i, ret = 0;
2208 u32 val;
2209
2210 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2211 val |= (BCM_PAGE_BITS - 8) << 16;
2212 REG_WR(bp, BNX2_CTX_COMMAND, val);
2213 for (i = 0; i < 10; i++) {
2214 val = REG_RD(bp, BNX2_CTX_COMMAND);
2215 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2216 break;
2217 udelay(2);
2218 }
2219 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2220 return -EBUSY;
2221
2222 for (i = 0; i < bp->ctx_pages; i++) {
2223 int j;
2224
2225 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2226 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2227 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2228 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2229 (u64) bp->ctx_blk_mapping[i] >> 32);
2230 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2231 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2232 for (j = 0; j < 10; j++) {
2233
2234 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2235 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2236 break;
2237 udelay(5);
2238 }
2239 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2240 ret = -EBUSY;
2241 break;
2242 }
2243 }
2244 return ret;
2245 }
2246
2247 static void
2248 bnx2_init_context(struct bnx2 *bp)
2249 {
2250 u32 vcid;
2251
2252 vcid = 96;
2253 while (vcid) {
2254 u32 vcid_addr, pcid_addr, offset;
2255 int i;
2256
2257 vcid--;
2258
2259 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2260 u32 new_vcid;
2261
2262 vcid_addr = GET_PCID_ADDR(vcid);
2263 if (vcid & 0x8) {
2264 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2265 }
2266 else {
2267 new_vcid = vcid;
2268 }
2269 pcid_addr = GET_PCID_ADDR(new_vcid);
2270 }
2271 else {
2272 vcid_addr = GET_CID_ADDR(vcid);
2273 pcid_addr = vcid_addr;
2274 }
2275
2276 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2277 vcid_addr += (i << PHY_CTX_SHIFT);
2278 pcid_addr += (i << PHY_CTX_SHIFT);
2279
2280 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2281 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2282
2283 /* Zero out the context. */
2284 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2285 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2286 }
2287 }
2288 }
2289
2290 static int
2291 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2292 {
2293 u16 *good_mbuf;
2294 u32 good_mbuf_cnt;
2295 u32 val;
2296
2297 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2298 if (good_mbuf == NULL) {
2299 printk(KERN_ERR PFX "Failed to allocate memory in "
2300 "bnx2_alloc_bad_rbuf\n");
2301 return -ENOMEM;
2302 }
2303
2304 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2305 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2306
2307 good_mbuf_cnt = 0;
2308
2309 /* Allocate a bunch of mbufs and save the good ones in an array. */
2310 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2311 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2312 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2313 BNX2_RBUF_COMMAND_ALLOC_REQ);
2314
2315 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2316
2317 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2318
2319 /* The addresses with Bit 9 set are bad memory blocks. */
2320 if (!(val & (1 << 9))) {
2321 good_mbuf[good_mbuf_cnt] = (u16) val;
2322 good_mbuf_cnt++;
2323 }
2324
2325 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2326 }
2327
2328 /* Free the good ones back to the mbuf pool thus discarding
2329 * all the bad ones. */
2330 while (good_mbuf_cnt) {
2331 good_mbuf_cnt--;
2332
2333 val = good_mbuf[good_mbuf_cnt];
2334 val = (val << 9) | val | 1;
2335
2336 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2337 }
2338 kfree(good_mbuf);
2339 return 0;
2340 }
2341
2342 static void
2343 bnx2_set_mac_addr(struct bnx2 *bp)
2344 {
2345 u32 val;
2346 u8 *mac_addr = bp->dev->dev_addr;
2347
2348 val = (mac_addr[0] << 8) | mac_addr[1];
2349
2350 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2351
2352 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2353 (mac_addr[4] << 8) | mac_addr[5];
2354
2355 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2356 }
2357
2358 static inline int
2359 bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2360 {
2361 dma_addr_t mapping;
2362 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2363 struct rx_bd *rxbd =
2364 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2365 struct page *page = alloc_page(GFP_ATOMIC);
2366
2367 if (!page)
2368 return -ENOMEM;
2369 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2370 PCI_DMA_FROMDEVICE);
2371 rx_pg->page = page;
2372 pci_unmap_addr_set(rx_pg, mapping, mapping);
2373 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2374 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2375 return 0;
2376 }
2377
2378 static void
2379 bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2380 {
2381 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2382 struct page *page = rx_pg->page;
2383
2384 if (!page)
2385 return;
2386
2387 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2388 PCI_DMA_FROMDEVICE);
2389
2390 __free_page(page);
2391 rx_pg->page = NULL;
2392 }
2393
2394 static inline int
2395 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
2396 {
2397 struct sk_buff *skb;
2398 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2399 dma_addr_t mapping;
2400 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2401 unsigned long align;
2402
2403 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2404 if (skb == NULL) {
2405 return -ENOMEM;
2406 }
2407
2408 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2409 skb_reserve(skb, BNX2_RX_ALIGN - align);
2410
2411 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2412 PCI_DMA_FROMDEVICE);
2413
2414 rx_buf->skb = skb;
2415 pci_unmap_addr_set(rx_buf, mapping, mapping);
2416
2417 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2418 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2419
2420 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
2421
2422 return 0;
2423 }
2424
2425 static int
2426 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2427 {
2428 struct status_block *sblk = bnapi->status_blk;
2429 u32 new_link_state, old_link_state;
2430 int is_set = 1;
2431
2432 new_link_state = sblk->status_attn_bits & event;
2433 old_link_state = sblk->status_attn_bits_ack & event;
2434 if (new_link_state != old_link_state) {
2435 if (new_link_state)
2436 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2437 else
2438 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2439 } else
2440 is_set = 0;
2441
2442 return is_set;
2443 }
2444
2445 static void
2446 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2447 {
2448 spin_lock(&bp->phy_lock);
2449
2450 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2451 bnx2_set_link(bp);
2452 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2453 bnx2_set_remote_link(bp);
2454
2455 spin_unlock(&bp->phy_lock);
2456
2457 }
2458
2459 static inline u16
2460 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2461 {
2462 u16 cons;
2463
2464 if (bnapi->int_num == 0)
2465 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2466 else
2467 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
2468
2469 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2470 cons++;
2471 return cons;
2472 }
2473
2474 static int
2475 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2476 {
2477 u16 hw_cons, sw_cons, sw_ring_cons;
2478 int tx_pkt = 0;
2479
2480 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2481 sw_cons = bnapi->tx_cons;
2482
2483 while (sw_cons != hw_cons) {
2484 struct sw_bd *tx_buf;
2485 struct sk_buff *skb;
2486 int i, last;
2487
2488 sw_ring_cons = TX_RING_IDX(sw_cons);
2489
2490 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2491 skb = tx_buf->skb;
2492
2493 /* partial BD completions possible with TSO packets */
2494 if (skb_is_gso(skb)) {
2495 u16 last_idx, last_ring_idx;
2496
2497 last_idx = sw_cons +
2498 skb_shinfo(skb)->nr_frags + 1;
2499 last_ring_idx = sw_ring_cons +
2500 skb_shinfo(skb)->nr_frags + 1;
2501 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2502 last_idx++;
2503 }
2504 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2505 break;
2506 }
2507 }
2508
2509 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2510 skb_headlen(skb), PCI_DMA_TODEVICE);
2511
2512 tx_buf->skb = NULL;
2513 last = skb_shinfo(skb)->nr_frags;
2514
2515 for (i = 0; i < last; i++) {
2516 sw_cons = NEXT_TX_BD(sw_cons);
2517
2518 pci_unmap_page(bp->pdev,
2519 pci_unmap_addr(
2520 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2521 mapping),
2522 skb_shinfo(skb)->frags[i].size,
2523 PCI_DMA_TODEVICE);
2524 }
2525
2526 sw_cons = NEXT_TX_BD(sw_cons);
2527
2528 dev_kfree_skb(skb);
2529 tx_pkt++;
2530 if (tx_pkt == budget)
2531 break;
2532
2533 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2534 }
2535
2536 bnapi->hw_tx_cons = hw_cons;
2537 bnapi->tx_cons = sw_cons;
2538 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2539 * before checking for netif_queue_stopped(). Without the
2540 * memory barrier, there is a small possibility that bnx2_start_xmit()
2541 * will miss it and cause the queue to be stopped forever.
2542 */
2543 smp_mb();
2544
2545 if (unlikely(netif_queue_stopped(bp->dev)) &&
2546 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2547 netif_tx_lock(bp->dev);
2548 if ((netif_queue_stopped(bp->dev)) &&
2549 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
2550 netif_wake_queue(bp->dev);
2551 netif_tx_unlock(bp->dev);
2552 }
2553 return tx_pkt;
2554 }
2555
2556 static void
2557 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2558 struct sk_buff *skb, int count)
2559 {
2560 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2561 struct rx_bd *cons_bd, *prod_bd;
2562 dma_addr_t mapping;
2563 int i;
2564 u16 hw_prod = bnapi->rx_pg_prod, prod;
2565 u16 cons = bnapi->rx_pg_cons;
2566
2567 for (i = 0; i < count; i++) {
2568 prod = RX_PG_RING_IDX(hw_prod);
2569
2570 prod_rx_pg = &bp->rx_pg_ring[prod];
2571 cons_rx_pg = &bp->rx_pg_ring[cons];
2572 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2573 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2574
2575 if (i == 0 && skb) {
2576 struct page *page;
2577 struct skb_shared_info *shinfo;
2578
2579 shinfo = skb_shinfo(skb);
2580 shinfo->nr_frags--;
2581 page = shinfo->frags[shinfo->nr_frags].page;
2582 shinfo->frags[shinfo->nr_frags].page = NULL;
2583 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2584 PCI_DMA_FROMDEVICE);
2585 cons_rx_pg->page = page;
2586 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2587 dev_kfree_skb(skb);
2588 }
2589 if (prod != cons) {
2590 prod_rx_pg->page = cons_rx_pg->page;
2591 cons_rx_pg->page = NULL;
2592 pci_unmap_addr_set(prod_rx_pg, mapping,
2593 pci_unmap_addr(cons_rx_pg, mapping));
2594
2595 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2596 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2597
2598 }
2599 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2600 hw_prod = NEXT_RX_BD(hw_prod);
2601 }
2602 bnapi->rx_pg_prod = hw_prod;
2603 bnapi->rx_pg_cons = cons;
2604 }
2605
2606 static inline void
2607 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2608 u16 cons, u16 prod)
2609 {
2610 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2611 struct rx_bd *cons_bd, *prod_bd;
2612
2613 cons_rx_buf = &bp->rx_buf_ring[cons];
2614 prod_rx_buf = &bp->rx_buf_ring[prod];
2615
2616 pci_dma_sync_single_for_device(bp->pdev,
2617 pci_unmap_addr(cons_rx_buf, mapping),
2618 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2619
2620 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
2621
2622 prod_rx_buf->skb = skb;
2623
2624 if (cons == prod)
2625 return;
2626
2627 pci_unmap_addr_set(prod_rx_buf, mapping,
2628 pci_unmap_addr(cons_rx_buf, mapping));
2629
2630 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2631 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2632 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2633 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2634 }
2635
2636 static int
2637 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2638 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2639 u32 ring_idx)
2640 {
2641 int err;
2642 u16 prod = ring_idx & 0xffff;
2643
2644 err = bnx2_alloc_rx_skb(bp, bnapi, prod);
2645 if (unlikely(err)) {
2646 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
2647 if (hdr_len) {
2648 unsigned int raw_len = len + 4;
2649 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2650
2651 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
2652 }
2653 return err;
2654 }
2655
2656 skb_reserve(skb, bp->rx_offset);
2657 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2658 PCI_DMA_FROMDEVICE);
2659
2660 if (hdr_len == 0) {
2661 skb_put(skb, len);
2662 return 0;
2663 } else {
2664 unsigned int i, frag_len, frag_size, pages;
2665 struct sw_pg *rx_pg;
2666 u16 pg_cons = bnapi->rx_pg_cons;
2667 u16 pg_prod = bnapi->rx_pg_prod;
2668
2669 frag_size = len + 4 - hdr_len;
2670 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2671 skb_put(skb, hdr_len);
2672
2673 for (i = 0; i < pages; i++) {
2674 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2675 if (unlikely(frag_len <= 4)) {
2676 unsigned int tail = 4 - frag_len;
2677
2678 bnapi->rx_pg_cons = pg_cons;
2679 bnapi->rx_pg_prod = pg_prod;
2680 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2681 pages - i);
2682 skb->len -= tail;
2683 if (i == 0) {
2684 skb->tail -= tail;
2685 } else {
2686 skb_frag_t *frag =
2687 &skb_shinfo(skb)->frags[i - 1];
2688 frag->size -= tail;
2689 skb->data_len -= tail;
2690 skb->truesize -= tail;
2691 }
2692 return 0;
2693 }
2694 rx_pg = &bp->rx_pg_ring[pg_cons];
2695
2696 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2697 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2698
2699 if (i == pages - 1)
2700 frag_len -= 4;
2701
2702 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2703 rx_pg->page = NULL;
2704
2705 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2706 if (unlikely(err)) {
2707 bnapi->rx_pg_cons = pg_cons;
2708 bnapi->rx_pg_prod = pg_prod;
2709 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2710 pages - i);
2711 return err;
2712 }
2713
2714 frag_size -= frag_len;
2715 skb->data_len += frag_len;
2716 skb->truesize += frag_len;
2717 skb->len += frag_len;
2718
2719 pg_prod = NEXT_RX_BD(pg_prod);
2720 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2721 }
2722 bnapi->rx_pg_prod = pg_prod;
2723 bnapi->rx_pg_cons = pg_cons;
2724 }
2725 return 0;
2726 }
2727
2728 static inline u16
2729 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2730 {
2731 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
2732
2733 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2734 cons++;
2735 return cons;
2736 }
2737
2738 static int
2739 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2740 {
2741 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2742 struct l2_fhdr *rx_hdr;
2743 int rx_pkt = 0, pg_ring_used = 0;
2744
2745 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2746 sw_cons = bnapi->rx_cons;
2747 sw_prod = bnapi->rx_prod;
2748
2749 /* Memory barrier necessary as speculative reads of the rx
2750 * buffer can be ahead of the index in the status block
2751 */
2752 rmb();
2753 while (sw_cons != hw_cons) {
2754 unsigned int len, hdr_len;
2755 u32 status;
2756 struct sw_bd *rx_buf;
2757 struct sk_buff *skb;
2758 dma_addr_t dma_addr;
2759
2760 sw_ring_cons = RX_RING_IDX(sw_cons);
2761 sw_ring_prod = RX_RING_IDX(sw_prod);
2762
2763 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2764 skb = rx_buf->skb;
2765
2766 rx_buf->skb = NULL;
2767
2768 dma_addr = pci_unmap_addr(rx_buf, mapping);
2769
2770 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2771 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2772
2773 rx_hdr = (struct l2_fhdr *) skb->data;
2774 len = rx_hdr->l2_fhdr_pkt_len;
2775
2776 if ((status = rx_hdr->l2_fhdr_status) &
2777 (L2_FHDR_ERRORS_BAD_CRC |
2778 L2_FHDR_ERRORS_PHY_DECODE |
2779 L2_FHDR_ERRORS_ALIGNMENT |
2780 L2_FHDR_ERRORS_TOO_SHORT |
2781 L2_FHDR_ERRORS_GIANT_FRAME)) {
2782
2783 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2784 sw_ring_prod);
2785 goto next_rx;
2786 }
2787 hdr_len = 0;
2788 if (status & L2_FHDR_STATUS_SPLIT) {
2789 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2790 pg_ring_used = 1;
2791 } else if (len > bp->rx_jumbo_thresh) {
2792 hdr_len = bp->rx_jumbo_thresh;
2793 pg_ring_used = 1;
2794 }
2795
2796 len -= 4;
2797
2798 if (len <= bp->rx_copy_thresh) {
2799 struct sk_buff *new_skb;
2800
2801 new_skb = netdev_alloc_skb(bp->dev, len + 2);
2802 if (new_skb == NULL) {
2803 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2804 sw_ring_prod);
2805 goto next_rx;
2806 }
2807
2808 /* aligned copy */
2809 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2810 new_skb->data, len + 2);
2811 skb_reserve(new_skb, 2);
2812 skb_put(new_skb, len);
2813
2814 bnx2_reuse_rx_skb(bp, bnapi, skb,
2815 sw_ring_cons, sw_ring_prod);
2816
2817 skb = new_skb;
2818 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2819 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2820 goto next_rx;
2821
2822 skb->protocol = eth_type_trans(skb, bp->dev);
2823
2824 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2825 (ntohs(skb->protocol) != 0x8100)) {
2826
2827 dev_kfree_skb(skb);
2828 goto next_rx;
2829
2830 }
2831
2832 skb->ip_summed = CHECKSUM_NONE;
2833 if (bp->rx_csum &&
2834 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2835 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2836
2837 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2838 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2839 skb->ip_summed = CHECKSUM_UNNECESSARY;
2840 }
2841
2842 #ifdef BCM_VLAN
2843 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
2844 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2845 rx_hdr->l2_fhdr_vlan_tag);
2846 }
2847 else
2848 #endif
2849 netif_receive_skb(skb);
2850
2851 bp->dev->last_rx = jiffies;
2852 rx_pkt++;
2853
2854 next_rx:
2855 sw_cons = NEXT_RX_BD(sw_cons);
2856 sw_prod = NEXT_RX_BD(sw_prod);
2857
2858 if ((rx_pkt == budget))
2859 break;
2860
2861 /* Refresh hw_cons to see if there is new work */
2862 if (sw_cons == hw_cons) {
2863 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2864 rmb();
2865 }
2866 }
2867 bnapi->rx_cons = sw_cons;
2868 bnapi->rx_prod = sw_prod;
2869
2870 if (pg_ring_used)
2871 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
2872 bnapi->rx_pg_prod);
2873
2874 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2875
2876 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
2877
2878 mmiowb();
2879
2880 return rx_pkt;
2881
2882 }
2883
2884 /* MSI ISR - The only difference between this and the INTx ISR
2885 * is that the MSI interrupt is always serviced.
2886 */
2887 static irqreturn_t
2888 bnx2_msi(int irq, void *dev_instance)
2889 {
2890 struct net_device *dev = dev_instance;
2891 struct bnx2 *bp = netdev_priv(dev);
2892 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2893
2894 prefetch(bnapi->status_blk);
2895 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2896 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2897 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2898
2899 /* Return here if interrupt is disabled. */
2900 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2901 return IRQ_HANDLED;
2902
2903 netif_rx_schedule(dev, &bnapi->napi);
2904
2905 return IRQ_HANDLED;
2906 }
2907
2908 static irqreturn_t
2909 bnx2_msi_1shot(int irq, void *dev_instance)
2910 {
2911 struct net_device *dev = dev_instance;
2912 struct bnx2 *bp = netdev_priv(dev);
2913 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2914
2915 prefetch(bnapi->status_blk);
2916
2917 /* Return here if interrupt is disabled. */
2918 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2919 return IRQ_HANDLED;
2920
2921 netif_rx_schedule(dev, &bnapi->napi);
2922
2923 return IRQ_HANDLED;
2924 }
2925
2926 static irqreturn_t
2927 bnx2_interrupt(int irq, void *dev_instance)
2928 {
2929 struct net_device *dev = dev_instance;
2930 struct bnx2 *bp = netdev_priv(dev);
2931 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2932 struct status_block *sblk = bnapi->status_blk;
2933
2934 /* When using INTx, it is possible for the interrupt to arrive
2935 * at the CPU before the status block posted prior to the
2936 * interrupt. Reading a register will flush the status block.
2937 * When using MSI, the MSI message will always complete after
2938 * the status block write.
2939 */
2940 if ((sblk->status_idx == bnapi->last_status_idx) &&
2941 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2942 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2943 return IRQ_NONE;
2944
2945 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2946 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2947 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2948
2949 /* Read back to deassert IRQ immediately to avoid too many
2950 * spurious interrupts.
2951 */
2952 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2953
2954 /* Return here if interrupt is shared and is disabled. */
2955 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2956 return IRQ_HANDLED;
2957
2958 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2959 bnapi->last_status_idx = sblk->status_idx;
2960 __netif_rx_schedule(dev, &bnapi->napi);
2961 }
2962
2963 return IRQ_HANDLED;
2964 }
2965
2966 static irqreturn_t
2967 bnx2_tx_msix(int irq, void *dev_instance)
2968 {
2969 struct net_device *dev = dev_instance;
2970 struct bnx2 *bp = netdev_priv(dev);
2971 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2972
2973 prefetch(bnapi->status_blk_msix);
2974
2975 /* Return here if interrupt is disabled. */
2976 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2977 return IRQ_HANDLED;
2978
2979 netif_rx_schedule(dev, &bnapi->napi);
2980 return IRQ_HANDLED;
2981 }
2982
2983 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2984 STATUS_ATTN_BITS_TIMER_ABORT)
2985
2986 static inline int
2987 bnx2_has_work(struct bnx2_napi *bnapi)
2988 {
2989 struct status_block *sblk = bnapi->status_blk;
2990
2991 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
2992 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
2993 return 1;
2994
2995 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2996 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2997 return 1;
2998
2999 return 0;
3000 }
3001
3002 static int bnx2_tx_poll(struct napi_struct *napi, int budget)
3003 {
3004 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3005 struct bnx2 *bp = bnapi->bp;
3006 int work_done = 0;
3007 struct status_block_msix *sblk = bnapi->status_blk_msix;
3008
3009 do {
3010 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3011 if (unlikely(work_done >= budget))
3012 return work_done;
3013
3014 bnapi->last_status_idx = sblk->status_idx;
3015 rmb();
3016 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3017
3018 netif_rx_complete(bp->dev, napi);
3019 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3020 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3021 bnapi->last_status_idx);
3022 return work_done;
3023 }
3024
3025 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3026 int work_done, int budget)
3027 {
3028 struct status_block *sblk = bnapi->status_blk;
3029 u32 status_attn_bits = sblk->status_attn_bits;
3030 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3031
3032 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3033 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3034
3035 bnx2_phy_int(bp, bnapi);
3036
3037 /* This is needed to take care of transient status
3038 * during link changes.
3039 */
3040 REG_WR(bp, BNX2_HC_COMMAND,
3041 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3042 REG_RD(bp, BNX2_HC_COMMAND);
3043 }
3044
3045 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
3046 bnx2_tx_int(bp, bnapi, 0);
3047
3048 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
3049 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3050
3051 return work_done;
3052 }
3053
3054 static int bnx2_poll(struct napi_struct *napi, int budget)
3055 {
3056 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3057 struct bnx2 *bp = bnapi->bp;
3058 int work_done = 0;
3059 struct status_block *sblk = bnapi->status_blk;
3060
3061 while (1) {
3062 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3063
3064 if (unlikely(work_done >= budget))
3065 break;
3066
3067 /* bnapi->last_status_idx is used below to tell the hw how
3068 * much work has been processed, so we must read it before
3069 * checking for more work.
3070 */
3071 bnapi->last_status_idx = sblk->status_idx;
3072 rmb();
3073 if (likely(!bnx2_has_work(bnapi))) {
3074 netif_rx_complete(bp->dev, napi);
3075 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3076 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3077 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3078 bnapi->last_status_idx);
3079 break;
3080 }
3081 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3082 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3083 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3084 bnapi->last_status_idx);
3085
3086 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3087 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3088 bnapi->last_status_idx);
3089 break;
3090 }
3091 }
3092
3093 return work_done;
3094 }
3095
3096 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3097 * from set_multicast.
3098 */
3099 static void
3100 bnx2_set_rx_mode(struct net_device *dev)
3101 {
3102 struct bnx2 *bp = netdev_priv(dev);
3103 u32 rx_mode, sort_mode;
3104 int i;
3105
3106 spin_lock_bh(&bp->phy_lock);
3107
3108 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3109 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3110 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3111 #ifdef BCM_VLAN
3112 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
3113 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3114 #else
3115 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
3116 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3117 #endif
3118 if (dev->flags & IFF_PROMISC) {
3119 /* Promiscuous mode. */
3120 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3121 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3122 BNX2_RPM_SORT_USER0_PROM_VLAN;
3123 }
3124 else if (dev->flags & IFF_ALLMULTI) {
3125 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3126 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3127 0xffffffff);
3128 }
3129 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3130 }
3131 else {
3132 /* Accept one or more multicast(s). */
3133 struct dev_mc_list *mclist;
3134 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3135 u32 regidx;
3136 u32 bit;
3137 u32 crc;
3138
3139 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3140
3141 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3142 i++, mclist = mclist->next) {
3143
3144 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3145 bit = crc & 0xff;
3146 regidx = (bit & 0xe0) >> 5;
3147 bit &= 0x1f;
3148 mc_filter[regidx] |= (1 << bit);
3149 }
3150
3151 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3152 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3153 mc_filter[i]);
3154 }
3155
3156 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3157 }
3158
3159 if (rx_mode != bp->rx_mode) {
3160 bp->rx_mode = rx_mode;
3161 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3162 }
3163
3164 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3165 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3166 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3167
3168 spin_unlock_bh(&bp->phy_lock);
3169 }
3170
3171 static void
3172 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3173 u32 rv2p_proc)
3174 {
3175 int i;
3176 u32 val;
3177
3178
3179 for (i = 0; i < rv2p_code_len; i += 8) {
3180 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3181 rv2p_code++;
3182 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3183 rv2p_code++;
3184
3185 if (rv2p_proc == RV2P_PROC1) {
3186 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3187 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3188 }
3189 else {
3190 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3191 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3192 }
3193 }
3194
3195 /* Reset the processor, un-stall is done later. */
3196 if (rv2p_proc == RV2P_PROC1) {
3197 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3198 }
3199 else {
3200 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3201 }
3202 }
3203
3204 static int
3205 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3206 {
3207 u32 offset;
3208 u32 val;
3209 int rc;
3210
3211 /* Halt the CPU. */
3212 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3213 val |= cpu_reg->mode_value_halt;
3214 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3215 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3216
3217 /* Load the Text area. */
3218 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3219 if (fw->gz_text) {
3220 int j;
3221
3222 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3223 fw->gz_text_len);
3224 if (rc < 0)
3225 return rc;
3226
3227 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3228 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3229 }
3230 }
3231
3232 /* Load the Data area. */
3233 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3234 if (fw->data) {
3235 int j;
3236
3237 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3238 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3239 }
3240 }
3241
3242 /* Load the SBSS area. */
3243 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3244 if (fw->sbss_len) {
3245 int j;
3246
3247 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3248 bnx2_reg_wr_ind(bp, offset, 0);
3249 }
3250 }
3251
3252 /* Load the BSS area. */
3253 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3254 if (fw->bss_len) {
3255 int j;
3256
3257 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3258 bnx2_reg_wr_ind(bp, offset, 0);
3259 }
3260 }
3261
3262 /* Load the Read-Only area. */
3263 offset = cpu_reg->spad_base +
3264 (fw->rodata_addr - cpu_reg->mips_view_base);
3265 if (fw->rodata) {
3266 int j;
3267
3268 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3269 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3270 }
3271 }
3272
3273 /* Clear the pre-fetch instruction. */
3274 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3275 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3276
3277 /* Start the CPU. */
3278 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3279 val &= ~cpu_reg->mode_value_halt;
3280 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3281 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3282
3283 return 0;
3284 }
3285
3286 static int
3287 bnx2_init_cpus(struct bnx2 *bp)
3288 {
3289 struct cpu_reg cpu_reg;
3290 struct fw_info *fw;
3291 int rc, rv2p_len;
3292 void *text, *rv2p;
3293
3294 /* Initialize the RV2P processor. */
3295 text = vmalloc(FW_BUF_SIZE);
3296 if (!text)
3297 return -ENOMEM;
3298 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3299 rv2p = bnx2_xi_rv2p_proc1;
3300 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3301 } else {
3302 rv2p = bnx2_rv2p_proc1;
3303 rv2p_len = sizeof(bnx2_rv2p_proc1);
3304 }
3305 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3306 if (rc < 0)
3307 goto init_cpu_err;
3308
3309 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3310
3311 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3312 rv2p = bnx2_xi_rv2p_proc2;
3313 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3314 } else {
3315 rv2p = bnx2_rv2p_proc2;
3316 rv2p_len = sizeof(bnx2_rv2p_proc2);
3317 }
3318 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3319 if (rc < 0)
3320 goto init_cpu_err;
3321
3322 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3323
3324 /* Initialize the RX Processor. */
3325 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3326 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3327 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3328 cpu_reg.state = BNX2_RXP_CPU_STATE;
3329 cpu_reg.state_value_clear = 0xffffff;
3330 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3331 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3332 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3333 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3334 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3335 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3336 cpu_reg.mips_view_base = 0x8000000;
3337
3338 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3339 fw = &bnx2_rxp_fw_09;
3340 else
3341 fw = &bnx2_rxp_fw_06;
3342
3343 fw->text = text;
3344 rc = load_cpu_fw(bp, &cpu_reg, fw);
3345 if (rc)
3346 goto init_cpu_err;
3347
3348 /* Initialize the TX Processor. */
3349 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3350 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3351 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3352 cpu_reg.state = BNX2_TXP_CPU_STATE;
3353 cpu_reg.state_value_clear = 0xffffff;
3354 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3355 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3356 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3357 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3358 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3359 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3360 cpu_reg.mips_view_base = 0x8000000;
3361
3362 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3363 fw = &bnx2_txp_fw_09;
3364 else
3365 fw = &bnx2_txp_fw_06;
3366
3367 fw->text = text;
3368 rc = load_cpu_fw(bp, &cpu_reg, fw);
3369 if (rc)
3370 goto init_cpu_err;
3371
3372 /* Initialize the TX Patch-up Processor. */
3373 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3374 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3375 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3376 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3377 cpu_reg.state_value_clear = 0xffffff;
3378 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3379 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3380 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3381 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3382 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3383 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3384 cpu_reg.mips_view_base = 0x8000000;
3385
3386 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3387 fw = &bnx2_tpat_fw_09;
3388 else
3389 fw = &bnx2_tpat_fw_06;
3390
3391 fw->text = text;
3392 rc = load_cpu_fw(bp, &cpu_reg, fw);
3393 if (rc)
3394 goto init_cpu_err;
3395
3396 /* Initialize the Completion Processor. */
3397 cpu_reg.mode = BNX2_COM_CPU_MODE;
3398 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3399 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3400 cpu_reg.state = BNX2_COM_CPU_STATE;
3401 cpu_reg.state_value_clear = 0xffffff;
3402 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3403 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3404 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3405 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3406 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3407 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3408 cpu_reg.mips_view_base = 0x8000000;
3409
3410 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3411 fw = &bnx2_com_fw_09;
3412 else
3413 fw = &bnx2_com_fw_06;
3414
3415 fw->text = text;
3416 rc = load_cpu_fw(bp, &cpu_reg, fw);
3417 if (rc)
3418 goto init_cpu_err;
3419
3420 /* Initialize the Command Processor. */
3421 cpu_reg.mode = BNX2_CP_CPU_MODE;
3422 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3423 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3424 cpu_reg.state = BNX2_CP_CPU_STATE;
3425 cpu_reg.state_value_clear = 0xffffff;
3426 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3427 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3428 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3429 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3430 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3431 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3432 cpu_reg.mips_view_base = 0x8000000;
3433
3434 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3435 fw = &bnx2_cp_fw_09;
3436 else
3437 fw = &bnx2_cp_fw_06;
3438
3439 fw->text = text;
3440 rc = load_cpu_fw(bp, &cpu_reg, fw);
3441
3442 init_cpu_err:
3443 vfree(text);
3444 return rc;
3445 }
3446
3447 static int
3448 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3449 {
3450 u16 pmcsr;
3451
3452 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3453
3454 switch (state) {
3455 case PCI_D0: {
3456 u32 val;
3457
3458 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3459 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3460 PCI_PM_CTRL_PME_STATUS);
3461
3462 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3463 /* delay required during transition out of D3hot */
3464 msleep(20);
3465
3466 val = REG_RD(bp, BNX2_EMAC_MODE);
3467 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3468 val &= ~BNX2_EMAC_MODE_MPKT;
3469 REG_WR(bp, BNX2_EMAC_MODE, val);
3470
3471 val = REG_RD(bp, BNX2_RPM_CONFIG);
3472 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3473 REG_WR(bp, BNX2_RPM_CONFIG, val);
3474 break;
3475 }
3476 case PCI_D3hot: {
3477 int i;
3478 u32 val, wol_msg;
3479
3480 if (bp->wol) {
3481 u32 advertising;
3482 u8 autoneg;
3483
3484 autoneg = bp->autoneg;
3485 advertising = bp->advertising;
3486
3487 if (bp->phy_port == PORT_TP) {
3488 bp->autoneg = AUTONEG_SPEED;
3489 bp->advertising = ADVERTISED_10baseT_Half |
3490 ADVERTISED_10baseT_Full |
3491 ADVERTISED_100baseT_Half |
3492 ADVERTISED_100baseT_Full |
3493 ADVERTISED_Autoneg;
3494 }
3495
3496 spin_lock_bh(&bp->phy_lock);
3497 bnx2_setup_phy(bp, bp->phy_port);
3498 spin_unlock_bh(&bp->phy_lock);
3499
3500 bp->autoneg = autoneg;
3501 bp->advertising = advertising;
3502
3503 bnx2_set_mac_addr(bp);
3504
3505 val = REG_RD(bp, BNX2_EMAC_MODE);
3506
3507 /* Enable port mode. */
3508 val &= ~BNX2_EMAC_MODE_PORT;
3509 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3510 BNX2_EMAC_MODE_ACPI_RCVD |
3511 BNX2_EMAC_MODE_MPKT;
3512 if (bp->phy_port == PORT_TP)
3513 val |= BNX2_EMAC_MODE_PORT_MII;
3514 else {
3515 val |= BNX2_EMAC_MODE_PORT_GMII;
3516 if (bp->line_speed == SPEED_2500)
3517 val |= BNX2_EMAC_MODE_25G_MODE;
3518 }
3519
3520 REG_WR(bp, BNX2_EMAC_MODE, val);
3521
3522 /* receive all multicast */
3523 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3524 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3525 0xffffffff);
3526 }
3527 REG_WR(bp, BNX2_EMAC_RX_MODE,
3528 BNX2_EMAC_RX_MODE_SORT_MODE);
3529
3530 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3531 BNX2_RPM_SORT_USER0_MC_EN;
3532 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3533 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3534 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3535 BNX2_RPM_SORT_USER0_ENA);
3536
3537 /* Need to enable EMAC and RPM for WOL. */
3538 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3539 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3540 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3541 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3542
3543 val = REG_RD(bp, BNX2_RPM_CONFIG);
3544 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3545 REG_WR(bp, BNX2_RPM_CONFIG, val);
3546
3547 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3548 }
3549 else {
3550 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3551 }
3552
3553 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3554 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3555
3556 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3557 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3558 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3559
3560 if (bp->wol)
3561 pmcsr |= 3;
3562 }
3563 else {
3564 pmcsr |= 3;
3565 }
3566 if (bp->wol) {
3567 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3568 }
3569 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3570 pmcsr);
3571
3572 /* No more memory access after this point until
3573 * device is brought back to D0.
3574 */
3575 udelay(50);
3576 break;
3577 }
3578 default:
3579 return -EINVAL;
3580 }
3581 return 0;
3582 }
3583
3584 static int
3585 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3586 {
3587 u32 val;
3588 int j;
3589
3590 /* Request access to the flash interface. */
3591 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3592 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3593 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3594 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3595 break;
3596
3597 udelay(5);
3598 }
3599
3600 if (j >= NVRAM_TIMEOUT_COUNT)
3601 return -EBUSY;
3602
3603 return 0;
3604 }
3605
3606 static int
3607 bnx2_release_nvram_lock(struct bnx2 *bp)
3608 {
3609 int j;
3610 u32 val;
3611
3612 /* Relinquish nvram interface. */
3613 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3614
3615 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3616 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3617 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3618 break;
3619
3620 udelay(5);
3621 }
3622
3623 if (j >= NVRAM_TIMEOUT_COUNT)
3624 return -EBUSY;
3625
3626 return 0;
3627 }
3628
3629
3630 static int
3631 bnx2_enable_nvram_write(struct bnx2 *bp)
3632 {
3633 u32 val;
3634
3635 val = REG_RD(bp, BNX2_MISC_CFG);
3636 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3637
3638 if (bp->flash_info->flags & BNX2_NV_WREN) {
3639 int j;
3640
3641 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3642 REG_WR(bp, BNX2_NVM_COMMAND,
3643 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3644
3645 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3646 udelay(5);
3647
3648 val = REG_RD(bp, BNX2_NVM_COMMAND);
3649 if (val & BNX2_NVM_COMMAND_DONE)
3650 break;
3651 }
3652
3653 if (j >= NVRAM_TIMEOUT_COUNT)
3654 return -EBUSY;
3655 }
3656 return 0;
3657 }
3658
3659 static void
3660 bnx2_disable_nvram_write(struct bnx2 *bp)
3661 {
3662 u32 val;
3663
3664 val = REG_RD(bp, BNX2_MISC_CFG);
3665 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3666 }
3667
3668
3669 static void
3670 bnx2_enable_nvram_access(struct bnx2 *bp)
3671 {
3672 u32 val;
3673
3674 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3675 /* Enable both bits, even on read. */
3676 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3677 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3678 }
3679
3680 static void
3681 bnx2_disable_nvram_access(struct bnx2 *bp)
3682 {
3683 u32 val;
3684
3685 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3686 /* Disable both bits, even after read. */
3687 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3688 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3689 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3690 }
3691
3692 static int
3693 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3694 {
3695 u32 cmd;
3696 int j;
3697
3698 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3699 /* Buffered flash, no erase needed */
3700 return 0;
3701
3702 /* Build an erase command */
3703 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3704 BNX2_NVM_COMMAND_DOIT;
3705
3706 /* Need to clear DONE bit separately. */
3707 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3708
3709 /* Address of the NVRAM to read from. */
3710 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3711
3712 /* Issue an erase command. */
3713 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3714
3715 /* Wait for completion. */
3716 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3717 u32 val;
3718
3719 udelay(5);
3720
3721 val = REG_RD(bp, BNX2_NVM_COMMAND);
3722 if (val & BNX2_NVM_COMMAND_DONE)
3723 break;
3724 }
3725
3726 if (j >= NVRAM_TIMEOUT_COUNT)
3727 return -EBUSY;
3728
3729 return 0;
3730 }
3731
3732 static int
3733 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3734 {
3735 u32 cmd;
3736 int j;
3737
3738 /* Build the command word. */
3739 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3740
3741 /* Calculate an offset of a buffered flash, not needed for 5709. */
3742 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3743 offset = ((offset / bp->flash_info->page_size) <<
3744 bp->flash_info->page_bits) +
3745 (offset % bp->flash_info->page_size);
3746 }
3747
3748 /* Need to clear DONE bit separately. */
3749 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3750
3751 /* Address of the NVRAM to read from. */
3752 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3753
3754 /* Issue a read command. */
3755 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3756
3757 /* Wait for completion. */
3758 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3759 u32 val;
3760
3761 udelay(5);
3762
3763 val = REG_RD(bp, BNX2_NVM_COMMAND);
3764 if (val & BNX2_NVM_COMMAND_DONE) {
3765 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3766 memcpy(ret_val, &v, 4);
3767 break;
3768 }
3769 }
3770 if (j >= NVRAM_TIMEOUT_COUNT)
3771 return -EBUSY;
3772
3773 return 0;
3774 }
3775
3776
3777 static int
3778 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3779 {
3780 u32 cmd;
3781 __be32 val32;
3782 int j;
3783
3784 /* Build the command word. */
3785 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3786
3787 /* Calculate an offset of a buffered flash, not needed for 5709. */
3788 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3789 offset = ((offset / bp->flash_info->page_size) <<
3790 bp->flash_info->page_bits) +
3791 (offset % bp->flash_info->page_size);
3792 }
3793
3794 /* Need to clear DONE bit separately. */
3795 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3796
3797 memcpy(&val32, val, 4);
3798
3799 /* Write the data. */
3800 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3801
3802 /* Address of the NVRAM to write to. */
3803 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3804
3805 /* Issue the write command. */
3806 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3807
3808 /* Wait for completion. */
3809 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3810 udelay(5);
3811
3812 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3813 break;
3814 }
3815 if (j >= NVRAM_TIMEOUT_COUNT)
3816 return -EBUSY;
3817
3818 return 0;
3819 }
3820
3821 static int
3822 bnx2_init_nvram(struct bnx2 *bp)
3823 {
3824 u32 val;
3825 int j, entry_count, rc = 0;
3826 struct flash_spec *flash;
3827
3828 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3829 bp->flash_info = &flash_5709;
3830 goto get_flash_size;
3831 }
3832
3833 /* Determine the selected interface. */
3834 val = REG_RD(bp, BNX2_NVM_CFG1);
3835
3836 entry_count = ARRAY_SIZE(flash_table);
3837
3838 if (val & 0x40000000) {
3839
3840 /* Flash interface has been reconfigured */
3841 for (j = 0, flash = &flash_table[0]; j < entry_count;
3842 j++, flash++) {
3843 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3844 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3845 bp->flash_info = flash;
3846 break;
3847 }
3848 }
3849 }
3850 else {
3851 u32 mask;
3852 /* Not yet been reconfigured */
3853
3854 if (val & (1 << 23))
3855 mask = FLASH_BACKUP_STRAP_MASK;
3856 else
3857 mask = FLASH_STRAP_MASK;
3858
3859 for (j = 0, flash = &flash_table[0]; j < entry_count;
3860 j++, flash++) {
3861
3862 if ((val & mask) == (flash->strapping & mask)) {
3863 bp->flash_info = flash;
3864
3865 /* Request access to the flash interface. */
3866 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3867 return rc;
3868
3869 /* Enable access to flash interface */
3870 bnx2_enable_nvram_access(bp);
3871
3872 /* Reconfigure the flash interface */
3873 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3874 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3875 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3876 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3877
3878 /* Disable access to flash interface */
3879 bnx2_disable_nvram_access(bp);
3880 bnx2_release_nvram_lock(bp);
3881
3882 break;
3883 }
3884 }
3885 } /* if (val & 0x40000000) */
3886
3887 if (j == entry_count) {
3888 bp->flash_info = NULL;
3889 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3890 return -ENODEV;
3891 }
3892
3893 get_flash_size:
3894 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
3895 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3896 if (val)
3897 bp->flash_size = val;
3898 else
3899 bp->flash_size = bp->flash_info->total_size;
3900
3901 return rc;
3902 }
3903
3904 static int
3905 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3906 int buf_size)
3907 {
3908 int rc = 0;
3909 u32 cmd_flags, offset32, len32, extra;
3910
3911 if (buf_size == 0)
3912 return 0;
3913
3914 /* Request access to the flash interface. */
3915 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3916 return rc;
3917
3918 /* Enable access to flash interface */
3919 bnx2_enable_nvram_access(bp);
3920
3921 len32 = buf_size;
3922 offset32 = offset;
3923 extra = 0;
3924
3925 cmd_flags = 0;
3926
3927 if (offset32 & 3) {
3928 u8 buf[4];
3929 u32 pre_len;
3930
3931 offset32 &= ~3;
3932 pre_len = 4 - (offset & 3);
3933
3934 if (pre_len >= len32) {
3935 pre_len = len32;
3936 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3937 BNX2_NVM_COMMAND_LAST;
3938 }
3939 else {
3940 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3941 }
3942
3943 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3944
3945 if (rc)
3946 return rc;
3947
3948 memcpy(ret_buf, buf + (offset & 3), pre_len);
3949
3950 offset32 += 4;
3951 ret_buf += pre_len;
3952 len32 -= pre_len;
3953 }
3954 if (len32 & 3) {
3955 extra = 4 - (len32 & 3);
3956 len32 = (len32 + 4) & ~3;
3957 }
3958
3959 if (len32 == 4) {
3960 u8 buf[4];
3961
3962 if (cmd_flags)
3963 cmd_flags = BNX2_NVM_COMMAND_LAST;
3964 else
3965 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3966 BNX2_NVM_COMMAND_LAST;
3967
3968 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3969
3970 memcpy(ret_buf, buf, 4 - extra);
3971 }
3972 else if (len32 > 0) {
3973 u8 buf[4];
3974
3975 /* Read the first word. */
3976 if (cmd_flags)
3977 cmd_flags = 0;
3978 else
3979 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3980
3981 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3982
3983 /* Advance to the next dword. */
3984 offset32 += 4;
3985 ret_buf += 4;
3986 len32 -= 4;
3987
3988 while (len32 > 4 && rc == 0) {
3989 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3990
3991 /* Advance to the next dword. */
3992 offset32 += 4;
3993 ret_buf += 4;
3994 len32 -= 4;
3995 }
3996
3997 if (rc)
3998 return rc;
3999
4000 cmd_flags = BNX2_NVM_COMMAND_LAST;
4001 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4002
4003 memcpy(ret_buf, buf, 4 - extra);
4004 }
4005
4006 /* Disable access to flash interface */
4007 bnx2_disable_nvram_access(bp);
4008
4009 bnx2_release_nvram_lock(bp);
4010
4011 return rc;
4012 }
4013
4014 static int
4015 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4016 int buf_size)
4017 {
4018 u32 written, offset32, len32;
4019 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4020 int rc = 0;
4021 int align_start, align_end;
4022
4023 buf = data_buf;
4024 offset32 = offset;
4025 len32 = buf_size;
4026 align_start = align_end = 0;
4027
4028 if ((align_start = (offset32 & 3))) {
4029 offset32 &= ~3;
4030 len32 += align_start;
4031 if (len32 < 4)
4032 len32 = 4;
4033 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4034 return rc;
4035 }
4036
4037 if (len32 & 3) {
4038 align_end = 4 - (len32 & 3);
4039 len32 += align_end;
4040 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4041 return rc;
4042 }
4043
4044 if (align_start || align_end) {
4045 align_buf = kmalloc(len32, GFP_KERNEL);
4046 if (align_buf == NULL)
4047 return -ENOMEM;
4048 if (align_start) {
4049 memcpy(align_buf, start, 4);
4050 }
4051 if (align_end) {
4052 memcpy(align_buf + len32 - 4, end, 4);
4053 }
4054 memcpy(align_buf + align_start, data_buf, buf_size);
4055 buf = align_buf;
4056 }
4057
4058 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4059 flash_buffer = kmalloc(264, GFP_KERNEL);
4060 if (flash_buffer == NULL) {
4061 rc = -ENOMEM;
4062 goto nvram_write_end;
4063 }
4064 }
4065
4066 written = 0;
4067 while ((written < len32) && (rc == 0)) {
4068 u32 page_start, page_end, data_start, data_end;
4069 u32 addr, cmd_flags;
4070 int i;
4071
4072 /* Find the page_start addr */
4073 page_start = offset32 + written;
4074 page_start -= (page_start % bp->flash_info->page_size);
4075 /* Find the page_end addr */
4076 page_end = page_start + bp->flash_info->page_size;
4077 /* Find the data_start addr */
4078 data_start = (written == 0) ? offset32 : page_start;
4079 /* Find the data_end addr */
4080 data_end = (page_end > offset32 + len32) ?
4081 (offset32 + len32) : page_end;
4082
4083 /* Request access to the flash interface. */
4084 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4085 goto nvram_write_end;
4086
4087 /* Enable access to flash interface */
4088 bnx2_enable_nvram_access(bp);
4089
4090 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4091 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4092 int j;
4093
4094 /* Read the whole page into the buffer
4095 * (non-buffer flash only) */
4096 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4097 if (j == (bp->flash_info->page_size - 4)) {
4098 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4099 }
4100 rc = bnx2_nvram_read_dword(bp,
4101 page_start + j,
4102 &flash_buffer[j],
4103 cmd_flags);
4104
4105 if (rc)
4106 goto nvram_write_end;
4107
4108 cmd_flags = 0;
4109 }
4110 }
4111
4112 /* Enable writes to flash interface (unlock write-protect) */
4113 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4114 goto nvram_write_end;
4115
4116 /* Loop to write back the buffer data from page_start to
4117 * data_start */
4118 i = 0;
4119 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4120 /* Erase the page */
4121 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4122 goto nvram_write_end;
4123
4124 /* Re-enable the write again for the actual write */
4125 bnx2_enable_nvram_write(bp);
4126
4127 for (addr = page_start; addr < data_start;
4128 addr += 4, i += 4) {
4129
4130 rc = bnx2_nvram_write_dword(bp, addr,
4131 &flash_buffer[i], cmd_flags);
4132
4133 if (rc != 0)
4134 goto nvram_write_end;
4135
4136 cmd_flags = 0;
4137 }
4138 }
4139
4140 /* Loop to write the new data from data_start to data_end */
4141 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4142 if ((addr == page_end - 4) ||
4143 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4144 (addr == data_end - 4))) {
4145
4146 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4147 }
4148 rc = bnx2_nvram_write_dword(bp, addr, buf,
4149 cmd_flags);
4150
4151 if (rc != 0)
4152 goto nvram_write_end;
4153
4154 cmd_flags = 0;
4155 buf += 4;
4156 }
4157
4158 /* Loop to write back the buffer data from data_end
4159 * to page_end */
4160 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4161 for (addr = data_end; addr < page_end;
4162 addr += 4, i += 4) {
4163
4164 if (addr == page_end-4) {
4165 cmd_flags = BNX2_NVM_COMMAND_LAST;
4166 }
4167 rc = bnx2_nvram_write_dword(bp, addr,
4168 &flash_buffer[i], cmd_flags);
4169
4170 if (rc != 0)
4171 goto nvram_write_end;
4172
4173 cmd_flags = 0;
4174 }
4175 }
4176
4177 /* Disable writes to flash interface (lock write-protect) */
4178 bnx2_disable_nvram_write(bp);
4179
4180 /* Disable access to flash interface */
4181 bnx2_disable_nvram_access(bp);
4182 bnx2_release_nvram_lock(bp);
4183
4184 /* Increment written */
4185 written += data_end - data_start;
4186 }
4187
4188 nvram_write_end:
4189 kfree(flash_buffer);
4190 kfree(align_buf);
4191 return rc;
4192 }
4193
4194 static void
4195 bnx2_init_remote_phy(struct bnx2 *bp)
4196 {
4197 u32 val;
4198
4199 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4200 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
4201 return;
4202
4203 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4204 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4205 return;
4206
4207 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
4208 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4209
4210 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4211 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4212 bp->phy_port = PORT_FIBRE;
4213 else
4214 bp->phy_port = PORT_TP;
4215
4216 if (netif_running(bp->dev)) {
4217 u32 sig;
4218
4219 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4220 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4221 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4222 }
4223 }
4224 }
4225
4226 static void
4227 bnx2_setup_msix_tbl(struct bnx2 *bp)
4228 {
4229 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4230
4231 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4232 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4233 }
4234
4235 static int
4236 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4237 {
4238 u32 val;
4239 int i, rc = 0;
4240 u8 old_port;
4241
4242 /* Wait for the current PCI transaction to complete before
4243 * issuing a reset. */
4244 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4245 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4246 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4247 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4248 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4249 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4250 udelay(5);
4251
4252 /* Wait for the firmware to tell us it is ok to issue a reset. */
4253 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4254
4255 /* Deposit a driver reset signature so the firmware knows that
4256 * this is a soft reset. */
4257 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4258 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4259
4260 /* Do a dummy read to force the chip to complete all current transaction
4261 * before we issue a reset. */
4262 val = REG_RD(bp, BNX2_MISC_ID);
4263
4264 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4265 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4266 REG_RD(bp, BNX2_MISC_COMMAND);
4267 udelay(5);
4268
4269 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4270 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4271
4272 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4273
4274 } else {
4275 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4276 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4277 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4278
4279 /* Chip reset. */
4280 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4281
4282 /* Reading back any register after chip reset will hang the
4283 * bus on 5706 A0 and A1. The msleep below provides plenty
4284 * of margin for write posting.
4285 */
4286 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4287 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4288 msleep(20);
4289
4290 /* Reset takes approximate 30 usec */
4291 for (i = 0; i < 10; i++) {
4292 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4293 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4294 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4295 break;
4296 udelay(10);
4297 }
4298
4299 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4300 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4301 printk(KERN_ERR PFX "Chip reset did not complete\n");
4302 return -EBUSY;
4303 }
4304 }
4305
4306 /* Make sure byte swapping is properly configured. */
4307 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4308 if (val != 0x01020304) {
4309 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4310 return -ENODEV;
4311 }
4312
4313 /* Wait for the firmware to finish its initialization. */
4314 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4315 if (rc)
4316 return rc;
4317
4318 spin_lock_bh(&bp->phy_lock);
4319 old_port = bp->phy_port;
4320 bnx2_init_remote_phy(bp);
4321 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4322 old_port != bp->phy_port)
4323 bnx2_set_default_remote_link(bp);
4324 spin_unlock_bh(&bp->phy_lock);
4325
4326 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4327 /* Adjust the voltage regular to two steps lower. The default
4328 * of this register is 0x0000000e. */
4329 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4330
4331 /* Remove bad rbuf memory from the free pool. */
4332 rc = bnx2_alloc_bad_rbuf(bp);
4333 }
4334
4335 if (bp->flags & BNX2_FLAG_USING_MSIX)
4336 bnx2_setup_msix_tbl(bp);
4337
4338 return rc;
4339 }
4340
4341 static int
4342 bnx2_init_chip(struct bnx2 *bp)
4343 {
4344 u32 val;
4345 int rc, i;
4346
4347 /* Make sure the interrupt is not active. */
4348 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4349
4350 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4351 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4352 #ifdef __BIG_ENDIAN
4353 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4354 #endif
4355 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4356 DMA_READ_CHANS << 12 |
4357 DMA_WRITE_CHANS << 16;
4358
4359 val |= (0x2 << 20) | (1 << 11);
4360
4361 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4362 val |= (1 << 23);
4363
4364 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4365 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4366 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4367
4368 REG_WR(bp, BNX2_DMA_CONFIG, val);
4369
4370 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4371 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4372 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4373 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4374 }
4375
4376 if (bp->flags & BNX2_FLAG_PCIX) {
4377 u16 val16;
4378
4379 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4380 &val16);
4381 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4382 val16 & ~PCI_X_CMD_ERO);
4383 }
4384
4385 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4386 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4387 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4388 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4389
4390 /* Initialize context mapping and zero out the quick contexts. The
4391 * context block must have already been enabled. */
4392 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4393 rc = bnx2_init_5709_context(bp);
4394 if (rc)
4395 return rc;
4396 } else
4397 bnx2_init_context(bp);
4398
4399 if ((rc = bnx2_init_cpus(bp)) != 0)
4400 return rc;
4401
4402 bnx2_init_nvram(bp);
4403
4404 bnx2_set_mac_addr(bp);
4405
4406 val = REG_RD(bp, BNX2_MQ_CONFIG);
4407 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4408 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4409 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4410 val |= BNX2_MQ_CONFIG_HALT_DIS;
4411
4412 REG_WR(bp, BNX2_MQ_CONFIG, val);
4413
4414 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4415 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4416 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4417
4418 val = (BCM_PAGE_BITS - 8) << 24;
4419 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4420
4421 /* Configure page size. */
4422 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4423 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4424 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4425 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4426
4427 val = bp->mac_addr[0] +
4428 (bp->mac_addr[1] << 8) +
4429 (bp->mac_addr[2] << 16) +
4430 bp->mac_addr[3] +
4431 (bp->mac_addr[4] << 8) +
4432 (bp->mac_addr[5] << 16);
4433 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4434
4435 /* Program the MTU. Also include 4 bytes for CRC32. */
4436 val = bp->dev->mtu + ETH_HLEN + 4;
4437 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4438 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4439 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4440
4441 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4442 bp->bnx2_napi[i].last_status_idx = 0;
4443
4444 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4445
4446 /* Set up how to generate a link change interrupt. */
4447 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4448
4449 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4450 (u64) bp->status_blk_mapping & 0xffffffff);
4451 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4452
4453 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4454 (u64) bp->stats_blk_mapping & 0xffffffff);
4455 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4456 (u64) bp->stats_blk_mapping >> 32);
4457
4458 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4459 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4460
4461 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4462 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4463
4464 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4465 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4466
4467 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4468
4469 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4470
4471 REG_WR(bp, BNX2_HC_COM_TICKS,
4472 (bp->com_ticks_int << 16) | bp->com_ticks);
4473
4474 REG_WR(bp, BNX2_HC_CMD_TICKS,
4475 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4476
4477 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4478 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4479 else
4480 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4481 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4482
4483 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4484 val = BNX2_HC_CONFIG_COLLECT_STATS;
4485 else {
4486 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4487 BNX2_HC_CONFIG_COLLECT_STATS;
4488 }
4489
4490 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4491 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4492 BNX2_HC_SB_CONFIG_1;
4493
4494 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4495 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4496
4497 REG_WR(bp, base,
4498 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4499 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4500
4501 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4502 (bp->tx_quick_cons_trip_int << 16) |
4503 bp->tx_quick_cons_trip);
4504
4505 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4506 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4507
4508 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4509 }
4510
4511 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4512 val |= BNX2_HC_CONFIG_ONE_SHOT;
4513
4514 REG_WR(bp, BNX2_HC_CONFIG, val);
4515
4516 /* Clear internal stats counters. */
4517 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4518
4519 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4520
4521 /* Initialize the receive filter. */
4522 bnx2_set_rx_mode(bp->dev);
4523
4524 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4525 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4526 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4527 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4528 }
4529 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4530 0);
4531
4532 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4533 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4534
4535 udelay(20);
4536
4537 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4538
4539 return rc;
4540 }
4541
4542 static void
4543 bnx2_clear_ring_states(struct bnx2 *bp)
4544 {
4545 struct bnx2_napi *bnapi;
4546 int i;
4547
4548 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4549 bnapi = &bp->bnx2_napi[i];
4550
4551 bnapi->tx_cons = 0;
4552 bnapi->hw_tx_cons = 0;
4553 bnapi->rx_prod_bseq = 0;
4554 bnapi->rx_prod = 0;
4555 bnapi->rx_cons = 0;
4556 bnapi->rx_pg_prod = 0;
4557 bnapi->rx_pg_cons = 0;
4558 }
4559 }
4560
4561 static void
4562 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4563 {
4564 u32 val, offset0, offset1, offset2, offset3;
4565 u32 cid_addr = GET_CID_ADDR(cid);
4566
4567 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4568 offset0 = BNX2_L2CTX_TYPE_XI;
4569 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4570 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4571 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4572 } else {
4573 offset0 = BNX2_L2CTX_TYPE;
4574 offset1 = BNX2_L2CTX_CMD_TYPE;
4575 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4576 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4577 }
4578 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4579 bnx2_ctx_wr(bp, cid_addr, offset0, val);
4580
4581 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4582 bnx2_ctx_wr(bp, cid_addr, offset1, val);
4583
4584 val = (u64) bp->tx_desc_mapping >> 32;
4585 bnx2_ctx_wr(bp, cid_addr, offset2, val);
4586
4587 val = (u64) bp->tx_desc_mapping & 0xffffffff;
4588 bnx2_ctx_wr(bp, cid_addr, offset3, val);
4589 }
4590
4591 static void
4592 bnx2_init_tx_ring(struct bnx2 *bp)
4593 {
4594 struct tx_bd *txbd;
4595 u32 cid = TX_CID;
4596 struct bnx2_napi *bnapi;
4597
4598 bp->tx_vec = 0;
4599 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4600 cid = TX_TSS_CID;
4601 bp->tx_vec = BNX2_TX_VEC;
4602 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4603 (TX_TSS_CID << 7));
4604 }
4605 bnapi = &bp->bnx2_napi[bp->tx_vec];
4606
4607 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4608
4609 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4610
4611 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4612 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4613
4614 bp->tx_prod = 0;
4615 bp->tx_prod_bseq = 0;
4616
4617 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4618 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4619
4620 bnx2_init_tx_context(bp, cid);
4621 }
4622
4623 static void
4624 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4625 int num_rings)
4626 {
4627 int i;
4628 struct rx_bd *rxbd;
4629
4630 for (i = 0; i < num_rings; i++) {
4631 int j;
4632
4633 rxbd = &rx_ring[i][0];
4634 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4635 rxbd->rx_bd_len = buf_size;
4636 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4637 }
4638 if (i == (num_rings - 1))
4639 j = 0;
4640 else
4641 j = i + 1;
4642 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4643 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4644 }
4645 }
4646
4647 static void
4648 bnx2_init_rx_ring(struct bnx2 *bp)
4649 {
4650 int i;
4651 u16 prod, ring_prod;
4652 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
4653 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
4654
4655 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4656 bp->rx_buf_use_size, bp->rx_max_ring);
4657
4658 bnx2_init_rx_context0(bp);
4659
4660 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4661 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4662 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4663 }
4664
4665 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4666 if (bp->rx_pg_ring_size) {
4667 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4668 bp->rx_pg_desc_mapping,
4669 PAGE_SIZE, bp->rx_max_pg_ring);
4670 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4671 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4672 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4673 BNX2_L2CTX_RBDC_JUMBO_KEY);
4674
4675 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
4676 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4677
4678 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
4679 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4680
4681 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4682 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4683 }
4684
4685 val = (u64) bp->rx_desc_mapping[0] >> 32;
4686 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4687
4688 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4689 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4690
4691 ring_prod = prod = bnapi->rx_pg_prod;
4692 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4693 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4694 break;
4695 prod = NEXT_RX_BD(prod);
4696 ring_prod = RX_PG_RING_IDX(prod);
4697 }
4698 bnapi->rx_pg_prod = prod;
4699
4700 ring_prod = prod = bnapi->rx_prod;
4701 for (i = 0; i < bp->rx_ring_size; i++) {
4702 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
4703 break;
4704 }
4705 prod = NEXT_RX_BD(prod);
4706 ring_prod = RX_RING_IDX(prod);
4707 }
4708 bnapi->rx_prod = prod;
4709
4710 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4711 bnapi->rx_pg_prod);
4712 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4713
4714 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
4715 }
4716
4717 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4718 {
4719 u32 max, num_rings = 1;
4720
4721 while (ring_size > MAX_RX_DESC_CNT) {
4722 ring_size -= MAX_RX_DESC_CNT;
4723 num_rings++;
4724 }
4725 /* round to next power of 2 */
4726 max = max_size;
4727 while ((max & num_rings) == 0)
4728 max >>= 1;
4729
4730 if (num_rings != max)
4731 max <<= 1;
4732
4733 return max;
4734 }
4735
4736 static void
4737 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4738 {
4739 u32 rx_size, rx_space, jumbo_size;
4740
4741 /* 8 for CRC and VLAN */
4742 rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4743
4744 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4745 sizeof(struct skb_shared_info);
4746
4747 bp->rx_copy_thresh = RX_COPY_THRESH;
4748 bp->rx_pg_ring_size = 0;
4749 bp->rx_max_pg_ring = 0;
4750 bp->rx_max_pg_ring_idx = 0;
4751 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4752 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4753
4754 jumbo_size = size * pages;
4755 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4756 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4757
4758 bp->rx_pg_ring_size = jumbo_size;
4759 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4760 MAX_RX_PG_RINGS);
4761 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4762 rx_size = RX_COPY_THRESH + bp->rx_offset;
4763 bp->rx_copy_thresh = 0;
4764 }
4765
4766 bp->rx_buf_use_size = rx_size;
4767 /* hw alignment */
4768 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4769 bp->rx_jumbo_thresh = rx_size - bp->rx_offset;
4770 bp->rx_ring_size = size;
4771 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4772 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4773 }
4774
4775 static void
4776 bnx2_free_tx_skbs(struct bnx2 *bp)
4777 {
4778 int i;
4779
4780 if (bp->tx_buf_ring == NULL)
4781 return;
4782
4783 for (i = 0; i < TX_DESC_CNT; ) {
4784 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4785 struct sk_buff *skb = tx_buf->skb;
4786 int j, last;
4787
4788 if (skb == NULL) {
4789 i++;
4790 continue;
4791 }
4792
4793 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4794 skb_headlen(skb), PCI_DMA_TODEVICE);
4795
4796 tx_buf->skb = NULL;
4797
4798 last = skb_shinfo(skb)->nr_frags;
4799 for (j = 0; j < last; j++) {
4800 tx_buf = &bp->tx_buf_ring[i + j + 1];
4801 pci_unmap_page(bp->pdev,
4802 pci_unmap_addr(tx_buf, mapping),
4803 skb_shinfo(skb)->frags[j].size,
4804 PCI_DMA_TODEVICE);
4805 }
4806 dev_kfree_skb(skb);
4807 i += j + 1;
4808 }
4809
4810 }
4811
4812 static void
4813 bnx2_free_rx_skbs(struct bnx2 *bp)
4814 {
4815 int i;
4816
4817 if (bp->rx_buf_ring == NULL)
4818 return;
4819
4820 for (i = 0; i < bp->rx_max_ring_idx; i++) {
4821 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4822 struct sk_buff *skb = rx_buf->skb;
4823
4824 if (skb == NULL)
4825 continue;
4826
4827 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4828 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4829
4830 rx_buf->skb = NULL;
4831
4832 dev_kfree_skb(skb);
4833 }
4834 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4835 bnx2_free_rx_page(bp, i);
4836 }
4837
4838 static void
4839 bnx2_free_skbs(struct bnx2 *bp)
4840 {
4841 bnx2_free_tx_skbs(bp);
4842 bnx2_free_rx_skbs(bp);
4843 }
4844
4845 static int
4846 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4847 {
4848 int rc;
4849
4850 rc = bnx2_reset_chip(bp, reset_code);
4851 bnx2_free_skbs(bp);
4852 if (rc)
4853 return rc;
4854
4855 if ((rc = bnx2_init_chip(bp)) != 0)
4856 return rc;
4857
4858 bnx2_clear_ring_states(bp);
4859 bnx2_init_tx_ring(bp);
4860 bnx2_init_rx_ring(bp);
4861 return 0;
4862 }
4863
4864 static int
4865 bnx2_init_nic(struct bnx2 *bp)
4866 {
4867 int rc;
4868
4869 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4870 return rc;
4871
4872 spin_lock_bh(&bp->phy_lock);
4873 bnx2_init_phy(bp);
4874 bnx2_set_link(bp);
4875 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4876 bnx2_remote_phy_event(bp);
4877 spin_unlock_bh(&bp->phy_lock);
4878 return 0;
4879 }
4880
4881 static int
4882 bnx2_test_registers(struct bnx2 *bp)
4883 {
4884 int ret;
4885 int i, is_5709;
4886 static const struct {
4887 u16 offset;
4888 u16 flags;
4889 #define BNX2_FL_NOT_5709 1
4890 u32 rw_mask;
4891 u32 ro_mask;
4892 } reg_tbl[] = {
4893 { 0x006c, 0, 0x00000000, 0x0000003f },
4894 { 0x0090, 0, 0xffffffff, 0x00000000 },
4895 { 0x0094, 0, 0x00000000, 0x00000000 },
4896
4897 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4898 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4899 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4900 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4901 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4902 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4903 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4904 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4905 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4906
4907 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4908 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4909 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4910 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4911 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4912 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4913
4914 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4915 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4916 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
4917
4918 { 0x1000, 0, 0x00000000, 0x00000001 },
4919 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
4920
4921 { 0x1408, 0, 0x01c00800, 0x00000000 },
4922 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4923 { 0x14a8, 0, 0x00000000, 0x000001ff },
4924 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4925 { 0x14b0, 0, 0x00000002, 0x00000001 },
4926 { 0x14b8, 0, 0x00000000, 0x00000000 },
4927 { 0x14c0, 0, 0x00000000, 0x00000009 },
4928 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4929 { 0x14cc, 0, 0x00000000, 0x00000001 },
4930 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4931
4932 { 0x1800, 0, 0x00000000, 0x00000001 },
4933 { 0x1804, 0, 0x00000000, 0x00000003 },
4934
4935 { 0x2800, 0, 0x00000000, 0x00000001 },
4936 { 0x2804, 0, 0x00000000, 0x00003f01 },
4937 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4938 { 0x2810, 0, 0xffff0000, 0x00000000 },
4939 { 0x2814, 0, 0xffff0000, 0x00000000 },
4940 { 0x2818, 0, 0xffff0000, 0x00000000 },
4941 { 0x281c, 0, 0xffff0000, 0x00000000 },
4942 { 0x2834, 0, 0xffffffff, 0x00000000 },
4943 { 0x2840, 0, 0x00000000, 0xffffffff },
4944 { 0x2844, 0, 0x00000000, 0xffffffff },
4945 { 0x2848, 0, 0xffffffff, 0x00000000 },
4946 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4947
4948 { 0x2c00, 0, 0x00000000, 0x00000011 },
4949 { 0x2c04, 0, 0x00000000, 0x00030007 },
4950
4951 { 0x3c00, 0, 0x00000000, 0x00000001 },
4952 { 0x3c04, 0, 0x00000000, 0x00070000 },
4953 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4954 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4955 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4956 { 0x3c14, 0, 0x00000000, 0xffffffff },
4957 { 0x3c18, 0, 0x00000000, 0xffffffff },
4958 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4959 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4960
4961 { 0x5004, 0, 0x00000000, 0x0000007f },
4962 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4963
4964 { 0x5c00, 0, 0x00000000, 0x00000001 },
4965 { 0x5c04, 0, 0x00000000, 0x0003000f },
4966 { 0x5c08, 0, 0x00000003, 0x00000000 },
4967 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4968 { 0x5c10, 0, 0x00000000, 0xffffffff },
4969 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4970 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4971 { 0x5c88, 0, 0x00000000, 0x00077373 },
4972 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4973
4974 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4975 { 0x680c, 0, 0xffffffff, 0x00000000 },
4976 { 0x6810, 0, 0xffffffff, 0x00000000 },
4977 { 0x6814, 0, 0xffffffff, 0x00000000 },
4978 { 0x6818, 0, 0xffffffff, 0x00000000 },
4979 { 0x681c, 0, 0xffffffff, 0x00000000 },
4980 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4981 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4982 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4983 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4984 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4985 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4986 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4987 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4988 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4989 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4990 { 0x684c, 0, 0xffffffff, 0x00000000 },
4991 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4992 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4993 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4994 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4995 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4996 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4997
4998 { 0xffff, 0, 0x00000000, 0x00000000 },
4999 };
5000
5001 ret = 0;
5002 is_5709 = 0;
5003 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5004 is_5709 = 1;
5005
5006 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5007 u32 offset, rw_mask, ro_mask, save_val, val;
5008 u16 flags = reg_tbl[i].flags;
5009
5010 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5011 continue;
5012
5013 offset = (u32) reg_tbl[i].offset;
5014 rw_mask = reg_tbl[i].rw_mask;
5015 ro_mask = reg_tbl[i].ro_mask;
5016
5017 save_val = readl(bp->regview + offset);
5018
5019 writel(0, bp->regview + offset);
5020
5021 val = readl(bp->regview + offset);
5022 if ((val & rw_mask) != 0) {
5023 goto reg_test_err;
5024 }
5025
5026 if ((val & ro_mask) != (save_val & ro_mask)) {
5027 goto reg_test_err;
5028 }
5029
5030 writel(0xffffffff, bp->regview + offset);
5031
5032 val = readl(bp->regview + offset);
5033 if ((val & rw_mask) != rw_mask) {
5034 goto reg_test_err;
5035 }
5036
5037 if ((val & ro_mask) != (save_val & ro_mask)) {
5038 goto reg_test_err;
5039 }
5040
5041 writel(save_val, bp->regview + offset);
5042 continue;
5043
5044 reg_test_err:
5045 writel(save_val, bp->regview + offset);
5046 ret = -ENODEV;
5047 break;
5048 }
5049 return ret;
5050 }
5051
5052 static int
5053 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5054 {
5055 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5056 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5057 int i;
5058
5059 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5060 u32 offset;
5061
5062 for (offset = 0; offset < size; offset += 4) {
5063
5064 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5065
5066 if (bnx2_reg_rd_ind(bp, start + offset) !=
5067 test_pattern[i]) {
5068 return -ENODEV;
5069 }
5070 }
5071 }
5072 return 0;
5073 }
5074
5075 static int
5076 bnx2_test_memory(struct bnx2 *bp)
5077 {
5078 int ret = 0;
5079 int i;
5080 static struct mem_entry {
5081 u32 offset;
5082 u32 len;
5083 } mem_tbl_5706[] = {
5084 { 0x60000, 0x4000 },
5085 { 0xa0000, 0x3000 },
5086 { 0xe0000, 0x4000 },
5087 { 0x120000, 0x4000 },
5088 { 0x1a0000, 0x4000 },
5089 { 0x160000, 0x4000 },
5090 { 0xffffffff, 0 },
5091 },
5092 mem_tbl_5709[] = {
5093 { 0x60000, 0x4000 },
5094 { 0xa0000, 0x3000 },
5095 { 0xe0000, 0x4000 },
5096 { 0x120000, 0x4000 },
5097 { 0x1a0000, 0x4000 },
5098 { 0xffffffff, 0 },
5099 };
5100 struct mem_entry *mem_tbl;
5101
5102 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5103 mem_tbl = mem_tbl_5709;
5104 else
5105 mem_tbl = mem_tbl_5706;
5106
5107 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5108 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5109 mem_tbl[i].len)) != 0) {
5110 return ret;
5111 }
5112 }
5113
5114 return ret;
5115 }
5116
5117 #define BNX2_MAC_LOOPBACK 0
5118 #define BNX2_PHY_LOOPBACK 1
5119
5120 static int
5121 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5122 {
5123 unsigned int pkt_size, num_pkts, i;
5124 struct sk_buff *skb, *rx_skb;
5125 unsigned char *packet;
5126 u16 rx_start_idx, rx_idx;
5127 dma_addr_t map;
5128 struct tx_bd *txbd;
5129 struct sw_bd *rx_buf;
5130 struct l2_fhdr *rx_hdr;
5131 int ret = -ENODEV;
5132 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5133
5134 tx_napi = bnapi;
5135 if (bp->flags & BNX2_FLAG_USING_MSIX)
5136 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
5137
5138 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5139 bp->loopback = MAC_LOOPBACK;
5140 bnx2_set_mac_loopback(bp);
5141 }
5142 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5143 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5144 return 0;
5145
5146 bp->loopback = PHY_LOOPBACK;
5147 bnx2_set_phy_loopback(bp);
5148 }
5149 else
5150 return -EINVAL;
5151
5152 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5153 skb = netdev_alloc_skb(bp->dev, pkt_size);
5154 if (!skb)
5155 return -ENOMEM;
5156 packet = skb_put(skb, pkt_size);
5157 memcpy(packet, bp->dev->dev_addr, 6);
5158 memset(packet + 6, 0x0, 8);
5159 for (i = 14; i < pkt_size; i++)
5160 packet[i] = (unsigned char) (i & 0xff);
5161
5162 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5163 PCI_DMA_TODEVICE);
5164
5165 REG_WR(bp, BNX2_HC_COMMAND,
5166 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5167
5168 REG_RD(bp, BNX2_HC_COMMAND);
5169
5170 udelay(5);
5171 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5172
5173 num_pkts = 0;
5174
5175 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
5176
5177 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5178 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5179 txbd->tx_bd_mss_nbytes = pkt_size;
5180 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5181
5182 num_pkts++;
5183 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5184 bp->tx_prod_bseq += pkt_size;
5185
5186 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5187 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5188
5189 udelay(100);
5190
5191 REG_WR(bp, BNX2_HC_COMMAND,
5192 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5193
5194 REG_RD(bp, BNX2_HC_COMMAND);
5195
5196 udelay(5);
5197
5198 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5199 dev_kfree_skb(skb);
5200
5201 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
5202 goto loopback_test_done;
5203
5204 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5205 if (rx_idx != rx_start_idx + num_pkts) {
5206 goto loopback_test_done;
5207 }
5208
5209 rx_buf = &bp->rx_buf_ring[rx_start_idx];
5210 rx_skb = rx_buf->skb;
5211
5212 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5213 skb_reserve(rx_skb, bp->rx_offset);
5214
5215 pci_dma_sync_single_for_cpu(bp->pdev,
5216 pci_unmap_addr(rx_buf, mapping),
5217 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5218
5219 if (rx_hdr->l2_fhdr_status &
5220 (L2_FHDR_ERRORS_BAD_CRC |
5221 L2_FHDR_ERRORS_PHY_DECODE |
5222 L2_FHDR_ERRORS_ALIGNMENT |
5223 L2_FHDR_ERRORS_TOO_SHORT |
5224 L2_FHDR_ERRORS_GIANT_FRAME)) {
5225
5226 goto loopback_test_done;
5227 }
5228
5229 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5230 goto loopback_test_done;
5231 }
5232
5233 for (i = 14; i < pkt_size; i++) {
5234 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5235 goto loopback_test_done;
5236 }
5237 }
5238
5239 ret = 0;
5240
5241 loopback_test_done:
5242 bp->loopback = 0;
5243 return ret;
5244 }
5245
5246 #define BNX2_MAC_LOOPBACK_FAILED 1
5247 #define BNX2_PHY_LOOPBACK_FAILED 2
5248 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5249 BNX2_PHY_LOOPBACK_FAILED)
5250
5251 static int
5252 bnx2_test_loopback(struct bnx2 *bp)
5253 {
5254 int rc = 0;
5255
5256 if (!netif_running(bp->dev))
5257 return BNX2_LOOPBACK_FAILED;
5258
5259 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5260 spin_lock_bh(&bp->phy_lock);
5261 bnx2_init_phy(bp);
5262 spin_unlock_bh(&bp->phy_lock);
5263 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5264 rc |= BNX2_MAC_LOOPBACK_FAILED;
5265 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5266 rc |= BNX2_PHY_LOOPBACK_FAILED;
5267 return rc;
5268 }
5269
5270 #define NVRAM_SIZE 0x200
5271 #define CRC32_RESIDUAL 0xdebb20e3
5272
5273 static int
5274 bnx2_test_nvram(struct bnx2 *bp)
5275 {
5276 __be32 buf[NVRAM_SIZE / 4];
5277 u8 *data = (u8 *) buf;
5278 int rc = 0;
5279 u32 magic, csum;
5280
5281 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5282 goto test_nvram_done;
5283
5284 magic = be32_to_cpu(buf[0]);
5285 if (magic != 0x669955aa) {
5286 rc = -ENODEV;
5287 goto test_nvram_done;
5288 }
5289
5290 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5291 goto test_nvram_done;
5292
5293 csum = ether_crc_le(0x100, data);
5294 if (csum != CRC32_RESIDUAL) {
5295 rc = -ENODEV;
5296 goto test_nvram_done;
5297 }
5298
5299 csum = ether_crc_le(0x100, data + 0x100);
5300 if (csum != CRC32_RESIDUAL) {
5301 rc = -ENODEV;
5302 }
5303
5304 test_nvram_done:
5305 return rc;
5306 }
5307
5308 static int
5309 bnx2_test_link(struct bnx2 *bp)
5310 {
5311 u32 bmsr;
5312
5313 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5314 if (bp->link_up)
5315 return 0;
5316 return -ENODEV;
5317 }
5318 spin_lock_bh(&bp->phy_lock);
5319 bnx2_enable_bmsr1(bp);
5320 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5321 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5322 bnx2_disable_bmsr1(bp);
5323 spin_unlock_bh(&bp->phy_lock);
5324
5325 if (bmsr & BMSR_LSTATUS) {
5326 return 0;
5327 }
5328 return -ENODEV;
5329 }
5330
5331 static int
5332 bnx2_test_intr(struct bnx2 *bp)
5333 {
5334 int i;
5335 u16 status_idx;
5336
5337 if (!netif_running(bp->dev))
5338 return -ENODEV;
5339
5340 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5341
5342 /* This register is not touched during run-time. */
5343 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5344 REG_RD(bp, BNX2_HC_COMMAND);
5345
5346 for (i = 0; i < 10; i++) {
5347 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5348 status_idx) {
5349
5350 break;
5351 }
5352
5353 msleep_interruptible(10);
5354 }
5355 if (i < 10)
5356 return 0;
5357
5358 return -ENODEV;
5359 }
5360
5361 /* Determining link for parallel detection. */
5362 static int
5363 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5364 {
5365 u32 mode_ctl, an_dbg, exp;
5366
5367 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5368 return 0;
5369
5370 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5371 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5372
5373 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5374 return 0;
5375
5376 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5377 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5378 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5379
5380 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5381 return 0;
5382
5383 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5384 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5385 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5386
5387 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5388 return 0;
5389
5390 return 1;
5391 }
5392
5393 static void
5394 bnx2_5706_serdes_timer(struct bnx2 *bp)
5395 {
5396 int check_link = 1;
5397
5398 spin_lock(&bp->phy_lock);
5399 if (bp->serdes_an_pending) {
5400 bp->serdes_an_pending--;
5401 check_link = 0;
5402 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5403 u32 bmcr;
5404
5405 bp->current_interval = bp->timer_interval;
5406
5407 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5408
5409 if (bmcr & BMCR_ANENABLE) {
5410 if (bnx2_5706_serdes_has_link(bp)) {
5411 bmcr &= ~BMCR_ANENABLE;
5412 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5413 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5414 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5415 }
5416 }
5417 }
5418 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5419 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5420 u32 phy2;
5421
5422 bnx2_write_phy(bp, 0x17, 0x0f01);
5423 bnx2_read_phy(bp, 0x15, &phy2);
5424 if (phy2 & 0x20) {
5425 u32 bmcr;
5426
5427 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5428 bmcr |= BMCR_ANENABLE;
5429 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5430
5431 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5432 }
5433 } else
5434 bp->current_interval = bp->timer_interval;
5435
5436 if (check_link) {
5437 u32 val;
5438
5439 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5440 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5441 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5442
5443 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5444 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5445 bnx2_5706s_force_link_dn(bp, 1);
5446 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5447 } else
5448 bnx2_set_link(bp);
5449 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5450 bnx2_set_link(bp);
5451 }
5452 spin_unlock(&bp->phy_lock);
5453 }
5454
5455 static void
5456 bnx2_5708_serdes_timer(struct bnx2 *bp)
5457 {
5458 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5459 return;
5460
5461 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5462 bp->serdes_an_pending = 0;
5463 return;
5464 }
5465
5466 spin_lock(&bp->phy_lock);
5467 if (bp->serdes_an_pending)
5468 bp->serdes_an_pending--;
5469 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5470 u32 bmcr;
5471
5472 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5473 if (bmcr & BMCR_ANENABLE) {
5474 bnx2_enable_forced_2g5(bp);
5475 bp->current_interval = SERDES_FORCED_TIMEOUT;
5476 } else {
5477 bnx2_disable_forced_2g5(bp);
5478 bp->serdes_an_pending = 2;
5479 bp->current_interval = bp->timer_interval;
5480 }
5481
5482 } else
5483 bp->current_interval = bp->timer_interval;
5484
5485 spin_unlock(&bp->phy_lock);
5486 }
5487
5488 static void
5489 bnx2_timer(unsigned long data)
5490 {
5491 struct bnx2 *bp = (struct bnx2 *) data;
5492
5493 if (!netif_running(bp->dev))
5494 return;
5495
5496 if (atomic_read(&bp->intr_sem) != 0)
5497 goto bnx2_restart_timer;
5498
5499 bnx2_send_heart_beat(bp);
5500
5501 bp->stats_blk->stat_FwRxDrop =
5502 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5503
5504 /* workaround occasional corrupted counters */
5505 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5506 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5507 BNX2_HC_COMMAND_STATS_NOW);
5508
5509 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5510 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5511 bnx2_5706_serdes_timer(bp);
5512 else
5513 bnx2_5708_serdes_timer(bp);
5514 }
5515
5516 bnx2_restart_timer:
5517 mod_timer(&bp->timer, jiffies + bp->current_interval);
5518 }
5519
5520 static int
5521 bnx2_request_irq(struct bnx2 *bp)
5522 {
5523 struct net_device *dev = bp->dev;
5524 unsigned long flags;
5525 struct bnx2_irq *irq;
5526 int rc = 0, i;
5527
5528 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5529 flags = 0;
5530 else
5531 flags = IRQF_SHARED;
5532
5533 for (i = 0; i < bp->irq_nvecs; i++) {
5534 irq = &bp->irq_tbl[i];
5535 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5536 dev);
5537 if (rc)
5538 break;
5539 irq->requested = 1;
5540 }
5541 return rc;
5542 }
5543
5544 static void
5545 bnx2_free_irq(struct bnx2 *bp)
5546 {
5547 struct net_device *dev = bp->dev;
5548 struct bnx2_irq *irq;
5549 int i;
5550
5551 for (i = 0; i < bp->irq_nvecs; i++) {
5552 irq = &bp->irq_tbl[i];
5553 if (irq->requested)
5554 free_irq(irq->vector, dev);
5555 irq->requested = 0;
5556 }
5557 if (bp->flags & BNX2_FLAG_USING_MSI)
5558 pci_disable_msi(bp->pdev);
5559 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5560 pci_disable_msix(bp->pdev);
5561
5562 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5563 }
5564
5565 static void
5566 bnx2_enable_msix(struct bnx2 *bp)
5567 {
5568 int i, rc;
5569 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5570
5571 bnx2_setup_msix_tbl(bp);
5572 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5573 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5574 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5575
5576 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5577 msix_ent[i].entry = i;
5578 msix_ent[i].vector = 0;
5579 }
5580
5581 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5582 if (rc != 0)
5583 return;
5584
5585 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5586 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5587
5588 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5589 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5590 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5591 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5592
5593 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
5594 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5595 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5596 bp->irq_tbl[i].vector = msix_ent[i].vector;
5597 }
5598
5599 static void
5600 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5601 {
5602 bp->irq_tbl[0].handler = bnx2_interrupt;
5603 strcpy(bp->irq_tbl[0].name, bp->dev->name);
5604 bp->irq_nvecs = 1;
5605 bp->irq_tbl[0].vector = bp->pdev->irq;
5606
5607 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5608 bnx2_enable_msix(bp);
5609
5610 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5611 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5612 if (pci_enable_msi(bp->pdev) == 0) {
5613 bp->flags |= BNX2_FLAG_USING_MSI;
5614 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5615 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5616 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5617 } else
5618 bp->irq_tbl[0].handler = bnx2_msi;
5619
5620 bp->irq_tbl[0].vector = bp->pdev->irq;
5621 }
5622 }
5623 }
5624
5625 /* Called with rtnl_lock */
5626 static int
5627 bnx2_open(struct net_device *dev)
5628 {
5629 struct bnx2 *bp = netdev_priv(dev);
5630 int rc;
5631
5632 netif_carrier_off(dev);
5633
5634 bnx2_set_power_state(bp, PCI_D0);
5635 bnx2_disable_int(bp);
5636
5637 rc = bnx2_alloc_mem(bp);
5638 if (rc)
5639 return rc;
5640
5641 bnx2_setup_int_mode(bp, disable_msi);
5642 bnx2_napi_enable(bp);
5643 rc = bnx2_request_irq(bp);
5644
5645 if (rc) {
5646 bnx2_napi_disable(bp);
5647 bnx2_free_mem(bp);
5648 return rc;
5649 }
5650
5651 rc = bnx2_init_nic(bp);
5652
5653 if (rc) {
5654 bnx2_napi_disable(bp);
5655 bnx2_free_irq(bp);
5656 bnx2_free_skbs(bp);
5657 bnx2_free_mem(bp);
5658 return rc;
5659 }
5660
5661 mod_timer(&bp->timer, jiffies + bp->current_interval);
5662
5663 atomic_set(&bp->intr_sem, 0);
5664
5665 bnx2_enable_int(bp);
5666
5667 if (bp->flags & BNX2_FLAG_USING_MSI) {
5668 /* Test MSI to make sure it is working
5669 * If MSI test fails, go back to INTx mode
5670 */
5671 if (bnx2_test_intr(bp) != 0) {
5672 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5673 " using MSI, switching to INTx mode. Please"
5674 " report this failure to the PCI maintainer"
5675 " and include system chipset information.\n",
5676 bp->dev->name);
5677
5678 bnx2_disable_int(bp);
5679 bnx2_free_irq(bp);
5680
5681 bnx2_setup_int_mode(bp, 1);
5682
5683 rc = bnx2_init_nic(bp);
5684
5685 if (!rc)
5686 rc = bnx2_request_irq(bp);
5687
5688 if (rc) {
5689 bnx2_napi_disable(bp);
5690 bnx2_free_skbs(bp);
5691 bnx2_free_mem(bp);
5692 del_timer_sync(&bp->timer);
5693 return rc;
5694 }
5695 bnx2_enable_int(bp);
5696 }
5697 }
5698 if (bp->flags & BNX2_FLAG_USING_MSI)
5699 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5700 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5701 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5702
5703 netif_start_queue(dev);
5704
5705 return 0;
5706 }
5707
5708 static void
5709 bnx2_reset_task(struct work_struct *work)
5710 {
5711 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5712
5713 if (!netif_running(bp->dev))
5714 return;
5715
5716 bp->in_reset_task = 1;
5717 bnx2_netif_stop(bp);
5718
5719 bnx2_init_nic(bp);
5720
5721 atomic_set(&bp->intr_sem, 1);
5722 bnx2_netif_start(bp);
5723 bp->in_reset_task = 0;
5724 }
5725
5726 static void
5727 bnx2_tx_timeout(struct net_device *dev)
5728 {
5729 struct bnx2 *bp = netdev_priv(dev);
5730
5731 /* This allows the netif to be shutdown gracefully before resetting */
5732 schedule_work(&bp->reset_task);
5733 }
5734
5735 #ifdef BCM_VLAN
5736 /* Called with rtnl_lock */
5737 static void
5738 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5739 {
5740 struct bnx2 *bp = netdev_priv(dev);
5741
5742 bnx2_netif_stop(bp);
5743
5744 bp->vlgrp = vlgrp;
5745 bnx2_set_rx_mode(dev);
5746
5747 bnx2_netif_start(bp);
5748 }
5749 #endif
5750
5751 /* Called with netif_tx_lock.
5752 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5753 * netif_wake_queue().
5754 */
5755 static int
5756 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5757 {
5758 struct bnx2 *bp = netdev_priv(dev);
5759 dma_addr_t mapping;
5760 struct tx_bd *txbd;
5761 struct sw_bd *tx_buf;
5762 u32 len, vlan_tag_flags, last_frag, mss;
5763 u16 prod, ring_prod;
5764 int i;
5765 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
5766
5767 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5768 (skb_shinfo(skb)->nr_frags + 1))) {
5769 netif_stop_queue(dev);
5770 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5771 dev->name);
5772
5773 return NETDEV_TX_BUSY;
5774 }
5775 len = skb_headlen(skb);
5776 prod = bp->tx_prod;
5777 ring_prod = TX_RING_IDX(prod);
5778
5779 vlan_tag_flags = 0;
5780 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5781 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5782 }
5783
5784 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
5785 vlan_tag_flags |=
5786 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5787 }
5788 if ((mss = skb_shinfo(skb)->gso_size)) {
5789 u32 tcp_opt_len, ip_tcp_len;
5790 struct iphdr *iph;
5791
5792 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5793
5794 tcp_opt_len = tcp_optlen(skb);
5795
5796 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5797 u32 tcp_off = skb_transport_offset(skb) -
5798 sizeof(struct ipv6hdr) - ETH_HLEN;
5799
5800 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5801 TX_BD_FLAGS_SW_FLAGS;
5802 if (likely(tcp_off == 0))
5803 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5804 else {
5805 tcp_off >>= 3;
5806 vlan_tag_flags |= ((tcp_off & 0x3) <<
5807 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5808 ((tcp_off & 0x10) <<
5809 TX_BD_FLAGS_TCP6_OFF4_SHL);
5810 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5811 }
5812 } else {
5813 if (skb_header_cloned(skb) &&
5814 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5815 dev_kfree_skb(skb);
5816 return NETDEV_TX_OK;
5817 }
5818
5819 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5820
5821 iph = ip_hdr(skb);
5822 iph->check = 0;
5823 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5824 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5825 iph->daddr, 0,
5826 IPPROTO_TCP,
5827 0);
5828 if (tcp_opt_len || (iph->ihl > 5)) {
5829 vlan_tag_flags |= ((iph->ihl - 5) +
5830 (tcp_opt_len >> 2)) << 8;
5831 }
5832 }
5833 } else
5834 mss = 0;
5835
5836 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5837
5838 tx_buf = &bp->tx_buf_ring[ring_prod];
5839 tx_buf->skb = skb;
5840 pci_unmap_addr_set(tx_buf, mapping, mapping);
5841
5842 txbd = &bp->tx_desc_ring[ring_prod];
5843
5844 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5845 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5846 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5847 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5848
5849 last_frag = skb_shinfo(skb)->nr_frags;
5850
5851 for (i = 0; i < last_frag; i++) {
5852 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5853
5854 prod = NEXT_TX_BD(prod);
5855 ring_prod = TX_RING_IDX(prod);
5856 txbd = &bp->tx_desc_ring[ring_prod];
5857
5858 len = frag->size;
5859 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5860 len, PCI_DMA_TODEVICE);
5861 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5862 mapping, mapping);
5863
5864 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5865 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5866 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5867 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5868
5869 }
5870 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5871
5872 prod = NEXT_TX_BD(prod);
5873 bp->tx_prod_bseq += skb->len;
5874
5875 REG_WR16(bp, bp->tx_bidx_addr, prod);
5876 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5877
5878 mmiowb();
5879
5880 bp->tx_prod = prod;
5881 dev->trans_start = jiffies;
5882
5883 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
5884 netif_stop_queue(dev);
5885 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
5886 netif_wake_queue(dev);
5887 }
5888
5889 return NETDEV_TX_OK;
5890 }
5891
5892 /* Called with rtnl_lock */
5893 static int
5894 bnx2_close(struct net_device *dev)
5895 {
5896 struct bnx2 *bp = netdev_priv(dev);
5897 u32 reset_code;
5898
5899 /* Calling flush_scheduled_work() may deadlock because
5900 * linkwatch_event() may be on the workqueue and it will try to get
5901 * the rtnl_lock which we are holding.
5902 */
5903 while (bp->in_reset_task)
5904 msleep(1);
5905
5906 bnx2_disable_int_sync(bp);
5907 bnx2_napi_disable(bp);
5908 del_timer_sync(&bp->timer);
5909 if (bp->flags & BNX2_FLAG_NO_WOL)
5910 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5911 else if (bp->wol)
5912 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5913 else
5914 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5915 bnx2_reset_chip(bp, reset_code);
5916 bnx2_free_irq(bp);
5917 bnx2_free_skbs(bp);
5918 bnx2_free_mem(bp);
5919 bp->link_up = 0;
5920 netif_carrier_off(bp->dev);
5921 bnx2_set_power_state(bp, PCI_D3hot);
5922 return 0;
5923 }
5924
5925 #define GET_NET_STATS64(ctr) \
5926 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5927 (unsigned long) (ctr##_lo)
5928
5929 #define GET_NET_STATS32(ctr) \
5930 (ctr##_lo)
5931
5932 #if (BITS_PER_LONG == 64)
5933 #define GET_NET_STATS GET_NET_STATS64
5934 #else
5935 #define GET_NET_STATS GET_NET_STATS32
5936 #endif
5937
5938 static struct net_device_stats *
5939 bnx2_get_stats(struct net_device *dev)
5940 {
5941 struct bnx2 *bp = netdev_priv(dev);
5942 struct statistics_block *stats_blk = bp->stats_blk;
5943 struct net_device_stats *net_stats = &bp->net_stats;
5944
5945 if (bp->stats_blk == NULL) {
5946 return net_stats;
5947 }
5948 net_stats->rx_packets =
5949 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5950 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5951 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5952
5953 net_stats->tx_packets =
5954 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5955 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5956 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5957
5958 net_stats->rx_bytes =
5959 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5960
5961 net_stats->tx_bytes =
5962 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5963
5964 net_stats->multicast =
5965 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5966
5967 net_stats->collisions =
5968 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5969
5970 net_stats->rx_length_errors =
5971 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5972 stats_blk->stat_EtherStatsOverrsizePkts);
5973
5974 net_stats->rx_over_errors =
5975 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5976
5977 net_stats->rx_frame_errors =
5978 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5979
5980 net_stats->rx_crc_errors =
5981 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5982
5983 net_stats->rx_errors = net_stats->rx_length_errors +
5984 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5985 net_stats->rx_crc_errors;
5986
5987 net_stats->tx_aborted_errors =
5988 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5989 stats_blk->stat_Dot3StatsLateCollisions);
5990
5991 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5992 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5993 net_stats->tx_carrier_errors = 0;
5994 else {
5995 net_stats->tx_carrier_errors =
5996 (unsigned long)
5997 stats_blk->stat_Dot3StatsCarrierSenseErrors;
5998 }
5999
6000 net_stats->tx_errors =
6001 (unsigned long)
6002 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6003 +
6004 net_stats->tx_aborted_errors +
6005 net_stats->tx_carrier_errors;
6006
6007 net_stats->rx_missed_errors =
6008 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6009 stats_blk->stat_FwRxDrop);
6010
6011 return net_stats;
6012 }
6013
6014 /* All ethtool functions called with rtnl_lock */
6015
6016 static int
6017 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6018 {
6019 struct bnx2 *bp = netdev_priv(dev);
6020 int support_serdes = 0, support_copper = 0;
6021
6022 cmd->supported = SUPPORTED_Autoneg;
6023 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6024 support_serdes = 1;
6025 support_copper = 1;
6026 } else if (bp->phy_port == PORT_FIBRE)
6027 support_serdes = 1;
6028 else
6029 support_copper = 1;
6030
6031 if (support_serdes) {
6032 cmd->supported |= SUPPORTED_1000baseT_Full |
6033 SUPPORTED_FIBRE;
6034 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6035 cmd->supported |= SUPPORTED_2500baseX_Full;
6036
6037 }
6038 if (support_copper) {
6039 cmd->supported |= SUPPORTED_10baseT_Half |
6040 SUPPORTED_10baseT_Full |
6041 SUPPORTED_100baseT_Half |
6042 SUPPORTED_100baseT_Full |
6043 SUPPORTED_1000baseT_Full |
6044 SUPPORTED_TP;
6045
6046 }
6047
6048 spin_lock_bh(&bp->phy_lock);
6049 cmd->port = bp->phy_port;
6050 cmd->advertising = bp->advertising;
6051
6052 if (bp->autoneg & AUTONEG_SPEED) {
6053 cmd->autoneg = AUTONEG_ENABLE;
6054 }
6055 else {
6056 cmd->autoneg = AUTONEG_DISABLE;
6057 }
6058
6059 if (netif_carrier_ok(dev)) {
6060 cmd->speed = bp->line_speed;
6061 cmd->duplex = bp->duplex;
6062 }
6063 else {
6064 cmd->speed = -1;
6065 cmd->duplex = -1;
6066 }
6067 spin_unlock_bh(&bp->phy_lock);
6068
6069 cmd->transceiver = XCVR_INTERNAL;
6070 cmd->phy_address = bp->phy_addr;
6071
6072 return 0;
6073 }
6074
6075 static int
6076 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6077 {
6078 struct bnx2 *bp = netdev_priv(dev);
6079 u8 autoneg = bp->autoneg;
6080 u8 req_duplex = bp->req_duplex;
6081 u16 req_line_speed = bp->req_line_speed;
6082 u32 advertising = bp->advertising;
6083 int err = -EINVAL;
6084
6085 spin_lock_bh(&bp->phy_lock);
6086
6087 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6088 goto err_out_unlock;
6089
6090 if (cmd->port != bp->phy_port &&
6091 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6092 goto err_out_unlock;
6093
6094 if (cmd->autoneg == AUTONEG_ENABLE) {
6095 autoneg |= AUTONEG_SPEED;
6096
6097 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6098
6099 /* allow advertising 1 speed */
6100 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6101 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6102 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6103 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6104
6105 if (cmd->port == PORT_FIBRE)
6106 goto err_out_unlock;
6107
6108 advertising = cmd->advertising;
6109
6110 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6111 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6112 (cmd->port == PORT_TP))
6113 goto err_out_unlock;
6114 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6115 advertising = cmd->advertising;
6116 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6117 goto err_out_unlock;
6118 else {
6119 if (cmd->port == PORT_FIBRE)
6120 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6121 else
6122 advertising = ETHTOOL_ALL_COPPER_SPEED;
6123 }
6124 advertising |= ADVERTISED_Autoneg;
6125 }
6126 else {
6127 if (cmd->port == PORT_FIBRE) {
6128 if ((cmd->speed != SPEED_1000 &&
6129 cmd->speed != SPEED_2500) ||
6130 (cmd->duplex != DUPLEX_FULL))
6131 goto err_out_unlock;
6132
6133 if (cmd->speed == SPEED_2500 &&
6134 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6135 goto err_out_unlock;
6136 }
6137 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6138 goto err_out_unlock;
6139
6140 autoneg &= ~AUTONEG_SPEED;
6141 req_line_speed = cmd->speed;
6142 req_duplex = cmd->duplex;
6143 advertising = 0;
6144 }
6145
6146 bp->autoneg = autoneg;
6147 bp->advertising = advertising;
6148 bp->req_line_speed = req_line_speed;
6149 bp->req_duplex = req_duplex;
6150
6151 err = bnx2_setup_phy(bp, cmd->port);
6152
6153 err_out_unlock:
6154 spin_unlock_bh(&bp->phy_lock);
6155
6156 return err;
6157 }
6158
6159 static void
6160 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6161 {
6162 struct bnx2 *bp = netdev_priv(dev);
6163
6164 strcpy(info->driver, DRV_MODULE_NAME);
6165 strcpy(info->version, DRV_MODULE_VERSION);
6166 strcpy(info->bus_info, pci_name(bp->pdev));
6167 strcpy(info->fw_version, bp->fw_version);
6168 }
6169
6170 #define BNX2_REGDUMP_LEN (32 * 1024)
6171
6172 static int
6173 bnx2_get_regs_len(struct net_device *dev)
6174 {
6175 return BNX2_REGDUMP_LEN;
6176 }
6177
6178 static void
6179 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6180 {
6181 u32 *p = _p, i, offset;
6182 u8 *orig_p = _p;
6183 struct bnx2 *bp = netdev_priv(dev);
6184 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6185 0x0800, 0x0880, 0x0c00, 0x0c10,
6186 0x0c30, 0x0d08, 0x1000, 0x101c,
6187 0x1040, 0x1048, 0x1080, 0x10a4,
6188 0x1400, 0x1490, 0x1498, 0x14f0,
6189 0x1500, 0x155c, 0x1580, 0x15dc,
6190 0x1600, 0x1658, 0x1680, 0x16d8,
6191 0x1800, 0x1820, 0x1840, 0x1854,
6192 0x1880, 0x1894, 0x1900, 0x1984,
6193 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6194 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6195 0x2000, 0x2030, 0x23c0, 0x2400,
6196 0x2800, 0x2820, 0x2830, 0x2850,
6197 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6198 0x3c00, 0x3c94, 0x4000, 0x4010,
6199 0x4080, 0x4090, 0x43c0, 0x4458,
6200 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6201 0x4fc0, 0x5010, 0x53c0, 0x5444,
6202 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6203 0x5fc0, 0x6000, 0x6400, 0x6428,
6204 0x6800, 0x6848, 0x684c, 0x6860,
6205 0x6888, 0x6910, 0x8000 };
6206
6207 regs->version = 0;
6208
6209 memset(p, 0, BNX2_REGDUMP_LEN);
6210
6211 if (!netif_running(bp->dev))
6212 return;
6213
6214 i = 0;
6215 offset = reg_boundaries[0];
6216 p += offset;
6217 while (offset < BNX2_REGDUMP_LEN) {
6218 *p++ = REG_RD(bp, offset);
6219 offset += 4;
6220 if (offset == reg_boundaries[i + 1]) {
6221 offset = reg_boundaries[i + 2];
6222 p = (u32 *) (orig_p + offset);
6223 i += 2;
6224 }
6225 }
6226 }
6227
6228 static void
6229 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6230 {
6231 struct bnx2 *bp = netdev_priv(dev);
6232
6233 if (bp->flags & BNX2_FLAG_NO_WOL) {
6234 wol->supported = 0;
6235 wol->wolopts = 0;
6236 }
6237 else {
6238 wol->supported = WAKE_MAGIC;
6239 if (bp->wol)
6240 wol->wolopts = WAKE_MAGIC;
6241 else
6242 wol->wolopts = 0;
6243 }
6244 memset(&wol->sopass, 0, sizeof(wol->sopass));
6245 }
6246
6247 static int
6248 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6249 {
6250 struct bnx2 *bp = netdev_priv(dev);
6251
6252 if (wol->wolopts & ~WAKE_MAGIC)
6253 return -EINVAL;
6254
6255 if (wol->wolopts & WAKE_MAGIC) {
6256 if (bp->flags & BNX2_FLAG_NO_WOL)
6257 return -EINVAL;
6258
6259 bp->wol = 1;
6260 }
6261 else {
6262 bp->wol = 0;
6263 }
6264 return 0;
6265 }
6266
6267 static int
6268 bnx2_nway_reset(struct net_device *dev)
6269 {
6270 struct bnx2 *bp = netdev_priv(dev);
6271 u32 bmcr;
6272
6273 if (!(bp->autoneg & AUTONEG_SPEED)) {
6274 return -EINVAL;
6275 }
6276
6277 spin_lock_bh(&bp->phy_lock);
6278
6279 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6280 int rc;
6281
6282 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6283 spin_unlock_bh(&bp->phy_lock);
6284 return rc;
6285 }
6286
6287 /* Force a link down visible on the other side */
6288 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6289 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6290 spin_unlock_bh(&bp->phy_lock);
6291
6292 msleep(20);
6293
6294 spin_lock_bh(&bp->phy_lock);
6295
6296 bp->current_interval = SERDES_AN_TIMEOUT;
6297 bp->serdes_an_pending = 1;
6298 mod_timer(&bp->timer, jiffies + bp->current_interval);
6299 }
6300
6301 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6302 bmcr &= ~BMCR_LOOPBACK;
6303 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6304
6305 spin_unlock_bh(&bp->phy_lock);
6306
6307 return 0;
6308 }
6309
6310 static int
6311 bnx2_get_eeprom_len(struct net_device *dev)
6312 {
6313 struct bnx2 *bp = netdev_priv(dev);
6314
6315 if (bp->flash_info == NULL)
6316 return 0;
6317
6318 return (int) bp->flash_size;
6319 }
6320
6321 static int
6322 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6323 u8 *eebuf)
6324 {
6325 struct bnx2 *bp = netdev_priv(dev);
6326 int rc;
6327
6328 /* parameters already validated in ethtool_get_eeprom */
6329
6330 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6331
6332 return rc;
6333 }
6334
6335 static int
6336 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6337 u8 *eebuf)
6338 {
6339 struct bnx2 *bp = netdev_priv(dev);
6340 int rc;
6341
6342 /* parameters already validated in ethtool_set_eeprom */
6343
6344 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6345
6346 return rc;
6347 }
6348
6349 static int
6350 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6351 {
6352 struct bnx2 *bp = netdev_priv(dev);
6353
6354 memset(coal, 0, sizeof(struct ethtool_coalesce));
6355
6356 coal->rx_coalesce_usecs = bp->rx_ticks;
6357 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6358 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6359 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6360
6361 coal->tx_coalesce_usecs = bp->tx_ticks;
6362 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6363 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6364 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6365
6366 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6367
6368 return 0;
6369 }
6370
6371 static int
6372 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6373 {
6374 struct bnx2 *bp = netdev_priv(dev);
6375
6376 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6377 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6378
6379 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6380 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6381
6382 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6383 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6384
6385 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6386 if (bp->rx_quick_cons_trip_int > 0xff)
6387 bp->rx_quick_cons_trip_int = 0xff;
6388
6389 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6390 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6391
6392 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6393 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6394
6395 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6396 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6397
6398 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6399 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6400 0xff;
6401
6402 bp->stats_ticks = coal->stats_block_coalesce_usecs;
6403 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6404 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6405 bp->stats_ticks = USEC_PER_SEC;
6406 }
6407 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6408 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6409 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6410
6411 if (netif_running(bp->dev)) {
6412 bnx2_netif_stop(bp);
6413 bnx2_init_nic(bp);
6414 bnx2_netif_start(bp);
6415 }
6416
6417 return 0;
6418 }
6419
6420 static void
6421 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6422 {
6423 struct bnx2 *bp = netdev_priv(dev);
6424
6425 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6426 ering->rx_mini_max_pending = 0;
6427 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6428
6429 ering->rx_pending = bp->rx_ring_size;
6430 ering->rx_mini_pending = 0;
6431 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6432
6433 ering->tx_max_pending = MAX_TX_DESC_CNT;
6434 ering->tx_pending = bp->tx_ring_size;
6435 }
6436
6437 static int
6438 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6439 {
6440 if (netif_running(bp->dev)) {
6441 bnx2_netif_stop(bp);
6442 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6443 bnx2_free_skbs(bp);
6444 bnx2_free_mem(bp);
6445 }
6446
6447 bnx2_set_rx_ring_size(bp, rx);
6448 bp->tx_ring_size = tx;
6449
6450 if (netif_running(bp->dev)) {
6451 int rc;
6452
6453 rc = bnx2_alloc_mem(bp);
6454 if (rc)
6455 return rc;
6456 bnx2_init_nic(bp);
6457 bnx2_netif_start(bp);
6458 }
6459 return 0;
6460 }
6461
6462 static int
6463 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6464 {
6465 struct bnx2 *bp = netdev_priv(dev);
6466 int rc;
6467
6468 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6469 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6470 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6471
6472 return -EINVAL;
6473 }
6474 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6475 return rc;
6476 }
6477
6478 static void
6479 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6480 {
6481 struct bnx2 *bp = netdev_priv(dev);
6482
6483 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6484 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6485 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6486 }
6487
6488 static int
6489 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6490 {
6491 struct bnx2 *bp = netdev_priv(dev);
6492
6493 bp->req_flow_ctrl = 0;
6494 if (epause->rx_pause)
6495 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6496 if (epause->tx_pause)
6497 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6498
6499 if (epause->autoneg) {
6500 bp->autoneg |= AUTONEG_FLOW_CTRL;
6501 }
6502 else {
6503 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6504 }
6505
6506 spin_lock_bh(&bp->phy_lock);
6507
6508 bnx2_setup_phy(bp, bp->phy_port);
6509
6510 spin_unlock_bh(&bp->phy_lock);
6511
6512 return 0;
6513 }
6514
6515 static u32
6516 bnx2_get_rx_csum(struct net_device *dev)
6517 {
6518 struct bnx2 *bp = netdev_priv(dev);
6519
6520 return bp->rx_csum;
6521 }
6522
6523 static int
6524 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6525 {
6526 struct bnx2 *bp = netdev_priv(dev);
6527
6528 bp->rx_csum = data;
6529 return 0;
6530 }
6531
6532 static int
6533 bnx2_set_tso(struct net_device *dev, u32 data)
6534 {
6535 struct bnx2 *bp = netdev_priv(dev);
6536
6537 if (data) {
6538 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6539 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6540 dev->features |= NETIF_F_TSO6;
6541 } else
6542 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6543 NETIF_F_TSO_ECN);
6544 return 0;
6545 }
6546
6547 #define BNX2_NUM_STATS 46
6548
6549 static struct {
6550 char string[ETH_GSTRING_LEN];
6551 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6552 { "rx_bytes" },
6553 { "rx_error_bytes" },
6554 { "tx_bytes" },
6555 { "tx_error_bytes" },
6556 { "rx_ucast_packets" },
6557 { "rx_mcast_packets" },
6558 { "rx_bcast_packets" },
6559 { "tx_ucast_packets" },
6560 { "tx_mcast_packets" },
6561 { "tx_bcast_packets" },
6562 { "tx_mac_errors" },
6563 { "tx_carrier_errors" },
6564 { "rx_crc_errors" },
6565 { "rx_align_errors" },
6566 { "tx_single_collisions" },
6567 { "tx_multi_collisions" },
6568 { "tx_deferred" },
6569 { "tx_excess_collisions" },
6570 { "tx_late_collisions" },
6571 { "tx_total_collisions" },
6572 { "rx_fragments" },
6573 { "rx_jabbers" },
6574 { "rx_undersize_packets" },
6575 { "rx_oversize_packets" },
6576 { "rx_64_byte_packets" },
6577 { "rx_65_to_127_byte_packets" },
6578 { "rx_128_to_255_byte_packets" },
6579 { "rx_256_to_511_byte_packets" },
6580 { "rx_512_to_1023_byte_packets" },
6581 { "rx_1024_to_1522_byte_packets" },
6582 { "rx_1523_to_9022_byte_packets" },
6583 { "tx_64_byte_packets" },
6584 { "tx_65_to_127_byte_packets" },
6585 { "tx_128_to_255_byte_packets" },
6586 { "tx_256_to_511_byte_packets" },
6587 { "tx_512_to_1023_byte_packets" },
6588 { "tx_1024_to_1522_byte_packets" },
6589 { "tx_1523_to_9022_byte_packets" },
6590 { "rx_xon_frames" },
6591 { "rx_xoff_frames" },
6592 { "tx_xon_frames" },
6593 { "tx_xoff_frames" },
6594 { "rx_mac_ctrl_frames" },
6595 { "rx_filtered_packets" },
6596 { "rx_discards" },
6597 { "rx_fw_discards" },
6598 };
6599
6600 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6601
6602 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6603 STATS_OFFSET32(stat_IfHCInOctets_hi),
6604 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6605 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6606 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6607 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6608 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6609 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6610 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6611 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6612 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6613 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6614 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6615 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6616 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6617 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6618 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6619 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6620 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6621 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6622 STATS_OFFSET32(stat_EtherStatsCollisions),
6623 STATS_OFFSET32(stat_EtherStatsFragments),
6624 STATS_OFFSET32(stat_EtherStatsJabbers),
6625 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6626 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6627 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6628 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6629 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6630 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6631 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6632 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6633 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6634 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6635 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6636 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6637 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6638 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6639 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6640 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6641 STATS_OFFSET32(stat_XonPauseFramesReceived),
6642 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6643 STATS_OFFSET32(stat_OutXonSent),
6644 STATS_OFFSET32(stat_OutXoffSent),
6645 STATS_OFFSET32(stat_MacControlFramesReceived),
6646 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6647 STATS_OFFSET32(stat_IfInMBUFDiscards),
6648 STATS_OFFSET32(stat_FwRxDrop),
6649 };
6650
6651 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6652 * skipped because of errata.
6653 */
6654 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6655 8,0,8,8,8,8,8,8,8,8,
6656 4,0,4,4,4,4,4,4,4,4,
6657 4,4,4,4,4,4,4,4,4,4,
6658 4,4,4,4,4,4,4,4,4,4,
6659 4,4,4,4,4,4,
6660 };
6661
6662 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6663 8,0,8,8,8,8,8,8,8,8,
6664 4,4,4,4,4,4,4,4,4,4,
6665 4,4,4,4,4,4,4,4,4,4,
6666 4,4,4,4,4,4,4,4,4,4,
6667 4,4,4,4,4,4,
6668 };
6669
6670 #define BNX2_NUM_TESTS 6
6671
6672 static struct {
6673 char string[ETH_GSTRING_LEN];
6674 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6675 { "register_test (offline)" },
6676 { "memory_test (offline)" },
6677 { "loopback_test (offline)" },
6678 { "nvram_test (online)" },
6679 { "interrupt_test (online)" },
6680 { "link_test (online)" },
6681 };
6682
6683 static int
6684 bnx2_get_sset_count(struct net_device *dev, int sset)
6685 {
6686 switch (sset) {
6687 case ETH_SS_TEST:
6688 return BNX2_NUM_TESTS;
6689 case ETH_SS_STATS:
6690 return BNX2_NUM_STATS;
6691 default:
6692 return -EOPNOTSUPP;
6693 }
6694 }
6695
6696 static void
6697 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6698 {
6699 struct bnx2 *bp = netdev_priv(dev);
6700
6701 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6702 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6703 int i;
6704
6705 bnx2_netif_stop(bp);
6706 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6707 bnx2_free_skbs(bp);
6708
6709 if (bnx2_test_registers(bp) != 0) {
6710 buf[0] = 1;
6711 etest->flags |= ETH_TEST_FL_FAILED;
6712 }
6713 if (bnx2_test_memory(bp) != 0) {
6714 buf[1] = 1;
6715 etest->flags |= ETH_TEST_FL_FAILED;
6716 }
6717 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6718 etest->flags |= ETH_TEST_FL_FAILED;
6719
6720 if (!netif_running(bp->dev)) {
6721 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6722 }
6723 else {
6724 bnx2_init_nic(bp);
6725 bnx2_netif_start(bp);
6726 }
6727
6728 /* wait for link up */
6729 for (i = 0; i < 7; i++) {
6730 if (bp->link_up)
6731 break;
6732 msleep_interruptible(1000);
6733 }
6734 }
6735
6736 if (bnx2_test_nvram(bp) != 0) {
6737 buf[3] = 1;
6738 etest->flags |= ETH_TEST_FL_FAILED;
6739 }
6740 if (bnx2_test_intr(bp) != 0) {
6741 buf[4] = 1;
6742 etest->flags |= ETH_TEST_FL_FAILED;
6743 }
6744
6745 if (bnx2_test_link(bp) != 0) {
6746 buf[5] = 1;
6747 etest->flags |= ETH_TEST_FL_FAILED;
6748
6749 }
6750 }
6751
6752 static void
6753 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6754 {
6755 switch (stringset) {
6756 case ETH_SS_STATS:
6757 memcpy(buf, bnx2_stats_str_arr,
6758 sizeof(bnx2_stats_str_arr));
6759 break;
6760 case ETH_SS_TEST:
6761 memcpy(buf, bnx2_tests_str_arr,
6762 sizeof(bnx2_tests_str_arr));
6763 break;
6764 }
6765 }
6766
6767 static void
6768 bnx2_get_ethtool_stats(struct net_device *dev,
6769 struct ethtool_stats *stats, u64 *buf)
6770 {
6771 struct bnx2 *bp = netdev_priv(dev);
6772 int i;
6773 u32 *hw_stats = (u32 *) bp->stats_blk;
6774 u8 *stats_len_arr = NULL;
6775
6776 if (hw_stats == NULL) {
6777 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6778 return;
6779 }
6780
6781 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6782 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6783 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6784 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6785 stats_len_arr = bnx2_5706_stats_len_arr;
6786 else
6787 stats_len_arr = bnx2_5708_stats_len_arr;
6788
6789 for (i = 0; i < BNX2_NUM_STATS; i++) {
6790 if (stats_len_arr[i] == 0) {
6791 /* skip this counter */
6792 buf[i] = 0;
6793 continue;
6794 }
6795 if (stats_len_arr[i] == 4) {
6796 /* 4-byte counter */
6797 buf[i] = (u64)
6798 *(hw_stats + bnx2_stats_offset_arr[i]);
6799 continue;
6800 }
6801 /* 8-byte counter */
6802 buf[i] = (((u64) *(hw_stats +
6803 bnx2_stats_offset_arr[i])) << 32) +
6804 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6805 }
6806 }
6807
6808 static int
6809 bnx2_phys_id(struct net_device *dev, u32 data)
6810 {
6811 struct bnx2 *bp = netdev_priv(dev);
6812 int i;
6813 u32 save;
6814
6815 if (data == 0)
6816 data = 2;
6817
6818 save = REG_RD(bp, BNX2_MISC_CFG);
6819 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6820
6821 for (i = 0; i < (data * 2); i++) {
6822 if ((i % 2) == 0) {
6823 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6824 }
6825 else {
6826 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6827 BNX2_EMAC_LED_1000MB_OVERRIDE |
6828 BNX2_EMAC_LED_100MB_OVERRIDE |
6829 BNX2_EMAC_LED_10MB_OVERRIDE |
6830 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6831 BNX2_EMAC_LED_TRAFFIC);
6832 }
6833 msleep_interruptible(500);
6834 if (signal_pending(current))
6835 break;
6836 }
6837 REG_WR(bp, BNX2_EMAC_LED, 0);
6838 REG_WR(bp, BNX2_MISC_CFG, save);
6839 return 0;
6840 }
6841
6842 static int
6843 bnx2_set_tx_csum(struct net_device *dev, u32 data)
6844 {
6845 struct bnx2 *bp = netdev_priv(dev);
6846
6847 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6848 return (ethtool_op_set_tx_ipv6_csum(dev, data));
6849 else
6850 return (ethtool_op_set_tx_csum(dev, data));
6851 }
6852
6853 static const struct ethtool_ops bnx2_ethtool_ops = {
6854 .get_settings = bnx2_get_settings,
6855 .set_settings = bnx2_set_settings,
6856 .get_drvinfo = bnx2_get_drvinfo,
6857 .get_regs_len = bnx2_get_regs_len,
6858 .get_regs = bnx2_get_regs,
6859 .get_wol = bnx2_get_wol,
6860 .set_wol = bnx2_set_wol,
6861 .nway_reset = bnx2_nway_reset,
6862 .get_link = ethtool_op_get_link,
6863 .get_eeprom_len = bnx2_get_eeprom_len,
6864 .get_eeprom = bnx2_get_eeprom,
6865 .set_eeprom = bnx2_set_eeprom,
6866 .get_coalesce = bnx2_get_coalesce,
6867 .set_coalesce = bnx2_set_coalesce,
6868 .get_ringparam = bnx2_get_ringparam,
6869 .set_ringparam = bnx2_set_ringparam,
6870 .get_pauseparam = bnx2_get_pauseparam,
6871 .set_pauseparam = bnx2_set_pauseparam,
6872 .get_rx_csum = bnx2_get_rx_csum,
6873 .set_rx_csum = bnx2_set_rx_csum,
6874 .set_tx_csum = bnx2_set_tx_csum,
6875 .set_sg = ethtool_op_set_sg,
6876 .set_tso = bnx2_set_tso,
6877 .self_test = bnx2_self_test,
6878 .get_strings = bnx2_get_strings,
6879 .phys_id = bnx2_phys_id,
6880 .get_ethtool_stats = bnx2_get_ethtool_stats,
6881 .get_sset_count = bnx2_get_sset_count,
6882 };
6883
6884 /* Called with rtnl_lock */
6885 static int
6886 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6887 {
6888 struct mii_ioctl_data *data = if_mii(ifr);
6889 struct bnx2 *bp = netdev_priv(dev);
6890 int err;
6891
6892 switch(cmd) {
6893 case SIOCGMIIPHY:
6894 data->phy_id = bp->phy_addr;
6895
6896 /* fallthru */
6897 case SIOCGMIIREG: {
6898 u32 mii_regval;
6899
6900 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6901 return -EOPNOTSUPP;
6902
6903 if (!netif_running(dev))
6904 return -EAGAIN;
6905
6906 spin_lock_bh(&bp->phy_lock);
6907 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
6908 spin_unlock_bh(&bp->phy_lock);
6909
6910 data->val_out = mii_regval;
6911
6912 return err;
6913 }
6914
6915 case SIOCSMIIREG:
6916 if (!capable(CAP_NET_ADMIN))
6917 return -EPERM;
6918
6919 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6920 return -EOPNOTSUPP;
6921
6922 if (!netif_running(dev))
6923 return -EAGAIN;
6924
6925 spin_lock_bh(&bp->phy_lock);
6926 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
6927 spin_unlock_bh(&bp->phy_lock);
6928
6929 return err;
6930
6931 default:
6932 /* do nothing */
6933 break;
6934 }
6935 return -EOPNOTSUPP;
6936 }
6937
6938 /* Called with rtnl_lock */
6939 static int
6940 bnx2_change_mac_addr(struct net_device *dev, void *p)
6941 {
6942 struct sockaddr *addr = p;
6943 struct bnx2 *bp = netdev_priv(dev);
6944
6945 if (!is_valid_ether_addr(addr->sa_data))
6946 return -EINVAL;
6947
6948 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6949 if (netif_running(dev))
6950 bnx2_set_mac_addr(bp);
6951
6952 return 0;
6953 }
6954
6955 /* Called with rtnl_lock */
6956 static int
6957 bnx2_change_mtu(struct net_device *dev, int new_mtu)
6958 {
6959 struct bnx2 *bp = netdev_priv(dev);
6960
6961 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6962 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6963 return -EINVAL;
6964
6965 dev->mtu = new_mtu;
6966 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
6967 }
6968
6969 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6970 static void
6971 poll_bnx2(struct net_device *dev)
6972 {
6973 struct bnx2 *bp = netdev_priv(dev);
6974
6975 disable_irq(bp->pdev->irq);
6976 bnx2_interrupt(bp->pdev->irq, dev);
6977 enable_irq(bp->pdev->irq);
6978 }
6979 #endif
6980
6981 static void __devinit
6982 bnx2_get_5709_media(struct bnx2 *bp)
6983 {
6984 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6985 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6986 u32 strap;
6987
6988 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6989 return;
6990 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
6991 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
6992 return;
6993 }
6994
6995 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
6996 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
6997 else
6998 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
6999
7000 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7001 switch (strap) {
7002 case 0x4:
7003 case 0x5:
7004 case 0x6:
7005 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7006 return;
7007 }
7008 } else {
7009 switch (strap) {
7010 case 0x1:
7011 case 0x2:
7012 case 0x4:
7013 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7014 return;
7015 }
7016 }
7017 }
7018
7019 static void __devinit
7020 bnx2_get_pci_speed(struct bnx2 *bp)
7021 {
7022 u32 reg;
7023
7024 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7025 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7026 u32 clkreg;
7027
7028 bp->flags |= BNX2_FLAG_PCIX;
7029
7030 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7031
7032 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7033 switch (clkreg) {
7034 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7035 bp->bus_speed_mhz = 133;
7036 break;
7037
7038 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7039 bp->bus_speed_mhz = 100;
7040 break;
7041
7042 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7043 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7044 bp->bus_speed_mhz = 66;
7045 break;
7046
7047 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7048 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7049 bp->bus_speed_mhz = 50;
7050 break;
7051
7052 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7053 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7054 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7055 bp->bus_speed_mhz = 33;
7056 break;
7057 }
7058 }
7059 else {
7060 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7061 bp->bus_speed_mhz = 66;
7062 else
7063 bp->bus_speed_mhz = 33;
7064 }
7065
7066 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7067 bp->flags |= BNX2_FLAG_PCI_32BIT;
7068
7069 }
7070
7071 static int __devinit
7072 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7073 {
7074 struct bnx2 *bp;
7075 unsigned long mem_len;
7076 int rc, i, j;
7077 u32 reg;
7078 u64 dma_mask, persist_dma_mask;
7079
7080 SET_NETDEV_DEV(dev, &pdev->dev);
7081 bp = netdev_priv(dev);
7082
7083 bp->flags = 0;
7084 bp->phy_flags = 0;
7085
7086 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7087 rc = pci_enable_device(pdev);
7088 if (rc) {
7089 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7090 goto err_out;
7091 }
7092
7093 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7094 dev_err(&pdev->dev,
7095 "Cannot find PCI device base address, aborting.\n");
7096 rc = -ENODEV;
7097 goto err_out_disable;
7098 }
7099
7100 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7101 if (rc) {
7102 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7103 goto err_out_disable;
7104 }
7105
7106 pci_set_master(pdev);
7107
7108 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7109 if (bp->pm_cap == 0) {
7110 dev_err(&pdev->dev,
7111 "Cannot find power management capability, aborting.\n");
7112 rc = -EIO;
7113 goto err_out_release;
7114 }
7115
7116 bp->dev = dev;
7117 bp->pdev = pdev;
7118
7119 spin_lock_init(&bp->phy_lock);
7120 spin_lock_init(&bp->indirect_lock);
7121 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7122
7123 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7124 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
7125 dev->mem_end = dev->mem_start + mem_len;
7126 dev->irq = pdev->irq;
7127
7128 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7129
7130 if (!bp->regview) {
7131 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7132 rc = -ENOMEM;
7133 goto err_out_release;
7134 }
7135
7136 /* Configure byte swap and enable write to the reg_window registers.
7137 * Rely on CPU to do target byte swapping on big endian systems
7138 * The chip's target access swapping will not swap all accesses
7139 */
7140 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7141 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7142 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7143
7144 bnx2_set_power_state(bp, PCI_D0);
7145
7146 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7147
7148 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7149 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7150 dev_err(&pdev->dev,
7151 "Cannot find PCIE capability, aborting.\n");
7152 rc = -EIO;
7153 goto err_out_unmap;
7154 }
7155 bp->flags |= BNX2_FLAG_PCIE;
7156 if (CHIP_REV(bp) == CHIP_REV_Ax)
7157 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7158 } else {
7159 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7160 if (bp->pcix_cap == 0) {
7161 dev_err(&pdev->dev,
7162 "Cannot find PCIX capability, aborting.\n");
7163 rc = -EIO;
7164 goto err_out_unmap;
7165 }
7166 }
7167
7168 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7169 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7170 bp->flags |= BNX2_FLAG_MSIX_CAP;
7171 }
7172
7173 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7174 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7175 bp->flags |= BNX2_FLAG_MSI_CAP;
7176 }
7177
7178 /* 5708 cannot support DMA addresses > 40-bit. */
7179 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7180 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7181 else
7182 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7183
7184 /* Configure DMA attributes. */
7185 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7186 dev->features |= NETIF_F_HIGHDMA;
7187 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7188 if (rc) {
7189 dev_err(&pdev->dev,
7190 "pci_set_consistent_dma_mask failed, aborting.\n");
7191 goto err_out_unmap;
7192 }
7193 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7194 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7195 goto err_out_unmap;
7196 }
7197
7198 if (!(bp->flags & BNX2_FLAG_PCIE))
7199 bnx2_get_pci_speed(bp);
7200
7201 /* 5706A0 may falsely detect SERR and PERR. */
7202 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7203 reg = REG_RD(bp, PCI_COMMAND);
7204 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7205 REG_WR(bp, PCI_COMMAND, reg);
7206 }
7207 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7208 !(bp->flags & BNX2_FLAG_PCIX)) {
7209
7210 dev_err(&pdev->dev,
7211 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7212 goto err_out_unmap;
7213 }
7214
7215 bnx2_init_nvram(bp);
7216
7217 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7218
7219 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7220 BNX2_SHM_HDR_SIGNATURE_SIG) {
7221 u32 off = PCI_FUNC(pdev->devfn) << 2;
7222
7223 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7224 } else
7225 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7226
7227 /* Get the permanent MAC address. First we need to make sure the
7228 * firmware is actually running.
7229 */
7230 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7231
7232 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7233 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7234 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7235 rc = -ENODEV;
7236 goto err_out_unmap;
7237 }
7238
7239 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7240 for (i = 0, j = 0; i < 3; i++) {
7241 u8 num, k, skip0;
7242
7243 num = (u8) (reg >> (24 - (i * 8)));
7244 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7245 if (num >= k || !skip0 || k == 1) {
7246 bp->fw_version[j++] = (num / k) + '0';
7247 skip0 = 0;
7248 }
7249 }
7250 if (i != 2)
7251 bp->fw_version[j++] = '.';
7252 }
7253 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7254 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7255 bp->wol = 1;
7256
7257 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7258 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7259
7260 for (i = 0; i < 30; i++) {
7261 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7262 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7263 break;
7264 msleep(10);
7265 }
7266 }
7267 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7268 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7269 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7270 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7271 int i;
7272 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7273
7274 bp->fw_version[j++] = ' ';
7275 for (i = 0; i < 3; i++) {
7276 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7277 reg = swab32(reg);
7278 memcpy(&bp->fw_version[j], &reg, 4);
7279 j += 4;
7280 }
7281 }
7282
7283 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7284 bp->mac_addr[0] = (u8) (reg >> 8);
7285 bp->mac_addr[1] = (u8) reg;
7286
7287 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7288 bp->mac_addr[2] = (u8) (reg >> 24);
7289 bp->mac_addr[3] = (u8) (reg >> 16);
7290 bp->mac_addr[4] = (u8) (reg >> 8);
7291 bp->mac_addr[5] = (u8) reg;
7292
7293 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
7294
7295 bp->tx_ring_size = MAX_TX_DESC_CNT;
7296 bnx2_set_rx_ring_size(bp, 255);
7297
7298 bp->rx_csum = 1;
7299
7300 bp->tx_quick_cons_trip_int = 20;
7301 bp->tx_quick_cons_trip = 20;
7302 bp->tx_ticks_int = 80;
7303 bp->tx_ticks = 80;
7304
7305 bp->rx_quick_cons_trip_int = 6;
7306 bp->rx_quick_cons_trip = 6;
7307 bp->rx_ticks_int = 18;
7308 bp->rx_ticks = 18;
7309
7310 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7311
7312 bp->timer_interval = HZ;
7313 bp->current_interval = HZ;
7314
7315 bp->phy_addr = 1;
7316
7317 /* Disable WOL support if we are running on a SERDES chip. */
7318 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7319 bnx2_get_5709_media(bp);
7320 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7321 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7322
7323 bp->phy_port = PORT_TP;
7324 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7325 bp->phy_port = PORT_FIBRE;
7326 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7327 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7328 bp->flags |= BNX2_FLAG_NO_WOL;
7329 bp->wol = 0;
7330 }
7331 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7332 /* Don't do parallel detect on this board because of
7333 * some board problems. The link will not go down
7334 * if we do parallel detect.
7335 */
7336 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7337 pdev->subsystem_device == 0x310c)
7338 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7339 } else {
7340 bp->phy_addr = 2;
7341 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7342 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7343 }
7344 bnx2_init_remote_phy(bp);
7345
7346 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7347 CHIP_NUM(bp) == CHIP_NUM_5708)
7348 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7349 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7350 (CHIP_REV(bp) == CHIP_REV_Ax ||
7351 CHIP_REV(bp) == CHIP_REV_Bx))
7352 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7353
7354 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7355 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7356 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7357 bp->flags |= BNX2_FLAG_NO_WOL;
7358 bp->wol = 0;
7359 }
7360
7361 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7362 bp->tx_quick_cons_trip_int =
7363 bp->tx_quick_cons_trip;
7364 bp->tx_ticks_int = bp->tx_ticks;
7365 bp->rx_quick_cons_trip_int =
7366 bp->rx_quick_cons_trip;
7367 bp->rx_ticks_int = bp->rx_ticks;
7368 bp->comp_prod_trip_int = bp->comp_prod_trip;
7369 bp->com_ticks_int = bp->com_ticks;
7370 bp->cmd_ticks_int = bp->cmd_ticks;
7371 }
7372
7373 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7374 *
7375 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7376 * with byte enables disabled on the unused 32-bit word. This is legal
7377 * but causes problems on the AMD 8132 which will eventually stop
7378 * responding after a while.
7379 *
7380 * AMD believes this incompatibility is unique to the 5706, and
7381 * prefers to locally disable MSI rather than globally disabling it.
7382 */
7383 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7384 struct pci_dev *amd_8132 = NULL;
7385
7386 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7387 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7388 amd_8132))) {
7389
7390 if (amd_8132->revision >= 0x10 &&
7391 amd_8132->revision <= 0x13) {
7392 disable_msi = 1;
7393 pci_dev_put(amd_8132);
7394 break;
7395 }
7396 }
7397 }
7398
7399 bnx2_set_default_link(bp);
7400 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7401
7402 init_timer(&bp->timer);
7403 bp->timer.expires = RUN_AT(bp->timer_interval);
7404 bp->timer.data = (unsigned long) bp;
7405 bp->timer.function = bnx2_timer;
7406
7407 return 0;
7408
7409 err_out_unmap:
7410 if (bp->regview) {
7411 iounmap(bp->regview);
7412 bp->regview = NULL;
7413 }
7414
7415 err_out_release:
7416 pci_release_regions(pdev);
7417
7418 err_out_disable:
7419 pci_disable_device(pdev);
7420 pci_set_drvdata(pdev, NULL);
7421
7422 err_out:
7423 return rc;
7424 }
7425
7426 static char * __devinit
7427 bnx2_bus_string(struct bnx2 *bp, char *str)
7428 {
7429 char *s = str;
7430
7431 if (bp->flags & BNX2_FLAG_PCIE) {
7432 s += sprintf(s, "PCI Express");
7433 } else {
7434 s += sprintf(s, "PCI");
7435 if (bp->flags & BNX2_FLAG_PCIX)
7436 s += sprintf(s, "-X");
7437 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7438 s += sprintf(s, " 32-bit");
7439 else
7440 s += sprintf(s, " 64-bit");
7441 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7442 }
7443 return str;
7444 }
7445
7446 static void __devinit
7447 bnx2_init_napi(struct bnx2 *bp)
7448 {
7449 int i;
7450 struct bnx2_napi *bnapi;
7451
7452 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7453 bnapi = &bp->bnx2_napi[i];
7454 bnapi->bp = bp;
7455 }
7456 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
7457 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7458 64);
7459 }
7460
7461 static int __devinit
7462 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7463 {
7464 static int version_printed = 0;
7465 struct net_device *dev = NULL;
7466 struct bnx2 *bp;
7467 int rc;
7468 char str[40];
7469 DECLARE_MAC_BUF(mac);
7470
7471 if (version_printed++ == 0)
7472 printk(KERN_INFO "%s", version);
7473
7474 /* dev zeroed in init_etherdev */
7475 dev = alloc_etherdev(sizeof(*bp));
7476
7477 if (!dev)
7478 return -ENOMEM;
7479
7480 rc = bnx2_init_board(pdev, dev);
7481 if (rc < 0) {
7482 free_netdev(dev);
7483 return rc;
7484 }
7485
7486 dev->open = bnx2_open;
7487 dev->hard_start_xmit = bnx2_start_xmit;
7488 dev->stop = bnx2_close;
7489 dev->get_stats = bnx2_get_stats;
7490 dev->set_multicast_list = bnx2_set_rx_mode;
7491 dev->do_ioctl = bnx2_ioctl;
7492 dev->set_mac_address = bnx2_change_mac_addr;
7493 dev->change_mtu = bnx2_change_mtu;
7494 dev->tx_timeout = bnx2_tx_timeout;
7495 dev->watchdog_timeo = TX_TIMEOUT;
7496 #ifdef BCM_VLAN
7497 dev->vlan_rx_register = bnx2_vlan_rx_register;
7498 #endif
7499 dev->ethtool_ops = &bnx2_ethtool_ops;
7500
7501 bp = netdev_priv(dev);
7502 bnx2_init_napi(bp);
7503
7504 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7505 dev->poll_controller = poll_bnx2;
7506 #endif
7507
7508 pci_set_drvdata(pdev, dev);
7509
7510 memcpy(dev->dev_addr, bp->mac_addr, 6);
7511 memcpy(dev->perm_addr, bp->mac_addr, 6);
7512 bp->name = board_info[ent->driver_data].name;
7513
7514 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7515 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7516 dev->features |= NETIF_F_IPV6_CSUM;
7517
7518 #ifdef BCM_VLAN
7519 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7520 #endif
7521 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7522 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7523 dev->features |= NETIF_F_TSO6;
7524
7525 if ((rc = register_netdev(dev))) {
7526 dev_err(&pdev->dev, "Cannot register net device\n");
7527 if (bp->regview)
7528 iounmap(bp->regview);
7529 pci_release_regions(pdev);
7530 pci_disable_device(pdev);
7531 pci_set_drvdata(pdev, NULL);
7532 free_netdev(dev);
7533 return rc;
7534 }
7535
7536 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7537 "IRQ %d, node addr %s\n",
7538 dev->name,
7539 bp->name,
7540 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7541 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7542 bnx2_bus_string(bp, str),
7543 dev->base_addr,
7544 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7545
7546 return 0;
7547 }
7548
7549 static void __devexit
7550 bnx2_remove_one(struct pci_dev *pdev)
7551 {
7552 struct net_device *dev = pci_get_drvdata(pdev);
7553 struct bnx2 *bp = netdev_priv(dev);
7554
7555 flush_scheduled_work();
7556
7557 unregister_netdev(dev);
7558
7559 if (bp->regview)
7560 iounmap(bp->regview);
7561
7562 free_netdev(dev);
7563 pci_release_regions(pdev);
7564 pci_disable_device(pdev);
7565 pci_set_drvdata(pdev, NULL);
7566 }
7567
7568 static int
7569 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7570 {
7571 struct net_device *dev = pci_get_drvdata(pdev);
7572 struct bnx2 *bp = netdev_priv(dev);
7573 u32 reset_code;
7574
7575 /* PCI register 4 needs to be saved whether netif_running() or not.
7576 * MSI address and data need to be saved if using MSI and
7577 * netif_running().
7578 */
7579 pci_save_state(pdev);
7580 if (!netif_running(dev))
7581 return 0;
7582
7583 flush_scheduled_work();
7584 bnx2_netif_stop(bp);
7585 netif_device_detach(dev);
7586 del_timer_sync(&bp->timer);
7587 if (bp->flags & BNX2_FLAG_NO_WOL)
7588 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
7589 else if (bp->wol)
7590 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7591 else
7592 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7593 bnx2_reset_chip(bp, reset_code);
7594 bnx2_free_skbs(bp);
7595 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7596 return 0;
7597 }
7598
7599 static int
7600 bnx2_resume(struct pci_dev *pdev)
7601 {
7602 struct net_device *dev = pci_get_drvdata(pdev);
7603 struct bnx2 *bp = netdev_priv(dev);
7604
7605 pci_restore_state(pdev);
7606 if (!netif_running(dev))
7607 return 0;
7608
7609 bnx2_set_power_state(bp, PCI_D0);
7610 netif_device_attach(dev);
7611 bnx2_init_nic(bp);
7612 bnx2_netif_start(bp);
7613 return 0;
7614 }
7615
7616 static struct pci_driver bnx2_pci_driver = {
7617 .name = DRV_MODULE_NAME,
7618 .id_table = bnx2_pci_tbl,
7619 .probe = bnx2_init_one,
7620 .remove = __devexit_p(bnx2_remove_one),
7621 .suspend = bnx2_suspend,
7622 .resume = bnx2_resume,
7623 };
7624
7625 static int __init bnx2_init(void)
7626 {
7627 return pci_register_driver(&bnx2_pci_driver);
7628 }
7629
7630 static void __exit bnx2_cleanup(void)
7631 {
7632 pci_unregister_driver(&bnx2_pci_driver);
7633 }
7634
7635 module_init(bnx2_init);
7636 module_exit(bnx2_cleanup);
7637
7638
7639
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree