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8139too: Force usage of PIO on OQO2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / 8139too.c
blobf62ac64e98fed4b7ff92d737cb0115a54ef562c6
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/delay.h>
105 #include <linux/ethtool.h>
106 #include <linux/mii.h>
107 #include <linux/completion.h>
108 #include <linux/crc32.h>
109 #include <linux/io.h>
110 #include <linux/uaccess.h>
111 #include <asm/irq.h>
112
113 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
114 #define PFX DRV_NAME ": "
115
116 /* Default Message level */
117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 NETIF_MSG_PROBE | \
119 NETIF_MSG_LINK)
120
121
122 /* define to 1, 2 or 3 to enable copious debugging info */
123 #define RTL8139_DEBUG 0
124
125 /* define to 1 to disable lightweight runtime debugging checks */
126 #undef RTL8139_NDEBUG
127
128
129 #if RTL8139_DEBUG
130 /* note: prints function name for you */
131 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
132 #else
133 # define DPRINTK(fmt, args...)
134 #endif
135
136 #ifdef RTL8139_NDEBUG
137 # define assert(expr) do {} while (0)
138 #else
139 # define assert(expr) \
140 if(unlikely(!(expr))) { \
141 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
142 #expr, __FILE__, __func__, __LINE__); \
143 }
144 #endif
145
146
147 /* A few user-configurable values. */
148 /* media options */
149 #define MAX_UNITS 8
150 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
151 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
152
153 /* Whether to use MMIO or PIO. Default to MMIO. */
154 #ifdef CONFIG_8139TOO_PIO
155 static int use_io = 1;
156 #else
157 static int use_io = 0;
158 #endif
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 0 /* 8K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static const struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 FlashReg = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 PARA7c = 0x7c, /* Magic transceiver parameter register. */
329 Config5 = 0xD8, /* absent on RTL-8139A */
330 };
331
332 enum ClearBitMasks {
333 MultiIntrClear = 0xF000,
334 ChipCmdClear = 0xE2,
335 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
336 };
337
338 enum ChipCmdBits {
339 CmdReset = 0x10,
340 CmdRxEnb = 0x08,
341 CmdTxEnb = 0x04,
342 RxBufEmpty = 0x01,
343 };
344
345 /* Interrupt register bits, using my own meaningful names. */
346 enum IntrStatusBits {
347 PCIErr = 0x8000,
348 PCSTimeout = 0x4000,
349 RxFIFOOver = 0x40,
350 RxUnderrun = 0x20,
351 RxOverflow = 0x10,
352 TxErr = 0x08,
353 TxOK = 0x04,
354 RxErr = 0x02,
355 RxOK = 0x01,
356
357 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
358 };
359
360 enum TxStatusBits {
361 TxHostOwns = 0x2000,
362 TxUnderrun = 0x4000,
363 TxStatOK = 0x8000,
364 TxOutOfWindow = 0x20000000,
365 TxAborted = 0x40000000,
366 TxCarrierLost = 0x80000000,
367 };
368 enum RxStatusBits {
369 RxMulticast = 0x8000,
370 RxPhysical = 0x4000,
371 RxBroadcast = 0x2000,
372 RxBadSymbol = 0x0020,
373 RxRunt = 0x0010,
374 RxTooLong = 0x0008,
375 RxCRCErr = 0x0004,
376 RxBadAlign = 0x0002,
377 RxStatusOK = 0x0001,
378 };
379
380 /* Bits in RxConfig. */
381 enum rx_mode_bits {
382 AcceptErr = 0x20,
383 AcceptRunt = 0x10,
384 AcceptBroadcast = 0x08,
385 AcceptMulticast = 0x04,
386 AcceptMyPhys = 0x02,
387 AcceptAllPhys = 0x01,
388 };
389
390 /* Bits in TxConfig. */
391 enum tx_config_bits {
392 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
393 TxIFGShift = 24,
394 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
395 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
396 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
397 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
398
399 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
400 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
401 TxClearAbt = (1 << 0), /* Clear abort (WO) */
402 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
403 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
404
405 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
406 };
407
408 /* Bits in Config1 */
409 enum Config1Bits {
410 Cfg1_PM_Enable = 0x01,
411 Cfg1_VPD_Enable = 0x02,
412 Cfg1_PIO = 0x04,
413 Cfg1_MMIO = 0x08,
414 LWAKE = 0x10, /* not on 8139, 8139A */
415 Cfg1_Driver_Load = 0x20,
416 Cfg1_LED0 = 0x40,
417 Cfg1_LED1 = 0x80,
418 SLEEP = (1 << 1), /* only on 8139, 8139A */
419 PWRDN = (1 << 0), /* only on 8139, 8139A */
420 };
421
422 /* Bits in Config3 */
423 enum Config3Bits {
424 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
425 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
426 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
427 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
428 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
429 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
430 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
431 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
432 };
433
434 /* Bits in Config4 */
435 enum Config4Bits {
436 LWPTN = (1 << 2), /* not on 8139, 8139A */
437 };
438
439 /* Bits in Config5 */
440 enum Config5Bits {
441 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
442 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
443 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
444 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
445 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
446 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
447 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
448 };
449
450 enum RxConfigBits {
451 /* rx fifo threshold */
452 RxCfgFIFOShift = 13,
453 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454
455 /* Max DMA burst */
456 RxCfgDMAShift = 8,
457 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
458
459 /* rx ring buffer length */
460 RxCfgRcv8K = 0,
461 RxCfgRcv16K = (1 << 11),
462 RxCfgRcv32K = (1 << 12),
463 RxCfgRcv64K = (1 << 11) | (1 << 12),
464
465 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
466 RxNoWrap = (1 << 7),
467 };
468
469 /* Twister tuning parameters from RealTek.
470 Completely undocumented, but required to tune bad links on some boards. */
471 enum CSCRBits {
472 CSCR_LinkOKBit = 0x0400,
473 CSCR_LinkChangeBit = 0x0800,
474 CSCR_LinkStatusBits = 0x0f000,
475 CSCR_LinkDownOffCmd = 0x003c0,
476 CSCR_LinkDownCmd = 0x0f3c0,
477 };
478
479 enum Cfg9346Bits {
480 Cfg9346_Lock = 0x00,
481 Cfg9346_Unlock = 0xC0,
482 };
483
484 typedef enum {
485 CH_8139 = 0,
486 CH_8139_K,
487 CH_8139A,
488 CH_8139A_G,
489 CH_8139B,
490 CH_8130,
491 CH_8139C,
492 CH_8100,
493 CH_8100B_8139D,
494 CH_8101,
495 } chip_t;
496
497 enum chip_flags {
498 HasHltClk = (1 << 0),
499 HasLWake = (1 << 1),
500 };
501
502 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
503 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
504 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
505
506 /* directly indexed by chip_t, above */
507 static const struct {
508 const char *name;
509 u32 version; /* from RTL8139C/RTL8139D docs */
510 u32 flags;
511 } rtl_chip_info[] = {
512 { "RTL-8139",
513 HW_REVID(1, 0, 0, 0, 0, 0, 0),
514 HasHltClk,
515 },
516
517 { "RTL-8139 rev K",
518 HW_REVID(1, 1, 0, 0, 0, 0, 0),
519 HasHltClk,
520 },
521
522 { "RTL-8139A",
523 HW_REVID(1, 1, 1, 0, 0, 0, 0),
524 HasHltClk, /* XXX undocumented? */
525 },
526
527 { "RTL-8139A rev G",
528 HW_REVID(1, 1, 1, 0, 0, 1, 0),
529 HasHltClk, /* XXX undocumented? */
530 },
531
532 { "RTL-8139B",
533 HW_REVID(1, 1, 1, 1, 0, 0, 0),
534 HasLWake,
535 },
536
537 { "RTL-8130",
538 HW_REVID(1, 1, 1, 1, 1, 0, 0),
539 HasLWake,
540 },
541
542 { "RTL-8139C",
543 HW_REVID(1, 1, 1, 0, 1, 0, 0),
544 HasLWake,
545 },
546
547 { "RTL-8100",
548 HW_REVID(1, 1, 1, 1, 0, 1, 0),
549 HasLWake,
550 },
551
552 { "RTL-8100B/8139D",
553 HW_REVID(1, 1, 1, 0, 1, 0, 1),
554 HasHltClk /* XXX undocumented? */
555 | HasLWake,
556 },
557
558 { "RTL-8101",
559 HW_REVID(1, 1, 1, 0, 1, 1, 1),
560 HasLWake,
561 },
562 };
563
564 struct rtl_extra_stats {
565 unsigned long early_rx;
566 unsigned long tx_buf_mapped;
567 unsigned long tx_timeouts;
568 unsigned long rx_lost_in_ring;
569 };
570
571 struct rtl8139_private {
572 void __iomem *mmio_addr;
573 int drv_flags;
574 struct pci_dev *pci_dev;
575 u32 msg_enable;
576 struct napi_struct napi;
577 struct net_device *dev;
578
579 unsigned char *rx_ring;
580 unsigned int cur_rx; /* RX buf index of next pkt */
581 dma_addr_t rx_ring_dma;
582
583 unsigned int tx_flag;
584 unsigned long cur_tx;
585 unsigned long dirty_tx;
586 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
587 unsigned char *tx_bufs; /* Tx bounce buffer region. */
588 dma_addr_t tx_bufs_dma;
589
590 signed char phys[4]; /* MII device addresses. */
591
592 /* Twister tune state. */
593 char twistie, twist_row, twist_col;
594
595 unsigned int watchdog_fired : 1;
596 unsigned int default_port : 4; /* Last dev->if_port value. */
597 unsigned int have_thread : 1;
598
599 spinlock_t lock;
600 spinlock_t rx_lock;
601
602 chip_t chipset;
603 u32 rx_config;
604 struct rtl_extra_stats xstats;
605
606 struct delayed_work thread;
607
608 struct mii_if_info mii;
609 unsigned int regs_len;
610 unsigned long fifo_copy_timeout;
611 };
612
613 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
614 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
615 MODULE_LICENSE("GPL");
616 MODULE_VERSION(DRV_VERSION);
617
618 module_param(use_io, int, 0);
619 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
620 module_param(multicast_filter_limit, int, 0);
621 module_param_array(media, int, NULL, 0);
622 module_param_array(full_duplex, int, NULL, 0);
623 module_param(debug, int, 0);
624 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
625 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
626 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
627 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
628
629 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
630 static int rtl8139_open (struct net_device *dev);
631 static int mdio_read (struct net_device *dev, int phy_id, int location);
632 static void mdio_write (struct net_device *dev, int phy_id, int location,
633 int val);
634 static void rtl8139_start_thread(struct rtl8139_private *tp);
635 static void rtl8139_tx_timeout (struct net_device *dev);
636 static void rtl8139_init_ring (struct net_device *dev);
637 static int rtl8139_start_xmit (struct sk_buff *skb,
638 struct net_device *dev);
639 #ifdef CONFIG_NET_POLL_CONTROLLER
640 static void rtl8139_poll_controller(struct net_device *dev);
641 #endif
642 static int rtl8139_poll(struct napi_struct *napi, int budget);
643 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
644 static int rtl8139_close (struct net_device *dev);
645 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
646 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
647 static void rtl8139_set_rx_mode (struct net_device *dev);
648 static void __set_rx_mode (struct net_device *dev);
649 static void rtl8139_hw_start (struct net_device *dev);
650 static void rtl8139_thread (struct work_struct *work);
651 static void rtl8139_tx_timeout_task(struct work_struct *work);
652 static const struct ethtool_ops rtl8139_ethtool_ops;
653
654 /* write MMIO register, with flush */
655 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
656 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
657 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
658 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
659
660 /* write MMIO register */
661 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
662 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
663 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
664
665 /* read MMIO register */
666 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
667 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
668 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
669
670
671 static const u16 rtl8139_intr_mask =
672 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
673 TxErr | TxOK | RxErr | RxOK;
674
675 static const u16 rtl8139_norx_intr_mask =
676 PCIErr | PCSTimeout | RxUnderrun |
677 TxErr | TxOK | RxErr ;
678
679 #if RX_BUF_IDX == 0
680 static const unsigned int rtl8139_rx_config =
681 RxCfgRcv8K | RxNoWrap |
682 (RX_FIFO_THRESH << RxCfgFIFOShift) |
683 (RX_DMA_BURST << RxCfgDMAShift);
684 #elif RX_BUF_IDX == 1
685 static const unsigned int rtl8139_rx_config =
686 RxCfgRcv16K | RxNoWrap |
687 (RX_FIFO_THRESH << RxCfgFIFOShift) |
688 (RX_DMA_BURST << RxCfgDMAShift);
689 #elif RX_BUF_IDX == 2
690 static const unsigned int rtl8139_rx_config =
691 RxCfgRcv32K | RxNoWrap |
692 (RX_FIFO_THRESH << RxCfgFIFOShift) |
693 (RX_DMA_BURST << RxCfgDMAShift);
694 #elif RX_BUF_IDX == 3
695 static const unsigned int rtl8139_rx_config =
696 RxCfgRcv64K |
697 (RX_FIFO_THRESH << RxCfgFIFOShift) |
698 (RX_DMA_BURST << RxCfgDMAShift);
699 #else
700 #error "Invalid configuration for 8139_RXBUF_IDX"
701 #endif
702
703 static const unsigned int rtl8139_tx_config =
704 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
705
706 static void __rtl8139_cleanup_dev (struct net_device *dev)
707 {
708 struct rtl8139_private *tp = netdev_priv(dev);
709 struct pci_dev *pdev;
710
711 assert (dev != NULL);
712 assert (tp->pci_dev != NULL);
713 pdev = tp->pci_dev;
714
715 if (tp->mmio_addr)
716 pci_iounmap (pdev, tp->mmio_addr);
717
718 /* it's ok to call this even if we have no regions to free */
719 pci_release_regions (pdev);
720
721 free_netdev(dev);
722 pci_set_drvdata (pdev, NULL);
723 }
724
725
726 static void rtl8139_chip_reset (void __iomem *ioaddr)
727 {
728 int i;
729
730 /* Soft reset the chip. */
731 RTL_W8 (ChipCmd, CmdReset);
732
733 /* Check that the chip has finished the reset. */
734 for (i = 1000; i > 0; i--) {
735 barrier();
736 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
737 break;
738 udelay (10);
739 }
740 }
741
742
743 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
744 struct net_device **dev_out)
745 {
746 void __iomem *ioaddr;
747 struct net_device *dev;
748 struct rtl8139_private *tp;
749 u8 tmp8;
750 int rc, disable_dev_on_err = 0;
751 unsigned int i;
752 unsigned long pio_start, pio_end, pio_flags, pio_len;
753 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
754 u32 version;
755
756 assert (pdev != NULL);
757
758 *dev_out = NULL;
759
760 /* dev and priv zeroed in alloc_etherdev */
761 dev = alloc_etherdev (sizeof (*tp));
762 if (dev == NULL) {
763 dev_err(&pdev->dev, "Unable to alloc new net device\n");
764 return -ENOMEM;
765 }
766 SET_NETDEV_DEV(dev, &pdev->dev);
767
768 tp = netdev_priv(dev);
769 tp->pci_dev = pdev;
770
771 /* enable device (incl. PCI PM wakeup and hotplug setup) */
772 rc = pci_enable_device (pdev);
773 if (rc)
774 goto err_out;
775
776 pio_start = pci_resource_start (pdev, 0);
777 pio_end = pci_resource_end (pdev, 0);
778 pio_flags = pci_resource_flags (pdev, 0);
779 pio_len = pci_resource_len (pdev, 0);
780
781 mmio_start = pci_resource_start (pdev, 1);
782 mmio_end = pci_resource_end (pdev, 1);
783 mmio_flags = pci_resource_flags (pdev, 1);
784 mmio_len = pci_resource_len (pdev, 1);
785
786 /* set this immediately, we need to know before
787 * we talk to the chip directly */
788 DPRINTK("PIO region size == 0x%02X\n", pio_len);
789 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
790
791 if (use_io) {
792 /* make sure PCI base addr 0 is PIO */
793 if (!(pio_flags & IORESOURCE_IO)) {
794 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
795 rc = -ENODEV;
796 goto err_out;
797 }
798 /* check for weird/broken PCI region reporting */
799 if (pio_len < RTL_MIN_IO_SIZE) {
800 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
801 rc = -ENODEV;
802 goto err_out;
803 }
804 } else {
805 /* make sure PCI base addr 1 is MMIO */
806 if (!(mmio_flags & IORESOURCE_MEM)) {
807 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
808 rc = -ENODEV;
809 goto err_out;
810 }
811 if (mmio_len < RTL_MIN_IO_SIZE) {
812 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
813 rc = -ENODEV;
814 goto err_out;
815 }
816 }
817
818 rc = pci_request_regions (pdev, DRV_NAME);
819 if (rc)
820 goto err_out;
821 disable_dev_on_err = 1;
822
823 /* enable PCI bus-mastering */
824 pci_set_master (pdev);
825
826 if (use_io) {
827 ioaddr = pci_iomap(pdev, 0, 0);
828 if (!ioaddr) {
829 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
830 rc = -EIO;
831 goto err_out;
832 }
833 dev->base_addr = pio_start;
834 tp->regs_len = pio_len;
835 } else {
836 /* ioremap MMIO region */
837 ioaddr = pci_iomap(pdev, 1, 0);
838 if (ioaddr == NULL) {
839 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
840 rc = -EIO;
841 goto err_out;
842 }
843 dev->base_addr = (long) ioaddr;
844 tp->regs_len = mmio_len;
845 }
846 tp->mmio_addr = ioaddr;
847
848 /* Bring old chips out of low-power mode. */
849 RTL_W8 (HltClk, 'R');
850
851 /* check for missing/broken hardware */
852 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
853 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
854 rc = -EIO;
855 goto err_out;
856 }
857
858 /* identify chip attached to board */
859 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
860 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
861 if (version == rtl_chip_info[i].version) {
862 tp->chipset = i;
863 goto match;
864 }
865
866 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
867 dev_printk (KERN_DEBUG, &pdev->dev,
868 "unknown chip version, assuming RTL-8139\n");
869 dev_printk (KERN_DEBUG, &pdev->dev,
870 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
871 tp->chipset = 0;
872
873 match:
874 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
875 version, i, rtl_chip_info[i].name);
876
877 if (tp->chipset >= CH_8139B) {
878 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
879 DPRINTK("PCI PM wakeup\n");
880 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
881 (tmp8 & LWAKE))
882 new_tmp8 &= ~LWAKE;
883 new_tmp8 |= Cfg1_PM_Enable;
884 if (new_tmp8 != tmp8) {
885 RTL_W8 (Cfg9346, Cfg9346_Unlock);
886 RTL_W8 (Config1, tmp8);
887 RTL_W8 (Cfg9346, Cfg9346_Lock);
888 }
889 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
890 tmp8 = RTL_R8 (Config4);
891 if (tmp8 & LWPTN) {
892 RTL_W8 (Cfg9346, Cfg9346_Unlock);
893 RTL_W8 (Config4, tmp8 & ~LWPTN);
894 RTL_W8 (Cfg9346, Cfg9346_Lock);
895 }
896 }
897 } else {
898 DPRINTK("Old chip wakeup\n");
899 tmp8 = RTL_R8 (Config1);
900 tmp8 &= ~(SLEEP | PWRDN);
901 RTL_W8 (Config1, tmp8);
902 }
903
904 rtl8139_chip_reset (ioaddr);
905
906 *dev_out = dev;
907 return 0;
908
909 err_out:
910 __rtl8139_cleanup_dev (dev);
911 if (disable_dev_on_err)
912 pci_disable_device (pdev);
913 return rc;
914 }
915
916
917 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
918 const struct pci_device_id *ent)
919 {
920 struct net_device *dev = NULL;
921 struct rtl8139_private *tp;
922 int i, addr_len, option;
923 void __iomem *ioaddr;
924 static int board_idx = -1;
925 DECLARE_MAC_BUF(mac);
926
927 assert (pdev != NULL);
928 assert (ent != NULL);
929
930 board_idx++;
931
932 /* when we're built into the kernel, the driver version message
933 * is only printed if at least one 8139 board has been found
934 */
935 #ifndef MODULE
936 {
937 static int printed_version;
938 if (!printed_version++)
939 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
940 }
941 #endif
942
943 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
944 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
945 dev_info(&pdev->dev,
946 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
947 pdev->vendor, pdev->device, pdev->revision);
948 dev_info(&pdev->dev,
949 "Use the \"8139cp\" driver for improved performance and stability.\n");
950 }
951
952 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
953 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
954 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
955 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
956 printk(KERN_INFO "8139too: OQO Model 2 detected. Forcing PIO\n");
957 use_io = 1;
958 }
959
960 i = rtl8139_init_board (pdev, &dev);
961 if (i < 0)
962 return i;
963
964 assert (dev != NULL);
965 tp = netdev_priv(dev);
966 tp->dev = dev;
967
968 ioaddr = tp->mmio_addr;
969 assert (ioaddr != NULL);
970
971 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
972 for (i = 0; i < 3; i++)
973 ((__le16 *) (dev->dev_addr))[i] =
974 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
975 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
976
977 /* The Rtl8139-specific entries in the device structure. */
978 dev->open = rtl8139_open;
979 dev->hard_start_xmit = rtl8139_start_xmit;
980 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
981 dev->stop = rtl8139_close;
982 dev->get_stats = rtl8139_get_stats;
983 dev->set_multicast_list = rtl8139_set_rx_mode;
984 dev->do_ioctl = netdev_ioctl;
985 dev->ethtool_ops = &rtl8139_ethtool_ops;
986 dev->tx_timeout = rtl8139_tx_timeout;
987 dev->watchdog_timeo = TX_TIMEOUT;
988 #ifdef CONFIG_NET_POLL_CONTROLLER
989 dev->poll_controller = rtl8139_poll_controller;
990 #endif
991
992 /* note: the hardware is not capable of sg/csum/highdma, however
993 * through the use of skb_copy_and_csum_dev we enable these
994 * features
995 */
996 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
997
998 dev->irq = pdev->irq;
999
1000 /* tp zeroed and aligned in alloc_etherdev */
1001 tp = netdev_priv(dev);
1002
1003 /* note: tp->chipset set in rtl8139_init_board */
1004 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1005 tp->mmio_addr = ioaddr;
1006 tp->msg_enable =
1007 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1008 spin_lock_init (&tp->lock);
1009 spin_lock_init (&tp->rx_lock);
1010 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1011 tp->mii.dev = dev;
1012 tp->mii.mdio_read = mdio_read;
1013 tp->mii.mdio_write = mdio_write;
1014 tp->mii.phy_id_mask = 0x3f;
1015 tp->mii.reg_num_mask = 0x1f;
1016
1017 /* dev is fully set up and ready to use now */
1018 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1019 i = register_netdev (dev);
1020 if (i) goto err_out;
1021
1022 pci_set_drvdata (pdev, dev);
1023
1024 printk (KERN_INFO "%s: %s at 0x%lx, "
1025 "%s, IRQ %d\n",
1026 dev->name,
1027 board_info[ent->driver_data].name,
1028 dev->base_addr,
1029 print_mac(mac, dev->dev_addr),
1030 dev->irq);
1031
1032 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1033 dev->name, rtl_chip_info[tp->chipset].name);
1034
1035 /* Find the connected MII xcvrs.
1036 Doing this in open() would allow detecting external xcvrs later, but
1037 takes too much time. */
1038 #ifdef CONFIG_8139TOO_8129
1039 if (tp->drv_flags & HAS_MII_XCVR) {
1040 int phy, phy_idx = 0;
1041 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1042 int mii_status = mdio_read(dev, phy, 1);
1043 if (mii_status != 0xffff && mii_status != 0x0000) {
1044 u16 advertising = mdio_read(dev, phy, 4);
1045 tp->phys[phy_idx++] = phy;
1046 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1047 "advertising %4.4x.\n",
1048 dev->name, phy, mii_status, advertising);
1049 }
1050 }
1051 if (phy_idx == 0) {
1052 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1053 "transceiver.\n",
1054 dev->name);
1055 tp->phys[0] = 32;
1056 }
1057 } else
1058 #endif
1059 tp->phys[0] = 32;
1060 tp->mii.phy_id = tp->phys[0];
1061
1062 /* The lower four bits are the media type. */
1063 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1064 if (option > 0) {
1065 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1066 tp->default_port = option & 0xFF;
1067 if (tp->default_port)
1068 tp->mii.force_media = 1;
1069 }
1070 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1071 tp->mii.full_duplex = full_duplex[board_idx];
1072 if (tp->mii.full_duplex) {
1073 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1074 /* Changing the MII-advertised media because might prevent
1075 re-connection. */
1076 tp->mii.force_media = 1;
1077 }
1078 if (tp->default_port) {
1079 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1080 (option & 0x20 ? 100 : 10),
1081 (option & 0x10 ? "full" : "half"));
1082 mdio_write(dev, tp->phys[0], 0,
1083 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1084 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1085 }
1086
1087 /* Put the chip into low-power mode. */
1088 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1089 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1090
1091 return 0;
1092
1093 err_out:
1094 __rtl8139_cleanup_dev (dev);
1095 pci_disable_device (pdev);
1096 return i;
1097 }
1098
1099
1100 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1101 {
1102 struct net_device *dev = pci_get_drvdata (pdev);
1103
1104 assert (dev != NULL);
1105
1106 flush_scheduled_work();
1107
1108 unregister_netdev (dev);
1109
1110 __rtl8139_cleanup_dev (dev);
1111 pci_disable_device (pdev);
1112 }
1113
1114
1115 /* Serial EEPROM section. */
1116
1117 /* EEPROM_Ctrl bits. */
1118 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1119 #define EE_CS 0x08 /* EEPROM chip select. */
1120 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1121 #define EE_WRITE_0 0x00
1122 #define EE_WRITE_1 0x02
1123 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1124 #define EE_ENB (0x80 | EE_CS)
1125
1126 /* Delay between EEPROM clock transitions.
1127 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1128 */
1129
1130 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1131
1132 /* The EEPROM commands include the alway-set leading bit. */
1133 #define EE_WRITE_CMD (5)
1134 #define EE_READ_CMD (6)
1135 #define EE_ERASE_CMD (7)
1136
1137 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1138 {
1139 int i;
1140 unsigned retval = 0;
1141 int read_cmd = location | (EE_READ_CMD << addr_len);
1142
1143 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1144 RTL_W8 (Cfg9346, EE_ENB);
1145 eeprom_delay ();
1146
1147 /* Shift the read command bits out. */
1148 for (i = 4 + addr_len; i >= 0; i--) {
1149 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1150 RTL_W8 (Cfg9346, EE_ENB | dataval);
1151 eeprom_delay ();
1152 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1153 eeprom_delay ();
1154 }
1155 RTL_W8 (Cfg9346, EE_ENB);
1156 eeprom_delay ();
1157
1158 for (i = 16; i > 0; i--) {
1159 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1160 eeprom_delay ();
1161 retval =
1162 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1163 0);
1164 RTL_W8 (Cfg9346, EE_ENB);
1165 eeprom_delay ();
1166 }
1167
1168 /* Terminate the EEPROM access. */
1169 RTL_W8 (Cfg9346, ~EE_CS);
1170 eeprom_delay ();
1171
1172 return retval;
1173 }
1174
1175 /* MII serial management: mostly bogus for now. */
1176 /* Read and write the MII management registers using software-generated
1177 serial MDIO protocol.
1178 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1179 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1180 "overclocking" issues. */
1181 #define MDIO_DIR 0x80
1182 #define MDIO_DATA_OUT 0x04
1183 #define MDIO_DATA_IN 0x02
1184 #define MDIO_CLK 0x01
1185 #define MDIO_WRITE0 (MDIO_DIR)
1186 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1187
1188 #define mdio_delay() RTL_R8(Config4)
1189
1190
1191 static const char mii_2_8139_map[8] = {
1192 BasicModeCtrl,
1193 BasicModeStatus,
1194 0,
1195 0,
1196 NWayAdvert,
1197 NWayLPAR,
1198 NWayExpansion,
1199 0
1200 };
1201
1202
1203 #ifdef CONFIG_8139TOO_8129
1204 /* Syncronize the MII management interface by shifting 32 one bits out. */
1205 static void mdio_sync (void __iomem *ioaddr)
1206 {
1207 int i;
1208
1209 for (i = 32; i >= 0; i--) {
1210 RTL_W8 (Config4, MDIO_WRITE1);
1211 mdio_delay ();
1212 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1213 mdio_delay ();
1214 }
1215 }
1216 #endif
1217
1218 static int mdio_read (struct net_device *dev, int phy_id, int location)
1219 {
1220 struct rtl8139_private *tp = netdev_priv(dev);
1221 int retval = 0;
1222 #ifdef CONFIG_8139TOO_8129
1223 void __iomem *ioaddr = tp->mmio_addr;
1224 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1225 int i;
1226 #endif
1227
1228 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1229 void __iomem *ioaddr = tp->mmio_addr;
1230 return location < 8 && mii_2_8139_map[location] ?
1231 RTL_R16 (mii_2_8139_map[location]) : 0;
1232 }
1233
1234 #ifdef CONFIG_8139TOO_8129
1235 mdio_sync (ioaddr);
1236 /* Shift the read command bits out. */
1237 for (i = 15; i >= 0; i--) {
1238 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1239
1240 RTL_W8 (Config4, MDIO_DIR | dataval);
1241 mdio_delay ();
1242 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1243 mdio_delay ();
1244 }
1245
1246 /* Read the two transition, 16 data, and wire-idle bits. */
1247 for (i = 19; i > 0; i--) {
1248 RTL_W8 (Config4, 0);
1249 mdio_delay ();
1250 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1251 RTL_W8 (Config4, MDIO_CLK);
1252 mdio_delay ();
1253 }
1254 #endif
1255
1256 return (retval >> 1) & 0xffff;
1257 }
1258
1259
1260 static void mdio_write (struct net_device *dev, int phy_id, int location,
1261 int value)
1262 {
1263 struct rtl8139_private *tp = netdev_priv(dev);
1264 #ifdef CONFIG_8139TOO_8129
1265 void __iomem *ioaddr = tp->mmio_addr;
1266 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1267 int i;
1268 #endif
1269
1270 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1271 void __iomem *ioaddr = tp->mmio_addr;
1272 if (location == 0) {
1273 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1274 RTL_W16 (BasicModeCtrl, value);
1275 RTL_W8 (Cfg9346, Cfg9346_Lock);
1276 } else if (location < 8 && mii_2_8139_map[location])
1277 RTL_W16 (mii_2_8139_map[location], value);
1278 return;
1279 }
1280
1281 #ifdef CONFIG_8139TOO_8129
1282 mdio_sync (ioaddr);
1283
1284 /* Shift the command bits out. */
1285 for (i = 31; i >= 0; i--) {
1286 int dataval =
1287 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1288 RTL_W8 (Config4, dataval);
1289 mdio_delay ();
1290 RTL_W8 (Config4, dataval | MDIO_CLK);
1291 mdio_delay ();
1292 }
1293 /* Clear out extra bits. */
1294 for (i = 2; i > 0; i--) {
1295 RTL_W8 (Config4, 0);
1296 mdio_delay ();
1297 RTL_W8 (Config4, MDIO_CLK);
1298 mdio_delay ();
1299 }
1300 #endif
1301 }
1302
1303
1304 static int rtl8139_open (struct net_device *dev)
1305 {
1306 struct rtl8139_private *tp = netdev_priv(dev);
1307 int retval;
1308 void __iomem *ioaddr = tp->mmio_addr;
1309
1310 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1311 if (retval)
1312 return retval;
1313
1314 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1315 &tp->tx_bufs_dma, GFP_KERNEL);
1316 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1317 &tp->rx_ring_dma, GFP_KERNEL);
1318 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1319 free_irq(dev->irq, dev);
1320
1321 if (tp->tx_bufs)
1322 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1323 tp->tx_bufs, tp->tx_bufs_dma);
1324 if (tp->rx_ring)
1325 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1326 tp->rx_ring, tp->rx_ring_dma);
1327
1328 return -ENOMEM;
1329
1330 }
1331
1332 napi_enable(&tp->napi);
1333
1334 tp->mii.full_duplex = tp->mii.force_media;
1335 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1336
1337 rtl8139_init_ring (dev);
1338 rtl8139_hw_start (dev);
1339 netif_start_queue (dev);
1340
1341 if (netif_msg_ifup(tp))
1342 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1343 " GP Pins %2.2x %s-duplex.\n", dev->name,
1344 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1345 dev->irq, RTL_R8 (MediaStatus),
1346 tp->mii.full_duplex ? "full" : "half");
1347
1348 rtl8139_start_thread(tp);
1349
1350 return 0;
1351 }
1352
1353
1354 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1355 {
1356 struct rtl8139_private *tp = netdev_priv(dev);
1357
1358 if (tp->phys[0] >= 0) {
1359 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1360 }
1361 }
1362
1363 /* Start the hardware at open or resume. */
1364 static void rtl8139_hw_start (struct net_device *dev)
1365 {
1366 struct rtl8139_private *tp = netdev_priv(dev);
1367 void __iomem *ioaddr = tp->mmio_addr;
1368 u32 i;
1369 u8 tmp;
1370
1371 /* Bring old chips out of low-power mode. */
1372 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1373 RTL_W8 (HltClk, 'R');
1374
1375 rtl8139_chip_reset (ioaddr);
1376
1377 /* unlock Config[01234] and BMCR register writes */
1378 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1379 /* Restore our idea of the MAC address. */
1380 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1381 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1382
1383 /* Must enable Tx/Rx before setting transfer thresholds! */
1384 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1385
1386 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1387 RTL_W32 (RxConfig, tp->rx_config);
1388 RTL_W32 (TxConfig, rtl8139_tx_config);
1389
1390 tp->cur_rx = 0;
1391
1392 rtl_check_media (dev, 1);
1393
1394 if (tp->chipset >= CH_8139B) {
1395 /* Disable magic packet scanning, which is enabled
1396 * when PM is enabled in Config1. It can be reenabled
1397 * via ETHTOOL_SWOL if desired. */
1398 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1399 }
1400
1401 DPRINTK("init buffer addresses\n");
1402
1403 /* Lock Config[01234] and BMCR register writes */
1404 RTL_W8 (Cfg9346, Cfg9346_Lock);
1405
1406 /* init Rx ring buffer DMA address */
1407 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1408
1409 /* init Tx buffer DMA addresses */
1410 for (i = 0; i < NUM_TX_DESC; i++)
1411 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1412
1413 RTL_W32 (RxMissed, 0);
1414
1415 rtl8139_set_rx_mode (dev);
1416
1417 /* no early-rx interrupts */
1418 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1419
1420 /* make sure RxTx has started */
1421 tmp = RTL_R8 (ChipCmd);
1422 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1423 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1424
1425 /* Enable all known interrupts by setting the interrupt mask. */
1426 RTL_W16 (IntrMask, rtl8139_intr_mask);
1427 }
1428
1429
1430 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1431 static void rtl8139_init_ring (struct net_device *dev)
1432 {
1433 struct rtl8139_private *tp = netdev_priv(dev);
1434 int i;
1435
1436 tp->cur_rx = 0;
1437 tp->cur_tx = 0;
1438 tp->dirty_tx = 0;
1439
1440 for (i = 0; i < NUM_TX_DESC; i++)
1441 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1442 }
1443
1444
1445 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1446 static int next_tick = 3 * HZ;
1447
1448 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1449 static inline void rtl8139_tune_twister (struct net_device *dev,
1450 struct rtl8139_private *tp) {}
1451 #else
1452 enum TwisterParamVals {
1453 PARA78_default = 0x78fa8388,
1454 PARA7c_default = 0xcb38de43, /* param[0][3] */
1455 PARA7c_xxx = 0xcb38de43,
1456 };
1457
1458 static const unsigned long param[4][4] = {
1459 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1460 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1461 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1462 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1463 };
1464
1465 static void rtl8139_tune_twister (struct net_device *dev,
1466 struct rtl8139_private *tp)
1467 {
1468 int linkcase;
1469 void __iomem *ioaddr = tp->mmio_addr;
1470
1471 /* This is a complicated state machine to configure the "twister" for
1472 impedance/echos based on the cable length.
1473 All of this is magic and undocumented.
1474 */
1475 switch (tp->twistie) {
1476 case 1:
1477 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1478 /* We have link beat, let us tune the twister. */
1479 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1480 tp->twistie = 2; /* Change to state 2. */
1481 next_tick = HZ / 10;
1482 } else {
1483 /* Just put in some reasonable defaults for when beat returns. */
1484 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1485 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1486 RTL_W32 (PARA78, PARA78_default);
1487 RTL_W32 (PARA7c, PARA7c_default);
1488 tp->twistie = 0; /* Bail from future actions. */
1489 }
1490 break;
1491 case 2:
1492 /* Read how long it took to hear the echo. */
1493 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1494 if (linkcase == 0x7000)
1495 tp->twist_row = 3;
1496 else if (linkcase == 0x3000)
1497 tp->twist_row = 2;
1498 else if (linkcase == 0x1000)
1499 tp->twist_row = 1;
1500 else
1501 tp->twist_row = 0;
1502 tp->twist_col = 0;
1503 tp->twistie = 3; /* Change to state 2. */
1504 next_tick = HZ / 10;
1505 break;
1506 case 3:
1507 /* Put out four tuning parameters, one per 100msec. */
1508 if (tp->twist_col == 0)
1509 RTL_W16 (FIFOTMS, 0);
1510 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1511 [(int) tp->twist_col]);
1512 next_tick = HZ / 10;
1513 if (++tp->twist_col >= 4) {
1514 /* For short cables we are done.
1515 For long cables (row == 3) check for mistune. */
1516 tp->twistie =
1517 (tp->twist_row == 3) ? 4 : 0;
1518 }
1519 break;
1520 case 4:
1521 /* Special case for long cables: check for mistune. */
1522 if ((RTL_R16 (CSCR) &
1523 CSCR_LinkStatusBits) == 0x7000) {
1524 tp->twistie = 0;
1525 break;
1526 } else {
1527 RTL_W32 (PARA7c, 0xfb38de03);
1528 tp->twistie = 5;
1529 next_tick = HZ / 10;
1530 }
1531 break;
1532 case 5:
1533 /* Retune for shorter cable (column 2). */
1534 RTL_W32 (FIFOTMS, 0x20);
1535 RTL_W32 (PARA78, PARA78_default);
1536 RTL_W32 (PARA7c, PARA7c_default);
1537 RTL_W32 (FIFOTMS, 0x00);
1538 tp->twist_row = 2;
1539 tp->twist_col = 0;
1540 tp->twistie = 3;
1541 next_tick = HZ / 10;
1542 break;
1543
1544 default:
1545 /* do nothing */
1546 break;
1547 }
1548 }
1549 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1550
1551 static inline void rtl8139_thread_iter (struct net_device *dev,
1552 struct rtl8139_private *tp,
1553 void __iomem *ioaddr)
1554 {
1555 int mii_lpa;
1556
1557 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1558
1559 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1560 int duplex = (mii_lpa & LPA_100FULL)
1561 || (mii_lpa & 0x01C0) == 0x0040;
1562 if (tp->mii.full_duplex != duplex) {
1563 tp->mii.full_duplex = duplex;
1564
1565 if (mii_lpa) {
1566 printk (KERN_INFO
1567 "%s: Setting %s-duplex based on MII #%d link"
1568 " partner ability of %4.4x.\n",
1569 dev->name,
1570 tp->mii.full_duplex ? "full" : "half",
1571 tp->phys[0], mii_lpa);
1572 } else {
1573 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1574 dev->name);
1575 }
1576 #if 0
1577 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1578 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1579 RTL_W8 (Cfg9346, Cfg9346_Lock);
1580 #endif
1581 }
1582 }
1583
1584 next_tick = HZ * 60;
1585
1586 rtl8139_tune_twister (dev, tp);
1587
1588 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1589 dev->name, RTL_R16 (NWayLPAR));
1590 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1591 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1592 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1593 dev->name, RTL_R8 (Config0),
1594 RTL_R8 (Config1));
1595 }
1596
1597 static void rtl8139_thread (struct work_struct *work)
1598 {
1599 struct rtl8139_private *tp =
1600 container_of(work, struct rtl8139_private, thread.work);
1601 struct net_device *dev = tp->mii.dev;
1602 unsigned long thr_delay = next_tick;
1603
1604 rtnl_lock();
1605
1606 if (!netif_running(dev))
1607 goto out_unlock;
1608
1609 if (tp->watchdog_fired) {
1610 tp->watchdog_fired = 0;
1611 rtl8139_tx_timeout_task(work);
1612 } else
1613 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1614
1615 if (tp->have_thread)
1616 schedule_delayed_work(&tp->thread, thr_delay);
1617 out_unlock:
1618 rtnl_unlock ();
1619 }
1620
1621 static void rtl8139_start_thread(struct rtl8139_private *tp)
1622 {
1623 tp->twistie = 0;
1624 if (tp->chipset == CH_8139_K)
1625 tp->twistie = 1;
1626 else if (tp->drv_flags & HAS_LNK_CHNG)
1627 return;
1628
1629 tp->have_thread = 1;
1630 tp->watchdog_fired = 0;
1631
1632 schedule_delayed_work(&tp->thread, next_tick);
1633 }
1634
1635 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1636 {
1637 tp->cur_tx = 0;
1638 tp->dirty_tx = 0;
1639
1640 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1641 }
1642
1643 static void rtl8139_tx_timeout_task (struct work_struct *work)
1644 {
1645 struct rtl8139_private *tp =
1646 container_of(work, struct rtl8139_private, thread.work);
1647 struct net_device *dev = tp->mii.dev;
1648 void __iomem *ioaddr = tp->mmio_addr;
1649 int i;
1650 u8 tmp8;
1651
1652 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1653 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1654 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1655 /* Emit info to figure out what went wrong. */
1656 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1657 dev->name, tp->cur_tx, tp->dirty_tx);
1658 for (i = 0; i < NUM_TX_DESC; i++)
1659 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1660 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1661 i == tp->dirty_tx % NUM_TX_DESC ?
1662 " (queue head)" : "");
1663
1664 tp->xstats.tx_timeouts++;
1665
1666 /* disable Tx ASAP, if not already */
1667 tmp8 = RTL_R8 (ChipCmd);
1668 if (tmp8 & CmdTxEnb)
1669 RTL_W8 (ChipCmd, CmdRxEnb);
1670
1671 spin_lock_bh(&tp->rx_lock);
1672 /* Disable interrupts by clearing the interrupt mask. */
1673 RTL_W16 (IntrMask, 0x0000);
1674
1675 /* Stop a shared interrupt from scavenging while we are. */
1676 spin_lock_irq(&tp->lock);
1677 rtl8139_tx_clear (tp);
1678 spin_unlock_irq(&tp->lock);
1679
1680 /* ...and finally, reset everything */
1681 if (netif_running(dev)) {
1682 rtl8139_hw_start (dev);
1683 netif_wake_queue (dev);
1684 }
1685 spin_unlock_bh(&tp->rx_lock);
1686 }
1687
1688 static void rtl8139_tx_timeout (struct net_device *dev)
1689 {
1690 struct rtl8139_private *tp = netdev_priv(dev);
1691
1692 tp->watchdog_fired = 1;
1693 if (!tp->have_thread) {
1694 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1695 schedule_delayed_work(&tp->thread, next_tick);
1696 }
1697 }
1698
1699 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1700 {
1701 struct rtl8139_private *tp = netdev_priv(dev);
1702 void __iomem *ioaddr = tp->mmio_addr;
1703 unsigned int entry;
1704 unsigned int len = skb->len;
1705 unsigned long flags;
1706
1707 /* Calculate the next Tx descriptor entry. */
1708 entry = tp->cur_tx % NUM_TX_DESC;
1709
1710 /* Note: the chip doesn't have auto-pad! */
1711 if (likely(len < TX_BUF_SIZE)) {
1712 if (len < ETH_ZLEN)
1713 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1714 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1715 dev_kfree_skb(skb);
1716 } else {
1717 dev_kfree_skb(skb);
1718 dev->stats.tx_dropped++;
1719 return 0;
1720 }
1721
1722 spin_lock_irqsave(&tp->lock, flags);
1723 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1724 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1725
1726 dev->trans_start = jiffies;
1727
1728 tp->cur_tx++;
1729 wmb();
1730
1731 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1732 netif_stop_queue (dev);
1733 spin_unlock_irqrestore(&tp->lock, flags);
1734
1735 if (netif_msg_tx_queued(tp))
1736 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1737 dev->name, len, entry);
1738
1739 return 0;
1740 }
1741
1742
1743 static void rtl8139_tx_interrupt (struct net_device *dev,
1744 struct rtl8139_private *tp,
1745 void __iomem *ioaddr)
1746 {
1747 unsigned long dirty_tx, tx_left;
1748
1749 assert (dev != NULL);
1750 assert (ioaddr != NULL);
1751
1752 dirty_tx = tp->dirty_tx;
1753 tx_left = tp->cur_tx - dirty_tx;
1754 while (tx_left > 0) {
1755 int entry = dirty_tx % NUM_TX_DESC;
1756 int txstatus;
1757
1758 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1759
1760 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1761 break; /* It still hasn't been Txed */
1762
1763 /* Note: TxCarrierLost is always asserted at 100mbps. */
1764 if (txstatus & (TxOutOfWindow | TxAborted)) {
1765 /* There was an major error, log it. */
1766 if (netif_msg_tx_err(tp))
1767 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1768 dev->name, txstatus);
1769 dev->stats.tx_errors++;
1770 if (txstatus & TxAborted) {
1771 dev->stats.tx_aborted_errors++;
1772 RTL_W32 (TxConfig, TxClearAbt);
1773 RTL_W16 (IntrStatus, TxErr);
1774 wmb();
1775 }
1776 if (txstatus & TxCarrierLost)
1777 dev->stats.tx_carrier_errors++;
1778 if (txstatus & TxOutOfWindow)
1779 dev->stats.tx_window_errors++;
1780 } else {
1781 if (txstatus & TxUnderrun) {
1782 /* Add 64 to the Tx FIFO threshold. */
1783 if (tp->tx_flag < 0x00300000)
1784 tp->tx_flag += 0x00020000;
1785 dev->stats.tx_fifo_errors++;
1786 }
1787 dev->stats.collisions += (txstatus >> 24) & 15;
1788 dev->stats.tx_bytes += txstatus & 0x7ff;
1789 dev->stats.tx_packets++;
1790 }
1791
1792 dirty_tx++;
1793 tx_left--;
1794 }
1795
1796 #ifndef RTL8139_NDEBUG
1797 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1798 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1799 dev->name, dirty_tx, tp->cur_tx);
1800 dirty_tx += NUM_TX_DESC;
1801 }
1802 #endif /* RTL8139_NDEBUG */
1803
1804 /* only wake the queue if we did work, and the queue is stopped */
1805 if (tp->dirty_tx != dirty_tx) {
1806 tp->dirty_tx = dirty_tx;
1807 mb();
1808 netif_wake_queue (dev);
1809 }
1810 }
1811
1812
1813 /* TODO: clean this up! Rx reset need not be this intensive */
1814 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1815 struct rtl8139_private *tp, void __iomem *ioaddr)
1816 {
1817 u8 tmp8;
1818 #ifdef CONFIG_8139_OLD_RX_RESET
1819 int tmp_work;
1820 #endif
1821
1822 if (netif_msg_rx_err (tp))
1823 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1824 dev->name, rx_status);
1825 dev->stats.rx_errors++;
1826 if (!(rx_status & RxStatusOK)) {
1827 if (rx_status & RxTooLong) {
1828 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1829 dev->name, rx_status);
1830 /* A.C.: The chip hangs here. */
1831 }
1832 if (rx_status & (RxBadSymbol | RxBadAlign))
1833 dev->stats.rx_frame_errors++;
1834 if (rx_status & (RxRunt | RxTooLong))
1835 dev->stats.rx_length_errors++;
1836 if (rx_status & RxCRCErr)
1837 dev->stats.rx_crc_errors++;
1838 } else {
1839 tp->xstats.rx_lost_in_ring++;
1840 }
1841
1842 #ifndef CONFIG_8139_OLD_RX_RESET
1843 tmp8 = RTL_R8 (ChipCmd);
1844 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1845 RTL_W8 (ChipCmd, tmp8);
1846 RTL_W32 (RxConfig, tp->rx_config);
1847 tp->cur_rx = 0;
1848 #else
1849 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1850
1851 /* disable receive */
1852 RTL_W8_F (ChipCmd, CmdTxEnb);
1853 tmp_work = 200;
1854 while (--tmp_work > 0) {
1855 udelay(1);
1856 tmp8 = RTL_R8 (ChipCmd);
1857 if (!(tmp8 & CmdRxEnb))
1858 break;
1859 }
1860 if (tmp_work <= 0)
1861 printk (KERN_WARNING PFX "rx stop wait too long\n");
1862 /* restart receive */
1863 tmp_work = 200;
1864 while (--tmp_work > 0) {
1865 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1866 udelay(1);
1867 tmp8 = RTL_R8 (ChipCmd);
1868 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1869 break;
1870 }
1871 if (tmp_work <= 0)
1872 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1873
1874 /* and reinitialize all rx related registers */
1875 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1876 /* Must enable Tx/Rx before setting transfer thresholds! */
1877 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1878
1879 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1880 RTL_W32 (RxConfig, tp->rx_config);
1881 tp->cur_rx = 0;
1882
1883 DPRINTK("init buffer addresses\n");
1884
1885 /* Lock Config[01234] and BMCR register writes */
1886 RTL_W8 (Cfg9346, Cfg9346_Lock);
1887
1888 /* init Rx ring buffer DMA address */
1889 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1890
1891 /* A.C.: Reset the multicast list. */
1892 __set_rx_mode (dev);
1893 #endif
1894 }
1895
1896 #if RX_BUF_IDX == 3
1897 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1898 u32 offset, unsigned int size)
1899 {
1900 u32 left = RX_BUF_LEN - offset;
1901
1902 if (size > left) {
1903 skb_copy_to_linear_data(skb, ring + offset, left);
1904 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1905 } else
1906 skb_copy_to_linear_data(skb, ring + offset, size);
1907 }
1908 #endif
1909
1910 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1911 {
1912 void __iomem *ioaddr = tp->mmio_addr;
1913 u16 status;
1914
1915 status = RTL_R16 (IntrStatus) & RxAckBits;
1916
1917 /* Clear out errors and receive interrupts */
1918 if (likely(status != 0)) {
1919 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1920 tp->dev->stats.rx_errors++;
1921 if (status & RxFIFOOver)
1922 tp->dev->stats.rx_fifo_errors++;
1923 }
1924 RTL_W16_F (IntrStatus, RxAckBits);
1925 }
1926 }
1927
1928 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1929 int budget)
1930 {
1931 void __iomem *ioaddr = tp->mmio_addr;
1932 int received = 0;
1933 unsigned char *rx_ring = tp->rx_ring;
1934 unsigned int cur_rx = tp->cur_rx;
1935 unsigned int rx_size = 0;
1936
1937 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1938 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1939 RTL_R16 (RxBufAddr),
1940 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1941
1942 while (netif_running(dev) && received < budget
1943 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1944 u32 ring_offset = cur_rx % RX_BUF_LEN;
1945 u32 rx_status;
1946 unsigned int pkt_size;
1947 struct sk_buff *skb;
1948
1949 rmb();
1950
1951 /* read size+status of next frame from DMA ring buffer */
1952 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1953 rx_size = rx_status >> 16;
1954 pkt_size = rx_size - 4;
1955
1956 if (netif_msg_rx_status(tp))
1957 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1958 " cur %4.4x.\n", dev->name, rx_status,
1959 rx_size, cur_rx);
1960 #if RTL8139_DEBUG > 2
1961 {
1962 int i;
1963 DPRINTK ("%s: Frame contents ", dev->name);
1964 for (i = 0; i < 70; i++)
1965 printk (" %2.2x",
1966 rx_ring[ring_offset + i]);
1967 printk (".\n");
1968 }
1969 #endif
1970
1971 /* Packet copy from FIFO still in progress.
1972 * Theoretically, this should never happen
1973 * since EarlyRx is disabled.
1974 */
1975 if (unlikely(rx_size == 0xfff0)) {
1976 if (!tp->fifo_copy_timeout)
1977 tp->fifo_copy_timeout = jiffies + 2;
1978 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1979 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1980 rx_size = 0;
1981 goto no_early_rx;
1982 }
1983 if (netif_msg_intr(tp)) {
1984 printk(KERN_DEBUG "%s: fifo copy in progress.",
1985 dev->name);
1986 }
1987 tp->xstats.early_rx++;
1988 break;
1989 }
1990
1991 no_early_rx:
1992 tp->fifo_copy_timeout = 0;
1993
1994 /* If Rx err or invalid rx_size/rx_status received
1995 * (which happens if we get lost in the ring),
1996 * Rx process gets reset, so we abort any further
1997 * Rx processing.
1998 */
1999 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2000 (rx_size < 8) ||
2001 (!(rx_status & RxStatusOK)))) {
2002 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2003 received = -1;
2004 goto out;
2005 }
2006
2007 /* Malloc up new buffer, compatible with net-2e. */
2008 /* Omit the four octet CRC from the length. */
2009
2010 skb = dev_alloc_skb (pkt_size + 2);
2011 if (likely(skb)) {
2012 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2013 #if RX_BUF_IDX == 3
2014 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2015 #else
2016 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2017 #endif
2018 skb_put (skb, pkt_size);
2019
2020 skb->protocol = eth_type_trans (skb, dev);
2021
2022 dev->last_rx = jiffies;
2023 dev->stats.rx_bytes += pkt_size;
2024 dev->stats.rx_packets++;
2025
2026 netif_receive_skb (skb);
2027 } else {
2028 if (net_ratelimit())
2029 printk (KERN_WARNING
2030 "%s: Memory squeeze, dropping packet.\n",
2031 dev->name);
2032 dev->stats.rx_dropped++;
2033 }
2034 received++;
2035
2036 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2037 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2038
2039 rtl8139_isr_ack(tp);
2040 }
2041
2042 if (unlikely(!received || rx_size == 0xfff0))
2043 rtl8139_isr_ack(tp);
2044
2045 #if RTL8139_DEBUG > 1
2046 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2047 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2048 RTL_R16 (RxBufAddr),
2049 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2050 #endif
2051
2052 tp->cur_rx = cur_rx;
2053
2054 /*
2055 * The receive buffer should be mostly empty.
2056 * Tell NAPI to reenable the Rx irq.
2057 */
2058 if (tp->fifo_copy_timeout)
2059 received = budget;
2060
2061 out:
2062 return received;
2063 }
2064
2065
2066 static void rtl8139_weird_interrupt (struct net_device *dev,
2067 struct rtl8139_private *tp,
2068 void __iomem *ioaddr,
2069 int status, int link_changed)
2070 {
2071 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2072 dev->name, status);
2073
2074 assert (dev != NULL);
2075 assert (tp != NULL);
2076 assert (ioaddr != NULL);
2077
2078 /* Update the error count. */
2079 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2080 RTL_W32 (RxMissed, 0);
2081
2082 if ((status & RxUnderrun) && link_changed &&
2083 (tp->drv_flags & HAS_LNK_CHNG)) {
2084 rtl_check_media(dev, 0);
2085 status &= ~RxUnderrun;
2086 }
2087
2088 if (status & (RxUnderrun | RxErr))
2089 dev->stats.rx_errors++;
2090
2091 if (status & PCSTimeout)
2092 dev->stats.rx_length_errors++;
2093 if (status & RxUnderrun)
2094 dev->stats.rx_fifo_errors++;
2095 if (status & PCIErr) {
2096 u16 pci_cmd_status;
2097 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2098 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2099
2100 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2101 dev->name, pci_cmd_status);
2102 }
2103 }
2104
2105 static int rtl8139_poll(struct napi_struct *napi, int budget)
2106 {
2107 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2108 struct net_device *dev = tp->dev;
2109 void __iomem *ioaddr = tp->mmio_addr;
2110 int work_done;
2111
2112 spin_lock(&tp->rx_lock);
2113 work_done = 0;
2114 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2115 work_done += rtl8139_rx(dev, tp, budget);
2116
2117 if (work_done < budget) {
2118 unsigned long flags;
2119 /*
2120 * Order is important since data can get interrupted
2121 * again when we think we are done.
2122 */
2123 spin_lock_irqsave(&tp->lock, flags);
2124 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2125 __netif_rx_complete(dev, napi);
2126 spin_unlock_irqrestore(&tp->lock, flags);
2127 }
2128 spin_unlock(&tp->rx_lock);
2129
2130 return work_done;
2131 }
2132
2133 /* The interrupt handler does all of the Rx thread work and cleans up
2134 after the Tx thread. */
2135 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2136 {
2137 struct net_device *dev = (struct net_device *) dev_instance;
2138 struct rtl8139_private *tp = netdev_priv(dev);
2139 void __iomem *ioaddr = tp->mmio_addr;
2140 u16 status, ackstat;
2141 int link_changed = 0; /* avoid bogus "uninit" warning */
2142 int handled = 0;
2143
2144 spin_lock (&tp->lock);
2145 status = RTL_R16 (IntrStatus);
2146
2147 /* shared irq? */
2148 if (unlikely((status & rtl8139_intr_mask) == 0))
2149 goto out;
2150
2151 handled = 1;
2152
2153 /* h/w no longer present (hotplug?) or major error, bail */
2154 if (unlikely(status == 0xFFFF))
2155 goto out;
2156
2157 /* close possible race's with dev_close */
2158 if (unlikely(!netif_running(dev))) {
2159 RTL_W16 (IntrMask, 0);
2160 goto out;
2161 }
2162
2163 /* Acknowledge all of the current interrupt sources ASAP, but
2164 an first get an additional status bit from CSCR. */
2165 if (unlikely(status & RxUnderrun))
2166 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2167
2168 ackstat = status & ~(RxAckBits | TxErr);
2169 if (ackstat)
2170 RTL_W16 (IntrStatus, ackstat);
2171
2172 /* Receive packets are processed by poll routine.
2173 If not running start it now. */
2174 if (status & RxAckBits){
2175 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2176 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2177 __netif_rx_schedule(dev, &tp->napi);
2178 }
2179 }
2180
2181 /* Check uncommon events with one test. */
2182 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2183 rtl8139_weird_interrupt (dev, tp, ioaddr,
2184 status, link_changed);
2185
2186 if (status & (TxOK | TxErr)) {
2187 rtl8139_tx_interrupt (dev, tp, ioaddr);
2188 if (status & TxErr)
2189 RTL_W16 (IntrStatus, TxErr);
2190 }
2191 out:
2192 spin_unlock (&tp->lock);
2193
2194 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2195 dev->name, RTL_R16 (IntrStatus));
2196 return IRQ_RETVAL(handled);
2197 }
2198
2199 #ifdef CONFIG_NET_POLL_CONTROLLER
2200 /*
2201 * Polling receive - used by netconsole and other diagnostic tools
2202 * to allow network i/o with interrupts disabled.
2203 */
2204 static void rtl8139_poll_controller(struct net_device *dev)
2205 {
2206 disable_irq(dev->irq);
2207 rtl8139_interrupt(dev->irq, dev);
2208 enable_irq(dev->irq);
2209 }
2210 #endif
2211
2212 static int rtl8139_close (struct net_device *dev)
2213 {
2214 struct rtl8139_private *tp = netdev_priv(dev);
2215 void __iomem *ioaddr = tp->mmio_addr;
2216 unsigned long flags;
2217
2218 netif_stop_queue(dev);
2219 napi_disable(&tp->napi);
2220
2221 if (netif_msg_ifdown(tp))
2222 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2223 dev->name, RTL_R16 (IntrStatus));
2224
2225 spin_lock_irqsave (&tp->lock, flags);
2226
2227 /* Stop the chip's Tx and Rx DMA processes. */
2228 RTL_W8 (ChipCmd, 0);
2229
2230 /* Disable interrupts by clearing the interrupt mask. */
2231 RTL_W16 (IntrMask, 0);
2232
2233 /* Update the error counts. */
2234 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2235 RTL_W32 (RxMissed, 0);
2236
2237 spin_unlock_irqrestore (&tp->lock, flags);
2238
2239 free_irq (dev->irq, dev);
2240
2241 rtl8139_tx_clear (tp);
2242
2243 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2244 tp->rx_ring, tp->rx_ring_dma);
2245 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2246 tp->tx_bufs, tp->tx_bufs_dma);
2247 tp->rx_ring = NULL;
2248 tp->tx_bufs = NULL;
2249
2250 /* Green! Put the chip in low-power mode. */
2251 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2252
2253 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2254 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2255
2256 return 0;
2257 }
2258
2259
2260 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2261 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2262 other threads or interrupts aren't messing with the 8139. */
2263 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2264 {
2265 struct rtl8139_private *np = netdev_priv(dev);
2266 void __iomem *ioaddr = np->mmio_addr;
2267
2268 spin_lock_irq(&np->lock);
2269 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2270 u8 cfg3 = RTL_R8 (Config3);
2271 u8 cfg5 = RTL_R8 (Config5);
2272
2273 wol->supported = WAKE_PHY | WAKE_MAGIC
2274 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2275
2276 wol->wolopts = 0;
2277 if (cfg3 & Cfg3_LinkUp)
2278 wol->wolopts |= WAKE_PHY;
2279 if (cfg3 & Cfg3_Magic)
2280 wol->wolopts |= WAKE_MAGIC;
2281 /* (KON)FIXME: See how netdev_set_wol() handles the
2282 following constants. */
2283 if (cfg5 & Cfg5_UWF)
2284 wol->wolopts |= WAKE_UCAST;
2285 if (cfg5 & Cfg5_MWF)
2286 wol->wolopts |= WAKE_MCAST;
2287 if (cfg5 & Cfg5_BWF)
2288 wol->wolopts |= WAKE_BCAST;
2289 }
2290 spin_unlock_irq(&np->lock);
2291 }
2292
2293
2294 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2295 that wol points to kernel memory and other threads or interrupts
2296 aren't messing with the 8139. */
2297 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2298 {
2299 struct rtl8139_private *np = netdev_priv(dev);
2300 void __iomem *ioaddr = np->mmio_addr;
2301 u32 support;
2302 u8 cfg3, cfg5;
2303
2304 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2305 ? (WAKE_PHY | WAKE_MAGIC
2306 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2307 : 0);
2308 if (wol->wolopts & ~support)
2309 return -EINVAL;
2310
2311 spin_lock_irq(&np->lock);
2312 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2313 if (wol->wolopts & WAKE_PHY)
2314 cfg3 |= Cfg3_LinkUp;
2315 if (wol->wolopts & WAKE_MAGIC)
2316 cfg3 |= Cfg3_Magic;
2317 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2318 RTL_W8 (Config3, cfg3);
2319 RTL_W8 (Cfg9346, Cfg9346_Lock);
2320
2321 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2322 /* (KON)FIXME: These are untested. We may have to set the
2323 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2324 documentation. */
2325 if (wol->wolopts & WAKE_UCAST)
2326 cfg5 |= Cfg5_UWF;
2327 if (wol->wolopts & WAKE_MCAST)
2328 cfg5 |= Cfg5_MWF;
2329 if (wol->wolopts & WAKE_BCAST)
2330 cfg5 |= Cfg5_BWF;
2331 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2332 spin_unlock_irq(&np->lock);
2333
2334 return 0;
2335 }
2336
2337 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2338 {
2339 struct rtl8139_private *np = netdev_priv(dev);
2340 strcpy(info->driver, DRV_NAME);
2341 strcpy(info->version, DRV_VERSION);
2342 strcpy(info->bus_info, pci_name(np->pci_dev));
2343 info->regdump_len = np->regs_len;
2344 }
2345
2346 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2347 {
2348 struct rtl8139_private *np = netdev_priv(dev);
2349 spin_lock_irq(&np->lock);
2350 mii_ethtool_gset(&np->mii, cmd);
2351 spin_unlock_irq(&np->lock);
2352 return 0;
2353 }
2354
2355 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2356 {
2357 struct rtl8139_private *np = netdev_priv(dev);
2358 int rc;
2359 spin_lock_irq(&np->lock);
2360 rc = mii_ethtool_sset(&np->mii, cmd);
2361 spin_unlock_irq(&np->lock);
2362 return rc;
2363 }
2364
2365 static int rtl8139_nway_reset(struct net_device *dev)
2366 {
2367 struct rtl8139_private *np = netdev_priv(dev);
2368 return mii_nway_restart(&np->mii);
2369 }
2370
2371 static u32 rtl8139_get_link(struct net_device *dev)
2372 {
2373 struct rtl8139_private *np = netdev_priv(dev);
2374 return mii_link_ok(&np->mii);
2375 }
2376
2377 static u32 rtl8139_get_msglevel(struct net_device *dev)
2378 {
2379 struct rtl8139_private *np = netdev_priv(dev);
2380 return np->msg_enable;
2381 }
2382
2383 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2384 {
2385 struct rtl8139_private *np = netdev_priv(dev);
2386 np->msg_enable = datum;
2387 }
2388
2389 static int rtl8139_get_regs_len(struct net_device *dev)
2390 {
2391 struct rtl8139_private *np;
2392 /* TODO: we are too slack to do reg dumping for pio, for now */
2393 if (use_io)
2394 return 0;
2395 np = netdev_priv(dev);
2396 return np->regs_len;
2397 }
2398
2399 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2400 {
2401 struct rtl8139_private *np;
2402
2403 /* TODO: we are too slack to do reg dumping for pio, for now */
2404 if (use_io)
2405 return;
2406 np = netdev_priv(dev);
2407
2408 regs->version = RTL_REGS_VER;
2409
2410 spin_lock_irq(&np->lock);
2411 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2412 spin_unlock_irq(&np->lock);
2413 }
2414
2415 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2416 {
2417 switch (sset) {
2418 case ETH_SS_STATS:
2419 return RTL_NUM_STATS;
2420 default:
2421 return -EOPNOTSUPP;
2422 }
2423 }
2424
2425 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2426 {
2427 struct rtl8139_private *np = netdev_priv(dev);
2428
2429 data[0] = np->xstats.early_rx;
2430 data[1] = np->xstats.tx_buf_mapped;
2431 data[2] = np->xstats.tx_timeouts;
2432 data[3] = np->xstats.rx_lost_in_ring;
2433 }
2434
2435 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2436 {
2437 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2438 }
2439
2440 static const struct ethtool_ops rtl8139_ethtool_ops = {
2441 .get_drvinfo = rtl8139_get_drvinfo,
2442 .get_settings = rtl8139_get_settings,
2443 .set_settings = rtl8139_set_settings,
2444 .get_regs_len = rtl8139_get_regs_len,
2445 .get_regs = rtl8139_get_regs,
2446 .nway_reset = rtl8139_nway_reset,
2447 .get_link = rtl8139_get_link,
2448 .get_msglevel = rtl8139_get_msglevel,
2449 .set_msglevel = rtl8139_set_msglevel,
2450 .get_wol = rtl8139_get_wol,
2451 .set_wol = rtl8139_set_wol,
2452 .get_strings = rtl8139_get_strings,
2453 .get_sset_count = rtl8139_get_sset_count,
2454 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2455 };
2456
2457 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2458 {
2459 struct rtl8139_private *np = netdev_priv(dev);
2460 int rc;
2461
2462 if (!netif_running(dev))
2463 return -EINVAL;
2464
2465 spin_lock_irq(&np->lock);
2466 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2467 spin_unlock_irq(&np->lock);
2468
2469 return rc;
2470 }
2471
2472
2473 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2474 {
2475 struct rtl8139_private *tp = netdev_priv(dev);
2476 void __iomem *ioaddr = tp->mmio_addr;
2477 unsigned long flags;
2478
2479 if (netif_running(dev)) {
2480 spin_lock_irqsave (&tp->lock, flags);
2481 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2482 RTL_W32 (RxMissed, 0);
2483 spin_unlock_irqrestore (&tp->lock, flags);
2484 }
2485
2486 return &dev->stats;
2487 }
2488
2489 /* Set or clear the multicast filter for this adaptor.
2490 This routine is not state sensitive and need not be SMP locked. */
2491
2492 static void __set_rx_mode (struct net_device *dev)
2493 {
2494 struct rtl8139_private *tp = netdev_priv(dev);
2495 void __iomem *ioaddr = tp->mmio_addr;
2496 u32 mc_filter[2]; /* Multicast hash filter */
2497 int i, rx_mode;
2498 u32 tmp;
2499
2500 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2501 dev->name, dev->flags, RTL_R32 (RxConfig));
2502
2503 /* Note: do not reorder, GCC is clever about common statements. */
2504 if (dev->flags & IFF_PROMISC) {
2505 rx_mode =
2506 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2507 AcceptAllPhys;
2508 mc_filter[1] = mc_filter[0] = 0xffffffff;
2509 } else if ((dev->mc_count > multicast_filter_limit)
2510 || (dev->flags & IFF_ALLMULTI)) {
2511 /* Too many to filter perfectly -- accept all multicasts. */
2512 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2513 mc_filter[1] = mc_filter[0] = 0xffffffff;
2514 } else {
2515 struct dev_mc_list *mclist;
2516 rx_mode = AcceptBroadcast | AcceptMyPhys;
2517 mc_filter[1] = mc_filter[0] = 0;
2518 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2519 i++, mclist = mclist->next) {
2520 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2521
2522 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2523 rx_mode |= AcceptMulticast;
2524 }
2525 }
2526
2527 /* We can safely update without stopping the chip. */
2528 tmp = rtl8139_rx_config | rx_mode;
2529 if (tp->rx_config != tmp) {
2530 RTL_W32_F (RxConfig, tmp);
2531 tp->rx_config = tmp;
2532 }
2533 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2534 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2535 }
2536
2537 static void rtl8139_set_rx_mode (struct net_device *dev)
2538 {
2539 unsigned long flags;
2540 struct rtl8139_private *tp = netdev_priv(dev);
2541
2542 spin_lock_irqsave (&tp->lock, flags);
2543 __set_rx_mode(dev);
2544 spin_unlock_irqrestore (&tp->lock, flags);
2545 }
2546
2547 #ifdef CONFIG_PM
2548
2549 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2550 {
2551 struct net_device *dev = pci_get_drvdata (pdev);
2552 struct rtl8139_private *tp = netdev_priv(dev);
2553 void __iomem *ioaddr = tp->mmio_addr;
2554 unsigned long flags;
2555
2556 pci_save_state (pdev);
2557
2558 if (!netif_running (dev))
2559 return 0;
2560
2561 netif_device_detach (dev);
2562
2563 spin_lock_irqsave (&tp->lock, flags);
2564
2565 /* Disable interrupts, stop Tx and Rx. */
2566 RTL_W16 (IntrMask, 0);
2567 RTL_W8 (ChipCmd, 0);
2568
2569 /* Update the error counts. */
2570 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2571 RTL_W32 (RxMissed, 0);
2572
2573 spin_unlock_irqrestore (&tp->lock, flags);
2574
2575 pci_set_power_state (pdev, PCI_D3hot);
2576
2577 return 0;
2578 }
2579
2580
2581 static int rtl8139_resume (struct pci_dev *pdev)
2582 {
2583 struct net_device *dev = pci_get_drvdata (pdev);
2584
2585 pci_restore_state (pdev);
2586 if (!netif_running (dev))
2587 return 0;
2588 pci_set_power_state (pdev, PCI_D0);
2589 rtl8139_init_ring (dev);
2590 rtl8139_hw_start (dev);
2591 netif_device_attach (dev);
2592 return 0;
2593 }
2594
2595 #endif /* CONFIG_PM */
2596
2597
2598 static struct pci_driver rtl8139_pci_driver = {
2599 .name = DRV_NAME,
2600 .id_table = rtl8139_pci_tbl,
2601 .probe = rtl8139_init_one,
2602 .remove = __devexit_p(rtl8139_remove_one),
2603 #ifdef CONFIG_PM
2604 .suspend = rtl8139_suspend,
2605 .resume = rtl8139_resume,
2606 #endif /* CONFIG_PM */
2607 };
2608
2609
2610 static int __init rtl8139_init_module (void)
2611 {
2612 /* when we're a module, we always print a version message,
2613 * even if no 8139 board is found.
2614 */
2615 #ifdef MODULE
2616 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2617 #endif
2618
2619 return pci_register_driver(&rtl8139_pci_driver);
2620 }
2621
2622
2623 static void __exit rtl8139_cleanup_module (void)
2624 {
2625 pci_unregister_driver (&rtl8139_pci_driver);
2626 }
2627
2628
2629 module_init(rtl8139_init_module);
2630 module_exit(rtl8139_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree