2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
28 #include <plat/mcbsp.h>
30 struct omap_mcbsp
**mcbsp_ptr
;
33 void omap_mcbsp_write(void __iomem
*io_base
, u16 reg
, u32 val
)
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16
)val
, io_base
+ reg
);
38 __raw_writel(val
, io_base
+ reg
);
41 int omap_mcbsp_read(void __iomem
*io_base
, u16 reg
)
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base
+ reg
);
46 return __raw_readl(io_base
+ reg
);
49 #define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51 #define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
54 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
57 static void omap_mcbsp_dump_reg(u8 id
)
59 struct omap_mcbsp
*mcbsp
= id_to_mcbsp_ptr(id
);
61 dev_dbg(mcbsp
->dev
, "**** McBSP%d regs ****\n", mcbsp
->id
);
62 dev_dbg(mcbsp
->dev
, "DRR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp
->io_base
, DRR2
));
64 dev_dbg(mcbsp
->dev
, "DRR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp
->io_base
, DRR1
));
66 dev_dbg(mcbsp
->dev
, "DXR2: 0x%04x\n",
67 OMAP_MCBSP_READ(mcbsp
->io_base
, DXR2
));
68 dev_dbg(mcbsp
->dev
, "DXR1: 0x%04x\n",
69 OMAP_MCBSP_READ(mcbsp
->io_base
, DXR1
));
70 dev_dbg(mcbsp
->dev
, "SPCR2: 0x%04x\n",
71 OMAP_MCBSP_READ(mcbsp
->io_base
, SPCR2
));
72 dev_dbg(mcbsp
->dev
, "SPCR1: 0x%04x\n",
73 OMAP_MCBSP_READ(mcbsp
->io_base
, SPCR1
));
74 dev_dbg(mcbsp
->dev
, "RCR2: 0x%04x\n",
75 OMAP_MCBSP_READ(mcbsp
->io_base
, RCR2
));
76 dev_dbg(mcbsp
->dev
, "RCR1: 0x%04x\n",
77 OMAP_MCBSP_READ(mcbsp
->io_base
, RCR1
));
78 dev_dbg(mcbsp
->dev
, "XCR2: 0x%04x\n",
79 OMAP_MCBSP_READ(mcbsp
->io_base
, XCR2
));
80 dev_dbg(mcbsp
->dev
, "XCR1: 0x%04x\n",
81 OMAP_MCBSP_READ(mcbsp
->io_base
, XCR1
));
82 dev_dbg(mcbsp
->dev
, "SRGR2: 0x%04x\n",
83 OMAP_MCBSP_READ(mcbsp
->io_base
, SRGR2
));
84 dev_dbg(mcbsp
->dev
, "SRGR1: 0x%04x\n",
85 OMAP_MCBSP_READ(mcbsp
->io_base
, SRGR1
));
86 dev_dbg(mcbsp
->dev
, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp
->io_base
, PCR0
));
88 dev_dbg(mcbsp
->dev
, "***********************\n");
91 static irqreturn_t
omap_mcbsp_tx_irq_handler(int irq
, void *dev_id
)
93 struct omap_mcbsp
*mcbsp_tx
= dev_id
;
96 irqst_spcr2
= OMAP_MCBSP_READ(mcbsp_tx
->io_base
, SPCR2
);
97 dev_dbg(mcbsp_tx
->dev
, "TX IRQ callback : 0x%x\n", irqst_spcr2
);
99 if (irqst_spcr2
& XSYNC_ERR
) {
100 dev_err(mcbsp_tx
->dev
, "TX Frame Sync Error! : 0x%x\n",
102 /* Writing zero to XSYNC_ERR clears the IRQ */
103 OMAP_MCBSP_WRITE(mcbsp_tx
->io_base
, SPCR2
,
104 irqst_spcr2
& ~(XSYNC_ERR
));
106 complete(&mcbsp_tx
->tx_irq_completion
);
112 static irqreturn_t
omap_mcbsp_rx_irq_handler(int irq
, void *dev_id
)
114 struct omap_mcbsp
*mcbsp_rx
= dev_id
;
117 irqst_spcr1
= OMAP_MCBSP_READ(mcbsp_rx
->io_base
, SPCR1
);
118 dev_dbg(mcbsp_rx
->dev
, "RX IRQ callback : 0x%x\n", irqst_spcr1
);
120 if (irqst_spcr1
& RSYNC_ERR
) {
121 dev_err(mcbsp_rx
->dev
, "RX Frame Sync Error! : 0x%x\n",
123 /* Writing zero to RSYNC_ERR clears the IRQ */
124 OMAP_MCBSP_WRITE(mcbsp_rx
->io_base
, SPCR1
,
125 irqst_spcr1
& ~(RSYNC_ERR
));
127 complete(&mcbsp_rx
->tx_irq_completion
);
133 static void omap_mcbsp_tx_dma_callback(int lch
, u16 ch_status
, void *data
)
135 struct omap_mcbsp
*mcbsp_dma_tx
= data
;
137 dev_dbg(mcbsp_dma_tx
->dev
, "TX DMA callback : 0x%x\n",
138 OMAP_MCBSP_READ(mcbsp_dma_tx
->io_base
, SPCR2
));
140 /* We can free the channels */
141 omap_free_dma(mcbsp_dma_tx
->dma_tx_lch
);
142 mcbsp_dma_tx
->dma_tx_lch
= -1;
144 complete(&mcbsp_dma_tx
->tx_dma_completion
);
147 static void omap_mcbsp_rx_dma_callback(int lch
, u16 ch_status
, void *data
)
149 struct omap_mcbsp
*mcbsp_dma_rx
= data
;
151 dev_dbg(mcbsp_dma_rx
->dev
, "RX DMA callback : 0x%x\n",
152 OMAP_MCBSP_READ(mcbsp_dma_rx
->io_base
, SPCR2
));
154 /* We can free the channels */
155 omap_free_dma(mcbsp_dma_rx
->dma_rx_lch
);
156 mcbsp_dma_rx
->dma_rx_lch
= -1;
158 complete(&mcbsp_dma_rx
->rx_dma_completion
);
162 * omap_mcbsp_config simply write a config to the
164 * You either call this function or set the McBSP registers
165 * by yourself before calling omap_mcbsp_start().
167 void omap_mcbsp_config(unsigned int id
, const struct omap_mcbsp_reg_cfg
*config
)
169 struct omap_mcbsp
*mcbsp
;
170 void __iomem
*io_base
;
172 if (!omap_mcbsp_check_valid_id(id
)) {
173 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
176 mcbsp
= id_to_mcbsp_ptr(id
);
178 io_base
= mcbsp
->io_base
;
179 dev_dbg(mcbsp
->dev
, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp
->id
, mcbsp
->phys_base
);
182 /* We write the given config */
183 OMAP_MCBSP_WRITE(io_base
, SPCR2
, config
->spcr2
);
184 OMAP_MCBSP_WRITE(io_base
, SPCR1
, config
->spcr1
);
185 OMAP_MCBSP_WRITE(io_base
, RCR2
, config
->rcr2
);
186 OMAP_MCBSP_WRITE(io_base
, RCR1
, config
->rcr1
);
187 OMAP_MCBSP_WRITE(io_base
, XCR2
, config
->xcr2
);
188 OMAP_MCBSP_WRITE(io_base
, XCR1
, config
->xcr1
);
189 OMAP_MCBSP_WRITE(io_base
, SRGR2
, config
->srgr2
);
190 OMAP_MCBSP_WRITE(io_base
, SRGR1
, config
->srgr1
);
191 OMAP_MCBSP_WRITE(io_base
, MCR2
, config
->mcr2
);
192 OMAP_MCBSP_WRITE(io_base
, MCR1
, config
->mcr1
);
193 OMAP_MCBSP_WRITE(io_base
, PCR0
, config
->pcr0
);
194 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
195 OMAP_MCBSP_WRITE(io_base
, XCCR
, config
->xccr
);
196 OMAP_MCBSP_WRITE(io_base
, RCCR
, config
->rccr
);
199 EXPORT_SYMBOL(omap_mcbsp_config
);
201 #ifdef CONFIG_ARCH_OMAP3
203 * omap_mcbsp_set_tx_threshold configures how to deal
204 * with transmit threshold. the threshold value and handler can be
207 void omap_mcbsp_set_tx_threshold(unsigned int id
, u16 threshold
)
209 struct omap_mcbsp
*mcbsp
;
210 void __iomem
*io_base
;
212 if (!cpu_is_omap34xx())
215 if (!omap_mcbsp_check_valid_id(id
)) {
216 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
219 mcbsp
= id_to_mcbsp_ptr(id
);
220 io_base
= mcbsp
->io_base
;
222 OMAP_MCBSP_WRITE(io_base
, THRSH2
, threshold
);
224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold
);
227 * omap_mcbsp_set_rx_threshold configures how to deal
228 * with receive threshold. the threshold value and handler can be
231 void omap_mcbsp_set_rx_threshold(unsigned int id
, u16 threshold
)
233 struct omap_mcbsp
*mcbsp
;
234 void __iomem
*io_base
;
236 if (!cpu_is_omap34xx())
239 if (!omap_mcbsp_check_valid_id(id
)) {
240 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
243 mcbsp
= id_to_mcbsp_ptr(id
);
244 io_base
= mcbsp
->io_base
;
246 OMAP_MCBSP_WRITE(io_base
, THRSH1
, threshold
);
248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold
);
251 * omap_mcbsp_get_max_tx_thres just return the current configured
252 * maximum threshold for transmission
254 u16
omap_mcbsp_get_max_tx_threshold(unsigned int id
)
256 struct omap_mcbsp
*mcbsp
;
258 if (!omap_mcbsp_check_valid_id(id
)) {
259 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
262 mcbsp
= id_to_mcbsp_ptr(id
);
264 return mcbsp
->max_tx_thres
;
266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold
);
269 * omap_mcbsp_get_max_rx_thres just return the current configured
270 * maximum threshold for reception
272 u16
omap_mcbsp_get_max_rx_threshold(unsigned int id
)
274 struct omap_mcbsp
*mcbsp
;
276 if (!omap_mcbsp_check_valid_id(id
)) {
277 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
280 mcbsp
= id_to_mcbsp_ptr(id
);
282 return mcbsp
->max_rx_thres
;
284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold
);
287 * omap_mcbsp_get_dma_op_mode just return the current configured
288 * operating mode for the mcbsp channel
290 int omap_mcbsp_get_dma_op_mode(unsigned int id
)
292 struct omap_mcbsp
*mcbsp
;
295 if (!omap_mcbsp_check_valid_id(id
)) {
296 printk(KERN_ERR
"%s: Invalid id (%u)\n", __func__
, id
+ 1);
299 mcbsp
= id_to_mcbsp_ptr(id
);
301 dma_op_mode
= mcbsp
->dma_op_mode
;
305 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode
);
307 static inline void omap34xx_mcbsp_request(struct omap_mcbsp
*mcbsp
)
310 * Enable wakup behavior, smart idle and all wakeups
311 * REVISIT: some wakeups may be unnecessary
313 if (cpu_is_omap34xx()) {
316 syscon
= OMAP_MCBSP_READ(mcbsp
->io_base
, SYSCON
);
317 syscon
&= ~(ENAWAKEUP
| SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
319 if (mcbsp
->dma_op_mode
== MCBSP_DMA_MODE_THRESHOLD
) {
320 syscon
|= (ENAWAKEUP
| SIDLEMODE(0x02) |
321 CLOCKACTIVITY(0x02));
322 OMAP_MCBSP_WRITE(mcbsp
->io_base
, WAKEUPEN
,
325 syscon
|= SIDLEMODE(0x01);
328 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SYSCON
, syscon
);
332 static inline void omap34xx_mcbsp_free(struct omap_mcbsp
*mcbsp
)
335 * Disable wakup behavior, smart idle and all wakeups
337 if (cpu_is_omap34xx()) {
340 syscon
= OMAP_MCBSP_READ(mcbsp
->io_base
, SYSCON
);
341 syscon
&= ~(ENAWAKEUP
| SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
343 * HW bug workaround - If no_idle mode is taken, we need to
344 * go to smart_idle before going to always_idle, or the
345 * device will not hit retention anymore.
347 syscon
|= SIDLEMODE(0x02);
348 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SYSCON
, syscon
);
350 syscon
&= ~(SIDLEMODE(0x03));
351 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SYSCON
, syscon
);
353 OMAP_MCBSP_WRITE(mcbsp
->io_base
, WAKEUPEN
, 0);
357 static inline void omap34xx_mcbsp_request(struct omap_mcbsp
*mcbsp
) {}
358 static inline void omap34xx_mcbsp_free(struct omap_mcbsp
*mcbsp
) {}
362 * We can choose between IRQ based or polled IO.
363 * This needs to be called before omap_mcbsp_request().
365 int omap_mcbsp_set_io_type(unsigned int id
, omap_mcbsp_io_type_t io_type
)
367 struct omap_mcbsp
*mcbsp
;
369 if (!omap_mcbsp_check_valid_id(id
)) {
370 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
373 mcbsp
= id_to_mcbsp_ptr(id
);
375 spin_lock(&mcbsp
->lock
);
378 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
380 spin_unlock(&mcbsp
->lock
);
384 mcbsp
->io_type
= io_type
;
386 spin_unlock(&mcbsp
->lock
);
390 EXPORT_SYMBOL(omap_mcbsp_set_io_type
);
392 int omap_mcbsp_request(unsigned int id
)
394 struct omap_mcbsp
*mcbsp
;
397 if (!omap_mcbsp_check_valid_id(id
)) {
398 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
401 mcbsp
= id_to_mcbsp_ptr(id
);
403 spin_lock(&mcbsp
->lock
);
405 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
407 spin_unlock(&mcbsp
->lock
);
412 spin_unlock(&mcbsp
->lock
);
414 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->request
)
415 mcbsp
->pdata
->ops
->request(id
);
417 clk_enable(mcbsp
->iclk
);
418 clk_enable(mcbsp
->fclk
);
420 /* Do procedure specific to omap34xx arch, if applicable */
421 omap34xx_mcbsp_request(mcbsp
);
424 * Make sure that transmitter, receiver and sample-rate generator are
425 * not running before activating IRQs.
427 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SPCR1
, 0);
428 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SPCR2
, 0);
430 if (mcbsp
->io_type
== OMAP_MCBSP_IRQ_IO
) {
431 /* We need to get IRQs here */
432 init_completion(&mcbsp
->tx_irq_completion
);
433 err
= request_irq(mcbsp
->tx_irq
, omap_mcbsp_tx_irq_handler
,
434 0, "McBSP", (void *)mcbsp
);
436 dev_err(mcbsp
->dev
, "Unable to request TX IRQ %d "
437 "for McBSP%d\n", mcbsp
->tx_irq
,
442 init_completion(&mcbsp
->rx_irq_completion
);
443 err
= request_irq(mcbsp
->rx_irq
, omap_mcbsp_rx_irq_handler
,
444 0, "McBSP", (void *)mcbsp
);
446 dev_err(mcbsp
->dev
, "Unable to request RX IRQ %d "
447 "for McBSP%d\n", mcbsp
->rx_irq
,
455 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
457 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->free
)
458 mcbsp
->pdata
->ops
->free(id
);
460 /* Do procedure specific to omap34xx arch, if applicable */
461 omap34xx_mcbsp_free(mcbsp
);
463 clk_disable(mcbsp
->fclk
);
464 clk_disable(mcbsp
->iclk
);
470 EXPORT_SYMBOL(omap_mcbsp_request
);
472 void omap_mcbsp_free(unsigned int id
)
474 struct omap_mcbsp
*mcbsp
;
476 if (!omap_mcbsp_check_valid_id(id
)) {
477 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
480 mcbsp
= id_to_mcbsp_ptr(id
);
482 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->free
)
483 mcbsp
->pdata
->ops
->free(id
);
485 /* Do procedure specific to omap34xx arch, if applicable */
486 omap34xx_mcbsp_free(mcbsp
);
488 clk_disable(mcbsp
->fclk
);
489 clk_disable(mcbsp
->iclk
);
491 if (mcbsp
->io_type
== OMAP_MCBSP_IRQ_IO
) {
493 free_irq(mcbsp
->rx_irq
, (void *)mcbsp
);
494 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
497 spin_lock(&mcbsp
->lock
);
499 dev_err(mcbsp
->dev
, "McBSP%d was not reserved\n",
501 spin_unlock(&mcbsp
->lock
);
506 spin_unlock(&mcbsp
->lock
);
508 EXPORT_SYMBOL(omap_mcbsp_free
);
511 * Here we start the McBSP, by enabling transmitter, receiver or both.
512 * If no transmitter or receiver is active prior calling, then sample-rate
513 * generator and frame sync are started.
515 void omap_mcbsp_start(unsigned int id
, int tx
, int rx
)
517 struct omap_mcbsp
*mcbsp
;
518 void __iomem
*io_base
;
522 if (!omap_mcbsp_check_valid_id(id
)) {
523 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
526 mcbsp
= id_to_mcbsp_ptr(id
);
527 io_base
= mcbsp
->io_base
;
529 mcbsp
->rx_word_length
= (OMAP_MCBSP_READ(io_base
, RCR1
) >> 5) & 0x7;
530 mcbsp
->tx_word_length
= (OMAP_MCBSP_READ(io_base
, XCR1
) >> 5) & 0x7;
532 idle
= !((OMAP_MCBSP_READ(io_base
, SPCR2
) |
533 OMAP_MCBSP_READ(io_base
, SPCR1
)) & 1);
536 /* Start the sample generator */
537 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
538 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| (1 << 6));
541 /* Enable transmitter and receiver */
543 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
544 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| tx
);
547 w
= OMAP_MCBSP_READ(io_base
, SPCR1
);
548 OMAP_MCBSP_WRITE(io_base
, SPCR1
, w
| rx
);
551 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
552 * REVISIT: 100us may give enough time for two CLKSRG, however
553 * due to some unknown PM related, clock gating etc. reason it
559 /* Start frame sync */
560 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
561 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| (1 << 7));
564 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
565 /* Release the transmitter and receiver */
566 w
= OMAP_MCBSP_READ(io_base
, XCCR
);
567 w
&= ~(tx
? XDISABLE
: 0);
568 OMAP_MCBSP_WRITE(io_base
, XCCR
, w
);
569 w
= OMAP_MCBSP_READ(io_base
, RCCR
);
570 w
&= ~(rx
? RDISABLE
: 0);
571 OMAP_MCBSP_WRITE(io_base
, RCCR
, w
);
574 /* Dump McBSP Regs */
575 omap_mcbsp_dump_reg(id
);
577 EXPORT_SYMBOL(omap_mcbsp_start
);
579 void omap_mcbsp_stop(unsigned int id
, int tx
, int rx
)
581 struct omap_mcbsp
*mcbsp
;
582 void __iomem
*io_base
;
586 if (!omap_mcbsp_check_valid_id(id
)) {
587 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
591 mcbsp
= id_to_mcbsp_ptr(id
);
592 io_base
= mcbsp
->io_base
;
594 /* Reset transmitter */
596 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
597 w
= OMAP_MCBSP_READ(io_base
, XCCR
);
598 w
|= (tx
? XDISABLE
: 0);
599 OMAP_MCBSP_WRITE(io_base
, XCCR
, w
);
601 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
602 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
& ~tx
);
606 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
607 w
= OMAP_MCBSP_READ(io_base
, RCCR
);
608 w
|= (rx
? RDISABLE
: 0);
609 OMAP_MCBSP_WRITE(io_base
, RCCR
, w
);
611 w
= OMAP_MCBSP_READ(io_base
, SPCR1
);
612 OMAP_MCBSP_WRITE(io_base
, SPCR1
, w
& ~rx
);
614 idle
= !((OMAP_MCBSP_READ(io_base
, SPCR2
) |
615 OMAP_MCBSP_READ(io_base
, SPCR1
)) & 1);
618 /* Reset the sample rate generator */
619 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
620 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
& ~(1 << 6));
623 EXPORT_SYMBOL(omap_mcbsp_stop
);
625 /* polled mcbsp i/o operations */
626 int omap_mcbsp_pollwrite(unsigned int id
, u16 buf
)
628 struct omap_mcbsp
*mcbsp
;
631 if (!omap_mcbsp_check_valid_id(id
)) {
632 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
636 mcbsp
= id_to_mcbsp_ptr(id
);
637 base
= mcbsp
->io_base
;
639 OMAP_MCBSP_WRITE(base
, DXR1
, buf
);
640 /* if frame sync error - clear the error */
641 if (OMAP_MCBSP_READ(base
, SPCR2
) & XSYNC_ERR
) {
643 OMAP_MCBSP_WRITE(base
, SPCR2
,
644 OMAP_MCBSP_READ(base
, SPCR2
) & (~XSYNC_ERR
));
648 /* wait for transmit confirmation */
650 while (!(OMAP_MCBSP_READ(base
, SPCR2
) & XRDY
)) {
651 if (attemps
++ > 1000) {
652 OMAP_MCBSP_WRITE(base
, SPCR2
,
653 OMAP_MCBSP_READ(base
, SPCR2
) &
656 OMAP_MCBSP_WRITE(base
, SPCR2
,
657 OMAP_MCBSP_READ(base
, SPCR2
) |
660 dev_err(mcbsp
->dev
, "Could not write to"
661 " McBSP%d Register\n", mcbsp
->id
);
669 EXPORT_SYMBOL(omap_mcbsp_pollwrite
);
671 int omap_mcbsp_pollread(unsigned int id
, u16
*buf
)
673 struct omap_mcbsp
*mcbsp
;
676 if (!omap_mcbsp_check_valid_id(id
)) {
677 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
680 mcbsp
= id_to_mcbsp_ptr(id
);
682 base
= mcbsp
->io_base
;
683 /* if frame sync error - clear the error */
684 if (OMAP_MCBSP_READ(base
, SPCR1
) & RSYNC_ERR
) {
686 OMAP_MCBSP_WRITE(base
, SPCR1
,
687 OMAP_MCBSP_READ(base
, SPCR1
) & (~RSYNC_ERR
));
691 /* wait for recieve confirmation */
693 while (!(OMAP_MCBSP_READ(base
, SPCR1
) & RRDY
)) {
694 if (attemps
++ > 1000) {
695 OMAP_MCBSP_WRITE(base
, SPCR1
,
696 OMAP_MCBSP_READ(base
, SPCR1
) &
699 OMAP_MCBSP_WRITE(base
, SPCR1
,
700 OMAP_MCBSP_READ(base
, SPCR1
) |
703 dev_err(mcbsp
->dev
, "Could not read from"
704 " McBSP%d Register\n", mcbsp
->id
);
709 *buf
= OMAP_MCBSP_READ(base
, DRR1
);
713 EXPORT_SYMBOL(omap_mcbsp_pollread
);
716 * IRQ based word transmission.
718 void omap_mcbsp_xmit_word(unsigned int id
, u32 word
)
720 struct omap_mcbsp
*mcbsp
;
721 void __iomem
*io_base
;
722 omap_mcbsp_word_length word_length
;
724 if (!omap_mcbsp_check_valid_id(id
)) {
725 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
729 mcbsp
= id_to_mcbsp_ptr(id
);
730 io_base
= mcbsp
->io_base
;
731 word_length
= mcbsp
->tx_word_length
;
733 wait_for_completion(&mcbsp
->tx_irq_completion
);
735 if (word_length
> OMAP_MCBSP_WORD_16
)
736 OMAP_MCBSP_WRITE(io_base
, DXR2
, word
>> 16);
737 OMAP_MCBSP_WRITE(io_base
, DXR1
, word
& 0xffff);
739 EXPORT_SYMBOL(omap_mcbsp_xmit_word
);
741 u32
omap_mcbsp_recv_word(unsigned int id
)
743 struct omap_mcbsp
*mcbsp
;
744 void __iomem
*io_base
;
745 u16 word_lsb
, word_msb
= 0;
746 omap_mcbsp_word_length word_length
;
748 if (!omap_mcbsp_check_valid_id(id
)) {
749 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
752 mcbsp
= id_to_mcbsp_ptr(id
);
754 word_length
= mcbsp
->rx_word_length
;
755 io_base
= mcbsp
->io_base
;
757 wait_for_completion(&mcbsp
->rx_irq_completion
);
759 if (word_length
> OMAP_MCBSP_WORD_16
)
760 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
761 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
763 return (word_lsb
| (word_msb
<< 16));
765 EXPORT_SYMBOL(omap_mcbsp_recv_word
);
767 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id
, u32 word
)
769 struct omap_mcbsp
*mcbsp
;
770 void __iomem
*io_base
;
771 omap_mcbsp_word_length tx_word_length
;
772 omap_mcbsp_word_length rx_word_length
;
773 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
775 if (!omap_mcbsp_check_valid_id(id
)) {
776 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
779 mcbsp
= id_to_mcbsp_ptr(id
);
780 io_base
= mcbsp
->io_base
;
781 tx_word_length
= mcbsp
->tx_word_length
;
782 rx_word_length
= mcbsp
->rx_word_length
;
784 if (tx_word_length
!= rx_word_length
)
787 /* First we wait for the transmitter to be ready */
788 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
789 while (!(spcr2
& XRDY
)) {
790 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
791 if (attempts
++ > 1000) {
792 /* We must reset the transmitter */
793 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
& (~XRST
));
795 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
| XRST
);
797 dev_err(mcbsp
->dev
, "McBSP%d transmitter not "
798 "ready\n", mcbsp
->id
);
803 /* Now we can push the data */
804 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
805 OMAP_MCBSP_WRITE(io_base
, DXR2
, word
>> 16);
806 OMAP_MCBSP_WRITE(io_base
, DXR1
, word
& 0xffff);
808 /* We wait for the receiver to be ready */
809 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
810 while (!(spcr1
& RRDY
)) {
811 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
812 if (attempts
++ > 1000) {
813 /* We must reset the receiver */
814 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
& (~RRST
));
816 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
| RRST
);
818 dev_err(mcbsp
->dev
, "McBSP%d receiver not "
819 "ready\n", mcbsp
->id
);
824 /* Receiver is ready, let's read the dummy data */
825 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
826 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
827 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
831 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll
);
833 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id
, u32
*word
)
835 struct omap_mcbsp
*mcbsp
;
837 void __iomem
*io_base
;
838 omap_mcbsp_word_length tx_word_length
;
839 omap_mcbsp_word_length rx_word_length
;
840 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
842 if (!omap_mcbsp_check_valid_id(id
)) {
843 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
847 mcbsp
= id_to_mcbsp_ptr(id
);
848 io_base
= mcbsp
->io_base
;
850 tx_word_length
= mcbsp
->tx_word_length
;
851 rx_word_length
= mcbsp
->rx_word_length
;
853 if (tx_word_length
!= rx_word_length
)
856 /* First we wait for the transmitter to be ready */
857 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
858 while (!(spcr2
& XRDY
)) {
859 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
860 if (attempts
++ > 1000) {
861 /* We must reset the transmitter */
862 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
& (~XRST
));
864 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
| XRST
);
866 dev_err(mcbsp
->dev
, "McBSP%d transmitter not "
867 "ready\n", mcbsp
->id
);
872 /* We first need to enable the bus clock */
873 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
874 OMAP_MCBSP_WRITE(io_base
, DXR2
, clock_word
>> 16);
875 OMAP_MCBSP_WRITE(io_base
, DXR1
, clock_word
& 0xffff);
877 /* We wait for the receiver to be ready */
878 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
879 while (!(spcr1
& RRDY
)) {
880 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
881 if (attempts
++ > 1000) {
882 /* We must reset the receiver */
883 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
& (~RRST
));
885 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
| RRST
);
887 dev_err(mcbsp
->dev
, "McBSP%d receiver not "
888 "ready\n", mcbsp
->id
);
893 /* Receiver is ready, there is something for us */
894 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
895 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
896 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
898 word
[0] = (word_lsb
| (word_msb
<< 16));
902 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll
);
905 * Simple DMA based buffer rx/tx routines.
906 * Nothing fancy, just a single buffer tx/rx through DMA.
907 * The DMA resources are released once the transfer is done.
908 * For anything fancier, you should use your own customized DMA
909 * routines and callbacks.
911 int omap_mcbsp_xmit_buffer(unsigned int id
, dma_addr_t buffer
,
914 struct omap_mcbsp
*mcbsp
;
920 if (!omap_mcbsp_check_valid_id(id
)) {
921 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
924 mcbsp
= id_to_mcbsp_ptr(id
);
926 if (omap_request_dma(mcbsp
->dma_tx_sync
, "McBSP TX",
927 omap_mcbsp_tx_dma_callback
,
930 dev_err(mcbsp
->dev
, " Unable to request DMA channel for "
931 "McBSP%d TX. Trying IRQ based TX\n",
935 mcbsp
->dma_tx_lch
= dma_tx_ch
;
937 dev_err(mcbsp
->dev
, "McBSP%d TX DMA on channel %d\n", mcbsp
->id
,
940 init_completion(&mcbsp
->tx_dma_completion
);
942 if (cpu_class_is_omap1()) {
943 src_port
= OMAP_DMA_PORT_TIPB
;
944 dest_port
= OMAP_DMA_PORT_EMIFF
;
946 if (cpu_class_is_omap2())
947 sync_dev
= mcbsp
->dma_tx_sync
;
949 omap_set_dma_transfer_params(mcbsp
->dma_tx_lch
,
950 OMAP_DMA_DATA_TYPE_S16
,
952 OMAP_DMA_SYNC_ELEMENT
,
955 omap_set_dma_dest_params(mcbsp
->dma_tx_lch
,
957 OMAP_DMA_AMODE_CONSTANT
,
958 mcbsp
->phys_base
+ OMAP_MCBSP_REG_DXR1
,
961 omap_set_dma_src_params(mcbsp
->dma_tx_lch
,
963 OMAP_DMA_AMODE_POST_INC
,
967 omap_start_dma(mcbsp
->dma_tx_lch
);
968 wait_for_completion(&mcbsp
->tx_dma_completion
);
972 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer
);
974 int omap_mcbsp_recv_buffer(unsigned int id
, dma_addr_t buffer
,
977 struct omap_mcbsp
*mcbsp
;
983 if (!omap_mcbsp_check_valid_id(id
)) {
984 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
987 mcbsp
= id_to_mcbsp_ptr(id
);
989 if (omap_request_dma(mcbsp
->dma_rx_sync
, "McBSP RX",
990 omap_mcbsp_rx_dma_callback
,
993 dev_err(mcbsp
->dev
, "Unable to request DMA channel for "
994 "McBSP%d RX. Trying IRQ based RX\n",
998 mcbsp
->dma_rx_lch
= dma_rx_ch
;
1000 dev_err(mcbsp
->dev
, "McBSP%d RX DMA on channel %d\n", mcbsp
->id
,
1003 init_completion(&mcbsp
->rx_dma_completion
);
1005 if (cpu_class_is_omap1()) {
1006 src_port
= OMAP_DMA_PORT_TIPB
;
1007 dest_port
= OMAP_DMA_PORT_EMIFF
;
1009 if (cpu_class_is_omap2())
1010 sync_dev
= mcbsp
->dma_rx_sync
;
1012 omap_set_dma_transfer_params(mcbsp
->dma_rx_lch
,
1013 OMAP_DMA_DATA_TYPE_S16
,
1015 OMAP_DMA_SYNC_ELEMENT
,
1018 omap_set_dma_src_params(mcbsp
->dma_rx_lch
,
1020 OMAP_DMA_AMODE_CONSTANT
,
1021 mcbsp
->phys_base
+ OMAP_MCBSP_REG_DRR1
,
1024 omap_set_dma_dest_params(mcbsp
->dma_rx_lch
,
1026 OMAP_DMA_AMODE_POST_INC
,
1030 omap_start_dma(mcbsp
->dma_rx_lch
);
1031 wait_for_completion(&mcbsp
->rx_dma_completion
);
1035 EXPORT_SYMBOL(omap_mcbsp_recv_buffer
);
1039 * Since SPI setup is much simpler than the generic McBSP one,
1040 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1041 * Once this is done, you can call omap_mcbsp_start().
1043 void omap_mcbsp_set_spi_mode(unsigned int id
,
1044 const struct omap_mcbsp_spi_cfg
*spi_cfg
)
1046 struct omap_mcbsp
*mcbsp
;
1047 struct omap_mcbsp_reg_cfg mcbsp_cfg
;
1049 if (!omap_mcbsp_check_valid_id(id
)) {
1050 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
1053 mcbsp
= id_to_mcbsp_ptr(id
);
1055 memset(&mcbsp_cfg
, 0, sizeof(struct omap_mcbsp_reg_cfg
));
1057 /* SPI has only one frame */
1058 mcbsp_cfg
.rcr1
|= (RWDLEN1(spi_cfg
->word_length
) | RFRLEN1(0));
1059 mcbsp_cfg
.xcr1
|= (XWDLEN1(spi_cfg
->word_length
) | XFRLEN1(0));
1061 /* Clock stop mode */
1062 if (spi_cfg
->clk_stp_mode
== OMAP_MCBSP_CLK_STP_MODE_NO_DELAY
)
1063 mcbsp_cfg
.spcr1
|= (1 << 12);
1065 mcbsp_cfg
.spcr1
|= (3 << 11);
1067 /* Set clock parities */
1068 if (spi_cfg
->rx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
1069 mcbsp_cfg
.pcr0
|= CLKRP
;
1071 mcbsp_cfg
.pcr0
&= ~CLKRP
;
1073 if (spi_cfg
->tx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
1074 mcbsp_cfg
.pcr0
&= ~CLKXP
;
1076 mcbsp_cfg
.pcr0
|= CLKXP
;
1078 /* Set SCLKME to 0 and CLKSM to 1 */
1079 mcbsp_cfg
.pcr0
&= ~SCLKME
;
1080 mcbsp_cfg
.srgr2
|= CLKSM
;
1083 if (spi_cfg
->fsx_polarity
== OMAP_MCBSP_FS_ACTIVE_HIGH
)
1084 mcbsp_cfg
.pcr0
&= ~FSXP
;
1086 mcbsp_cfg
.pcr0
|= FSXP
;
1088 if (spi_cfg
->spi_mode
== OMAP_MCBSP_SPI_MASTER
) {
1089 mcbsp_cfg
.pcr0
|= CLKXM
;
1090 mcbsp_cfg
.srgr1
|= CLKGDV(spi_cfg
->clk_div
- 1);
1091 mcbsp_cfg
.pcr0
|= FSXM
;
1092 mcbsp_cfg
.srgr2
&= ~FSGM
;
1093 mcbsp_cfg
.xcr2
|= XDATDLY(1);
1094 mcbsp_cfg
.rcr2
|= RDATDLY(1);
1096 mcbsp_cfg
.pcr0
&= ~CLKXM
;
1097 mcbsp_cfg
.srgr1
|= CLKGDV(1);
1098 mcbsp_cfg
.pcr0
&= ~FSXM
;
1099 mcbsp_cfg
.xcr2
&= ~XDATDLY(3);
1100 mcbsp_cfg
.rcr2
&= ~RDATDLY(3);
1103 mcbsp_cfg
.xcr2
&= ~XPHASE
;
1104 mcbsp_cfg
.rcr2
&= ~RPHASE
;
1106 omap_mcbsp_config(id
, &mcbsp_cfg
);
1108 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode
);
1110 #ifdef CONFIG_ARCH_OMAP3
1111 #define max_thres(m) (mcbsp->pdata->buffer_size)
1112 #define valid_threshold(m, val) ((val) <= max_thres(m))
1113 #define THRESHOLD_PROP_BUILDER(prop) \
1114 static ssize_t prop##_show(struct device *dev, \
1115 struct device_attribute *attr, char *buf) \
1117 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1119 return sprintf(buf, "%u\n", mcbsp->prop); \
1122 static ssize_t prop##_store(struct device *dev, \
1123 struct device_attribute *attr, \
1124 const char *buf, size_t size) \
1126 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1127 unsigned long val; \
1130 status = strict_strtoul(buf, 0, &val); \
1134 if (!valid_threshold(mcbsp, val)) \
1137 mcbsp->prop = val; \
1141 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1143 THRESHOLD_PROP_BUILDER(max_tx_thres
);
1144 THRESHOLD_PROP_BUILDER(max_rx_thres
);
1146 static const char *dma_op_modes
[] = {
1147 "element", "threshold", "frame",
1150 static ssize_t
dma_op_mode_show(struct device
*dev
,
1151 struct device_attribute
*attr
, char *buf
)
1153 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1154 int dma_op_mode
, i
= 0;
1156 const char * const *s
;
1158 dma_op_mode
= mcbsp
->dma_op_mode
;
1160 for (s
= &dma_op_modes
[i
]; i
< ARRAY_SIZE(dma_op_modes
); s
++, i
++) {
1161 if (dma_op_mode
== i
)
1162 len
+= sprintf(buf
+ len
, "[%s] ", *s
);
1164 len
+= sprintf(buf
+ len
, "%s ", *s
);
1166 len
+= sprintf(buf
+ len
, "\n");
1171 static ssize_t
dma_op_mode_store(struct device
*dev
,
1172 struct device_attribute
*attr
,
1173 const char *buf
, size_t size
)
1175 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1176 const char * const *s
;
1179 for (s
= &dma_op_modes
[i
]; i
< ARRAY_SIZE(dma_op_modes
); s
++, i
++)
1180 if (sysfs_streq(buf
, *s
))
1183 if (i
== ARRAY_SIZE(dma_op_modes
))
1186 spin_lock_irq(&mcbsp
->lock
);
1191 mcbsp
->dma_op_mode
= i
;
1194 spin_unlock_irq(&mcbsp
->lock
);
1199 static DEVICE_ATTR(dma_op_mode
, 0644, dma_op_mode_show
, dma_op_mode_store
);
1201 static const struct attribute
*additional_attrs
[] = {
1202 &dev_attr_max_tx_thres
.attr
,
1203 &dev_attr_max_rx_thres
.attr
,
1204 &dev_attr_dma_op_mode
.attr
,
1208 static const struct attribute_group additional_attr_group
= {
1209 .attrs
= (struct attribute
**)additional_attrs
,
1212 static inline int __devinit
omap_additional_add(struct device
*dev
)
1214 return sysfs_create_group(&dev
->kobj
, &additional_attr_group
);
1217 static inline void __devexit
omap_additional_remove(struct device
*dev
)
1219 sysfs_remove_group(&dev
->kobj
, &additional_attr_group
);
1222 static inline void __devinit
omap34xx_device_init(struct omap_mcbsp
*mcbsp
)
1224 mcbsp
->dma_op_mode
= MCBSP_DMA_MODE_ELEMENT
;
1225 if (cpu_is_omap34xx()) {
1226 mcbsp
->max_tx_thres
= max_thres(mcbsp
);
1227 mcbsp
->max_rx_thres
= max_thres(mcbsp
);
1229 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1230 * for mcbsp2 instances.
1232 if (omap_additional_add(mcbsp
->dev
))
1233 dev_warn(mcbsp
->dev
,
1234 "Unable to create additional controls\n");
1236 mcbsp
->max_tx_thres
= -EINVAL
;
1237 mcbsp
->max_rx_thres
= -EINVAL
;
1241 static inline void __devexit
omap34xx_device_exit(struct omap_mcbsp
*mcbsp
)
1243 if (cpu_is_omap34xx())
1244 omap_additional_remove(mcbsp
->dev
);
1247 static inline void __devinit
omap34xx_device_init(struct omap_mcbsp
*mcbsp
) {}
1248 static inline void __devexit
omap34xx_device_exit(struct omap_mcbsp
*mcbsp
) {}
1249 #endif /* CONFIG_ARCH_OMAP3 */
1252 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1253 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1255 static int __devinit
omap_mcbsp_probe(struct platform_device
*pdev
)
1257 struct omap_mcbsp_platform_data
*pdata
= pdev
->dev
.platform_data
;
1258 struct omap_mcbsp
*mcbsp
;
1259 int id
= pdev
->id
- 1;
1263 dev_err(&pdev
->dev
, "McBSP device initialized without"
1269 dev_dbg(&pdev
->dev
, "Initializing OMAP McBSP (%d).\n", pdev
->id
);
1271 if (id
>= omap_mcbsp_count
) {
1272 dev_err(&pdev
->dev
, "Invalid McBSP device id (%d)\n", id
);
1277 mcbsp
= kzalloc(sizeof(struct omap_mcbsp
), GFP_KERNEL
);
1283 spin_lock_init(&mcbsp
->lock
);
1286 mcbsp
->dma_tx_lch
= -1;
1287 mcbsp
->dma_rx_lch
= -1;
1289 mcbsp
->phys_base
= pdata
->phys_base
;
1290 mcbsp
->io_base
= ioremap(pdata
->phys_base
, SZ_4K
);
1291 if (!mcbsp
->io_base
) {
1296 /* Default I/O is IRQ based */
1297 mcbsp
->io_type
= OMAP_MCBSP_IRQ_IO
;
1298 mcbsp
->tx_irq
= pdata
->tx_irq
;
1299 mcbsp
->rx_irq
= pdata
->rx_irq
;
1300 mcbsp
->dma_rx_sync
= pdata
->dma_rx_sync
;
1301 mcbsp
->dma_tx_sync
= pdata
->dma_tx_sync
;
1303 mcbsp
->iclk
= clk_get(&pdev
->dev
, "ick");
1304 if (IS_ERR(mcbsp
->iclk
)) {
1305 ret
= PTR_ERR(mcbsp
->iclk
);
1306 dev_err(&pdev
->dev
, "unable to get ick: %d\n", ret
);
1310 mcbsp
->fclk
= clk_get(&pdev
->dev
, "fck");
1311 if (IS_ERR(mcbsp
->fclk
)) {
1312 ret
= PTR_ERR(mcbsp
->fclk
);
1313 dev_err(&pdev
->dev
, "unable to get fck: %d\n", ret
);
1317 mcbsp
->pdata
= pdata
;
1318 mcbsp
->dev
= &pdev
->dev
;
1319 mcbsp_ptr
[id
] = mcbsp
;
1320 platform_set_drvdata(pdev
, mcbsp
);
1322 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1323 omap34xx_device_init(mcbsp
);
1328 clk_put(mcbsp
->iclk
);
1330 iounmap(mcbsp
->io_base
);
1337 static int __devexit
omap_mcbsp_remove(struct platform_device
*pdev
)
1339 struct omap_mcbsp
*mcbsp
= platform_get_drvdata(pdev
);
1341 platform_set_drvdata(pdev
, NULL
);
1344 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&&
1345 mcbsp
->pdata
->ops
->free
)
1346 mcbsp
->pdata
->ops
->free(mcbsp
->id
);
1348 omap34xx_device_exit(mcbsp
);
1350 clk_disable(mcbsp
->fclk
);
1351 clk_disable(mcbsp
->iclk
);
1352 clk_put(mcbsp
->fclk
);
1353 clk_put(mcbsp
->iclk
);
1355 iounmap(mcbsp
->io_base
);
1366 static struct platform_driver omap_mcbsp_driver
= {
1367 .probe
= omap_mcbsp_probe
,
1368 .remove
= __devexit_p(omap_mcbsp_remove
),
1370 .name
= "omap-mcbsp",
1374 int __init
omap_mcbsp_init(void)
1376 /* Register the McBSP driver */
1377 return platform_driver_register(&omap_mcbsp_driver
);