?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] sem2mutex: misc static one-file mutexes
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / powerpc / platforms / powermac / cpufreq_64.c
blobb57e465a1b71d3ceb3409f6efd84a233c0c871e5
1 /*
2 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
3 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
10 * that is iMac G5 and latest single CPU desktop.
11 */
12
13 #include <linux/config.h>
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/cpufreq.h>
22 #include <linux/init.h>
23 #include <linux/completion.h>
24 #include <linux/mutex.h>
25 #include <asm/prom.h>
26 #include <asm/machdep.h>
27 #include <asm/irq.h>
28 #include <asm/sections.h>
29 #include <asm/cputable.h>
30 #include <asm/time.h>
31 #include <asm/smu.h>
32 #include <asm/pmac_pfunc.h>
33
34 #undef DEBUG
35
36 #ifdef DEBUG
37 #define DBG(fmt...) printk(fmt)
38 #else
39 #define DBG(fmt...)
40 #endif
41
42 /* see 970FX user manual */
43
44 #define SCOM_PCR 0x0aa001 /* PCR scom addr */
45
46 #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
47 #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
48 #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
49 #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
50 #define PCR_SPEED_MASK 0x000e0000U /* speed mask */
51 #define PCR_SPEED_SHIFT 17
52 #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
53 #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
54 #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
55 #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
56 #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
57 #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
58
59 #define SCOM_PSR 0x408001 /* PSR scom addr */
60 /* warning: PSR is a 64 bits register */
61 #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
62 #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
63 #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
64 #define PSR_CUR_SPEED_SHIFT (56)
65
66 /*
67 * The G5 only supports two frequencies (Quarter speed is not supported)
68 */
69 #define CPUFREQ_HIGH 0
70 #define CPUFREQ_LOW 1
71
72 static struct cpufreq_frequency_table g5_cpu_freqs[] = {
73 {CPUFREQ_HIGH, 0},
74 {CPUFREQ_LOW, 0},
75 {0, CPUFREQ_TABLE_END},
76 };
77
78 static struct freq_attr* g5_cpu_freqs_attr[] = {
79 &cpufreq_freq_attr_scaling_available_freqs,
80 NULL,
81 };
82
83 /* Power mode data is an array of the 32 bits PCR values to use for
84 * the various frequencies, retrieved from the device-tree
85 */
86 static u32 *g5_pmode_data;
87 static int g5_pmode_max;
88 static int g5_pmode_cur;
89
90 static void (*g5_switch_volt)(int speed_mode);
91 static int (*g5_switch_freq)(int speed_mode);
92 static int (*g5_query_freq)(void);
93
94 static DEFINE_MUTEX(g5_switch_mutex);
95
96
97 static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
98 static int g5_fvt_count; /* number of op. points */
99 static int g5_fvt_cur; /* current op. point */
100
101 /*
102 * SMU based voltage switching for Neo2 platforms
103 */
104
105 static void g5_smu_switch_volt(int speed_mode)
106 {
107 struct smu_simple_cmd cmd;
108
109 DECLARE_COMPLETION(comp);
110 smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
111 &comp, 'V', 'S', 'L', 'E', 'W',
112 0xff, g5_fvt_cur+1, speed_mode);
113 wait_for_completion(&comp);
114 }
115
116 /*
117 * Platform function based voltage/vdnap switching for Neo2
118 */
119
120 static struct pmf_function *pfunc_set_vdnap0;
121 static struct pmf_function *pfunc_vdnap0_complete;
122
123 static void g5_vdnap_switch_volt(int speed_mode)
124 {
125 struct pmf_args args;
126 u32 slew, done = 0;
127 unsigned long timeout;
128
129 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
130 args.count = 1;
131 args.u[0].p = &slew;
132
133 pmf_call_one(pfunc_set_vdnap0, &args);
134
135 /* It's an irq GPIO so we should be able to just block here,
136 * I'll do that later after I've properly tested the IRQ code for
137 * platform functions
138 */
139 timeout = jiffies + HZ/10;
140 while(!time_after(jiffies, timeout)) {
141 args.count = 1;
142 args.u[0].p = &done;
143 pmf_call_one(pfunc_vdnap0_complete, &args);
144 if (done)
145 break;
146 msleep(1);
147 }
148 if (done == 0)
149 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
150 }
151
152
153 /*
154 * SCOM based frequency switching for 970FX rev3
155 */
156 static int g5_scom_switch_freq(int speed_mode)
157 {
158 unsigned long flags;
159 int to;
160
161 /* If frequency is going up, first ramp up the voltage */
162 if (speed_mode < g5_pmode_cur)
163 g5_switch_volt(speed_mode);
164
165 local_irq_save(flags);
166
167 /* Clear PCR high */
168 scom970_write(SCOM_PCR, 0);
169 /* Clear PCR low */
170 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
171 /* Set PCR low */
172 scom970_write(SCOM_PCR, PCR_HILO_SELECT |
173 g5_pmode_data[speed_mode]);
174
175 /* Wait for completion */
176 for (to = 0; to < 10; to++) {
177 unsigned long psr = scom970_read(SCOM_PSR);
178
179 if ((psr & PSR_CMD_RECEIVED) == 0 &&
180 (((psr >> PSR_CUR_SPEED_SHIFT) ^
181 (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
182 == 0)
183 break;
184 if (psr & PSR_CMD_COMPLETED)
185 break;
186 udelay(100);
187 }
188
189 local_irq_restore(flags);
190
191 /* If frequency is going down, last ramp the voltage */
192 if (speed_mode > g5_pmode_cur)
193 g5_switch_volt(speed_mode);
194
195 g5_pmode_cur = speed_mode;
196 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
197
198 return 0;
199 }
200
201 static int g5_scom_query_freq(void)
202 {
203 unsigned long psr = scom970_read(SCOM_PSR);
204 int i;
205
206 for (i = 0; i <= g5_pmode_max; i++)
207 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
208 (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
209 break;
210 return i;
211 }
212
213 /*
214 * Platform function based voltage switching for PowerMac7,2 & 7,3
215 */
216
217 static struct pmf_function *pfunc_cpu0_volt_high;
218 static struct pmf_function *pfunc_cpu0_volt_low;
219 static struct pmf_function *pfunc_cpu1_volt_high;
220 static struct pmf_function *pfunc_cpu1_volt_low;
221
222 static void g5_pfunc_switch_volt(int speed_mode)
223 {
224 if (speed_mode == CPUFREQ_HIGH) {
225 if (pfunc_cpu0_volt_high)
226 pmf_call_one(pfunc_cpu0_volt_high, NULL);
227 if (pfunc_cpu1_volt_high)
228 pmf_call_one(pfunc_cpu1_volt_high, NULL);
229 } else {
230 if (pfunc_cpu0_volt_low)
231 pmf_call_one(pfunc_cpu0_volt_low, NULL);
232 if (pfunc_cpu1_volt_low)
233 pmf_call_one(pfunc_cpu1_volt_low, NULL);
234 }
235 msleep(10); /* should be faster , to fix */
236 }
237
238 /*
239 * Platform function based frequency switching for PowerMac7,2 & 7,3
240 */
241
242 static struct pmf_function *pfunc_cpu_setfreq_high;
243 static struct pmf_function *pfunc_cpu_setfreq_low;
244 static struct pmf_function *pfunc_cpu_getfreq;
245 static struct pmf_function *pfunc_slewing_done;;
246
247 static int g5_pfunc_switch_freq(int speed_mode)
248 {
249 struct pmf_args args;
250 u32 done = 0;
251 unsigned long timeout;
252
253 /* If frequency is going up, first ramp up the voltage */
254 if (speed_mode < g5_pmode_cur)
255 g5_switch_volt(speed_mode);
256
257 /* Do it */
258 if (speed_mode == CPUFREQ_HIGH)
259 pmf_call_one(pfunc_cpu_setfreq_high, NULL);
260 else
261 pmf_call_one(pfunc_cpu_setfreq_low, NULL);
262
263 /* It's an irq GPIO so we should be able to just block here,
264 * I'll do that later after I've properly tested the IRQ code for
265 * platform functions
266 */
267 timeout = jiffies + HZ/10;
268 while(!time_after(jiffies, timeout)) {
269 args.count = 1;
270 args.u[0].p = &done;
271 pmf_call_one(pfunc_slewing_done, &args);
272 if (done)
273 break;
274 msleep(1);
275 }
276 if (done == 0)
277 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
278
279 /* If frequency is going down, last ramp the voltage */
280 if (speed_mode > g5_pmode_cur)
281 g5_switch_volt(speed_mode);
282
283 g5_pmode_cur = speed_mode;
284 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
285
286 return 0;
287 }
288
289 static int g5_pfunc_query_freq(void)
290 {
291 struct pmf_args args;
292 u32 val = 0;
293
294 args.count = 1;
295 args.u[0].p = &val;
296 pmf_call_one(pfunc_cpu_getfreq, &args);
297 return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
298 }
299
300 /*
301 * Fake voltage switching for platforms with missing support
302 */
303
304 static void g5_dummy_switch_volt(int speed_mode)
305 {
306 }
307
308 /*
309 * Common interface to the cpufreq core
310 */
311
312 static int g5_cpufreq_verify(struct cpufreq_policy *policy)
313 {
314 return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
315 }
316
317 static int g5_cpufreq_target(struct cpufreq_policy *policy,
318 unsigned int target_freq, unsigned int relation)
319 {
320 unsigned int newstate = 0;
321 struct cpufreq_freqs freqs;
322 int rc;
323
324 if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
325 target_freq, relation, &newstate))
326 return -EINVAL;
327
328 if (g5_pmode_cur == newstate)
329 return 0;
330
331 mutex_lock(&g5_switch_mutex);
332
333 freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
334 freqs.new = g5_cpu_freqs[newstate].frequency;
335 freqs.cpu = 0;
336
337 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
338 rc = g5_switch_freq(newstate);
339 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
340
341 mutex_unlock(&g5_switch_mutex);
342
343 return rc;
344 }
345
346 static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
347 {
348 return g5_cpu_freqs[g5_pmode_cur].frequency;
349 }
350
351 static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
352 {
353 if (policy->cpu != 0)
354 return -ENODEV;
355
356 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
357 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
358 policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
359 policy->cpus = cpu_possible_map;
360 cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
361
362 return cpufreq_frequency_table_cpuinfo(policy,
363 g5_cpu_freqs);
364 }
365
366
367 static struct cpufreq_driver g5_cpufreq_driver = {
368 .name = "powermac",
369 .owner = THIS_MODULE,
370 .flags = CPUFREQ_CONST_LOOPS,
371 .init = g5_cpufreq_cpu_init,
372 .verify = g5_cpufreq_verify,
373 .target = g5_cpufreq_target,
374 .get = g5_cpufreq_get_speed,
375 .attr = g5_cpu_freqs_attr,
376 };
377
378
379 static int __init g5_neo2_cpufreq_init(struct device_node *cpus)
380 {
381 struct device_node *cpunode;
382 unsigned int psize, ssize;
383 unsigned long max_freq;
384 char *freq_method, *volt_method;
385 u32 *valp, pvr_hi;
386 int use_volts_vdnap = 0;
387 int use_volts_smu = 0;
388 int rc = -ENODEV;
389
390 /* Check supported platforms */
391 if (machine_is_compatible("PowerMac8,1") ||
392 machine_is_compatible("PowerMac8,2") ||
393 machine_is_compatible("PowerMac9,1"))
394 use_volts_smu = 1;
395 else if (machine_is_compatible("PowerMac11,2"))
396 use_volts_vdnap = 1;
397 else
398 return -ENODEV;
399
400 /* Get first CPU node */
401 for (cpunode = NULL;
402 (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
403 u32 *reg =
404 (u32 *)get_property(cpunode, "reg", NULL);
405 if (reg == NULL || (*reg) != 0)
406 continue;
407 if (!strcmp(cpunode->type, "cpu"))
408 break;
409 }
410 if (cpunode == NULL) {
411 printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
412 return -ENODEV;
413 }
414
415 /* Check 970FX for now */
416 valp = (u32 *)get_property(cpunode, "cpu-version", NULL);
417 if (!valp) {
418 DBG("No cpu-version property !\n");
419 goto bail_noprops;
420 }
421 pvr_hi = (*valp) >> 16;
422 if (pvr_hi != 0x3c && pvr_hi != 0x44) {
423 printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
424 goto bail_noprops;
425 }
426
427 /* Look for the powertune data in the device-tree */
428 g5_pmode_data = (u32 *)get_property(cpunode, "power-mode-data",&psize);
429 if (!g5_pmode_data) {
430 DBG("No power-mode-data !\n");
431 goto bail_noprops;
432 }
433 g5_pmode_max = psize / sizeof(u32) - 1;
434
435 if (use_volts_smu) {
436 struct smu_sdbp_header *shdr;
437
438 /* Look for the FVT table */
439 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
440 if (!shdr)
441 goto bail_noprops;
442 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
443 ssize = (shdr->len * sizeof(u32)) -
444 sizeof(struct smu_sdbp_header);
445 g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
446 g5_fvt_cur = 0;
447
448 /* Sanity checking */
449 if (g5_fvt_count < 1 || g5_pmode_max < 1)
450 goto bail_noprops;
451
452 g5_switch_volt = g5_smu_switch_volt;
453 volt_method = "SMU";
454 } else if (use_volts_vdnap) {
455 struct device_node *root;
456
457 root = of_find_node_by_path("/");
458 if (root == NULL) {
459 printk(KERN_ERR "cpufreq: Can't find root of "
460 "device tree\n");
461 goto bail_noprops;
462 }
463 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
464 pfunc_vdnap0_complete =
465 pmf_find_function(root, "slewing-done");
466 if (pfunc_set_vdnap0 == NULL ||
467 pfunc_vdnap0_complete == NULL) {
468 printk(KERN_ERR "cpufreq: Can't find required "
469 "platform function\n");
470 goto bail_noprops;
471 }
472
473 g5_switch_volt = g5_vdnap_switch_volt;
474 volt_method = "GPIO";
475 } else {
476 g5_switch_volt = g5_dummy_switch_volt;
477 volt_method = "none";
478 }
479
480 /*
481 * From what I see, clock-frequency is always the maximal frequency.
482 * The current driver can not slew sysclk yet, so we really only deal
483 * with powertune steps for now. We also only implement full freq and
484 * half freq in this version. So far, I haven't yet seen a machine
485 * supporting anything else.
486 */
487 valp = (u32 *)get_property(cpunode, "clock-frequency", NULL);
488 if (!valp)
489 return -ENODEV;
490 max_freq = (*valp)/1000;
491 g5_cpu_freqs[0].frequency = max_freq;
492 g5_cpu_freqs[1].frequency = max_freq/2;
493
494 /* Set callbacks */
495 g5_switch_freq = g5_scom_switch_freq;
496 g5_query_freq = g5_scom_query_freq;
497 freq_method = "SCOM";
498
499 /* Force apply current frequency to make sure everything is in
500 * sync (voltage is right for example). Firmware may leave us with
501 * a strange setting ...
502 */
503 g5_switch_volt(CPUFREQ_HIGH);
504 msleep(10);
505 g5_pmode_cur = -1;
506 g5_switch_freq(g5_query_freq());
507
508 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
509 printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
510 freq_method, volt_method);
511 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
512 g5_cpu_freqs[1].frequency/1000,
513 g5_cpu_freqs[0].frequency/1000,
514 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
515
516 rc = cpufreq_register_driver(&g5_cpufreq_driver);
517
518 /* We keep the CPU node on hold... hopefully, Apple G5 don't have
519 * hotplug CPU with a dynamic device-tree ...
520 */
521 return rc;
522
523 bail_noprops:
524 of_node_put(cpunode);
525
526 return rc;
527 }
528
529 static int __init g5_pm72_cpufreq_init(struct device_node *cpus)
530 {
531 struct device_node *cpuid = NULL, *hwclock = NULL, *cpunode = NULL;
532 u8 *eeprom = NULL;
533 u32 *valp;
534 u64 max_freq, min_freq, ih, il;
535 int has_volt = 1, rc = 0;
536
537 /* Get first CPU node */
538 for (cpunode = NULL;
539 (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
540 if (!strcmp(cpunode->type, "cpu"))
541 break;
542 }
543 if (cpunode == NULL) {
544 printk(KERN_ERR "cpufreq: Can't find any CPU node\n");
545 return -ENODEV;
546 }
547
548 /* Lookup the cpuid eeprom node */
549 cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
550 if (cpuid != NULL)
551 eeprom = (u8 *)get_property(cpuid, "cpuid", NULL);
552 if (eeprom == NULL) {
553 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
554 rc = -ENODEV;
555 goto bail;
556 }
557
558 /* Lookup the i2c hwclock */
559 for (hwclock = NULL;
560 (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){
561 char *loc = get_property(hwclock, "hwctrl-location", NULL);
562 if (loc == NULL)
563 continue;
564 if (strcmp(loc, "CPU CLOCK"))
565 continue;
566 if (!get_property(hwclock, "platform-get-frequency", NULL))
567 continue;
568 break;
569 }
570 if (hwclock == NULL) {
571 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
572 rc = -ENODEV;
573 goto bail;
574 }
575
576 DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
577
578 /* Now get all the platform functions */
579 pfunc_cpu_getfreq =
580 pmf_find_function(hwclock, "get-frequency");
581 pfunc_cpu_setfreq_high =
582 pmf_find_function(hwclock, "set-frequency-high");
583 pfunc_cpu_setfreq_low =
584 pmf_find_function(hwclock, "set-frequency-low");
585 pfunc_slewing_done =
586 pmf_find_function(hwclock, "slewing-done");
587 pfunc_cpu0_volt_high =
588 pmf_find_function(hwclock, "set-voltage-high-0");
589 pfunc_cpu0_volt_low =
590 pmf_find_function(hwclock, "set-voltage-low-0");
591 pfunc_cpu1_volt_high =
592 pmf_find_function(hwclock, "set-voltage-high-1");
593 pfunc_cpu1_volt_low =
594 pmf_find_function(hwclock, "set-voltage-low-1");
595
596 /* Check we have minimum requirements */
597 if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
598 pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
599 printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
600 rc = -ENODEV;
601 goto bail;
602 }
603
604 /* Check that we have complete sets */
605 if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
606 pmf_put_function(pfunc_cpu0_volt_high);
607 pmf_put_function(pfunc_cpu0_volt_low);
608 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
609 has_volt = 0;
610 }
611 if (!has_volt ||
612 pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
613 pmf_put_function(pfunc_cpu1_volt_high);
614 pmf_put_function(pfunc_cpu1_volt_low);
615 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
616 }
617
618 /* Note: The device tree also contains a "platform-set-values"
619 * function for which I haven't quite figured out the usage. It
620 * might have to be called on init and/or wakeup, I'm not too sure
621 * but things seem to work fine without it so far ...
622 */
623
624 /* Get max frequency from device-tree */
625 valp = (u32 *)get_property(cpunode, "clock-frequency", NULL);
626 if (!valp) {
627 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
628 rc = -ENODEV;
629 goto bail;
630 }
631
632 max_freq = (*valp)/1000;
633
634 /* Now calculate reduced frequency by using the cpuid input freq
635 * ratio. This requires 64 bits math unless we are willing to lose
636 * some precision
637 */
638 ih = *((u32 *)(eeprom + 0x10));
639 il = *((u32 *)(eeprom + 0x20));
640 min_freq = 0;
641 if (ih != 0 && il != 0)
642 min_freq = (max_freq * il) / ih;
643
644 /* Sanity check */
645 if (min_freq >= max_freq || min_freq < 1000) {
646 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
647 rc = -ENODEV;
648 goto bail;
649 }
650 g5_cpu_freqs[0].frequency = max_freq;
651 g5_cpu_freqs[1].frequency = min_freq;
652
653 /* Set callbacks */
654 g5_switch_volt = g5_pfunc_switch_volt;
655 g5_switch_freq = g5_pfunc_switch_freq;
656 g5_query_freq = g5_pfunc_query_freq;
657
658 /* Force apply current frequency to make sure everything is in
659 * sync (voltage is right for example). Firmware may leave us with
660 * a strange setting ...
661 */
662 g5_switch_volt(CPUFREQ_HIGH);
663 msleep(10);
664 g5_pmode_cur = -1;
665 g5_switch_freq(g5_query_freq());
666
667 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
668 printk(KERN_INFO "Frequency method: i2c/pfunc, "
669 "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
670 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
671 g5_cpu_freqs[1].frequency/1000,
672 g5_cpu_freqs[0].frequency/1000,
673 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
674
675 rc = cpufreq_register_driver(&g5_cpufreq_driver);
676 bail:
677 if (rc != 0) {
678 pmf_put_function(pfunc_cpu_getfreq);
679 pmf_put_function(pfunc_cpu_setfreq_high);
680 pmf_put_function(pfunc_cpu_setfreq_low);
681 pmf_put_function(pfunc_slewing_done);
682 pmf_put_function(pfunc_cpu0_volt_high);
683 pmf_put_function(pfunc_cpu0_volt_low);
684 pmf_put_function(pfunc_cpu1_volt_high);
685 pmf_put_function(pfunc_cpu1_volt_low);
686 }
687 of_node_put(hwclock);
688 of_node_put(cpuid);
689 of_node_put(cpunode);
690
691 return rc;
692 }
693
694 static int __init g5_rm31_cpufreq_init(struct device_node *cpus)
695 {
696 /* NYI */
697 return 0;
698 }
699
700 static int __init g5_cpufreq_init(void)
701 {
702 struct device_node *cpus;
703 int rc;
704
705 cpus = of_find_node_by_path("/cpus");
706 if (cpus == NULL) {
707 DBG("No /cpus node !\n");
708 return -ENODEV;
709 }
710
711 if (machine_is_compatible("PowerMac7,2") ||
712 machine_is_compatible("PowerMac7,3"))
713 rc = g5_pm72_cpufreq_init(cpus);
714 else if (machine_is_compatible("RackMac3,1"))
715 rc = g5_rm31_cpufreq_init(cpus);
716 else
717 rc = g5_neo2_cpufreq_init(cpus);
718
719 of_node_put(cpus);
720 return rc;
721 }
722
723 module_init(g5_cpufreq_init);
724
725
726 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree