2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
53 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= drm_gem_object_alloc(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 mutex_lock(&dev
->struct_mutex
);
132 drm_gem_object_handle_unreference(obj
);
133 mutex_unlock(&dev
->struct_mutex
);
138 args
->handle
= handle
;
144 fast_shmem_read(struct page
**pages
,
145 loff_t page_base
, int page_offset
,
152 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
155 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
156 kunmap_atomic(vaddr
, KM_USER0
);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
166 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
167 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
169 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
170 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
174 slow_shmem_copy(struct page
*dst_page
,
176 struct page
*src_page
,
180 char *dst_vaddr
, *src_vaddr
;
182 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
183 if (dst_vaddr
== NULL
)
186 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
187 if (src_vaddr
== NULL
) {
188 kunmap_atomic(dst_vaddr
, KM_USER0
);
192 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
194 kunmap_atomic(src_vaddr
, KM_USER1
);
195 kunmap_atomic(dst_vaddr
, KM_USER0
);
201 slow_shmem_bit17_copy(struct page
*gpu_page
,
203 struct page
*cpu_page
,
208 char *gpu_vaddr
, *cpu_vaddr
;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page
, cpu_offset
,
214 gpu_page
, gpu_offset
, length
);
216 return slow_shmem_copy(gpu_page
, gpu_offset
,
217 cpu_page
, cpu_offset
, length
);
220 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
221 if (gpu_vaddr
== NULL
)
224 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
225 if (cpu_vaddr
== NULL
) {
226 kunmap_atomic(gpu_vaddr
, KM_USER0
);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
235 int this_length
= min(cacheline_end
- gpu_offset
, length
);
236 int swizzled_gpu_offset
= gpu_offset
^ 64;
239 memcpy(cpu_vaddr
+ cpu_offset
,
240 gpu_vaddr
+ swizzled_gpu_offset
,
243 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
244 cpu_vaddr
+ cpu_offset
,
247 cpu_offset
+= this_length
;
248 gpu_offset
+= this_length
;
249 length
-= this_length
;
252 kunmap_atomic(cpu_vaddr
, KM_USER1
);
253 kunmap_atomic(gpu_vaddr
, KM_USER0
);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
265 struct drm_i915_gem_pread
*args
,
266 struct drm_file
*file_priv
)
268 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
270 loff_t offset
, page_base
;
271 char __user
*user_data
;
272 int page_offset
, page_length
;
275 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
278 mutex_lock(&dev
->struct_mutex
);
280 ret
= i915_gem_object_get_pages(obj
);
284 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
289 obj_priv
= obj
->driver_private
;
290 offset
= args
->offset
;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base
= (offset
& ~(PAGE_SIZE
-1));
300 page_offset
= offset
& (PAGE_SIZE
-1);
301 page_length
= remain
;
302 if ((page_offset
+ remain
) > PAGE_SIZE
)
303 page_length
= PAGE_SIZE
- page_offset
;
305 ret
= fast_shmem_read(obj_priv
->pages
,
306 page_base
, page_offset
,
307 user_data
, page_length
);
311 remain
-= page_length
;
312 user_data
+= page_length
;
313 offset
+= page_length
;
317 i915_gem_object_put_pages(obj
);
319 mutex_unlock(&dev
->struct_mutex
);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object
*obj
)
327 return mapping_gfp_mask(obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object
*obj
, gfp_t gfp
)
333 mapping_set_gfp_mask(obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
, gfp
);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
341 ret
= i915_gem_object_get_pages(obj
);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret
== -ENOMEM
) {
347 struct drm_device
*dev
= obj
->dev
;
350 ret
= i915_gem_evict_something(dev
, obj
->size
);
354 gfp
= i915_gem_object_get_page_gfp_mask(obj
);
355 i915_gem_object_set_page_gfp_mask(obj
, gfp
& ~__GFP_NORETRY
);
356 ret
= i915_gem_object_get_pages(obj
);
357 i915_gem_object_set_page_gfp_mask (obj
, gfp
);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
371 struct drm_i915_gem_pread
*args
,
372 struct drm_file
*file_priv
)
374 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
375 struct mm_struct
*mm
= current
->mm
;
376 struct page
**user_pages
;
378 loff_t offset
, pinned_pages
, i
;
379 loff_t first_data_page
, last_data_page
, num_pages
;
380 int shmem_page_index
, shmem_page_offset
;
381 int data_page_index
, data_page_offset
;
384 uint64_t data_ptr
= args
->data_ptr
;
385 int do_bit17_swizzling
;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page
= data_ptr
/ PAGE_SIZE
;
394 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
395 num_pages
= last_data_page
- first_data_page
+ 1;
397 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
398 if (user_pages
== NULL
)
401 down_read(&mm
->mmap_sem
);
402 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
403 num_pages
, 1, 0, user_pages
, NULL
);
404 up_read(&mm
->mmap_sem
);
405 if (pinned_pages
< num_pages
) {
407 goto fail_put_user_pages
;
410 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
412 mutex_lock(&dev
->struct_mutex
);
414 ret
= i915_gem_object_get_pages_or_evict(obj
);
418 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
423 obj_priv
= obj
->driver_private
;
424 offset
= args
->offset
;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index
= offset
/ PAGE_SIZE
;
436 shmem_page_offset
= offset
& ~PAGE_MASK
;
437 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
438 data_page_offset
= data_ptr
& ~PAGE_MASK
;
440 page_length
= remain
;
441 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
442 page_length
= PAGE_SIZE
- shmem_page_offset
;
443 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
444 page_length
= PAGE_SIZE
- data_page_offset
;
446 if (do_bit17_swizzling
) {
447 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
449 user_pages
[data_page_index
],
454 ret
= slow_shmem_copy(user_pages
[data_page_index
],
456 obj_priv
->pages
[shmem_page_index
],
463 remain
-= page_length
;
464 data_ptr
+= page_length
;
465 offset
+= page_length
;
469 i915_gem_object_put_pages(obj
);
471 mutex_unlock(&dev
->struct_mutex
);
473 for (i
= 0; i
< pinned_pages
; i
++) {
474 SetPageDirty(user_pages
[i
]);
475 page_cache_release(user_pages
[i
]);
477 drm_free_large(user_pages
);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
489 struct drm_file
*file_priv
)
491 struct drm_i915_gem_pread
*args
= data
;
492 struct drm_gem_object
*obj
;
493 struct drm_i915_gem_object
*obj_priv
;
496 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
499 obj_priv
= obj
->driver_private
;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
506 args
->offset
+ args
->size
> obj
->size
) {
507 drm_gem_object_unreference(obj
);
511 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
512 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
514 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
516 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
520 drm_gem_object_unreference(obj
);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping
*mapping
,
531 loff_t page_base
, int page_offset
,
532 char __user
*user_data
,
536 unsigned long unwritten
;
538 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
539 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
541 io_mapping_unmap_atomic(vaddr_atomic
);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping
*mapping
,
553 loff_t gtt_base
, int gtt_offset
,
554 struct page
*user_page
, int user_offset
,
557 char *src_vaddr
, *dst_vaddr
;
558 unsigned long unwritten
;
560 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
561 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
562 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
563 src_vaddr
+ user_offset
,
565 kunmap_atomic(src_vaddr
, KM_USER1
);
566 io_mapping_unmap_atomic(dst_vaddr
);
573 fast_shmem_write(struct page
**pages
,
574 loff_t page_base
, int page_offset
,
579 unsigned long unwritten
;
581 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
584 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
585 kunmap_atomic(vaddr
, KM_USER0
);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
598 struct drm_i915_gem_pwrite
*args
,
599 struct drm_file
*file_priv
)
601 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
602 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
604 loff_t offset
, page_base
;
605 char __user
*user_data
;
606 int page_offset
, page_length
;
609 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
611 if (!access_ok(VERIFY_READ
, user_data
, remain
))
615 mutex_lock(&dev
->struct_mutex
);
616 ret
= i915_gem_object_pin(obj
, 0);
618 mutex_unlock(&dev
->struct_mutex
);
621 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
625 obj_priv
= obj
->driver_private
;
626 offset
= obj_priv
->gtt_offset
+ args
->offset
;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base
= (offset
& ~(PAGE_SIZE
-1));
636 page_offset
= offset
& (PAGE_SIZE
-1);
637 page_length
= remain
;
638 if ((page_offset
+ remain
) > PAGE_SIZE
)
639 page_length
= PAGE_SIZE
- page_offset
;
641 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
642 page_offset
, user_data
, page_length
);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain
-= page_length
;
652 user_data
+= page_length
;
653 offset
+= page_length
;
657 i915_gem_object_unpin(obj
);
658 mutex_unlock(&dev
->struct_mutex
);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
672 struct drm_i915_gem_pwrite
*args
,
673 struct drm_file
*file_priv
)
675 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
676 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
678 loff_t gtt_page_base
, offset
;
679 loff_t first_data_page
, last_data_page
, num_pages
;
680 loff_t pinned_pages
, i
;
681 struct page
**user_pages
;
682 struct mm_struct
*mm
= current
->mm
;
683 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
685 uint64_t data_ptr
= args
->data_ptr
;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page
= data_ptr
/ PAGE_SIZE
;
694 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
695 num_pages
= last_data_page
- first_data_page
+ 1;
697 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
698 if (user_pages
== NULL
)
701 down_read(&mm
->mmap_sem
);
702 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
703 num_pages
, 0, 0, user_pages
, NULL
);
704 up_read(&mm
->mmap_sem
);
705 if (pinned_pages
< num_pages
) {
707 goto out_unpin_pages
;
710 mutex_lock(&dev
->struct_mutex
);
711 ret
= i915_gem_object_pin(obj
, 0);
715 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
717 goto out_unpin_object
;
719 obj_priv
= obj
->driver_private
;
720 offset
= obj_priv
->gtt_offset
+ args
->offset
;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base
= offset
& PAGE_MASK
;
732 gtt_page_offset
= offset
& ~PAGE_MASK
;
733 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
734 data_page_offset
= data_ptr
& ~PAGE_MASK
;
736 page_length
= remain
;
737 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
738 page_length
= PAGE_SIZE
- gtt_page_offset
;
739 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
740 page_length
= PAGE_SIZE
- data_page_offset
;
742 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
743 gtt_page_base
, gtt_page_offset
,
744 user_pages
[data_page_index
],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object
;
755 remain
-= page_length
;
756 offset
+= page_length
;
757 data_ptr
+= page_length
;
761 i915_gem_object_unpin(obj
);
763 mutex_unlock(&dev
->struct_mutex
);
765 for (i
= 0; i
< pinned_pages
; i
++)
766 page_cache_release(user_pages
[i
]);
767 drm_free_large(user_pages
);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
778 struct drm_i915_gem_pwrite
*args
,
779 struct drm_file
*file_priv
)
781 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
783 loff_t offset
, page_base
;
784 char __user
*user_data
;
785 int page_offset
, page_length
;
788 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
791 mutex_lock(&dev
->struct_mutex
);
793 ret
= i915_gem_object_get_pages(obj
);
797 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
801 obj_priv
= obj
->driver_private
;
802 offset
= args
->offset
;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base
= (offset
& ~(PAGE_SIZE
-1));
813 page_offset
= offset
& (PAGE_SIZE
-1);
814 page_length
= remain
;
815 if ((page_offset
+ remain
) > PAGE_SIZE
)
816 page_length
= PAGE_SIZE
- page_offset
;
818 ret
= fast_shmem_write(obj_priv
->pages
,
819 page_base
, page_offset
,
820 user_data
, page_length
);
824 remain
-= page_length
;
825 user_data
+= page_length
;
826 offset
+= page_length
;
830 i915_gem_object_put_pages(obj
);
832 mutex_unlock(&dev
->struct_mutex
);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
846 struct drm_i915_gem_pwrite
*args
,
847 struct drm_file
*file_priv
)
849 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
850 struct mm_struct
*mm
= current
->mm
;
851 struct page
**user_pages
;
853 loff_t offset
, pinned_pages
, i
;
854 loff_t first_data_page
, last_data_page
, num_pages
;
855 int shmem_page_index
, shmem_page_offset
;
856 int data_page_index
, data_page_offset
;
859 uint64_t data_ptr
= args
->data_ptr
;
860 int do_bit17_swizzling
;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page
= data_ptr
/ PAGE_SIZE
;
869 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
870 num_pages
= last_data_page
- first_data_page
+ 1;
872 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
873 if (user_pages
== NULL
)
876 down_read(&mm
->mmap_sem
);
877 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
878 num_pages
, 0, 0, user_pages
, NULL
);
879 up_read(&mm
->mmap_sem
);
880 if (pinned_pages
< num_pages
) {
882 goto fail_put_user_pages
;
885 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
887 mutex_lock(&dev
->struct_mutex
);
889 ret
= i915_gem_object_get_pages_or_evict(obj
);
893 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
897 obj_priv
= obj
->driver_private
;
898 offset
= args
->offset
;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index
= offset
/ PAGE_SIZE
;
911 shmem_page_offset
= offset
& ~PAGE_MASK
;
912 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
913 data_page_offset
= data_ptr
& ~PAGE_MASK
;
915 page_length
= remain
;
916 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
917 page_length
= PAGE_SIZE
- shmem_page_offset
;
918 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
919 page_length
= PAGE_SIZE
- data_page_offset
;
921 if (do_bit17_swizzling
) {
922 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
924 user_pages
[data_page_index
],
929 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
931 user_pages
[data_page_index
],
938 remain
-= page_length
;
939 data_ptr
+= page_length
;
940 offset
+= page_length
;
944 i915_gem_object_put_pages(obj
);
946 mutex_unlock(&dev
->struct_mutex
);
948 for (i
= 0; i
< pinned_pages
; i
++)
949 page_cache_release(user_pages
[i
]);
950 drm_free_large(user_pages
);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
962 struct drm_file
*file_priv
)
964 struct drm_i915_gem_pwrite
*args
= data
;
965 struct drm_gem_object
*obj
;
966 struct drm_i915_gem_object
*obj_priv
;
969 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
972 obj_priv
= obj
->driver_private
;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
979 args
->offset
+ args
->size
> obj
->size
) {
980 drm_gem_object_unreference(obj
);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv
->phys_obj
)
991 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
992 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
993 dev
->gtt_total
!= 0) {
994 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
995 if (ret
== -EFAULT
) {
996 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
1000 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
1002 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
1003 if (ret
== -EFAULT
) {
1004 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
1011 DRM_INFO("pwrite failed %d\n", ret
);
1014 drm_gem_object_unreference(obj
);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1025 struct drm_file
*file_priv
)
1027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1028 struct drm_i915_gem_set_domain
*args
= data
;
1029 struct drm_gem_object
*obj
;
1030 struct drm_i915_gem_object
*obj_priv
;
1031 uint32_t read_domains
= args
->read_domains
;
1032 uint32_t write_domain
= args
->write_domain
;
1035 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1042 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain
!= 0 && read_domains
!= write_domain
)
1051 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1054 obj_priv
= obj
->driver_private
;
1056 mutex_lock(&dev
->struct_mutex
);
1058 intel_mark_busy(dev
, obj
);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj
, obj
->size
, read_domains
, write_domain
);
1064 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1065 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1071 list_move_tail(&obj_priv
->fence_list
,
1072 &dev_priv
->mm
.fence_list
);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1085 drm_gem_object_unreference(obj
);
1086 mutex_unlock(&dev
->struct_mutex
);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1095 struct drm_file
*file_priv
)
1097 struct drm_i915_gem_sw_finish
*args
= data
;
1098 struct drm_gem_object
*obj
;
1099 struct drm_i915_gem_object
*obj_priv
;
1102 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1105 mutex_lock(&dev
->struct_mutex
);
1106 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1108 mutex_unlock(&dev
->struct_mutex
);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__
, args
->handle
, obj
, obj
->size
);
1116 obj_priv
= obj
->driver_private
;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv
->pin_count
)
1120 i915_gem_object_flush_cpu_write_domain(obj
);
1122 drm_gem_object_unreference(obj
);
1123 mutex_unlock(&dev
->struct_mutex
);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1136 struct drm_file
*file_priv
)
1138 struct drm_i915_gem_mmap
*args
= data
;
1139 struct drm_gem_object
*obj
;
1143 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1146 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1150 offset
= args
->offset
;
1152 down_write(¤t
->mm
->mmap_sem
);
1153 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1154 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1156 up_write(¤t
->mm
->mmap_sem
);
1157 mutex_lock(&dev
->struct_mutex
);
1158 drm_gem_object_unreference(obj
);
1159 mutex_unlock(&dev
->struct_mutex
);
1160 if (IS_ERR((void *)addr
))
1163 args
->addr_ptr
= (uint64_t) addr
;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1186 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1187 struct drm_device
*dev
= obj
->dev
;
1188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1189 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1190 pgoff_t page_offset
;
1193 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev
->struct_mutex
);
1201 if (!obj_priv
->gtt_space
) {
1202 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1206 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1208 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1213 /* Need a new fence register? */
1214 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1215 ret
= i915_gem_object_get_fence_reg(obj
);
1220 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1223 /* Finally, remap it using the new GTT offset */
1224 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1226 mutex_unlock(&dev
->struct_mutex
);
1231 return VM_FAULT_NOPAGE
;
1234 return VM_FAULT_OOM
;
1236 return VM_FAULT_SIGBUS
;
1241 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1242 * @obj: obj in question
1244 * GEM memory mapping works by handing back to userspace a fake mmap offset
1245 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1246 * up the object based on the offset and sets up the various memory mapping
1249 * This routine allocates and attaches a fake offset for @obj.
1252 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1254 struct drm_device
*dev
= obj
->dev
;
1255 struct drm_gem_mm
*mm
= dev
->mm_private
;
1256 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1257 struct drm_map_list
*list
;
1258 struct drm_local_map
*map
;
1261 /* Set the object up for mmap'ing */
1262 list
= &obj
->map_list
;
1263 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1268 map
->type
= _DRM_GEM
;
1269 map
->size
= obj
->size
;
1272 /* Get a DRM GEM mmap offset allocated... */
1273 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1274 obj
->size
/ PAGE_SIZE
, 0, 0);
1275 if (!list
->file_offset_node
) {
1276 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1281 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1282 obj
->size
/ PAGE_SIZE
, 0);
1283 if (!list
->file_offset_node
) {
1288 list
->hash
.key
= list
->file_offset_node
->start
;
1289 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1290 DRM_ERROR("failed to add to map hash\n");
1295 /* By now we should be all set, any drm_mmap request on the offset
1296 * below will get to our mmap & fault handler */
1297 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1302 drm_mm_put_block(list
->file_offset_node
);
1310 * i915_gem_release_mmap - remove physical page mappings
1311 * @obj: obj in question
1313 * Preserve the reservation of the mmaping with the DRM core code, but
1314 * relinquish ownership of the pages back to the system.
1316 * It is vital that we remove the page mapping if we have mapped a tiled
1317 * object through the GTT and then lose the fence register due to
1318 * resource pressure. Similarly if the object has been moved out of the
1319 * aperture, than pages mapped into userspace must be revoked. Removing the
1320 * mapping will then trigger a page fault on the next user access, allowing
1321 * fixup by i915_gem_fault().
1324 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1326 struct drm_device
*dev
= obj
->dev
;
1327 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1329 if (dev
->dev_mapping
)
1330 unmap_mapping_range(dev
->dev_mapping
,
1331 obj_priv
->mmap_offset
, obj
->size
, 1);
1335 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1337 struct drm_device
*dev
= obj
->dev
;
1338 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1339 struct drm_gem_mm
*mm
= dev
->mm_private
;
1340 struct drm_map_list
*list
;
1342 list
= &obj
->map_list
;
1343 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1345 if (list
->file_offset_node
) {
1346 drm_mm_put_block(list
->file_offset_node
);
1347 list
->file_offset_node
= NULL
;
1355 obj_priv
->mmap_offset
= 0;
1359 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1360 * @obj: object to check
1362 * Return the required GTT alignment for an object, taking into account
1363 * potential fence register mapping if needed.
1366 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1368 struct drm_device
*dev
= obj
->dev
;
1369 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1373 * Minimum alignment is 4k (GTT page size), but might be greater
1374 * if a fence register is needed for the object.
1376 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1380 * Previous chips need to be aligned to the size of the smallest
1381 * fence register that can contain the object.
1388 for (i
= start
; i
< obj
->size
; i
<<= 1)
1395 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1397 * @data: GTT mapping ioctl data
1398 * @file_priv: GEM object info
1400 * Simply returns the fake offset to userspace so it can mmap it.
1401 * The mmap call will end up in drm_gem_mmap(), which will set things
1402 * up so we can get faults in the handler above.
1404 * The fault handler will take care of binding the object into the GTT
1405 * (since it may have been evicted to make room for something), allocating
1406 * a fence register, and mapping the appropriate aperture address into
1410 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1411 struct drm_file
*file_priv
)
1413 struct drm_i915_gem_mmap_gtt
*args
= data
;
1414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1415 struct drm_gem_object
*obj
;
1416 struct drm_i915_gem_object
*obj_priv
;
1419 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1422 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1426 mutex_lock(&dev
->struct_mutex
);
1428 obj_priv
= obj
->driver_private
;
1430 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1431 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1432 drm_gem_object_unreference(obj
);
1433 mutex_unlock(&dev
->struct_mutex
);
1438 if (!obj_priv
->mmap_offset
) {
1439 ret
= i915_gem_create_mmap_offset(obj
);
1441 drm_gem_object_unreference(obj
);
1442 mutex_unlock(&dev
->struct_mutex
);
1447 args
->offset
= obj_priv
->mmap_offset
;
1450 * Pull it into the GTT so that we have a page list (makes the
1451 * initial fault faster and any subsequent flushing possible).
1453 if (!obj_priv
->agp_mem
) {
1454 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1456 drm_gem_object_unreference(obj
);
1457 mutex_unlock(&dev
->struct_mutex
);
1460 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1463 drm_gem_object_unreference(obj
);
1464 mutex_unlock(&dev
->struct_mutex
);
1470 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1472 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1473 int page_count
= obj
->size
/ PAGE_SIZE
;
1476 BUG_ON(obj_priv
->pages_refcount
== 0);
1477 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1479 if (--obj_priv
->pages_refcount
!= 0)
1482 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1483 i915_gem_object_save_bit_17_swizzle(obj
);
1485 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1486 obj_priv
->dirty
= 0;
1488 for (i
= 0; i
< page_count
; i
++) {
1489 if (obj_priv
->pages
[i
] == NULL
)
1492 if (obj_priv
->dirty
)
1493 set_page_dirty(obj_priv
->pages
[i
]);
1495 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1496 mark_page_accessed(obj_priv
->pages
[i
]);
1498 page_cache_release(obj_priv
->pages
[i
]);
1500 obj_priv
->dirty
= 0;
1502 drm_free_large(obj_priv
->pages
);
1503 obj_priv
->pages
= NULL
;
1507 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1509 struct drm_device
*dev
= obj
->dev
;
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1513 /* Add a reference if we're newly entering the active list. */
1514 if (!obj_priv
->active
) {
1515 drm_gem_object_reference(obj
);
1516 obj_priv
->active
= 1;
1518 /* Move from whatever list we were on to the tail of execution. */
1519 spin_lock(&dev_priv
->mm
.active_list_lock
);
1520 list_move_tail(&obj_priv
->list
,
1521 &dev_priv
->mm
.active_list
);
1522 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1523 obj_priv
->last_rendering_seqno
= seqno
;
1527 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1529 struct drm_device
*dev
= obj
->dev
;
1530 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1531 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1533 BUG_ON(!obj_priv
->active
);
1534 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1535 obj_priv
->last_rendering_seqno
= 0;
1538 /* Immediately discard the backing storage */
1540 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1542 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1543 struct inode
*inode
;
1545 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1546 if (inode
->i_op
->truncate
)
1547 inode
->i_op
->truncate (inode
);
1549 obj_priv
->madv
= __I915_MADV_PURGED
;
1553 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1555 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1559 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1561 struct drm_device
*dev
= obj
->dev
;
1562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1563 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1565 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1566 if (obj_priv
->pin_count
!= 0)
1567 list_del_init(&obj_priv
->list
);
1569 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1571 obj_priv
->last_rendering_seqno
= 0;
1572 if (obj_priv
->active
) {
1573 obj_priv
->active
= 0;
1574 drm_gem_object_unreference(obj
);
1576 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1580 * Creates a new sequence number, emitting a write of it to the status page
1581 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1583 * Must be called with struct_lock held.
1585 * Returned sequence numbers are nonzero on success.
1588 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1589 uint32_t flush_domains
)
1591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1592 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1593 struct drm_i915_gem_request
*request
;
1598 if (file_priv
!= NULL
)
1599 i915_file_priv
= file_priv
->driver_priv
;
1601 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1602 if (request
== NULL
)
1605 /* Grab the seqno we're going to make this request be, and bump the
1606 * next (skipping 0 so it can be the reserved no-seqno value).
1608 seqno
= dev_priv
->mm
.next_gem_seqno
;
1609 dev_priv
->mm
.next_gem_seqno
++;
1610 if (dev_priv
->mm
.next_gem_seqno
== 0)
1611 dev_priv
->mm
.next_gem_seqno
++;
1614 OUT_RING(MI_STORE_DWORD_INDEX
);
1615 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1618 OUT_RING(MI_USER_INTERRUPT
);
1621 DRM_DEBUG("%d\n", seqno
);
1623 request
->seqno
= seqno
;
1624 request
->emitted_jiffies
= jiffies
;
1625 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1626 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1627 if (i915_file_priv
) {
1628 list_add_tail(&request
->client_list
,
1629 &i915_file_priv
->mm
.request_list
);
1631 INIT_LIST_HEAD(&request
->client_list
);
1634 /* Associate any objects on the flushing list matching the write
1635 * domain we're flushing with our flush.
1637 if (flush_domains
!= 0) {
1638 struct drm_i915_gem_object
*obj_priv
, *next
;
1640 list_for_each_entry_safe(obj_priv
, next
,
1641 &dev_priv
->mm
.flushing_list
, list
) {
1642 struct drm_gem_object
*obj
= obj_priv
->obj
;
1644 if ((obj
->write_domain
& flush_domains
) ==
1645 obj
->write_domain
) {
1646 uint32_t old_write_domain
= obj
->write_domain
;
1648 obj
->write_domain
= 0;
1649 i915_gem_object_move_to_active(obj
, seqno
);
1651 trace_i915_gem_object_change_domain(obj
,
1659 if (!dev_priv
->mm
.suspended
) {
1660 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1662 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1668 * Command execution barrier
1670 * Ensures that all commands in the ring are finished
1671 * before signalling the CPU
1674 i915_retire_commands(struct drm_device
*dev
)
1676 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1677 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1678 uint32_t flush_domains
= 0;
1681 /* The sampler always gets flushed on i965 (sigh) */
1683 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1686 OUT_RING(0); /* noop */
1688 return flush_domains
;
1692 * Moves buffers associated only with the given active seqno from the active
1693 * to inactive list, potentially freeing them.
1696 i915_gem_retire_request(struct drm_device
*dev
,
1697 struct drm_i915_gem_request
*request
)
1699 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1701 trace_i915_gem_request_retire(dev
, request
->seqno
);
1703 /* Move any buffers on the active list that are no longer referenced
1704 * by the ringbuffer to the flushing/inactive lists as appropriate.
1706 spin_lock(&dev_priv
->mm
.active_list_lock
);
1707 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1708 struct drm_gem_object
*obj
;
1709 struct drm_i915_gem_object
*obj_priv
;
1711 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1712 struct drm_i915_gem_object
,
1714 obj
= obj_priv
->obj
;
1716 /* If the seqno being retired doesn't match the oldest in the
1717 * list, then the oldest in the list must still be newer than
1720 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1724 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1725 __func__
, request
->seqno
, obj
);
1728 if (obj
->write_domain
!= 0)
1729 i915_gem_object_move_to_flushing(obj
);
1731 /* Take a reference on the object so it won't be
1732 * freed while the spinlock is held. The list
1733 * protection for this spinlock is safe when breaking
1734 * the lock like this since the next thing we do
1735 * is just get the head of the list again.
1737 drm_gem_object_reference(obj
);
1738 i915_gem_object_move_to_inactive(obj
);
1739 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1740 drm_gem_object_unreference(obj
);
1741 spin_lock(&dev_priv
->mm
.active_list_lock
);
1745 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1749 * Returns true if seq1 is later than seq2.
1752 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1754 return (int32_t)(seq1
- seq2
) >= 0;
1758 i915_get_gem_seqno(struct drm_device
*dev
)
1760 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1762 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1766 * This function clears the request list as sequence numbers are passed.
1769 i915_gem_retire_requests(struct drm_device
*dev
)
1771 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1774 if (!dev_priv
->hw_status_page
|| list_empty(&dev_priv
->mm
.request_list
))
1777 seqno
= i915_get_gem_seqno(dev
);
1779 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1780 struct drm_i915_gem_request
*request
;
1781 uint32_t retiring_seqno
;
1783 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1784 struct drm_i915_gem_request
,
1786 retiring_seqno
= request
->seqno
;
1788 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1789 atomic_read(&dev_priv
->mm
.wedged
)) {
1790 i915_gem_retire_request(dev
, request
);
1792 list_del(&request
->list
);
1793 list_del(&request
->client_list
);
1799 if (unlikely (dev_priv
->trace_irq_seqno
&&
1800 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1801 i915_user_irq_put(dev
);
1802 dev_priv
->trace_irq_seqno
= 0;
1807 i915_gem_retire_work_handler(struct work_struct
*work
)
1809 drm_i915_private_t
*dev_priv
;
1810 struct drm_device
*dev
;
1812 dev_priv
= container_of(work
, drm_i915_private_t
,
1813 mm
.retire_work
.work
);
1814 dev
= dev_priv
->dev
;
1816 mutex_lock(&dev
->struct_mutex
);
1817 i915_gem_retire_requests(dev
);
1818 if (!dev_priv
->mm
.suspended
&&
1819 !list_empty(&dev_priv
->mm
.request_list
))
1820 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1821 mutex_unlock(&dev
->struct_mutex
);
1825 * Waits for a sequence number to be signaled, and cleans up the
1826 * request and object lists appropriately for that event.
1829 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1831 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1837 if (atomic_read(&dev_priv
->mm
.wedged
))
1840 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1842 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1844 ier
= I915_READ(IER
);
1846 DRM_ERROR("something (likely vbetool) disabled "
1847 "interrupts, re-enabling\n");
1848 i915_driver_irq_preinstall(dev
);
1849 i915_driver_irq_postinstall(dev
);
1852 trace_i915_gem_request_wait_begin(dev
, seqno
);
1854 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1855 i915_user_irq_get(dev
);
1856 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1857 i915_seqno_passed(i915_get_gem_seqno(dev
),
1859 atomic_read(&dev_priv
->mm
.wedged
));
1860 i915_user_irq_put(dev
);
1861 dev_priv
->mm
.waiting_gem_seqno
= 0;
1863 trace_i915_gem_request_wait_end(dev
, seqno
);
1865 if (atomic_read(&dev_priv
->mm
.wedged
))
1868 if (ret
&& ret
!= -ERESTARTSYS
)
1869 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1870 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1872 /* Directly dispatch request retiring. While we have the work queue
1873 * to handle this, the waiter on a request often wants an associated
1874 * buffer to have made it to the inactive list, and we would need
1875 * a separate wait queue to handle that.
1878 i915_gem_retire_requests(dev
);
1884 i915_gem_flush(struct drm_device
*dev
,
1885 uint32_t invalidate_domains
,
1886 uint32_t flush_domains
)
1888 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1893 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1894 invalidate_domains
, flush_domains
);
1896 trace_i915_gem_request_flush(dev
, dev_priv
->mm
.next_gem_seqno
,
1897 invalidate_domains
, flush_domains
);
1899 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1900 drm_agp_chipset_flush(dev
);
1902 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1904 * read/write caches:
1906 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1907 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1908 * also flushed at 2d versus 3d pipeline switches.
1912 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1913 * MI_READ_FLUSH is set, and is always flushed on 965.
1915 * I915_GEM_DOMAIN_COMMAND may not exist?
1917 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1918 * invalidated when MI_EXE_FLUSH is set.
1920 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1921 * invalidated with every MI_FLUSH.
1925 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1926 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1927 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1928 * are flushed at any MI_FLUSH.
1931 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1932 if ((invalidate_domains
|flush_domains
) &
1933 I915_GEM_DOMAIN_RENDER
)
1934 cmd
&= ~MI_NO_WRITE_FLUSH
;
1935 if (!IS_I965G(dev
)) {
1937 * On the 965, the sampler cache always gets flushed
1938 * and this bit is reserved.
1940 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1941 cmd
|= MI_READ_FLUSH
;
1943 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1944 cmd
|= MI_EXE_FLUSH
;
1947 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1951 OUT_RING(0); /* noop */
1957 * Ensures that all rendering to the object has completed and the object is
1958 * safe to unbind from the GTT or access from the CPU.
1961 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1963 struct drm_device
*dev
= obj
->dev
;
1964 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1967 /* This function only exists to support waiting for existing rendering,
1968 * not for emitting required flushes.
1970 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1972 /* If there is rendering queued on the buffer being evicted, wait for
1975 if (obj_priv
->active
) {
1977 DRM_INFO("%s: object %p wait for seqno %08x\n",
1978 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1980 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1989 * Unbinds an object from the GTT aperture.
1992 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1994 struct drm_device
*dev
= obj
->dev
;
1995 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1999 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
2000 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
2002 if (obj_priv
->gtt_space
== NULL
)
2005 if (obj_priv
->pin_count
!= 0) {
2006 DRM_ERROR("Attempting to unbind pinned buffer\n");
2010 /* blow away mappings if mapped through GTT */
2011 i915_gem_release_mmap(obj
);
2013 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2014 i915_gem_clear_fence_reg(obj
);
2016 /* Move the object to the CPU domain to ensure that
2017 * any possible CPU writes while it's not in the GTT
2018 * are flushed when we go to remap it. This will
2019 * also ensure that all pending GPU writes are finished
2022 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2024 if (ret
!= -ERESTARTSYS
)
2025 DRM_ERROR("set_domain failed: %d\n", ret
);
2029 BUG_ON(obj_priv
->active
);
2031 if (obj_priv
->agp_mem
!= NULL
) {
2032 drm_unbind_agp(obj_priv
->agp_mem
);
2033 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2034 obj_priv
->agp_mem
= NULL
;
2037 i915_gem_object_put_pages(obj
);
2038 BUG_ON(obj_priv
->pages_refcount
);
2040 if (obj_priv
->gtt_space
) {
2041 atomic_dec(&dev
->gtt_count
);
2042 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2044 drm_mm_put_block(obj_priv
->gtt_space
);
2045 obj_priv
->gtt_space
= NULL
;
2048 /* Remove ourselves from the LRU list if present. */
2049 if (!list_empty(&obj_priv
->list
))
2050 list_del_init(&obj_priv
->list
);
2052 if (i915_gem_object_is_purgeable(obj_priv
))
2053 i915_gem_object_truncate(obj
);
2055 trace_i915_gem_object_unbind(obj
);
2060 static struct drm_gem_object
*
2061 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2063 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2064 struct drm_i915_gem_object
*obj_priv
;
2065 struct drm_gem_object
*best
= NULL
;
2066 struct drm_gem_object
*first
= NULL
;
2068 /* Try to find the smallest clean object */
2069 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2070 struct drm_gem_object
*obj
= obj_priv
->obj
;
2071 if (obj
->size
>= min_size
) {
2072 if ((!obj_priv
->dirty
||
2073 i915_gem_object_is_purgeable(obj_priv
)) &&
2074 (!best
|| obj
->size
< best
->size
)) {
2076 if (best
->size
== min_size
)
2084 return best
? best
: first
;
2088 i915_gem_evict_everything(struct drm_device
*dev
)
2090 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2095 spin_lock(&dev_priv
->mm
.active_list_lock
);
2096 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2097 list_empty(&dev_priv
->mm
.flushing_list
) &&
2098 list_empty(&dev_priv
->mm
.active_list
));
2099 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2104 /* Flush everything (on to the inactive lists) and evict */
2105 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2106 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
2110 ret
= i915_wait_request(dev
, seqno
);
2114 ret
= i915_gem_evict_from_inactive_list(dev
);
2118 spin_lock(&dev_priv
->mm
.active_list_lock
);
2119 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2120 list_empty(&dev_priv
->mm
.flushing_list
) &&
2121 list_empty(&dev_priv
->mm
.active_list
));
2122 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2123 BUG_ON(!lists_empty
);
2129 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2131 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2132 struct drm_gem_object
*obj
;
2136 i915_gem_retire_requests(dev
);
2138 /* If there's an inactive buffer available now, grab it
2141 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2143 struct drm_i915_gem_object
*obj_priv
;
2146 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2148 obj_priv
= obj
->driver_private
;
2149 BUG_ON(obj_priv
->pin_count
!= 0);
2150 BUG_ON(obj_priv
->active
);
2152 /* Wait on the rendering and unbind the buffer. */
2153 return i915_gem_object_unbind(obj
);
2156 /* If we didn't get anything, but the ring is still processing
2157 * things, wait for the next to finish and hopefully leave us
2158 * a buffer to evict.
2160 if (!list_empty(&dev_priv
->mm
.request_list
)) {
2161 struct drm_i915_gem_request
*request
;
2163 request
= list_first_entry(&dev_priv
->mm
.request_list
,
2164 struct drm_i915_gem_request
,
2167 ret
= i915_wait_request(dev
, request
->seqno
);
2174 /* If we didn't have anything on the request list but there
2175 * are buffers awaiting a flush, emit one and try again.
2176 * When we wait on it, those buffers waiting for that flush
2177 * will get moved to inactive.
2179 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2180 struct drm_i915_gem_object
*obj_priv
;
2182 /* Find an object that we can immediately reuse */
2183 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2184 obj
= obj_priv
->obj
;
2185 if (obj
->size
>= min_size
)
2197 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2201 ret
= i915_wait_request(dev
, seqno
);
2209 /* If we didn't do any of the above, there's no single buffer
2210 * large enough to swap out for the new one, so just evict
2211 * everything and start again. (This should be rare.)
2213 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2214 return i915_gem_evict_from_inactive_list(dev
);
2216 return i915_gem_evict_everything(dev
);
2221 i915_gem_object_get_pages(struct drm_gem_object
*obj
)
2223 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2225 struct address_space
*mapping
;
2226 struct inode
*inode
;
2230 if (obj_priv
->pages_refcount
++ != 0)
2233 /* Get the list of pages out of our struct file. They'll be pinned
2234 * at this point until we release them.
2236 page_count
= obj
->size
/ PAGE_SIZE
;
2237 BUG_ON(obj_priv
->pages
!= NULL
);
2238 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2239 if (obj_priv
->pages
== NULL
) {
2240 obj_priv
->pages_refcount
--;
2244 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2245 mapping
= inode
->i_mapping
;
2246 for (i
= 0; i
< page_count
; i
++) {
2247 page
= read_mapping_page(mapping
, i
, NULL
);
2249 ret
= PTR_ERR(page
);
2250 i915_gem_object_put_pages(obj
);
2253 obj_priv
->pages
[i
] = page
;
2256 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2257 i915_gem_object_do_bit_17_swizzle(obj
);
2262 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2264 struct drm_gem_object
*obj
= reg
->obj
;
2265 struct drm_device
*dev
= obj
->dev
;
2266 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2267 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2268 int regnum
= obj_priv
->fence_reg
;
2271 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2273 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2274 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2275 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2276 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2277 val
|= I965_FENCE_REG_VALID
;
2279 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2282 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2284 struct drm_gem_object
*obj
= reg
->obj
;
2285 struct drm_device
*dev
= obj
->dev
;
2286 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2287 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2288 int regnum
= obj_priv
->fence_reg
;
2290 uint32_t fence_reg
, val
;
2293 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2294 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2295 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2296 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2300 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2301 HAS_128_BYTE_Y_TILING(dev
))
2306 /* Note: pitch better be a power of two tile widths */
2307 pitch_val
= obj_priv
->stride
/ tile_width
;
2308 pitch_val
= ffs(pitch_val
) - 1;
2310 val
= obj_priv
->gtt_offset
;
2311 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2312 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2313 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2314 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2315 val
|= I830_FENCE_REG_VALID
;
2318 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2320 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2321 I915_WRITE(fence_reg
, val
);
2324 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2326 struct drm_gem_object
*obj
= reg
->obj
;
2327 struct drm_device
*dev
= obj
->dev
;
2328 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2329 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2330 int regnum
= obj_priv
->fence_reg
;
2333 uint32_t fence_size_bits
;
2335 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2336 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2337 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2338 __func__
, obj_priv
->gtt_offset
);
2342 pitch_val
= obj_priv
->stride
/ 128;
2343 pitch_val
= ffs(pitch_val
) - 1;
2344 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2346 val
= obj_priv
->gtt_offset
;
2347 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2348 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2349 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2350 WARN_ON(fence_size_bits
& ~0x00000f00);
2351 val
|= fence_size_bits
;
2352 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2353 val
|= I830_FENCE_REG_VALID
;
2355 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2359 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2360 * @obj: object to map through a fence reg
2362 * When mapping objects through the GTT, userspace wants to be able to write
2363 * to them without having to worry about swizzling if the object is tiled.
2365 * This function walks the fence regs looking for a free one for @obj,
2366 * stealing one if it can't find any.
2368 * It then sets up the reg based on the object's properties: address, pitch
2369 * and tiling format.
2372 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2374 struct drm_device
*dev
= obj
->dev
;
2375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2376 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2377 struct drm_i915_fence_reg
*reg
= NULL
;
2378 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2381 /* Just update our place in the LRU if our fence is getting used. */
2382 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2383 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2387 switch (obj_priv
->tiling_mode
) {
2388 case I915_TILING_NONE
:
2389 WARN(1, "allocating a fence for non-tiled object?\n");
2392 if (!obj_priv
->stride
)
2394 WARN((obj_priv
->stride
& (512 - 1)),
2395 "object 0x%08x is X tiled but has non-512B pitch\n",
2396 obj_priv
->gtt_offset
);
2399 if (!obj_priv
->stride
)
2401 WARN((obj_priv
->stride
& (128 - 1)),
2402 "object 0x%08x is Y tiled but has non-128B pitch\n",
2403 obj_priv
->gtt_offset
);
2407 /* First try to find a free reg */
2409 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2410 reg
= &dev_priv
->fence_regs
[i
];
2414 old_obj_priv
= reg
->obj
->driver_private
;
2415 if (!old_obj_priv
->pin_count
)
2419 /* None available, try to steal one or wait for a user to finish */
2420 if (i
== dev_priv
->num_fence_regs
) {
2421 struct drm_gem_object
*old_obj
= NULL
;
2426 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2428 old_obj
= old_obj_priv
->obj
;
2430 if (old_obj_priv
->pin_count
)
2433 /* Take a reference, as otherwise the wait_rendering
2434 * below may cause the object to get freed out from
2437 drm_gem_object_reference(old_obj
);
2439 /* i915 uses fences for GPU access to tiled buffers */
2440 if (IS_I965G(dev
) || !old_obj_priv
->active
)
2443 /* This brings the object to the head of the LRU if it
2444 * had been written to. The only way this should
2445 * result in us waiting longer than the expected
2446 * optimal amount of time is if there was a
2447 * fence-using buffer later that was read-only.
2449 i915_gem_object_flush_gpu_write_domain(old_obj
);
2450 ret
= i915_gem_object_wait_rendering(old_obj
);
2452 drm_gem_object_unreference(old_obj
);
2460 * Zap this virtual mapping so we can set up a fence again
2461 * for this object next time we need it.
2463 i915_gem_release_mmap(old_obj
);
2465 i
= old_obj_priv
->fence_reg
;
2466 reg
= &dev_priv
->fence_regs
[i
];
2468 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2469 list_del_init(&old_obj_priv
->fence_list
);
2471 drm_gem_object_unreference(old_obj
);
2474 obj_priv
->fence_reg
= i
;
2475 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2480 i965_write_fence_reg(reg
);
2481 else if (IS_I9XX(dev
))
2482 i915_write_fence_reg(reg
);
2484 i830_write_fence_reg(reg
);
2486 trace_i915_gem_object_get_fence(obj
, i
, obj_priv
->tiling_mode
);
2492 * i915_gem_clear_fence_reg - clear out fence register info
2493 * @obj: object to clear
2495 * Zeroes out the fence register itself and clears out the associated
2496 * data structures in dev_priv and obj_priv.
2499 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2501 struct drm_device
*dev
= obj
->dev
;
2502 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2503 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2506 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2510 if (obj_priv
->fence_reg
< 8)
2511 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2513 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2516 I915_WRITE(fence_reg
, 0);
2519 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2520 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2521 list_del_init(&obj_priv
->fence_list
);
2525 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2526 * to the buffer to finish, and then resets the fence register.
2527 * @obj: tiled object holding a fence register.
2529 * Zeroes out the fence register itself and clears out the associated
2530 * data structures in dev_priv and obj_priv.
2533 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2535 struct drm_device
*dev
= obj
->dev
;
2536 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2538 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2541 /* On the i915, GPU access to tiled buffers is via a fence,
2542 * therefore we must wait for any outstanding access to complete
2543 * before clearing the fence.
2545 if (!IS_I965G(dev
)) {
2548 i915_gem_object_flush_gpu_write_domain(obj
);
2549 i915_gem_object_flush_gtt_write_domain(obj
);
2550 ret
= i915_gem_object_wait_rendering(obj
);
2555 i915_gem_clear_fence_reg (obj
);
2561 * Finds free space in the GTT aperture and binds the object there.
2564 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2566 struct drm_device
*dev
= obj
->dev
;
2567 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2568 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2569 struct drm_mm_node
*free_space
;
2570 bool retry_alloc
= false;
2573 if (dev_priv
->mm
.suspended
)
2576 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2577 DRM_ERROR("Attempting to bind a purgeable object\n");
2582 alignment
= i915_gem_get_gtt_alignment(obj
);
2583 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2584 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2589 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2590 obj
->size
, alignment
, 0);
2591 if (free_space
!= NULL
) {
2592 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2594 if (obj_priv
->gtt_space
!= NULL
) {
2595 obj_priv
->gtt_space
->private = obj
;
2596 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2599 if (obj_priv
->gtt_space
== NULL
) {
2600 /* If the gtt is empty and we're still having trouble
2601 * fitting our object in, we're out of memory.
2604 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2606 ret
= i915_gem_evict_something(dev
, obj
->size
);
2614 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2615 obj
->size
, obj_priv
->gtt_offset
);
2618 i915_gem_object_set_page_gfp_mask (obj
,
2619 i915_gem_object_get_page_gfp_mask (obj
) & ~__GFP_NORETRY
);
2621 ret
= i915_gem_object_get_pages(obj
);
2623 i915_gem_object_set_page_gfp_mask (obj
,
2624 i915_gem_object_get_page_gfp_mask (obj
) | __GFP_NORETRY
);
2627 drm_mm_put_block(obj_priv
->gtt_space
);
2628 obj_priv
->gtt_space
= NULL
;
2630 if (ret
== -ENOMEM
) {
2631 /* first try to clear up some space from the GTT */
2632 ret
= i915_gem_evict_something(dev
, obj
->size
);
2634 /* now try to shrink everyone else */
2635 if (! retry_alloc
) {
2649 /* Create an AGP memory structure pointing at our pages, and bind it
2652 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2654 obj
->size
>> PAGE_SHIFT
,
2655 obj_priv
->gtt_offset
,
2656 obj_priv
->agp_type
);
2657 if (obj_priv
->agp_mem
== NULL
) {
2658 i915_gem_object_put_pages(obj
);
2659 drm_mm_put_block(obj_priv
->gtt_space
);
2660 obj_priv
->gtt_space
= NULL
;
2662 ret
= i915_gem_evict_something(dev
, obj
->size
);
2668 atomic_inc(&dev
->gtt_count
);
2669 atomic_add(obj
->size
, &dev
->gtt_memory
);
2671 /* Assert that the object is not currently in any GPU domain. As it
2672 * wasn't in the GTT, there shouldn't be any way it could have been in
2675 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2676 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2678 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2684 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2686 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2688 /* If we don't have a page list set up, then we're not pinned
2689 * to GPU, and we can ignore the cache flush because it'll happen
2690 * again at bind time.
2692 if (obj_priv
->pages
== NULL
)
2695 trace_i915_gem_object_clflush(obj
);
2697 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2700 /** Flushes any GPU write domain for the object if it's dirty. */
2702 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2704 struct drm_device
*dev
= obj
->dev
;
2706 uint32_t old_write_domain
;
2708 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2711 /* Queue the GPU write cache flushing we need. */
2712 old_write_domain
= obj
->write_domain
;
2713 i915_gem_flush(dev
, 0, obj
->write_domain
);
2714 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2715 obj
->write_domain
= 0;
2716 i915_gem_object_move_to_active(obj
, seqno
);
2718 trace_i915_gem_object_change_domain(obj
,
2723 /** Flushes the GTT write domain for the object if it's dirty. */
2725 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2727 uint32_t old_write_domain
;
2729 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2732 /* No actual flushing is required for the GTT write domain. Writes
2733 * to it immediately go to main memory as far as we know, so there's
2734 * no chipset flush. It also doesn't land in render cache.
2736 old_write_domain
= obj
->write_domain
;
2737 obj
->write_domain
= 0;
2739 trace_i915_gem_object_change_domain(obj
,
2744 /** Flushes the CPU write domain for the object if it's dirty. */
2746 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2748 struct drm_device
*dev
= obj
->dev
;
2749 uint32_t old_write_domain
;
2751 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2754 i915_gem_clflush_object(obj
);
2755 drm_agp_chipset_flush(dev
);
2756 old_write_domain
= obj
->write_domain
;
2757 obj
->write_domain
= 0;
2759 trace_i915_gem_object_change_domain(obj
,
2765 * Moves a single object to the GTT read, and possibly write domain.
2767 * This function returns when the move is complete, including waiting on
2771 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2773 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2774 uint32_t old_write_domain
, old_read_domains
;
2777 /* Not valid to be called on unbound objects. */
2778 if (obj_priv
->gtt_space
== NULL
)
2781 i915_gem_object_flush_gpu_write_domain(obj
);
2782 /* Wait on any GPU rendering and flushing to occur. */
2783 ret
= i915_gem_object_wait_rendering(obj
);
2787 old_write_domain
= obj
->write_domain
;
2788 old_read_domains
= obj
->read_domains
;
2790 /* If we're writing through the GTT domain, then CPU and GPU caches
2791 * will need to be invalidated at next use.
2794 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2796 i915_gem_object_flush_cpu_write_domain(obj
);
2798 /* It should now be out of any other write domains, and we can update
2799 * the domain values for our changes.
2801 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2802 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2804 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2805 obj_priv
->dirty
= 1;
2808 trace_i915_gem_object_change_domain(obj
,
2816 * Moves a single object to the CPU read, and possibly write domain.
2818 * This function returns when the move is complete, including waiting on
2822 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2824 uint32_t old_write_domain
, old_read_domains
;
2827 i915_gem_object_flush_gpu_write_domain(obj
);
2828 /* Wait on any GPU rendering and flushing to occur. */
2829 ret
= i915_gem_object_wait_rendering(obj
);
2833 i915_gem_object_flush_gtt_write_domain(obj
);
2835 /* If we have a partially-valid cache of the object in the CPU,
2836 * finish invalidating it and free the per-page flags.
2838 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2840 old_write_domain
= obj
->write_domain
;
2841 old_read_domains
= obj
->read_domains
;
2843 /* Flush the CPU cache if it's still invalid. */
2844 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2845 i915_gem_clflush_object(obj
);
2847 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2850 /* It should now be out of any other write domains, and we can update
2851 * the domain values for our changes.
2853 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2855 /* If we're writing through the CPU, then the GPU read domains will
2856 * need to be invalidated at next use.
2859 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2860 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2863 trace_i915_gem_object_change_domain(obj
,
2871 * Set the next domain for the specified object. This
2872 * may not actually perform the necessary flushing/invaliding though,
2873 * as that may want to be batched with other set_domain operations
2875 * This is (we hope) the only really tricky part of gem. The goal
2876 * is fairly simple -- track which caches hold bits of the object
2877 * and make sure they remain coherent. A few concrete examples may
2878 * help to explain how it works. For shorthand, we use the notation
2879 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2880 * a pair of read and write domain masks.
2882 * Case 1: the batch buffer
2888 * 5. Unmapped from GTT
2891 * Let's take these a step at a time
2894 * Pages allocated from the kernel may still have
2895 * cache contents, so we set them to (CPU, CPU) always.
2896 * 2. Written by CPU (using pwrite)
2897 * The pwrite function calls set_domain (CPU, CPU) and
2898 * this function does nothing (as nothing changes)
2900 * This function asserts that the object is not
2901 * currently in any GPU-based read or write domains
2903 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2904 * As write_domain is zero, this function adds in the
2905 * current read domains (CPU+COMMAND, 0).
2906 * flush_domains is set to CPU.
2907 * invalidate_domains is set to COMMAND
2908 * clflush is run to get data out of the CPU caches
2909 * then i915_dev_set_domain calls i915_gem_flush to
2910 * emit an MI_FLUSH and drm_agp_chipset_flush
2911 * 5. Unmapped from GTT
2912 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2913 * flush_domains and invalidate_domains end up both zero
2914 * so no flushing/invalidating happens
2918 * Case 2: The shared render buffer
2922 * 3. Read/written by GPU
2923 * 4. set_domain to (CPU,CPU)
2924 * 5. Read/written by CPU
2925 * 6. Read/written by GPU
2928 * Same as last example, (CPU, CPU)
2930 * Nothing changes (assertions find that it is not in the GPU)
2931 * 3. Read/written by GPU
2932 * execbuffer calls set_domain (RENDER, RENDER)
2933 * flush_domains gets CPU
2934 * invalidate_domains gets GPU
2936 * MI_FLUSH and drm_agp_chipset_flush
2937 * 4. set_domain (CPU, CPU)
2938 * flush_domains gets GPU
2939 * invalidate_domains gets CPU
2940 * wait_rendering (obj) to make sure all drawing is complete.
2941 * This will include an MI_FLUSH to get the data from GPU
2943 * clflush (obj) to invalidate the CPU cache
2944 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2945 * 5. Read/written by CPU
2946 * cache lines are loaded and dirtied
2947 * 6. Read written by GPU
2948 * Same as last GPU access
2950 * Case 3: The constant buffer
2955 * 4. Updated (written) by CPU again
2964 * flush_domains = CPU
2965 * invalidate_domains = RENDER
2968 * drm_agp_chipset_flush
2969 * 4. Updated (written) by CPU again
2971 * flush_domains = 0 (no previous write domain)
2972 * invalidate_domains = 0 (no new read domains)
2975 * flush_domains = CPU
2976 * invalidate_domains = RENDER
2979 * drm_agp_chipset_flush
2982 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2984 struct drm_device
*dev
= obj
->dev
;
2985 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2986 uint32_t invalidate_domains
= 0;
2987 uint32_t flush_domains
= 0;
2988 uint32_t old_read_domains
;
2990 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2991 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2993 intel_mark_busy(dev
, obj
);
2996 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2998 obj
->read_domains
, obj
->pending_read_domains
,
2999 obj
->write_domain
, obj
->pending_write_domain
);
3002 * If the object isn't moving to a new write domain,
3003 * let the object stay in multiple read domains
3005 if (obj
->pending_write_domain
== 0)
3006 obj
->pending_read_domains
|= obj
->read_domains
;
3008 obj_priv
->dirty
= 1;
3011 * Flush the current write domain if
3012 * the new read domains don't match. Invalidate
3013 * any read domains which differ from the old
3016 if (obj
->write_domain
&&
3017 obj
->write_domain
!= obj
->pending_read_domains
) {
3018 flush_domains
|= obj
->write_domain
;
3019 invalidate_domains
|=
3020 obj
->pending_read_domains
& ~obj
->write_domain
;
3023 * Invalidate any read caches which may have
3024 * stale data. That is, any new read domains.
3026 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3027 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3029 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3030 __func__
, flush_domains
, invalidate_domains
);
3032 i915_gem_clflush_object(obj
);
3035 old_read_domains
= obj
->read_domains
;
3037 /* The actual obj->write_domain will be updated with
3038 * pending_write_domain after we emit the accumulated flush for all
3039 * of our domain changes in execbuffers (which clears objects'
3040 * write_domains). So if we have a current write domain that we
3041 * aren't changing, set pending_write_domain to that.
3043 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3044 obj
->pending_write_domain
= obj
->write_domain
;
3045 obj
->read_domains
= obj
->pending_read_domains
;
3047 dev
->invalidate_domains
|= invalidate_domains
;
3048 dev
->flush_domains
|= flush_domains
;
3050 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3052 obj
->read_domains
, obj
->write_domain
,
3053 dev
->invalidate_domains
, dev
->flush_domains
);
3056 trace_i915_gem_object_change_domain(obj
,
3062 * Moves the object from a partially CPU read to a full one.
3064 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3065 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3068 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3070 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3072 if (!obj_priv
->page_cpu_valid
)
3075 /* If we're partially in the CPU read domain, finish moving it in.
3077 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3080 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3081 if (obj_priv
->page_cpu_valid
[i
])
3083 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3087 /* Free the page_cpu_valid mappings which are now stale, whether
3088 * or not we've got I915_GEM_DOMAIN_CPU.
3090 kfree(obj_priv
->page_cpu_valid
);
3091 obj_priv
->page_cpu_valid
= NULL
;
3095 * Set the CPU read domain on a range of the object.
3097 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3098 * not entirely valid. The page_cpu_valid member of the object flags which
3099 * pages have been flushed, and will be respected by
3100 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3101 * of the whole object.
3103 * This function returns when the move is complete, including waiting on
3107 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3108 uint64_t offset
, uint64_t size
)
3110 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3111 uint32_t old_read_domains
;
3114 if (offset
== 0 && size
== obj
->size
)
3115 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3117 i915_gem_object_flush_gpu_write_domain(obj
);
3118 /* Wait on any GPU rendering and flushing to occur. */
3119 ret
= i915_gem_object_wait_rendering(obj
);
3122 i915_gem_object_flush_gtt_write_domain(obj
);
3124 /* If we're already fully in the CPU read domain, we're done. */
3125 if (obj_priv
->page_cpu_valid
== NULL
&&
3126 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3129 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3130 * newly adding I915_GEM_DOMAIN_CPU
3132 if (obj_priv
->page_cpu_valid
== NULL
) {
3133 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3135 if (obj_priv
->page_cpu_valid
== NULL
)
3137 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3138 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3140 /* Flush the cache on any pages that are still invalid from the CPU's
3143 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3145 if (obj_priv
->page_cpu_valid
[i
])
3148 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3150 obj_priv
->page_cpu_valid
[i
] = 1;
3153 /* It should now be out of any other write domains, and we can update
3154 * the domain values for our changes.
3156 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3158 old_read_domains
= obj
->read_domains
;
3159 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3161 trace_i915_gem_object_change_domain(obj
,
3169 * Pin an object to the GTT and evaluate the relocations landing in it.
3172 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3173 struct drm_file
*file_priv
,
3174 struct drm_i915_gem_exec_object
*entry
,
3175 struct drm_i915_gem_relocation_entry
*relocs
)
3177 struct drm_device
*dev
= obj
->dev
;
3178 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3179 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3181 void __iomem
*reloc_page
;
3183 /* Choose the GTT offset for our buffer and put it there. */
3184 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3188 entry
->offset
= obj_priv
->gtt_offset
;
3190 /* Apply the relocations, using the GTT aperture to avoid cache
3191 * flushing requirements.
3193 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3194 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3195 struct drm_gem_object
*target_obj
;
3196 struct drm_i915_gem_object
*target_obj_priv
;
3197 uint32_t reloc_val
, reloc_offset
;
3198 uint32_t __iomem
*reloc_entry
;
3200 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3201 reloc
->target_handle
);
3202 if (target_obj
== NULL
) {
3203 i915_gem_object_unpin(obj
);
3206 target_obj_priv
= target_obj
->driver_private
;
3209 DRM_INFO("%s: obj %p offset %08x target %d "
3210 "read %08x write %08x gtt %08x "
3211 "presumed %08x delta %08x\n",
3214 (int) reloc
->offset
,
3215 (int) reloc
->target_handle
,
3216 (int) reloc
->read_domains
,
3217 (int) reloc
->write_domain
,
3218 (int) target_obj_priv
->gtt_offset
,
3219 (int) reloc
->presumed_offset
,
3223 /* The target buffer should have appeared before us in the
3224 * exec_object list, so it should have a GTT space bound by now.
3226 if (target_obj_priv
->gtt_space
== NULL
) {
3227 DRM_ERROR("No GTT space found for object %d\n",
3228 reloc
->target_handle
);
3229 drm_gem_object_unreference(target_obj
);
3230 i915_gem_object_unpin(obj
);
3234 /* Validate that the target is in a valid r/w GPU domain */
3235 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3236 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3237 DRM_ERROR("reloc with read/write CPU domains: "
3238 "obj %p target %d offset %d "
3239 "read %08x write %08x",
3240 obj
, reloc
->target_handle
,
3241 (int) reloc
->offset
,
3242 reloc
->read_domains
,
3243 reloc
->write_domain
);
3244 drm_gem_object_unreference(target_obj
);
3245 i915_gem_object_unpin(obj
);
3248 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3249 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3250 DRM_ERROR("Write domain conflict: "
3251 "obj %p target %d offset %d "
3252 "new %08x old %08x\n",
3253 obj
, reloc
->target_handle
,
3254 (int) reloc
->offset
,
3255 reloc
->write_domain
,
3256 target_obj
->pending_write_domain
);
3257 drm_gem_object_unreference(target_obj
);
3258 i915_gem_object_unpin(obj
);
3262 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3263 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3265 /* If the relocation already has the right value in it, no
3266 * more work needs to be done.
3268 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3269 drm_gem_object_unreference(target_obj
);
3273 /* Check that the relocation address is valid... */
3274 if (reloc
->offset
> obj
->size
- 4) {
3275 DRM_ERROR("Relocation beyond object bounds: "
3276 "obj %p target %d offset %d size %d.\n",
3277 obj
, reloc
->target_handle
,
3278 (int) reloc
->offset
, (int) obj
->size
);
3279 drm_gem_object_unreference(target_obj
);
3280 i915_gem_object_unpin(obj
);
3283 if (reloc
->offset
& 3) {
3284 DRM_ERROR("Relocation not 4-byte aligned: "
3285 "obj %p target %d offset %d.\n",
3286 obj
, reloc
->target_handle
,
3287 (int) reloc
->offset
);
3288 drm_gem_object_unreference(target_obj
);
3289 i915_gem_object_unpin(obj
);
3293 /* and points to somewhere within the target object. */
3294 if (reloc
->delta
>= target_obj
->size
) {
3295 DRM_ERROR("Relocation beyond target object bounds: "
3296 "obj %p target %d delta %d size %d.\n",
3297 obj
, reloc
->target_handle
,
3298 (int) reloc
->delta
, (int) target_obj
->size
);
3299 drm_gem_object_unreference(target_obj
);
3300 i915_gem_object_unpin(obj
);
3304 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3306 drm_gem_object_unreference(target_obj
);
3307 i915_gem_object_unpin(obj
);
3311 /* Map the page containing the relocation we're going to
3314 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3315 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3318 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3319 (reloc_offset
& (PAGE_SIZE
- 1)));
3320 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3323 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3324 obj
, (unsigned int) reloc
->offset
,
3325 readl(reloc_entry
), reloc_val
);
3327 writel(reloc_val
, reloc_entry
);
3328 io_mapping_unmap_atomic(reloc_page
);
3330 /* The updated presumed offset for this entry will be
3331 * copied back out to the user.
3333 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3335 drm_gem_object_unreference(target_obj
);
3340 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3345 /** Dispatch a batchbuffer to the ring
3348 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3349 struct drm_i915_gem_execbuffer
*exec
,
3350 struct drm_clip_rect
*cliprects
,
3351 uint64_t exec_offset
)
3353 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3354 int nbox
= exec
->num_cliprects
;
3356 uint32_t exec_start
, exec_len
;
3359 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3360 exec_len
= (uint32_t) exec
->batch_len
;
3362 trace_i915_gem_request_submit(dev
, dev_priv
->mm
.next_gem_seqno
+ 1);
3364 count
= nbox
? nbox
: 1;
3366 for (i
= 0; i
< count
; i
++) {
3368 int ret
= i915_emit_box(dev
, cliprects
, i
,
3369 exec
->DR1
, exec
->DR4
);
3374 if (IS_I830(dev
) || IS_845G(dev
)) {
3376 OUT_RING(MI_BATCH_BUFFER
);
3377 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3378 OUT_RING(exec_start
+ exec_len
- 4);
3383 if (IS_I965G(dev
)) {
3384 OUT_RING(MI_BATCH_BUFFER_START
|
3386 MI_BATCH_NON_SECURE_I965
);
3387 OUT_RING(exec_start
);
3389 OUT_RING(MI_BATCH_BUFFER_START
|
3391 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3397 /* XXX breadcrumb */
3401 /* Throttle our rendering by waiting until the ring has completed our requests
3402 * emitted over 20 msec ago.
3404 * Note that if we were to use the current jiffies each time around the loop,
3405 * we wouldn't escape the function with any frames outstanding if the time to
3406 * render a frame was over 20ms.
3408 * This should get us reasonable parallelism between CPU and GPU but also
3409 * relatively low latency when blocking on a particular request to finish.
3412 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3414 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3416 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3418 mutex_lock(&dev
->struct_mutex
);
3419 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3420 struct drm_i915_gem_request
*request
;
3422 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3423 struct drm_i915_gem_request
,
3426 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3429 ret
= i915_wait_request(dev
, request
->seqno
);
3433 mutex_unlock(&dev
->struct_mutex
);
3439 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object
*exec_list
,
3440 uint32_t buffer_count
,
3441 struct drm_i915_gem_relocation_entry
**relocs
)
3443 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3447 for (i
= 0; i
< buffer_count
; i
++) {
3448 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3450 reloc_count
+= exec_list
[i
].relocation_count
;
3453 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3454 if (*relocs
== NULL
)
3457 for (i
= 0; i
< buffer_count
; i
++) {
3458 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3460 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3462 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3464 exec_list
[i
].relocation_count
*
3467 drm_free_large(*relocs
);
3472 reloc_index
+= exec_list
[i
].relocation_count
;
3479 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object
*exec_list
,
3480 uint32_t buffer_count
,
3481 struct drm_i915_gem_relocation_entry
*relocs
)
3483 uint32_t reloc_count
= 0, i
;
3486 for (i
= 0; i
< buffer_count
; i
++) {
3487 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3490 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3492 unwritten
= copy_to_user(user_relocs
,
3493 &relocs
[reloc_count
],
3494 exec_list
[i
].relocation_count
*
3502 reloc_count
+= exec_list
[i
].relocation_count
;
3506 drm_free_large(relocs
);
3512 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer
*exec
,
3513 uint64_t exec_offset
)
3515 uint32_t exec_start
, exec_len
;
3517 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3518 exec_len
= (uint32_t) exec
->batch_len
;
3520 if ((exec_start
| exec_len
) & 0x7)
3530 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3531 struct drm_file
*file_priv
)
3533 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3534 struct drm_i915_gem_execbuffer
*args
= data
;
3535 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3536 struct drm_gem_object
**object_list
= NULL
;
3537 struct drm_gem_object
*batch_obj
;
3538 struct drm_i915_gem_object
*obj_priv
;
3539 struct drm_clip_rect
*cliprects
= NULL
;
3540 struct drm_i915_gem_relocation_entry
*relocs
;
3541 int ret
, ret2
, i
, pinned
= 0;
3542 uint64_t exec_offset
;
3543 uint32_t seqno
, flush_domains
, reloc_index
;
3547 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3548 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3551 if (args
->buffer_count
< 1) {
3552 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3555 /* Copy in the exec list from userland */
3556 exec_list
= drm_calloc_large(sizeof(*exec_list
), args
->buffer_count
);
3557 object_list
= drm_calloc_large(sizeof(*object_list
), args
->buffer_count
);
3558 if (exec_list
== NULL
|| object_list
== NULL
) {
3559 DRM_ERROR("Failed to allocate exec or object list "
3561 args
->buffer_count
);
3565 ret
= copy_from_user(exec_list
,
3566 (struct drm_i915_relocation_entry __user
*)
3567 (uintptr_t) args
->buffers_ptr
,
3568 sizeof(*exec_list
) * args
->buffer_count
);
3570 DRM_ERROR("copy %d exec entries failed %d\n",
3571 args
->buffer_count
, ret
);
3575 if (args
->num_cliprects
!= 0) {
3576 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3578 if (cliprects
== NULL
)
3581 ret
= copy_from_user(cliprects
,
3582 (struct drm_clip_rect __user
*)
3583 (uintptr_t) args
->cliprects_ptr
,
3584 sizeof(*cliprects
) * args
->num_cliprects
);
3586 DRM_ERROR("copy %d cliprects failed: %d\n",
3587 args
->num_cliprects
, ret
);
3592 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3597 mutex_lock(&dev
->struct_mutex
);
3599 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3601 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3602 DRM_ERROR("Execbuf while wedged\n");
3603 mutex_unlock(&dev
->struct_mutex
);
3608 if (dev_priv
->mm
.suspended
) {
3609 DRM_ERROR("Execbuf while VT-switched.\n");
3610 mutex_unlock(&dev
->struct_mutex
);
3615 /* Look up object handles */
3616 for (i
= 0; i
< args
->buffer_count
; i
++) {
3617 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3618 exec_list
[i
].handle
);
3619 if (object_list
[i
] == NULL
) {
3620 DRM_ERROR("Invalid object handle %d at index %d\n",
3621 exec_list
[i
].handle
, i
);
3626 obj_priv
= object_list
[i
]->driver_private
;
3627 if (obj_priv
->in_execbuffer
) {
3628 DRM_ERROR("Object %p appears more than once in object list\n",
3633 obj_priv
->in_execbuffer
= true;
3636 /* Pin and relocate */
3637 for (pin_tries
= 0; ; pin_tries
++) {
3641 for (i
= 0; i
< args
->buffer_count
; i
++) {
3642 object_list
[i
]->pending_read_domains
= 0;
3643 object_list
[i
]->pending_write_domain
= 0;
3644 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3647 &relocs
[reloc_index
]);
3651 reloc_index
+= exec_list
[i
].relocation_count
;
3657 /* error other than GTT full, or we've already tried again */
3658 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3659 if (ret
!= -ERESTARTSYS
) {
3660 unsigned long long total_size
= 0;
3661 for (i
= 0; i
< args
->buffer_count
; i
++)
3662 total_size
+= object_list
[i
]->size
;
3663 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3664 pinned
+1, args
->buffer_count
,
3666 DRM_ERROR("%d objects [%d pinned], "
3667 "%d object bytes [%d pinned], "
3668 "%d/%d gtt bytes\n",
3669 atomic_read(&dev
->object_count
),
3670 atomic_read(&dev
->pin_count
),
3671 atomic_read(&dev
->object_memory
),
3672 atomic_read(&dev
->pin_memory
),
3673 atomic_read(&dev
->gtt_memory
),
3679 /* unpin all of our buffers */
3680 for (i
= 0; i
< pinned
; i
++)
3681 i915_gem_object_unpin(object_list
[i
]);
3684 /* evict everyone we can from the aperture */
3685 ret
= i915_gem_evict_everything(dev
);
3686 if (ret
&& ret
!= -ENOSPC
)
3690 /* Set the pending read domains for the batch buffer to COMMAND */
3691 batch_obj
= object_list
[args
->buffer_count
-1];
3692 if (batch_obj
->pending_write_domain
) {
3693 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3697 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3699 /* Sanity check the batch buffer, prior to moving objects */
3700 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3701 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3703 DRM_ERROR("execbuf with invalid offset/length\n");
3707 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3709 /* Zero the global flush/invalidate flags. These
3710 * will be modified as new domains are computed
3713 dev
->invalidate_domains
= 0;
3714 dev
->flush_domains
= 0;
3716 for (i
= 0; i
< args
->buffer_count
; i
++) {
3717 struct drm_gem_object
*obj
= object_list
[i
];
3719 /* Compute new gpu domains and update invalidate/flush */
3720 i915_gem_object_set_to_gpu_domain(obj
);
3723 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3725 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3727 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3729 dev
->invalidate_domains
,
3730 dev
->flush_domains
);
3733 dev
->invalidate_domains
,
3734 dev
->flush_domains
);
3735 if (dev
->flush_domains
)
3736 (void)i915_add_request(dev
, file_priv
,
3737 dev
->flush_domains
);
3740 for (i
= 0; i
< args
->buffer_count
; i
++) {
3741 struct drm_gem_object
*obj
= object_list
[i
];
3742 uint32_t old_write_domain
= obj
->write_domain
;
3744 obj
->write_domain
= obj
->pending_write_domain
;
3745 trace_i915_gem_object_change_domain(obj
,
3750 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3753 for (i
= 0; i
< args
->buffer_count
; i
++) {
3754 i915_gem_object_check_coherency(object_list
[i
],
3755 exec_list
[i
].handle
);
3760 i915_gem_dump_object(batch_obj
,
3766 /* Exec the batchbuffer */
3767 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3769 DRM_ERROR("dispatch failed %d\n", ret
);
3774 * Ensure that the commands in the batch buffer are
3775 * finished before the interrupt fires
3777 flush_domains
= i915_retire_commands(dev
);
3779 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3782 * Get a seqno representing the execution of the current buffer,
3783 * which we can wait on. We would like to mitigate these interrupts,
3784 * likely by only creating seqnos occasionally (so that we have
3785 * *some* interrupts representing completion of buffers that we can
3786 * wait on when trying to clear up gtt space).
3788 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3790 for (i
= 0; i
< args
->buffer_count
; i
++) {
3791 struct drm_gem_object
*obj
= object_list
[i
];
3793 i915_gem_object_move_to_active(obj
, seqno
);
3795 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3799 i915_dump_lru(dev
, __func__
);
3802 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3805 for (i
= 0; i
< pinned
; i
++)
3806 i915_gem_object_unpin(object_list
[i
]);
3808 for (i
= 0; i
< args
->buffer_count
; i
++) {
3809 if (object_list
[i
]) {
3810 obj_priv
= object_list
[i
]->driver_private
;
3811 obj_priv
->in_execbuffer
= false;
3813 drm_gem_object_unreference(object_list
[i
]);
3816 mutex_unlock(&dev
->struct_mutex
);
3819 /* Copy the new buffer offsets back to the user's exec list. */
3820 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3821 (uintptr_t) args
->buffers_ptr
,
3823 sizeof(*exec_list
) * args
->buffer_count
);
3826 DRM_ERROR("failed to copy %d exec entries "
3827 "back to user (%d)\n",
3828 args
->buffer_count
, ret
);
3832 /* Copy the updated relocations out regardless of current error
3833 * state. Failure to update the relocs would mean that the next
3834 * time userland calls execbuf, it would do so with presumed offset
3835 * state that didn't match the actual object state.
3837 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3840 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3847 drm_free_large(object_list
);
3848 drm_free_large(exec_list
);
3855 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
3857 struct drm_device
*dev
= obj
->dev
;
3858 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3861 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3862 if (obj_priv
->gtt_space
== NULL
) {
3863 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
3868 * Pre-965 chips need a fence register set up in order to
3869 * properly handle tiled surfaces.
3871 if (!IS_I965G(dev
) && obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
3872 ret
= i915_gem_object_get_fence_reg(obj
);
3874 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3875 DRM_ERROR("Failure to install fence: %d\n",
3880 obj_priv
->pin_count
++;
3882 /* If the object is not active and not pending a flush,
3883 * remove it from the inactive list
3885 if (obj_priv
->pin_count
== 1) {
3886 atomic_inc(&dev
->pin_count
);
3887 atomic_add(obj
->size
, &dev
->pin_memory
);
3888 if (!obj_priv
->active
&&
3889 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
3890 !list_empty(&obj_priv
->list
))
3891 list_del_init(&obj_priv
->list
);
3893 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3899 i915_gem_object_unpin(struct drm_gem_object
*obj
)
3901 struct drm_device
*dev
= obj
->dev
;
3902 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3903 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3905 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3906 obj_priv
->pin_count
--;
3907 BUG_ON(obj_priv
->pin_count
< 0);
3908 BUG_ON(obj_priv
->gtt_space
== NULL
);
3910 /* If the object is no longer pinned, and is
3911 * neither active nor being flushed, then stick it on
3914 if (obj_priv
->pin_count
== 0) {
3915 if (!obj_priv
->active
&&
3916 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
3917 list_move_tail(&obj_priv
->list
,
3918 &dev_priv
->mm
.inactive_list
);
3919 atomic_dec(&dev
->pin_count
);
3920 atomic_sub(obj
->size
, &dev
->pin_memory
);
3922 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3926 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3927 struct drm_file
*file_priv
)
3929 struct drm_i915_gem_pin
*args
= data
;
3930 struct drm_gem_object
*obj
;
3931 struct drm_i915_gem_object
*obj_priv
;
3934 mutex_lock(&dev
->struct_mutex
);
3936 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
3938 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3940 mutex_unlock(&dev
->struct_mutex
);
3943 obj_priv
= obj
->driver_private
;
3945 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
3946 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3947 drm_gem_object_unreference(obj
);
3948 mutex_unlock(&dev
->struct_mutex
);
3952 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
3953 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3955 drm_gem_object_unreference(obj
);
3956 mutex_unlock(&dev
->struct_mutex
);
3960 obj_priv
->user_pin_count
++;
3961 obj_priv
->pin_filp
= file_priv
;
3962 if (obj_priv
->user_pin_count
== 1) {
3963 ret
= i915_gem_object_pin(obj
, args
->alignment
);
3965 drm_gem_object_unreference(obj
);
3966 mutex_unlock(&dev
->struct_mutex
);
3971 /* XXX - flush the CPU caches for pinned objects
3972 * as the X server doesn't manage domains yet
3974 i915_gem_object_flush_cpu_write_domain(obj
);
3975 args
->offset
= obj_priv
->gtt_offset
;
3976 drm_gem_object_unreference(obj
);
3977 mutex_unlock(&dev
->struct_mutex
);
3983 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3984 struct drm_file
*file_priv
)
3986 struct drm_i915_gem_pin
*args
= data
;
3987 struct drm_gem_object
*obj
;
3988 struct drm_i915_gem_object
*obj_priv
;
3990 mutex_lock(&dev
->struct_mutex
);
3992 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
3994 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3996 mutex_unlock(&dev
->struct_mutex
);
4000 obj_priv
= obj
->driver_private
;
4001 if (obj_priv
->pin_filp
!= file_priv
) {
4002 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4004 drm_gem_object_unreference(obj
);
4005 mutex_unlock(&dev
->struct_mutex
);
4008 obj_priv
->user_pin_count
--;
4009 if (obj_priv
->user_pin_count
== 0) {
4010 obj_priv
->pin_filp
= NULL
;
4011 i915_gem_object_unpin(obj
);
4014 drm_gem_object_unreference(obj
);
4015 mutex_unlock(&dev
->struct_mutex
);
4020 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4021 struct drm_file
*file_priv
)
4023 struct drm_i915_gem_busy
*args
= data
;
4024 struct drm_gem_object
*obj
;
4025 struct drm_i915_gem_object
*obj_priv
;
4027 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4029 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4034 mutex_lock(&dev
->struct_mutex
);
4035 /* Update the active list for the hardware's current position.
4036 * Otherwise this only updates on a delayed timer or when irqs are
4037 * actually unmasked, and our working set ends up being larger than
4040 i915_gem_retire_requests(dev
);
4042 obj_priv
= obj
->driver_private
;
4043 /* Don't count being on the flushing list against the object being
4044 * done. Otherwise, a buffer left on the flushing list but not getting
4045 * flushed (because nobody's flushing that domain) won't ever return
4046 * unbusy and get reused by libdrm's bo cache. The other expected
4047 * consumer of this interface, OpenGL's occlusion queries, also specs
4048 * that the objects get unbusy "eventually" without any interference.
4050 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4052 drm_gem_object_unreference(obj
);
4053 mutex_unlock(&dev
->struct_mutex
);
4058 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4059 struct drm_file
*file_priv
)
4061 return i915_gem_ring_throttle(dev
, file_priv
);
4065 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4066 struct drm_file
*file_priv
)
4068 struct drm_i915_gem_madvise
*args
= data
;
4069 struct drm_gem_object
*obj
;
4070 struct drm_i915_gem_object
*obj_priv
;
4072 switch (args
->madv
) {
4073 case I915_MADV_DONTNEED
:
4074 case I915_MADV_WILLNEED
:
4080 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4082 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4087 mutex_lock(&dev
->struct_mutex
);
4088 obj_priv
= obj
->driver_private
;
4090 if (obj_priv
->pin_count
) {
4091 drm_gem_object_unreference(obj
);
4092 mutex_unlock(&dev
->struct_mutex
);
4094 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4098 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4099 obj_priv
->madv
= args
->madv
;
4101 /* if the object is no longer bound, discard its backing storage */
4102 if (i915_gem_object_is_purgeable(obj_priv
) &&
4103 obj_priv
->gtt_space
== NULL
)
4104 i915_gem_object_truncate(obj
);
4106 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4108 drm_gem_object_unreference(obj
);
4109 mutex_unlock(&dev
->struct_mutex
);
4114 int i915_gem_init_object(struct drm_gem_object
*obj
)
4116 struct drm_i915_gem_object
*obj_priv
;
4118 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
4119 if (obj_priv
== NULL
)
4123 * We've just allocated pages from the kernel,
4124 * so they've just been written by the CPU with
4125 * zeros. They'll need to be clflushed before we
4126 * use them with the GPU.
4128 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
4129 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
4131 obj_priv
->agp_type
= AGP_USER_MEMORY
;
4133 obj
->driver_private
= obj_priv
;
4134 obj_priv
->obj
= obj
;
4135 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
4136 INIT_LIST_HEAD(&obj_priv
->list
);
4137 INIT_LIST_HEAD(&obj_priv
->fence_list
);
4138 obj_priv
->madv
= I915_MADV_WILLNEED
;
4140 trace_i915_gem_object_create(obj
);
4145 void i915_gem_free_object(struct drm_gem_object
*obj
)
4147 struct drm_device
*dev
= obj
->dev
;
4148 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4150 trace_i915_gem_object_destroy(obj
);
4152 while (obj_priv
->pin_count
> 0)
4153 i915_gem_object_unpin(obj
);
4155 if (obj_priv
->phys_obj
)
4156 i915_gem_detach_phys_object(dev
, obj
);
4158 i915_gem_object_unbind(obj
);
4160 if (obj_priv
->mmap_offset
)
4161 i915_gem_free_mmap_offset(obj
);
4163 kfree(obj_priv
->page_cpu_valid
);
4164 kfree(obj_priv
->bit_17
);
4165 kfree(obj
->driver_private
);
4168 /** Unbinds all inactive objects. */
4170 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4172 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4174 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4175 struct drm_gem_object
*obj
;
4178 obj
= list_first_entry(&dev_priv
->mm
.inactive_list
,
4179 struct drm_i915_gem_object
,
4182 ret
= i915_gem_object_unbind(obj
);
4184 DRM_ERROR("Error unbinding object: %d\n", ret
);
4193 i915_gem_idle(struct drm_device
*dev
)
4195 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4196 uint32_t seqno
, cur_seqno
, last_seqno
;
4199 mutex_lock(&dev
->struct_mutex
);
4201 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
4202 mutex_unlock(&dev
->struct_mutex
);
4206 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4207 * We need to replace this with a semaphore, or something.
4209 dev_priv
->mm
.suspended
= 1;
4210 del_timer(&dev_priv
->hangcheck_timer
);
4212 /* Cancel the retire work handler, wait for it to finish if running
4214 mutex_unlock(&dev
->struct_mutex
);
4215 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4216 mutex_lock(&dev
->struct_mutex
);
4218 i915_kernel_lost_context(dev
);
4220 /* Flush the GPU along with all non-CPU write domains
4222 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
4223 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
4226 mutex_unlock(&dev
->struct_mutex
);
4230 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
4234 cur_seqno
= i915_get_gem_seqno(dev
);
4235 if (i915_seqno_passed(cur_seqno
, seqno
))
4237 if (last_seqno
== cur_seqno
) {
4238 if (stuck
++ > 100) {
4239 DRM_ERROR("hardware wedged\n");
4240 atomic_set(&dev_priv
->mm
.wedged
, 1);
4241 DRM_WAKEUP(&dev_priv
->irq_queue
);
4246 last_seqno
= cur_seqno
;
4248 dev_priv
->mm
.waiting_gem_seqno
= 0;
4250 i915_gem_retire_requests(dev
);
4252 spin_lock(&dev_priv
->mm
.active_list_lock
);
4253 if (!atomic_read(&dev_priv
->mm
.wedged
)) {
4254 /* Active and flushing should now be empty as we've
4255 * waited for a sequence higher than any pending execbuffer
4257 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
4258 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4259 /* Request should now be empty as we've also waited
4260 * for the last request in the list
4262 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
4265 /* Empty the active and flushing lists to inactive. If there's
4266 * anything left at this point, it means that we're wedged and
4267 * nothing good's going to happen by leaving them there. So strip
4268 * the GPU domains and just stuff them onto inactive.
4270 while (!list_empty(&dev_priv
->mm
.active_list
)) {
4271 struct drm_gem_object
*obj
;
4272 uint32_t old_write_domain
;
4274 obj
= list_first_entry(&dev_priv
->mm
.active_list
,
4275 struct drm_i915_gem_object
,
4277 old_write_domain
= obj
->write_domain
;
4278 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4279 i915_gem_object_move_to_inactive(obj
);
4281 trace_i915_gem_object_change_domain(obj
,
4285 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4287 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
4288 struct drm_gem_object
*obj
;
4289 uint32_t old_write_domain
;
4291 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
4292 struct drm_i915_gem_object
,
4294 old_write_domain
= obj
->write_domain
;
4295 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4296 i915_gem_object_move_to_inactive(obj
);
4298 trace_i915_gem_object_change_domain(obj
,
4304 /* Move all inactive buffers out of the GTT. */
4305 ret
= i915_gem_evict_from_inactive_list(dev
);
4306 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4308 mutex_unlock(&dev
->struct_mutex
);
4312 i915_gem_cleanup_ringbuffer(dev
);
4313 mutex_unlock(&dev
->struct_mutex
);
4319 i915_gem_init_hws(struct drm_device
*dev
)
4321 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4322 struct drm_gem_object
*obj
;
4323 struct drm_i915_gem_object
*obj_priv
;
4326 /* If we need a physical address for the status page, it's already
4327 * initialized at driver load time.
4329 if (!I915_NEED_GFX_HWS(dev
))
4332 obj
= drm_gem_object_alloc(dev
, 4096);
4334 DRM_ERROR("Failed to allocate status page\n");
4337 obj_priv
= obj
->driver_private
;
4338 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4340 ret
= i915_gem_object_pin(obj
, 4096);
4342 drm_gem_object_unreference(obj
);
4346 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4348 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4349 if (dev_priv
->hw_status_page
== NULL
) {
4350 DRM_ERROR("Failed to map status page.\n");
4351 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4352 i915_gem_object_unpin(obj
);
4353 drm_gem_object_unreference(obj
);
4356 dev_priv
->hws_obj
= obj
;
4357 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4358 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4359 I915_READ(HWS_PGA
); /* posting read */
4360 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4366 i915_gem_cleanup_hws(struct drm_device
*dev
)
4368 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4369 struct drm_gem_object
*obj
;
4370 struct drm_i915_gem_object
*obj_priv
;
4372 if (dev_priv
->hws_obj
== NULL
)
4375 obj
= dev_priv
->hws_obj
;
4376 obj_priv
= obj
->driver_private
;
4378 kunmap(obj_priv
->pages
[0]);
4379 i915_gem_object_unpin(obj
);
4380 drm_gem_object_unreference(obj
);
4381 dev_priv
->hws_obj
= NULL
;
4383 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4384 dev_priv
->hw_status_page
= NULL
;
4386 /* Write high address into HWS_PGA when disabling. */
4387 I915_WRITE(HWS_PGA
, 0x1ffff000);
4391 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4393 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4394 struct drm_gem_object
*obj
;
4395 struct drm_i915_gem_object
*obj_priv
;
4396 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4400 ret
= i915_gem_init_hws(dev
);
4404 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4406 DRM_ERROR("Failed to allocate ringbuffer\n");
4407 i915_gem_cleanup_hws(dev
);
4410 obj_priv
= obj
->driver_private
;
4412 ret
= i915_gem_object_pin(obj
, 4096);
4414 drm_gem_object_unreference(obj
);
4415 i915_gem_cleanup_hws(dev
);
4419 /* Set up the kernel mapping for the ring. */
4420 ring
->Size
= obj
->size
;
4422 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4423 ring
->map
.size
= obj
->size
;
4425 ring
->map
.flags
= 0;
4428 drm_core_ioremap_wc(&ring
->map
, dev
);
4429 if (ring
->map
.handle
== NULL
) {
4430 DRM_ERROR("Failed to map ringbuffer.\n");
4431 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4432 i915_gem_object_unpin(obj
);
4433 drm_gem_object_unreference(obj
);
4434 i915_gem_cleanup_hws(dev
);
4437 ring
->ring_obj
= obj
;
4438 ring
->virtual_start
= ring
->map
.handle
;
4440 /* Stop the ring if it's running. */
4441 I915_WRITE(PRB0_CTL
, 0);
4442 I915_WRITE(PRB0_TAIL
, 0);
4443 I915_WRITE(PRB0_HEAD
, 0);
4445 /* Initialize the ring. */
4446 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4447 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4449 /* G45 ring initialization fails to reset head to zero */
4451 DRM_ERROR("Ring head not reset to zero "
4452 "ctl %08x head %08x tail %08x start %08x\n",
4453 I915_READ(PRB0_CTL
),
4454 I915_READ(PRB0_HEAD
),
4455 I915_READ(PRB0_TAIL
),
4456 I915_READ(PRB0_START
));
4457 I915_WRITE(PRB0_HEAD
, 0);
4459 DRM_ERROR("Ring head forced to zero "
4460 "ctl %08x head %08x tail %08x start %08x\n",
4461 I915_READ(PRB0_CTL
),
4462 I915_READ(PRB0_HEAD
),
4463 I915_READ(PRB0_TAIL
),
4464 I915_READ(PRB0_START
));
4467 I915_WRITE(PRB0_CTL
,
4468 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4472 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4474 /* If the head is still not zero, the ring is dead */
4476 DRM_ERROR("Ring initialization failed "
4477 "ctl %08x head %08x tail %08x start %08x\n",
4478 I915_READ(PRB0_CTL
),
4479 I915_READ(PRB0_HEAD
),
4480 I915_READ(PRB0_TAIL
),
4481 I915_READ(PRB0_START
));
4485 /* Update our cache of the ring state */
4486 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4487 i915_kernel_lost_context(dev
);
4489 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4490 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4491 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4492 if (ring
->space
< 0)
4493 ring
->space
+= ring
->Size
;
4500 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4502 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4504 if (dev_priv
->ring
.ring_obj
== NULL
)
4507 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4509 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4510 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4511 dev_priv
->ring
.ring_obj
= NULL
;
4512 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4514 i915_gem_cleanup_hws(dev
);
4518 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4519 struct drm_file
*file_priv
)
4521 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4524 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4527 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4528 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4529 atomic_set(&dev_priv
->mm
.wedged
, 0);
4532 mutex_lock(&dev
->struct_mutex
);
4533 dev_priv
->mm
.suspended
= 0;
4535 ret
= i915_gem_init_ringbuffer(dev
);
4537 mutex_unlock(&dev
->struct_mutex
);
4541 spin_lock(&dev_priv
->mm
.active_list_lock
);
4542 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4543 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4545 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4546 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4547 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4548 mutex_unlock(&dev
->struct_mutex
);
4550 drm_irq_install(dev
);
4556 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4557 struct drm_file
*file_priv
)
4559 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4562 drm_irq_uninstall(dev
);
4563 return i915_gem_idle(dev
);
4567 i915_gem_lastclose(struct drm_device
*dev
)
4571 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4574 ret
= i915_gem_idle(dev
);
4576 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4580 i915_gem_load(struct drm_device
*dev
)
4583 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4585 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4586 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4587 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4588 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4589 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4590 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4591 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4592 i915_gem_retire_work_handler
);
4593 dev_priv
->mm
.next_gem_seqno
= 1;
4595 spin_lock(&shrink_list_lock
);
4596 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4597 spin_unlock(&shrink_list_lock
);
4599 /* Old X drivers will take 0-2 for front, back, depth buffers */
4600 dev_priv
->fence_reg_start
= 3;
4602 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4603 dev_priv
->num_fence_regs
= 16;
4605 dev_priv
->num_fence_regs
= 8;
4607 /* Initialize fence registers to zero */
4608 if (IS_I965G(dev
)) {
4609 for (i
= 0; i
< 16; i
++)
4610 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4612 for (i
= 0; i
< 8; i
++)
4613 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4614 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4615 for (i
= 0; i
< 8; i
++)
4616 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4619 i915_gem_detect_bit_6_swizzle(dev
);
4623 * Create a physically contiguous memory object for this object
4624 * e.g. for cursor + overlay regs
4626 int i915_gem_init_phys_object(struct drm_device
*dev
,
4629 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4630 struct drm_i915_gem_phys_object
*phys_obj
;
4633 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4636 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4642 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0, 0xffffffff);
4643 if (!phys_obj
->handle
) {
4648 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4651 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4659 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4662 struct drm_i915_gem_phys_object
*phys_obj
;
4664 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4667 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4668 if (phys_obj
->cur_obj
) {
4669 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4673 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4675 drm_pci_free(dev
, phys_obj
->handle
);
4677 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4680 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4684 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4685 i915_gem_free_phys_object(dev
, i
);
4688 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4689 struct drm_gem_object
*obj
)
4691 struct drm_i915_gem_object
*obj_priv
;
4696 obj_priv
= obj
->driver_private
;
4697 if (!obj_priv
->phys_obj
)
4700 ret
= i915_gem_object_get_pages(obj
);
4704 page_count
= obj
->size
/ PAGE_SIZE
;
4706 for (i
= 0; i
< page_count
; i
++) {
4707 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4708 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4710 memcpy(dst
, src
, PAGE_SIZE
);
4711 kunmap_atomic(dst
, KM_USER0
);
4713 drm_clflush_pages(obj_priv
->pages
, page_count
);
4714 drm_agp_chipset_flush(dev
);
4716 i915_gem_object_put_pages(obj
);
4718 obj_priv
->phys_obj
->cur_obj
= NULL
;
4719 obj_priv
->phys_obj
= NULL
;
4723 i915_gem_attach_phys_object(struct drm_device
*dev
,
4724 struct drm_gem_object
*obj
, int id
)
4726 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4727 struct drm_i915_gem_object
*obj_priv
;
4732 if (id
> I915_MAX_PHYS_OBJECT
)
4735 obj_priv
= obj
->driver_private
;
4737 if (obj_priv
->phys_obj
) {
4738 if (obj_priv
->phys_obj
->id
== id
)
4740 i915_gem_detach_phys_object(dev
, obj
);
4744 /* create a new object */
4745 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4746 ret
= i915_gem_init_phys_object(dev
, id
,
4749 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4754 /* bind to the object */
4755 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4756 obj_priv
->phys_obj
->cur_obj
= obj
;
4758 ret
= i915_gem_object_get_pages(obj
);
4760 DRM_ERROR("failed to get page list\n");
4764 page_count
= obj
->size
/ PAGE_SIZE
;
4766 for (i
= 0; i
< page_count
; i
++) {
4767 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4768 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4770 memcpy(dst
, src
, PAGE_SIZE
);
4771 kunmap_atomic(src
, KM_USER0
);
4774 i915_gem_object_put_pages(obj
);
4782 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4783 struct drm_i915_gem_pwrite
*args
,
4784 struct drm_file
*file_priv
)
4786 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4789 char __user
*user_data
;
4791 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4792 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4794 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4795 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4799 drm_agp_chipset_flush(dev
);
4803 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4805 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4807 /* Clean up our request list when the client is going away, so that
4808 * later retire_requests won't dereference our soon-to-be-gone
4811 mutex_lock(&dev
->struct_mutex
);
4812 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4813 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4814 mutex_unlock(&dev
->struct_mutex
);
4818 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
4820 drm_i915_private_t
*dev_priv
, *next_dev
;
4821 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4823 int would_deadlock
= 1;
4825 /* "fast-path" to count number of available objects */
4826 if (nr_to_scan
== 0) {
4827 spin_lock(&shrink_list_lock
);
4828 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4829 struct drm_device
*dev
= dev_priv
->dev
;
4831 if (mutex_trylock(&dev
->struct_mutex
)) {
4832 list_for_each_entry(obj_priv
,
4833 &dev_priv
->mm
.inactive_list
,
4836 mutex_unlock(&dev
->struct_mutex
);
4839 spin_unlock(&shrink_list_lock
);
4841 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4844 spin_lock(&shrink_list_lock
);
4846 /* first scan for clean buffers */
4847 list_for_each_entry_safe(dev_priv
, next_dev
,
4848 &shrink_list
, mm
.shrink_list
) {
4849 struct drm_device
*dev
= dev_priv
->dev
;
4851 if (! mutex_trylock(&dev
->struct_mutex
))
4854 spin_unlock(&shrink_list_lock
);
4856 i915_gem_retire_requests(dev
);
4858 list_for_each_entry_safe(obj_priv
, next_obj
,
4859 &dev_priv
->mm
.inactive_list
,
4861 if (i915_gem_object_is_purgeable(obj_priv
)) {
4862 i915_gem_object_unbind(obj_priv
->obj
);
4863 if (--nr_to_scan
<= 0)
4868 spin_lock(&shrink_list_lock
);
4869 mutex_unlock(&dev
->struct_mutex
);
4873 if (nr_to_scan
<= 0)
4877 /* second pass, evict/count anything still on the inactive list */
4878 list_for_each_entry_safe(dev_priv
, next_dev
,
4879 &shrink_list
, mm
.shrink_list
) {
4880 struct drm_device
*dev
= dev_priv
->dev
;
4882 if (! mutex_trylock(&dev
->struct_mutex
))
4885 spin_unlock(&shrink_list_lock
);
4887 list_for_each_entry_safe(obj_priv
, next_obj
,
4888 &dev_priv
->mm
.inactive_list
,
4890 if (nr_to_scan
> 0) {
4891 i915_gem_object_unbind(obj_priv
->obj
);
4897 spin_lock(&shrink_list_lock
);
4898 mutex_unlock(&dev
->struct_mutex
);
4903 spin_unlock(&shrink_list_lock
);
4908 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4913 static struct shrinker shrinker
= {
4914 .shrink
= i915_gem_shrink
,
4915 .seeks
= DEFAULT_SEEKS
,
4919 i915_gem_shrinker_init(void)
4921 register_shrinker(&shrinker
);
4925 i915_gem_shrinker_exit(void)
4927 unregister_shrinker(&shrinker
);