arch/arm/mach-davinci/board-dm365-evm.c

   1 /*
   2  * TI DaVinci DM365 EVM board support
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/i2c.h>
  19 #include <linux/io.h>
  20 #include <linux/clk.h>
  21 #include <linux/i2c/at24.h>
  22 #include <linux/leds.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/slab.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/input.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/eeprom.h>
  30
  31 #include <asm/mach-types.h>
  32 #include <asm/mach/arch.h>
  33
  34 #include <mach/mux.h>
  35 #include <mach/dm365.h>
  36 #include <mach/common.h>
  37 #include <mach/i2c.h>
  38 #include <mach/serial.h>
  39 #include <mach/mmc.h>
  40 #include <mach/nand.h>
  41 #include <mach/keyscan.h>
  42
  43 #include <media/tvp514x.h>
  44
  45 static inline int have_imager(void)
  46 {
  47         /* REVISIT when it's supported, trigger via Kconfig */
  48         return 0;
  49 }
  50
  51 static inline int have_tvp7002(void)
  52 {
  53         /* REVISIT when it's supported, trigger via Kconfig */
  54         return 0;
  55 }
  56
  57 #define DM365_EVM_PHY_MASK              (0x2)
  58 #define DM365_EVM_MDIO_FREQUENCY        (2200000) /* PHY bus frequency */
  59
  60 /*
  61  * A MAX-II CPLD is used for various board control functions.
  62  */
  63 #define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
  64
  65 #define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
  66 #define CPLD_TEST       CPLD_OFFSET(0,1)
  67 #define CPLD_LEDS       CPLD_OFFSET(0,2)
  68 #define CPLD_MUX        CPLD_OFFSET(0,3)
  69 #define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
  70 #define CPLD_POWER      CPLD_OFFSET(1,1)
  71 #define CPLD_VIDEO      CPLD_OFFSET(1,2)
  72 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
  73
  74 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
  75 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
  76
  77 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
  78 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
  79 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
  80 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
  81 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
  82 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
  83 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
  84 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
  85 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
  86
  87 #define CPLD_RESETS     CPLD_OFFSET(4,3)
  88
  89 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
  90 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
  91 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
  92 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
  93 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
  94 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
  95
  96 static void __iomem *cpld;
  97
  98
  99 /* NOTE:  this is geared for the standard config, with a socketed
 100  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 101  * swap chips with a different block size, partitioning will
 102  * need to be changed. This NAND chip MT29F16G08FAA is the default
 103  * NAND shipped with the Spectrum Digital DM365 EVM
 104  */
 105 #define NAND_BLOCK_SIZE         SZ_128K
 106
 107 static struct mtd_partition davinci_nand_partitions[] = {
 108         {
 109                 /* UBL (a few copies) plus U-Boot */
 110                 .name           = "bootloader",
 111                 .offset         = 0,
 112                 .size           = 28 * NAND_BLOCK_SIZE,
 113                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 114         }, {
 115                 /* U-Boot environment */
 116                 .name           = "params",
 117                 .offset         = MTDPART_OFS_APPEND,
 118                 .size           = 2 * NAND_BLOCK_SIZE,
 119                 .mask_flags     = 0,
 120         }, {
 121                 .name           = "kernel",
 122                 .offset         = MTDPART_OFS_APPEND,
 123                 .size           = SZ_4M,
 124                 .mask_flags     = 0,
 125         }, {
 126                 .name           = "filesystem1",
 127                 .offset         = MTDPART_OFS_APPEND,
 128                 .size           = SZ_512M,
 129                 .mask_flags     = 0,
 130         }, {
 131                 .name           = "filesystem2",
 132                 .offset         = MTDPART_OFS_APPEND,
 133                 .size           = MTDPART_SIZ_FULL,
 134                 .mask_flags     = 0,
 135         }
 136         /* two blocks with bad block table (and mirror) at the end */
 137 };
 138
 139 static struct davinci_nand_pdata davinci_nand_data = {
 140         .mask_chipsel           = BIT(14),
 141         .parts                  = davinci_nand_partitions,
 142         .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
 143         .ecc_mode               = NAND_ECC_HW,
 144         .options                = NAND_USE_FLASH_BBT,
 145         .ecc_bits               = 4,
 146 };
 147
 148 static struct resource davinci_nand_resources[] = {
 149         {
 150                 .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
 151                 .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 152                 .flags          = IORESOURCE_MEM,
 153         }, {
 154                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 155                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 156                 .flags          = IORESOURCE_MEM,
 157         },
 158 };
 159
 160 static struct platform_device davinci_nand_device = {
 161         .name                   = "davinci_nand",
 162         .id                     = 0,
 163         .num_resources          = ARRAY_SIZE(davinci_nand_resources),
 164         .resource               = davinci_nand_resources,
 165         .dev                    = {
 166                 .platform_data  = &davinci_nand_data,
 167         },
 168 };
 169
 170 static struct at24_platform_data eeprom_info = {
 171         .byte_len       = (256*1024) / 8,
 172         .page_size      = 64,
 173         .flags          = AT24_FLAG_ADDR16,
 174         .setup          = davinci_get_mac_addr,
 175         .context        = (void *)0x7f00,
 176 };
 177
 178 static struct snd_platform_data dm365_evm_snd_data = {
 179         .asp_chan_q = EVENTQ_3,
 180 };
 181
 182 static struct i2c_board_info i2c_info[] = {
 183         {
 184                 I2C_BOARD_INFO("24c256", 0x50),
 185                 .platform_data  = &eeprom_info,
 186         },
 187         {
 188                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
 189         },
 190 };
 191
 192 static struct davinci_i2c_platform_data i2c_pdata = {
 193         .bus_freq       = 400   /* kHz */,
 194         .bus_delay      = 0     /* usec */,
 195 };
 196
 197 static int dm365evm_keyscan_enable(struct device *dev)
 198 {
 199         return davinci_cfg_reg(DM365_KEYSCAN);
 200 }
 201
 202 static unsigned short dm365evm_keymap[] = {
 203         KEY_KP2,
 204         KEY_LEFT,
 205         KEY_EXIT,
 206         KEY_DOWN,
 207         KEY_ENTER,
 208         KEY_UP,
 209         KEY_KP1,
 210         KEY_RIGHT,
 211         KEY_MENU,
 212         KEY_RECORD,
 213         KEY_REWIND,
 214         KEY_KPMINUS,
 215         KEY_STOP,
 216         KEY_FASTFORWARD,
 217         KEY_KPPLUS,
 218         KEY_PLAYPAUSE,
 219         0
 220 };
 221
 222 static struct davinci_ks_platform_data dm365evm_ks_data = {
 223         .device_enable  = dm365evm_keyscan_enable,
 224         .keymap         = dm365evm_keymap,
 225         .keymapsize     = ARRAY_SIZE(dm365evm_keymap),
 226         .rep            = 1,
 227         /* Scan period = strobe + interval */
 228         .strobe         = 0x5,
 229         .interval       = 0x2,
 230         .matrix_type    = DAVINCI_KEYSCAN_MATRIX_4X4,
 231 };
 232
 233 static int cpld_mmc_get_cd(int module)
 234 {
 235         if (!cpld)
 236                 return -ENXIO;
 237
 238         /* low == card present */
 239         return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
 240 }
 241
 242 static int cpld_mmc_get_ro(int module)
 243 {
 244         if (!cpld)
 245                 return -ENXIO;
 246
 247         /* high == card's write protect switch active */
 248         return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
 249 }
 250
 251 static struct davinci_mmc_config dm365evm_mmc_config = {
 252         .get_cd         = cpld_mmc_get_cd,
 253         .get_ro         = cpld_mmc_get_ro,
 254         .wires          = 4,
 255         .max_freq       = 50000000,
 256         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 257         .version        = MMC_CTLR_VERSION_2,
 258 };
 259
 260 static void dm365evm_emac_configure(void)
 261 {
 262         /*
 263          * EMAC pins are multiplexed with GPIO and UART
 264          * Further details are available at the DM365 ARM
 265          * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
 266          */
 267         davinci_cfg_reg(DM365_EMAC_TX_EN);
 268         davinci_cfg_reg(DM365_EMAC_TX_CLK);
 269         davinci_cfg_reg(DM365_EMAC_COL);
 270         davinci_cfg_reg(DM365_EMAC_TXD3);
 271         davinci_cfg_reg(DM365_EMAC_TXD2);
 272         davinci_cfg_reg(DM365_EMAC_TXD1);
 273         davinci_cfg_reg(DM365_EMAC_TXD0);
 274         davinci_cfg_reg(DM365_EMAC_RXD3);
 275         davinci_cfg_reg(DM365_EMAC_RXD2);
 276         davinci_cfg_reg(DM365_EMAC_RXD1);
 277         davinci_cfg_reg(DM365_EMAC_RXD0);
 278         davinci_cfg_reg(DM365_EMAC_RX_CLK);
 279         davinci_cfg_reg(DM365_EMAC_RX_DV);
 280         davinci_cfg_reg(DM365_EMAC_RX_ER);
 281         davinci_cfg_reg(DM365_EMAC_CRS);
 282         davinci_cfg_reg(DM365_EMAC_MDIO);
 283         davinci_cfg_reg(DM365_EMAC_MDCLK);
 284
 285         /*
 286          * EMAC interrupts are multiplexed with GPIO interrupts
 287          * Details are available at the DM365 ARM
 288          * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
 289          */
 290         davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
 291         davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
 292         davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
 293         davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
 294 }
 295
 296 static void dm365evm_mmc_configure(void)
 297 {
 298         /*
 299          * MMC/SD pins are multiplexed with GPIO and EMIF
 300          * Further details are available at the DM365 ARM
 301          * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
 302          */
 303         davinci_cfg_reg(DM365_SD1_CLK);
 304         davinci_cfg_reg(DM365_SD1_CMD);
 305         davinci_cfg_reg(DM365_SD1_DATA3);
 306         davinci_cfg_reg(DM365_SD1_DATA2);
 307         davinci_cfg_reg(DM365_SD1_DATA1);
 308         davinci_cfg_reg(DM365_SD1_DATA0);
 309 }
 310
 311 static struct tvp514x_platform_data tvp5146_pdata = {
 312         .clk_polarity = 0,
 313         .hs_polarity = 1,
 314         .vs_polarity = 1
 315 };
 316
 317 #define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
 318 /* Inputs available at the TVP5146 */
 319 static struct v4l2_input tvp5146_inputs[] = {
 320         {
 321                 .index = 0,
 322                 .name = "Composite",
 323                 .type = V4L2_INPUT_TYPE_CAMERA,
 324                 .std = TVP514X_STD_ALL,
 325         },
 326         {
 327                 .index = 1,
 328                 .name = "S-Video",
 329                 .type = V4L2_INPUT_TYPE_CAMERA,
 330                 .std = TVP514X_STD_ALL,
 331         },
 332 };
 333
 334 /*
 335  * this is the route info for connecting each input to decoder
 336  * ouput that goes to vpfe. There is a one to one correspondence
 337  * with tvp5146_inputs
 338  */
 339 static struct vpfe_route tvp5146_routes[] = {
 340         {
 341                 .input = INPUT_CVBS_VI2B,
 342                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
 343         },
 344 {
 345                 .input = INPUT_SVIDEO_VI2C_VI1C,
 346                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
 347         },
 348 };
 349
 350 static struct vpfe_subdev_info vpfe_sub_devs[] = {
 351         {
 352                 .name = "tvp5146",
 353                 .grp_id = 0,
 354                 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
 355                 .inputs = tvp5146_inputs,
 356                 .routes = tvp5146_routes,
 357                 .can_route = 1,
 358                 .ccdc_if_params = {
 359                         .if_type = VPFE_BT656,
 360                         .hdpol = VPFE_PINPOL_POSITIVE,
 361                         .vdpol = VPFE_PINPOL_POSITIVE,
 362                 },
 363                 .board_info = {
 364                         I2C_BOARD_INFO("tvp5146", 0x5d),
 365                         .platform_data = &tvp5146_pdata,
 366                 },
 367         },
 368 };
 369
 370 static struct vpfe_config vpfe_cfg = {
 371         .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
 372         .sub_devs = vpfe_sub_devs,
 373         .i2c_adapter_id = 1,
 374         .card_name = "DM365 EVM",
 375         .ccdc = "ISIF",
 376 };
 377
 378 static void __init evm_init_i2c(void)
 379 {
 380         davinci_init_i2c(&i2c_pdata);
 381         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 382 }
 383
 384 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
 385         &davinci_nand_device,
 386 };
 387
 388 static inline int have_leds(void)
 389 {
 390 #ifdef CONFIG_LEDS_CLASS
 391         return 1;
 392 #else
 393         return 0;
 394 #endif
 395 }
 396
 397 struct cpld_led {
 398         struct led_classdev     cdev;
 399         u8                      mask;
 400 };
 401
 402 static const struct {
 403         const char *name;
 404         const char *trigger;
 405 } cpld_leds[] = {
 406         { "dm365evm::ds2", },
 407         { "dm365evm::ds3", },
 408         { "dm365evm::ds4", },
 409         { "dm365evm::ds5", },
 410         { "dm365evm::ds6", "nand-disk", },
 411         { "dm365evm::ds7", "mmc1", },
 412         { "dm365evm::ds8", "mmc0", },
 413         { "dm365evm::ds9", "heartbeat", },
 414 };
 415
 416 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
 417 {
 418         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 419         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 420
 421         if (b != LED_OFF)
 422                 reg &= ~led->mask;
 423         else
 424                 reg |= led->mask;
 425         __raw_writeb(reg, cpld + CPLD_LEDS);
 426 }
 427
 428 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
 429 {
 430         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 431         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 432
 433         return (reg & led->mask) ? LED_OFF : LED_FULL;
 434 }
 435
 436 static int __init cpld_leds_init(void)
 437 {
 438         int     i;
 439
 440         if (!have_leds() ||  !cpld)
 441                 return 0;
 442
 443         /* setup LEDs */
 444         __raw_writeb(0xff, cpld + CPLD_LEDS);
 445         for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
 446                 struct cpld_led *led;
 447
 448                 led = kzalloc(sizeof(*led), GFP_KERNEL);
 449                 if (!led)
 450                         break;
 451
 452                 led->cdev.name = cpld_leds[i].name;
 453                 led->cdev.brightness_set = cpld_led_set;
 454                 led->cdev.brightness_get = cpld_led_get;
 455                 led->cdev.default_trigger = cpld_leds[i].trigger;
 456                 led->mask = BIT(i);
 457
 458                 if (led_classdev_register(NULL, &led->cdev) < 0) {
 459                         kfree(led);
 460                         break;
 461                 }
 462         }
 463
 464         return 0;
 465 }
 466 /* run after subsys_initcall() for LEDs */
 467 fs_initcall(cpld_leds_init);
 468
 469
 470 static void __init evm_init_cpld(void)
 471 {
 472         u8 mux, resets;
 473         const char *label;
 474         struct clk *aemif_clk;
 475
 476         /* Make sure we can configure the CPLD through CS1.  Then
 477          * leave it on for later access to MMC and LED registers.
 478          */
 479         aemif_clk = clk_get(NULL, "aemif");
 480         if (IS_ERR(aemif_clk))
 481                 return;
 482         clk_enable(aemif_clk);
 483
 484         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
 485                         "cpld") == NULL)
 486                 goto fail;
 487         cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
 488         if (!cpld) {
 489                 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
 490                                 SECTION_SIZE);
 491 fail:
 492                 pr_err("ERROR: can't map CPLD\n");
 493                 clk_disable(aemif_clk);
 494                 return;
 495         }
 496
 497         /* External muxing for some signals */
 498         mux = 0;
 499
 500         /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
 501          * NOTE:  SW4 bus width setting must match!
 502          */
 503         if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
 504                 /* external keypad mux */
 505                 mux |= BIT(7);
 506
 507                 platform_add_devices(dm365_evm_nand_devices,
 508                                 ARRAY_SIZE(dm365_evm_nand_devices));
 509         } else {
 510                 /* no OneNAND support yet */
 511         }
 512
 513         /* Leave external chips in reset when unused. */
 514         resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
 515
 516         /* Static video input config with SN74CBT16214 1-of-3 mux:
 517          *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
 518          *  - port b2 == imager (mux lowbits == 2 or 7)
 519          *  - port b3 == tvp5146 (mux lowbits == 5)
 520          *
 521          * Runtime switching could work too, with limitations.
 522          */
 523         if (have_imager()) {
 524                 label = "HD imager";
 525                 mux |= 1;
 526
 527                 /* externally mux MMC1/ENET/AIC33 to imager */
 528                 mux |= BIT(6) | BIT(5) | BIT(3);
 529         } else {
 530                 struct davinci_soc_info *soc_info = &davinci_soc_info;
 531
 532                 /* we can use MMC1 ... */
 533                 dm365evm_mmc_configure();
 534                 davinci_setup_mmc(1, &dm365evm_mmc_config);
 535
 536                 /* ... and ENET ... */
 537                 dm365evm_emac_configure();
 538                 soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
 539                 soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
 540                 resets &= ~BIT(3);
 541
 542                 /* ... and AIC33 */
 543                 resets &= ~BIT(1);
 544
 545                 if (have_tvp7002()) {
 546                         mux |= 2;
 547                         resets &= ~BIT(2);
 548                         label = "tvp7002 HD";
 549                 } else {
 550                         /* default to tvp5146 */
 551                         mux |= 5;
 552                         resets &= ~BIT(0);
 553                         label = "tvp5146 SD";
 554                 }
 555         }
 556         __raw_writeb(mux, cpld + CPLD_MUX);
 557         __raw_writeb(resets, cpld + CPLD_RESETS);
 558         pr_info("EVM: %s video input\n", label);
 559
 560         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 561 }
 562
 563 static struct davinci_uart_config uart_config __initdata = {
 564         .enabled_uarts = (1 << 0),
 565 };
 566
 567 static void __init dm365_evm_map_io(void)
 568 {
 569         /* setup input configuration for VPFE input devices */
 570         dm365_set_vpfe_config(&vpfe_cfg);
 571         dm365_init();
 572 }
 573
 574 static struct spi_eeprom at25640 = {
 575         .byte_len       = SZ_64K / 8,
 576         .name           = "at25640",
 577         .page_size      = 32,
 578         .flags          = EE_ADDR2,
 579 };
 580
 581 static struct spi_board_info dm365_evm_spi_info[] __initconst = {
 582         {
 583                 .modalias       = "at25",
 584                 .platform_data  = &at25640,
 585                 .max_speed_hz   = 10 * 1000 * 1000,
 586                 .bus_num        = 0,
 587                 .chip_select    = 0,
 588                 .mode           = SPI_MODE_0,
 589         },
 590 };
 591
 592 static __init void dm365_evm_init(void)
 593 {
 594         evm_init_i2c();
 595         davinci_serial_init(&uart_config);
 596
 597         dm365evm_emac_configure();
 598         dm365evm_mmc_configure();
 599
 600         davinci_setup_mmc(0, &dm365evm_mmc_config);
 601
 602         /* maybe setup mmc1/etc ... _after_ mmc0 */
 603         evm_init_cpld();
 604
 605 #ifdef CONFIG_SND_DM365_AIC3X_CODEC
 606         dm365_init_asp(&dm365_evm_snd_data);
 607 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
 608         dm365_init_vc(&dm365_evm_snd_data);
 609 #endif
 610         dm365_init_rtc();
 611         dm365_init_ks(&dm365evm_ks_data);
 612
 613         dm365_init_spi0(BIT(0), dm365_evm_spi_info,
 614                         ARRAY_SIZE(dm365_evm_spi_info));
 615 }
 616
 617 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 618         .phys_io        = IO_PHYS,
 619         .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 620         .boot_params    = (0x80000100),
 621         .map_io         = dm365_evm_map_io,
 622         .init_irq       = davinci_irq_init,
 623         .timer          = &davinci_timer,
 624         .init_machine   = dm365_evm_init,
 625 MACHINE_END
 626