drm/i915: Release and unlock on mmap_gtt error path.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
blobf565b6afe414ec735a1f758623fc9a58455ca435
1 /*
2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include <linux/swap.h>
33 #include <linux/pci.h>
35 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37 static void
38 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
39 uint32_t read_domains,
40 uint32_t write_domain);
41 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
44 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
45 int write);
46 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 uint64_t offset,
48 uint64_t size);
49 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
50 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
51 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
52 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
54 unsigned alignment);
55 static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
56 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
57 static int i915_gem_evict_something(struct drm_device *dev);
58 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
59 struct drm_i915_gem_pwrite *args,
60 struct drm_file *file_priv);
62 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
63 unsigned long end)
65 drm_i915_private_t *dev_priv = dev->dev_private;
67 if (start >= end ||
68 (start & (PAGE_SIZE - 1)) != 0 ||
69 (end & (PAGE_SIZE - 1)) != 0) {
70 return -EINVAL;
73 drm_mm_init(&dev_priv->mm.gtt_space, start,
74 end - start);
76 dev->gtt_total = (uint32_t) (end - start);
78 return 0;
81 int
82 i915_gem_init_ioctl(struct drm_device *dev, void *data,
83 struct drm_file *file_priv)
85 struct drm_i915_gem_init *args = data;
86 int ret;
88 mutex_lock(&dev->struct_mutex);
89 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
90 mutex_unlock(&dev->struct_mutex);
92 return ret;
95 int
96 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
97 struct drm_file *file_priv)
99 struct drm_i915_gem_get_aperture *args = data;
101 if (!(dev->driver->driver_features & DRIVER_GEM))
102 return -ENODEV;
104 args->aper_size = dev->gtt_total;
105 args->aper_available_size = (args->aper_size -
106 atomic_read(&dev->pin_memory));
108 return 0;
113 * Creates a new mm object and returns a handle to it.
116 i915_gem_create_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv)
119 struct drm_i915_gem_create *args = data;
120 struct drm_gem_object *obj;
121 int handle, ret;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
135 if (ret)
136 return ret;
138 args->handle = handle;
140 return 0;
144 * Reads data from the object referenced by handle.
146 * On error, the contents of *data are undefined.
149 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
150 struct drm_file *file_priv)
152 struct drm_i915_gem_pread *args = data;
153 struct drm_gem_object *obj;
154 struct drm_i915_gem_object *obj_priv;
155 ssize_t read;
156 loff_t offset;
157 int ret;
159 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
160 if (obj == NULL)
161 return -EBADF;
162 obj_priv = obj->driver_private;
164 /* Bounds check source.
166 * XXX: This could use review for overflow issues...
168 if (args->offset > obj->size || args->size > obj->size ||
169 args->offset + args->size > obj->size) {
170 drm_gem_object_unreference(obj);
171 return -EINVAL;
174 mutex_lock(&dev->struct_mutex);
176 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
177 args->size);
178 if (ret != 0) {
179 drm_gem_object_unreference(obj);
180 mutex_unlock(&dev->struct_mutex);
181 return ret;
184 offset = args->offset;
186 read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
187 args->size, &offset);
188 if (read != args->size) {
189 drm_gem_object_unreference(obj);
190 mutex_unlock(&dev->struct_mutex);
191 if (read < 0)
192 return read;
193 else
194 return -EINVAL;
197 drm_gem_object_unreference(obj);
198 mutex_unlock(&dev->struct_mutex);
200 return 0;
203 /* This is the fast write path which cannot handle
204 * page faults in the source data
207 static inline int
208 fast_user_write(struct io_mapping *mapping,
209 loff_t page_base, int page_offset,
210 char __user *user_data,
211 int length)
213 char *vaddr_atomic;
214 unsigned long unwritten;
216 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
217 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
218 user_data, length);
219 io_mapping_unmap_atomic(vaddr_atomic);
220 if (unwritten)
221 return -EFAULT;
222 return 0;
225 /* Here's the write path which can sleep for
226 * page faults
229 static inline int
230 slow_user_write(struct io_mapping *mapping,
231 loff_t page_base, int page_offset,
232 char __user *user_data,
233 int length)
235 char __iomem *vaddr;
236 unsigned long unwritten;
238 vaddr = io_mapping_map_wc(mapping, page_base);
239 if (vaddr == NULL)
240 return -EFAULT;
241 unwritten = __copy_from_user(vaddr + page_offset,
242 user_data, length);
243 io_mapping_unmap(vaddr);
244 if (unwritten)
245 return -EFAULT;
246 return 0;
249 static int
250 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
251 struct drm_i915_gem_pwrite *args,
252 struct drm_file *file_priv)
254 struct drm_i915_gem_object *obj_priv = obj->driver_private;
255 drm_i915_private_t *dev_priv = dev->dev_private;
256 ssize_t remain;
257 loff_t offset, page_base;
258 char __user *user_data;
259 int page_offset, page_length;
260 int ret;
262 user_data = (char __user *) (uintptr_t) args->data_ptr;
263 remain = args->size;
264 if (!access_ok(VERIFY_READ, user_data, remain))
265 return -EFAULT;
268 mutex_lock(&dev->struct_mutex);
269 ret = i915_gem_object_pin(obj, 0);
270 if (ret) {
271 mutex_unlock(&dev->struct_mutex);
272 return ret;
274 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
275 if (ret)
276 goto fail;
278 obj_priv = obj->driver_private;
279 offset = obj_priv->gtt_offset + args->offset;
280 obj_priv->dirty = 1;
282 while (remain > 0) {
283 /* Operation in this page
285 * page_base = page offset within aperture
286 * page_offset = offset within page
287 * page_length = bytes to copy for this page
289 page_base = (offset & ~(PAGE_SIZE-1));
290 page_offset = offset & (PAGE_SIZE-1);
291 page_length = remain;
292 if ((page_offset + remain) > PAGE_SIZE)
293 page_length = PAGE_SIZE - page_offset;
295 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
296 page_offset, user_data, page_length);
298 /* If we get a fault while copying data, then (presumably) our
299 * source page isn't available. In this case, use the
300 * non-atomic function
302 if (ret) {
303 ret = slow_user_write (dev_priv->mm.gtt_mapping,
304 page_base, page_offset,
305 user_data, page_length);
306 if (ret)
307 goto fail;
310 remain -= page_length;
311 user_data += page_length;
312 offset += page_length;
315 fail:
316 i915_gem_object_unpin(obj);
317 mutex_unlock(&dev->struct_mutex);
319 return ret;
322 static int
323 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
324 struct drm_i915_gem_pwrite *args,
325 struct drm_file *file_priv)
327 int ret;
328 loff_t offset;
329 ssize_t written;
331 mutex_lock(&dev->struct_mutex);
333 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
334 if (ret) {
335 mutex_unlock(&dev->struct_mutex);
336 return ret;
339 offset = args->offset;
341 written = vfs_write(obj->filp,
342 (char __user *)(uintptr_t) args->data_ptr,
343 args->size, &offset);
344 if (written != args->size) {
345 mutex_unlock(&dev->struct_mutex);
346 if (written < 0)
347 return written;
348 else
349 return -EINVAL;
352 mutex_unlock(&dev->struct_mutex);
354 return 0;
358 * Writes data to the object referenced by handle.
360 * On error, the contents of the buffer that were to be modified are undefined.
363 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
364 struct drm_file *file_priv)
366 struct drm_i915_gem_pwrite *args = data;
367 struct drm_gem_object *obj;
368 struct drm_i915_gem_object *obj_priv;
369 int ret = 0;
371 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
372 if (obj == NULL)
373 return -EBADF;
374 obj_priv = obj->driver_private;
376 /* Bounds check destination.
378 * XXX: This could use review for overflow issues...
380 if (args->offset > obj->size || args->size > obj->size ||
381 args->offset + args->size > obj->size) {
382 drm_gem_object_unreference(obj);
383 return -EINVAL;
386 /* We can only do the GTT pwrite on untiled buffers, as otherwise
387 * it would end up going through the fenced access, and we'll get
388 * different detiling behavior between reading and writing.
389 * pread/pwrite currently are reading and writing from the CPU
390 * perspective, requiring manual detiling by the client.
392 if (obj_priv->phys_obj)
393 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
394 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
395 dev->gtt_total != 0)
396 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
397 else
398 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
400 #if WATCH_PWRITE
401 if (ret)
402 DRM_INFO("pwrite failed %d\n", ret);
403 #endif
405 drm_gem_object_unreference(obj);
407 return ret;
411 * Called when user space prepares to use an object with the CPU, either
412 * through the mmap ioctl's mapping or a GTT mapping.
415 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
416 struct drm_file *file_priv)
418 struct drm_i915_gem_set_domain *args = data;
419 struct drm_gem_object *obj;
420 uint32_t read_domains = args->read_domains;
421 uint32_t write_domain = args->write_domain;
422 int ret;
424 if (!(dev->driver->driver_features & DRIVER_GEM))
425 return -ENODEV;
427 /* Only handle setting domains to types used by the CPU. */
428 if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
429 return -EINVAL;
431 if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
432 return -EINVAL;
434 /* Having something in the write domain implies it's in the read
435 * domain, and only that read domain. Enforce that in the request.
437 if (write_domain != 0 && read_domains != write_domain)
438 return -EINVAL;
440 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
441 if (obj == NULL)
442 return -EBADF;
444 mutex_lock(&dev->struct_mutex);
445 #if WATCH_BUF
446 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
447 obj, obj->size, read_domains, write_domain);
448 #endif
449 if (read_domains & I915_GEM_DOMAIN_GTT) {
450 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
452 /* Silently promote "you're not bound, there was nothing to do"
453 * to success, since the client was just asking us to
454 * make sure everything was done.
456 if (ret == -EINVAL)
457 ret = 0;
458 } else {
459 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
462 drm_gem_object_unreference(obj);
463 mutex_unlock(&dev->struct_mutex);
464 return ret;
468 * Called when user space has done writes to this buffer
471 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv)
474 struct drm_i915_gem_sw_finish *args = data;
475 struct drm_gem_object *obj;
476 struct drm_i915_gem_object *obj_priv;
477 int ret = 0;
479 if (!(dev->driver->driver_features & DRIVER_GEM))
480 return -ENODEV;
482 mutex_lock(&dev->struct_mutex);
483 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
484 if (obj == NULL) {
485 mutex_unlock(&dev->struct_mutex);
486 return -EBADF;
489 #if WATCH_BUF
490 DRM_INFO("%s: sw_finish %d (%p %d)\n",
491 __func__, args->handle, obj, obj->size);
492 #endif
493 obj_priv = obj->driver_private;
495 /* Pinned buffers may be scanout, so flush the cache */
496 if (obj_priv->pin_count)
497 i915_gem_object_flush_cpu_write_domain(obj);
499 drm_gem_object_unreference(obj);
500 mutex_unlock(&dev->struct_mutex);
501 return ret;
505 * Maps the contents of an object, returning the address it is mapped
506 * into.
508 * While the mapping holds a reference on the contents of the object, it doesn't
509 * imply a ref on the object itself.
512 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *file_priv)
515 struct drm_i915_gem_mmap *args = data;
516 struct drm_gem_object *obj;
517 loff_t offset;
518 unsigned long addr;
520 if (!(dev->driver->driver_features & DRIVER_GEM))
521 return -ENODEV;
523 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
524 if (obj == NULL)
525 return -EBADF;
527 offset = args->offset;
529 down_write(&current->mm->mmap_sem);
530 addr = do_mmap(obj->filp, 0, args->size,
531 PROT_READ | PROT_WRITE, MAP_SHARED,
532 args->offset);
533 up_write(&current->mm->mmap_sem);
534 mutex_lock(&dev->struct_mutex);
535 drm_gem_object_unreference(obj);
536 mutex_unlock(&dev->struct_mutex);
537 if (IS_ERR((void *)addr))
538 return addr;
540 args->addr_ptr = (uint64_t) addr;
542 return 0;
546 * i915_gem_fault - fault a page into the GTT
547 * vma: VMA in question
548 * vmf: fault info
550 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
551 * from userspace. The fault handler takes care of binding the object to
552 * the GTT (if needed), allocating and programming a fence register (again,
553 * only if needed based on whether the old reg is still valid or the object
554 * is tiled) and inserting a new PTE into the faulting process.
556 * Note that the faulting process may involve evicting existing objects
557 * from the GTT and/or fence registers to make room. So performance may
558 * suffer if the GTT working set is large or there are few fence registers
559 * left.
561 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
563 struct drm_gem_object *obj = vma->vm_private_data;
564 struct drm_device *dev = obj->dev;
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 struct drm_i915_gem_object *obj_priv = obj->driver_private;
567 pgoff_t page_offset;
568 unsigned long pfn;
569 int ret = 0;
570 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
572 /* We don't use vmf->pgoff since that has the fake offset */
573 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
574 PAGE_SHIFT;
576 /* Now bind it into the GTT if needed */
577 mutex_lock(&dev->struct_mutex);
578 if (!obj_priv->gtt_space) {
579 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
580 if (ret) {
581 mutex_unlock(&dev->struct_mutex);
582 return VM_FAULT_SIGBUS;
584 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
587 /* Need a new fence register? */
588 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
589 obj_priv->tiling_mode != I915_TILING_NONE) {
590 ret = i915_gem_object_get_fence_reg(obj, write);
591 if (ret) {
592 mutex_unlock(&dev->struct_mutex);
593 return VM_FAULT_SIGBUS;
597 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
598 page_offset;
600 /* Finally, remap it using the new GTT offset */
601 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
603 mutex_unlock(&dev->struct_mutex);
605 switch (ret) {
606 case -ENOMEM:
607 case -EAGAIN:
608 return VM_FAULT_OOM;
609 case -EFAULT:
610 case -EBUSY:
611 DRM_ERROR("can't insert pfn?? fault or busy...\n");
612 return VM_FAULT_SIGBUS;
613 default:
614 return VM_FAULT_NOPAGE;
619 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
620 * @obj: obj in question
622 * GEM memory mapping works by handing back to userspace a fake mmap offset
623 * it can use in a subsequent mmap(2) call. The DRM core code then looks
624 * up the object based on the offset and sets up the various memory mapping
625 * structures.
627 * This routine allocates and attaches a fake offset for @obj.
629 static int
630 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
632 struct drm_device *dev = obj->dev;
633 struct drm_gem_mm *mm = dev->mm_private;
634 struct drm_i915_gem_object *obj_priv = obj->driver_private;
635 struct drm_map_list *list;
636 struct drm_map *map;
637 int ret = 0;
639 /* Set the object up for mmap'ing */
640 list = &obj->map_list;
641 list->map = drm_calloc(1, sizeof(struct drm_map_list),
642 DRM_MEM_DRIVER);
643 if (!list->map)
644 return -ENOMEM;
646 map = list->map;
647 map->type = _DRM_GEM;
648 map->size = obj->size;
649 map->handle = obj;
651 /* Get a DRM GEM mmap offset allocated... */
652 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
653 obj->size / PAGE_SIZE, 0, 0);
654 if (!list->file_offset_node) {
655 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
656 ret = -ENOMEM;
657 goto out_free_list;
660 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
661 obj->size / PAGE_SIZE, 0);
662 if (!list->file_offset_node) {
663 ret = -ENOMEM;
664 goto out_free_list;
667 list->hash.key = list->file_offset_node->start;
668 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
669 DRM_ERROR("failed to add to map hash\n");
670 goto out_free_mm;
673 /* By now we should be all set, any drm_mmap request on the offset
674 * below will get to our mmap & fault handler */
675 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
677 return 0;
679 out_free_mm:
680 drm_mm_put_block(list->file_offset_node);
681 out_free_list:
682 drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
684 return ret;
688 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
689 * @obj: object to check
691 * Return the required GTT alignment for an object, taking into account
692 * potential fence register mapping if needed.
694 static uint32_t
695 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
697 struct drm_device *dev = obj->dev;
698 struct drm_i915_gem_object *obj_priv = obj->driver_private;
699 int start, i;
702 * Minimum alignment is 4k (GTT page size), but might be greater
703 * if a fence register is needed for the object.
705 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
706 return 4096;
709 * Previous chips need to be aligned to the size of the smallest
710 * fence register that can contain the object.
712 if (IS_I9XX(dev))
713 start = 1024*1024;
714 else
715 start = 512*1024;
717 for (i = start; i < obj->size; i <<= 1)
720 return i;
724 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
725 * @dev: DRM device
726 * @data: GTT mapping ioctl data
727 * @file_priv: GEM object info
729 * Simply returns the fake offset to userspace so it can mmap it.
730 * The mmap call will end up in drm_gem_mmap(), which will set things
731 * up so we can get faults in the handler above.
733 * The fault handler will take care of binding the object into the GTT
734 * (since it may have been evicted to make room for something), allocating
735 * a fence register, and mapping the appropriate aperture address into
736 * userspace.
739 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *file_priv)
742 struct drm_i915_gem_mmap_gtt *args = data;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct drm_gem_object *obj;
745 struct drm_i915_gem_object *obj_priv;
746 int ret;
748 if (!(dev->driver->driver_features & DRIVER_GEM))
749 return -ENODEV;
751 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
752 if (obj == NULL)
753 return -EBADF;
755 mutex_lock(&dev->struct_mutex);
757 obj_priv = obj->driver_private;
759 if (!obj_priv->mmap_offset) {
760 ret = i915_gem_create_mmap_offset(obj);
761 if (ret) {
762 drm_gem_object_unreference(obj);
763 mutex_unlock(&dev->struct_mutex);
764 return ret;
768 args->offset = obj_priv->mmap_offset;
770 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
772 /* Make sure the alignment is correct for fence regs etc */
773 if (obj_priv->agp_mem &&
774 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
775 drm_gem_object_unreference(obj);
776 mutex_unlock(&dev->struct_mutex);
777 return -EINVAL;
781 * Pull it into the GTT so that we have a page list (makes the
782 * initial fault faster and any subsequent flushing possible).
784 if (!obj_priv->agp_mem) {
785 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
786 if (ret) {
787 drm_gem_object_unreference(obj);
788 mutex_unlock(&dev->struct_mutex);
789 return ret;
791 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
794 drm_gem_object_unreference(obj);
795 mutex_unlock(&dev->struct_mutex);
797 return 0;
800 static void
801 i915_gem_object_free_page_list(struct drm_gem_object *obj)
803 struct drm_i915_gem_object *obj_priv = obj->driver_private;
804 int page_count = obj->size / PAGE_SIZE;
805 int i;
807 if (obj_priv->page_list == NULL)
808 return;
811 for (i = 0; i < page_count; i++)
812 if (obj_priv->page_list[i] != NULL) {
813 if (obj_priv->dirty)
814 set_page_dirty(obj_priv->page_list[i]);
815 mark_page_accessed(obj_priv->page_list[i]);
816 page_cache_release(obj_priv->page_list[i]);
818 obj_priv->dirty = 0;
820 drm_free(obj_priv->page_list,
821 page_count * sizeof(struct page *),
822 DRM_MEM_DRIVER);
823 obj_priv->page_list = NULL;
826 static void
827 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
829 struct drm_device *dev = obj->dev;
830 drm_i915_private_t *dev_priv = dev->dev_private;
831 struct drm_i915_gem_object *obj_priv = obj->driver_private;
833 /* Add a reference if we're newly entering the active list. */
834 if (!obj_priv->active) {
835 drm_gem_object_reference(obj);
836 obj_priv->active = 1;
838 /* Move from whatever list we were on to the tail of execution. */
839 list_move_tail(&obj_priv->list,
840 &dev_priv->mm.active_list);
841 obj_priv->last_rendering_seqno = seqno;
844 static void
845 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
847 struct drm_device *dev = obj->dev;
848 drm_i915_private_t *dev_priv = dev->dev_private;
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
851 BUG_ON(!obj_priv->active);
852 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
853 obj_priv->last_rendering_seqno = 0;
856 static void
857 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
859 struct drm_device *dev = obj->dev;
860 drm_i915_private_t *dev_priv = dev->dev_private;
861 struct drm_i915_gem_object *obj_priv = obj->driver_private;
863 i915_verify_inactive(dev, __FILE__, __LINE__);
864 if (obj_priv->pin_count != 0)
865 list_del_init(&obj_priv->list);
866 else
867 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
869 obj_priv->last_rendering_seqno = 0;
870 if (obj_priv->active) {
871 obj_priv->active = 0;
872 drm_gem_object_unreference(obj);
874 i915_verify_inactive(dev, __FILE__, __LINE__);
878 * Creates a new sequence number, emitting a write of it to the status page
879 * plus an interrupt, which will trigger i915_user_interrupt_handler.
881 * Must be called with struct_lock held.
883 * Returned sequence numbers are nonzero on success.
885 static uint32_t
886 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
888 drm_i915_private_t *dev_priv = dev->dev_private;
889 struct drm_i915_gem_request *request;
890 uint32_t seqno;
891 int was_empty;
892 RING_LOCALS;
894 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
895 if (request == NULL)
896 return 0;
898 /* Grab the seqno we're going to make this request be, and bump the
899 * next (skipping 0 so it can be the reserved no-seqno value).
901 seqno = dev_priv->mm.next_gem_seqno;
902 dev_priv->mm.next_gem_seqno++;
903 if (dev_priv->mm.next_gem_seqno == 0)
904 dev_priv->mm.next_gem_seqno++;
906 BEGIN_LP_RING(4);
907 OUT_RING(MI_STORE_DWORD_INDEX);
908 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
909 OUT_RING(seqno);
911 OUT_RING(MI_USER_INTERRUPT);
912 ADVANCE_LP_RING();
914 DRM_DEBUG("%d\n", seqno);
916 request->seqno = seqno;
917 request->emitted_jiffies = jiffies;
918 was_empty = list_empty(&dev_priv->mm.request_list);
919 list_add_tail(&request->list, &dev_priv->mm.request_list);
921 /* Associate any objects on the flushing list matching the write
922 * domain we're flushing with our flush.
924 if (flush_domains != 0) {
925 struct drm_i915_gem_object *obj_priv, *next;
927 list_for_each_entry_safe(obj_priv, next,
928 &dev_priv->mm.flushing_list, list) {
929 struct drm_gem_object *obj = obj_priv->obj;
931 if ((obj->write_domain & flush_domains) ==
932 obj->write_domain) {
933 obj->write_domain = 0;
934 i915_gem_object_move_to_active(obj, seqno);
940 if (was_empty && !dev_priv->mm.suspended)
941 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
942 return seqno;
946 * Command execution barrier
948 * Ensures that all commands in the ring are finished
949 * before signalling the CPU
951 static uint32_t
952 i915_retire_commands(struct drm_device *dev)
954 drm_i915_private_t *dev_priv = dev->dev_private;
955 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
956 uint32_t flush_domains = 0;
957 RING_LOCALS;
959 /* The sampler always gets flushed on i965 (sigh) */
960 if (IS_I965G(dev))
961 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
962 BEGIN_LP_RING(2);
963 OUT_RING(cmd);
964 OUT_RING(0); /* noop */
965 ADVANCE_LP_RING();
966 return flush_domains;
970 * Moves buffers associated only with the given active seqno from the active
971 * to inactive list, potentially freeing them.
973 static void
974 i915_gem_retire_request(struct drm_device *dev,
975 struct drm_i915_gem_request *request)
977 drm_i915_private_t *dev_priv = dev->dev_private;
979 /* Move any buffers on the active list that are no longer referenced
980 * by the ringbuffer to the flushing/inactive lists as appropriate.
982 while (!list_empty(&dev_priv->mm.active_list)) {
983 struct drm_gem_object *obj;
984 struct drm_i915_gem_object *obj_priv;
986 obj_priv = list_first_entry(&dev_priv->mm.active_list,
987 struct drm_i915_gem_object,
988 list);
989 obj = obj_priv->obj;
991 /* If the seqno being retired doesn't match the oldest in the
992 * list, then the oldest in the list must still be newer than
993 * this seqno.
995 if (obj_priv->last_rendering_seqno != request->seqno)
996 return;
998 #if WATCH_LRU
999 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1000 __func__, request->seqno, obj);
1001 #endif
1003 if (obj->write_domain != 0)
1004 i915_gem_object_move_to_flushing(obj);
1005 else
1006 i915_gem_object_move_to_inactive(obj);
1011 * Returns true if seq1 is later than seq2.
1013 static int
1014 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1016 return (int32_t)(seq1 - seq2) >= 0;
1019 uint32_t
1020 i915_get_gem_seqno(struct drm_device *dev)
1022 drm_i915_private_t *dev_priv = dev->dev_private;
1024 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1028 * This function clears the request list as sequence numbers are passed.
1030 void
1031 i915_gem_retire_requests(struct drm_device *dev)
1033 drm_i915_private_t *dev_priv = dev->dev_private;
1034 uint32_t seqno;
1036 seqno = i915_get_gem_seqno(dev);
1038 while (!list_empty(&dev_priv->mm.request_list)) {
1039 struct drm_i915_gem_request *request;
1040 uint32_t retiring_seqno;
1042 request = list_first_entry(&dev_priv->mm.request_list,
1043 struct drm_i915_gem_request,
1044 list);
1045 retiring_seqno = request->seqno;
1047 if (i915_seqno_passed(seqno, retiring_seqno) ||
1048 dev_priv->mm.wedged) {
1049 i915_gem_retire_request(dev, request);
1051 list_del(&request->list);
1052 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1053 } else
1054 break;
1058 void
1059 i915_gem_retire_work_handler(struct work_struct *work)
1061 drm_i915_private_t *dev_priv;
1062 struct drm_device *dev;
1064 dev_priv = container_of(work, drm_i915_private_t,
1065 mm.retire_work.work);
1066 dev = dev_priv->dev;
1068 mutex_lock(&dev->struct_mutex);
1069 i915_gem_retire_requests(dev);
1070 if (!dev_priv->mm.suspended &&
1071 !list_empty(&dev_priv->mm.request_list))
1072 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1073 mutex_unlock(&dev->struct_mutex);
1077 * Waits for a sequence number to be signaled, and cleans up the
1078 * request and object lists appropriately for that event.
1080 static int
1081 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1083 drm_i915_private_t *dev_priv = dev->dev_private;
1084 int ret = 0;
1086 BUG_ON(seqno == 0);
1088 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1089 dev_priv->mm.waiting_gem_seqno = seqno;
1090 i915_user_irq_get(dev);
1091 ret = wait_event_interruptible(dev_priv->irq_queue,
1092 i915_seqno_passed(i915_get_gem_seqno(dev),
1093 seqno) ||
1094 dev_priv->mm.wedged);
1095 i915_user_irq_put(dev);
1096 dev_priv->mm.waiting_gem_seqno = 0;
1098 if (dev_priv->mm.wedged)
1099 ret = -EIO;
1101 if (ret && ret != -ERESTARTSYS)
1102 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1103 __func__, ret, seqno, i915_get_gem_seqno(dev));
1105 /* Directly dispatch request retiring. While we have the work queue
1106 * to handle this, the waiter on a request often wants an associated
1107 * buffer to have made it to the inactive list, and we would need
1108 * a separate wait queue to handle that.
1110 if (ret == 0)
1111 i915_gem_retire_requests(dev);
1113 return ret;
1116 static void
1117 i915_gem_flush(struct drm_device *dev,
1118 uint32_t invalidate_domains,
1119 uint32_t flush_domains)
1121 drm_i915_private_t *dev_priv = dev->dev_private;
1122 uint32_t cmd;
1123 RING_LOCALS;
1125 #if WATCH_EXEC
1126 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1127 invalidate_domains, flush_domains);
1128 #endif
1130 if (flush_domains & I915_GEM_DOMAIN_CPU)
1131 drm_agp_chipset_flush(dev);
1133 if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1134 I915_GEM_DOMAIN_GTT)) {
1136 * read/write caches:
1138 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1139 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1140 * also flushed at 2d versus 3d pipeline switches.
1142 * read-only caches:
1144 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1145 * MI_READ_FLUSH is set, and is always flushed on 965.
1147 * I915_GEM_DOMAIN_COMMAND may not exist?
1149 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1150 * invalidated when MI_EXE_FLUSH is set.
1152 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1153 * invalidated with every MI_FLUSH.
1155 * TLBs:
1157 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1158 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1159 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1160 * are flushed at any MI_FLUSH.
1163 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1164 if ((invalidate_domains|flush_domains) &
1165 I915_GEM_DOMAIN_RENDER)
1166 cmd &= ~MI_NO_WRITE_FLUSH;
1167 if (!IS_I965G(dev)) {
1169 * On the 965, the sampler cache always gets flushed
1170 * and this bit is reserved.
1172 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1173 cmd |= MI_READ_FLUSH;
1175 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1176 cmd |= MI_EXE_FLUSH;
1178 #if WATCH_EXEC
1179 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1180 #endif
1181 BEGIN_LP_RING(2);
1182 OUT_RING(cmd);
1183 OUT_RING(0); /* noop */
1184 ADVANCE_LP_RING();
1189 * Ensures that all rendering to the object has completed and the object is
1190 * safe to unbind from the GTT or access from the CPU.
1192 static int
1193 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1195 struct drm_device *dev = obj->dev;
1196 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1197 int ret;
1199 /* This function only exists to support waiting for existing rendering,
1200 * not for emitting required flushes.
1202 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1204 /* If there is rendering queued on the buffer being evicted, wait for
1205 * it.
1207 if (obj_priv->active) {
1208 #if WATCH_BUF
1209 DRM_INFO("%s: object %p wait for seqno %08x\n",
1210 __func__, obj, obj_priv->last_rendering_seqno);
1211 #endif
1212 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1213 if (ret != 0)
1214 return ret;
1217 return 0;
1221 * Unbinds an object from the GTT aperture.
1224 i915_gem_object_unbind(struct drm_gem_object *obj)
1226 struct drm_device *dev = obj->dev;
1227 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1228 loff_t offset;
1229 int ret = 0;
1231 #if WATCH_BUF
1232 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1233 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1234 #endif
1235 if (obj_priv->gtt_space == NULL)
1236 return 0;
1238 if (obj_priv->pin_count != 0) {
1239 DRM_ERROR("Attempting to unbind pinned buffer\n");
1240 return -EINVAL;
1243 /* Move the object to the CPU domain to ensure that
1244 * any possible CPU writes while it's not in the GTT
1245 * are flushed when we go to remap it. This will
1246 * also ensure that all pending GPU writes are finished
1247 * before we unbind.
1249 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1250 if (ret) {
1251 if (ret != -ERESTARTSYS)
1252 DRM_ERROR("set_domain failed: %d\n", ret);
1253 return ret;
1256 if (obj_priv->agp_mem != NULL) {
1257 drm_unbind_agp(obj_priv->agp_mem);
1258 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1259 obj_priv->agp_mem = NULL;
1262 BUG_ON(obj_priv->active);
1264 /* blow away mappings if mapped through GTT */
1265 offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1266 if (dev->dev_mapping)
1267 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1269 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1270 i915_gem_clear_fence_reg(obj);
1272 i915_gem_object_free_page_list(obj);
1274 if (obj_priv->gtt_space) {
1275 atomic_dec(&dev->gtt_count);
1276 atomic_sub(obj->size, &dev->gtt_memory);
1278 drm_mm_put_block(obj_priv->gtt_space);
1279 obj_priv->gtt_space = NULL;
1282 /* Remove ourselves from the LRU list if present. */
1283 if (!list_empty(&obj_priv->list))
1284 list_del_init(&obj_priv->list);
1286 return 0;
1289 static int
1290 i915_gem_evict_something(struct drm_device *dev)
1292 drm_i915_private_t *dev_priv = dev->dev_private;
1293 struct drm_gem_object *obj;
1294 struct drm_i915_gem_object *obj_priv;
1295 int ret = 0;
1297 for (;;) {
1298 /* If there's an inactive buffer available now, grab it
1299 * and be done.
1301 if (!list_empty(&dev_priv->mm.inactive_list)) {
1302 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1303 struct drm_i915_gem_object,
1304 list);
1305 obj = obj_priv->obj;
1306 BUG_ON(obj_priv->pin_count != 0);
1307 #if WATCH_LRU
1308 DRM_INFO("%s: evicting %p\n", __func__, obj);
1309 #endif
1310 BUG_ON(obj_priv->active);
1312 /* Wait on the rendering and unbind the buffer. */
1313 ret = i915_gem_object_unbind(obj);
1314 break;
1317 /* If we didn't get anything, but the ring is still processing
1318 * things, wait for one of those things to finish and hopefully
1319 * leave us a buffer to evict.
1321 if (!list_empty(&dev_priv->mm.request_list)) {
1322 struct drm_i915_gem_request *request;
1324 request = list_first_entry(&dev_priv->mm.request_list,
1325 struct drm_i915_gem_request,
1326 list);
1328 ret = i915_wait_request(dev, request->seqno);
1329 if (ret)
1330 break;
1332 /* if waiting caused an object to become inactive,
1333 * then loop around and wait for it. Otherwise, we
1334 * assume that waiting freed and unbound something,
1335 * so there should now be some space in the GTT
1337 if (!list_empty(&dev_priv->mm.inactive_list))
1338 continue;
1339 break;
1342 /* If we didn't have anything on the request list but there
1343 * are buffers awaiting a flush, emit one and try again.
1344 * When we wait on it, those buffers waiting for that flush
1345 * will get moved to inactive.
1347 if (!list_empty(&dev_priv->mm.flushing_list)) {
1348 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1349 struct drm_i915_gem_object,
1350 list);
1351 obj = obj_priv->obj;
1353 i915_gem_flush(dev,
1354 obj->write_domain,
1355 obj->write_domain);
1356 i915_add_request(dev, obj->write_domain);
1358 obj = NULL;
1359 continue;
1362 DRM_ERROR("inactive empty %d request empty %d "
1363 "flushing empty %d\n",
1364 list_empty(&dev_priv->mm.inactive_list),
1365 list_empty(&dev_priv->mm.request_list),
1366 list_empty(&dev_priv->mm.flushing_list));
1367 /* If we didn't do any of the above, there's nothing to be done
1368 * and we just can't fit it in.
1370 return -ENOMEM;
1372 return ret;
1375 static int
1376 i915_gem_evict_everything(struct drm_device *dev)
1378 int ret;
1380 for (;;) {
1381 ret = i915_gem_evict_something(dev);
1382 if (ret != 0)
1383 break;
1385 if (ret == -ENOMEM)
1386 return 0;
1387 return ret;
1390 static int
1391 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1393 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1394 int page_count, i;
1395 struct address_space *mapping;
1396 struct inode *inode;
1397 struct page *page;
1398 int ret;
1400 if (obj_priv->page_list)
1401 return 0;
1403 /* Get the list of pages out of our struct file. They'll be pinned
1404 * at this point until we release them.
1406 page_count = obj->size / PAGE_SIZE;
1407 BUG_ON(obj_priv->page_list != NULL);
1408 obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1409 DRM_MEM_DRIVER);
1410 if (obj_priv->page_list == NULL) {
1411 DRM_ERROR("Faled to allocate page list\n");
1412 return -ENOMEM;
1415 inode = obj->filp->f_path.dentry->d_inode;
1416 mapping = inode->i_mapping;
1417 for (i = 0; i < page_count; i++) {
1418 page = read_mapping_page(mapping, i, NULL);
1419 if (IS_ERR(page)) {
1420 ret = PTR_ERR(page);
1421 DRM_ERROR("read_mapping_page failed: %d\n", ret);
1422 i915_gem_object_free_page_list(obj);
1423 return ret;
1425 obj_priv->page_list[i] = page;
1427 return 0;
1430 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
1432 struct drm_gem_object *obj = reg->obj;
1433 struct drm_device *dev = obj->dev;
1434 drm_i915_private_t *dev_priv = dev->dev_private;
1435 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1436 int regnum = obj_priv->fence_reg;
1437 uint64_t val;
1439 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
1440 0xfffff000) << 32;
1441 val |= obj_priv->gtt_offset & 0xfffff000;
1442 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1443 if (obj_priv->tiling_mode == I915_TILING_Y)
1444 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1445 val |= I965_FENCE_REG_VALID;
1447 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
1450 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
1452 struct drm_gem_object *obj = reg->obj;
1453 struct drm_device *dev = obj->dev;
1454 drm_i915_private_t *dev_priv = dev->dev_private;
1455 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1456 int regnum = obj_priv->fence_reg;
1457 int tile_width;
1458 uint32_t val;
1459 uint32_t pitch_val;
1461 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1462 (obj_priv->gtt_offset & (obj->size - 1))) {
1463 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
1464 __func__, obj_priv->gtt_offset, obj->size);
1465 return;
1468 if (obj_priv->tiling_mode == I915_TILING_Y &&
1469 HAS_128_BYTE_Y_TILING(dev))
1470 tile_width = 128;
1471 else
1472 tile_width = 512;
1474 /* Note: pitch better be a power of two tile widths */
1475 pitch_val = obj_priv->stride / tile_width;
1476 pitch_val = ffs(pitch_val) - 1;
1478 val = obj_priv->gtt_offset;
1479 if (obj_priv->tiling_mode == I915_TILING_Y)
1480 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1481 val |= I915_FENCE_SIZE_BITS(obj->size);
1482 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1483 val |= I830_FENCE_REG_VALID;
1485 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1488 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
1490 struct drm_gem_object *obj = reg->obj;
1491 struct drm_device *dev = obj->dev;
1492 drm_i915_private_t *dev_priv = dev->dev_private;
1493 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1494 int regnum = obj_priv->fence_reg;
1495 uint32_t val;
1496 uint32_t pitch_val;
1498 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1499 (obj_priv->gtt_offset & (obj->size - 1))) {
1500 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1501 __func__, obj_priv->gtt_offset);
1502 return;
1505 pitch_val = (obj_priv->stride / 128) - 1;
1507 val = obj_priv->gtt_offset;
1508 if (obj_priv->tiling_mode == I915_TILING_Y)
1509 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1510 val |= I830_FENCE_SIZE_BITS(obj->size);
1511 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1512 val |= I830_FENCE_REG_VALID;
1514 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1519 * i915_gem_object_get_fence_reg - set up a fence reg for an object
1520 * @obj: object to map through a fence reg
1521 * @write: object is about to be written
1523 * When mapping objects through the GTT, userspace wants to be able to write
1524 * to them without having to worry about swizzling if the object is tiled.
1526 * This function walks the fence regs looking for a free one for @obj,
1527 * stealing one if it can't find any.
1529 * It then sets up the reg based on the object's properties: address, pitch
1530 * and tiling format.
1532 static int
1533 i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
1535 struct drm_device *dev = obj->dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1538 struct drm_i915_fence_reg *reg = NULL;
1539 int i, ret;
1541 switch (obj_priv->tiling_mode) {
1542 case I915_TILING_NONE:
1543 WARN(1, "allocating a fence for non-tiled object?\n");
1544 break;
1545 case I915_TILING_X:
1546 if (!obj_priv->stride)
1547 return -EINVAL;
1548 WARN((obj_priv->stride & (512 - 1)),
1549 "object 0x%08x is X tiled but has non-512B pitch\n",
1550 obj_priv->gtt_offset);
1551 break;
1552 case I915_TILING_Y:
1553 if (!obj_priv->stride)
1554 return -EINVAL;
1555 WARN((obj_priv->stride & (128 - 1)),
1556 "object 0x%08x is Y tiled but has non-128B pitch\n",
1557 obj_priv->gtt_offset);
1558 break;
1561 /* First try to find a free reg */
1562 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1563 reg = &dev_priv->fence_regs[i];
1564 if (!reg->obj)
1565 break;
1568 /* None available, try to steal one or wait for a user to finish */
1569 if (i == dev_priv->num_fence_regs) {
1570 struct drm_i915_gem_object *old_obj_priv = NULL;
1571 loff_t offset;
1573 try_again:
1574 /* Could try to use LRU here instead... */
1575 for (i = dev_priv->fence_reg_start;
1576 i < dev_priv->num_fence_regs; i++) {
1577 reg = &dev_priv->fence_regs[i];
1578 old_obj_priv = reg->obj->driver_private;
1579 if (!old_obj_priv->pin_count)
1580 break;
1584 * Now things get ugly... we have to wait for one of the
1585 * objects to finish before trying again.
1587 if (i == dev_priv->num_fence_regs) {
1588 ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
1589 if (ret) {
1590 WARN(ret != -ERESTARTSYS,
1591 "switch to GTT domain failed: %d\n", ret);
1592 return ret;
1594 goto try_again;
1598 * Zap this virtual mapping so we can set up a fence again
1599 * for this object next time we need it.
1601 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
1602 if (dev->dev_mapping)
1603 unmap_mapping_range(dev->dev_mapping, offset,
1604 reg->obj->size, 1);
1605 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
1608 obj_priv->fence_reg = i;
1609 reg->obj = obj;
1611 if (IS_I965G(dev))
1612 i965_write_fence_reg(reg);
1613 else if (IS_I9XX(dev))
1614 i915_write_fence_reg(reg);
1615 else
1616 i830_write_fence_reg(reg);
1618 return 0;
1622 * i915_gem_clear_fence_reg - clear out fence register info
1623 * @obj: object to clear
1625 * Zeroes out the fence register itself and clears out the associated
1626 * data structures in dev_priv and obj_priv.
1628 static void
1629 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
1631 struct drm_device *dev = obj->dev;
1632 drm_i915_private_t *dev_priv = dev->dev_private;
1633 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1635 if (IS_I965G(dev))
1636 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
1637 else
1638 I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
1640 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
1641 obj_priv->fence_reg = I915_FENCE_REG_NONE;
1645 * Finds free space in the GTT aperture and binds the object there.
1647 static int
1648 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1650 struct drm_device *dev = obj->dev;
1651 drm_i915_private_t *dev_priv = dev->dev_private;
1652 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1653 struct drm_mm_node *free_space;
1654 int page_count, ret;
1656 if (dev_priv->mm.suspended)
1657 return -EBUSY;
1658 if (alignment == 0)
1659 alignment = i915_gem_get_gtt_alignment(obj);
1660 if (alignment & (PAGE_SIZE - 1)) {
1661 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1662 return -EINVAL;
1665 search_free:
1666 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1667 obj->size, alignment, 0);
1668 if (free_space != NULL) {
1669 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1670 alignment);
1671 if (obj_priv->gtt_space != NULL) {
1672 obj_priv->gtt_space->private = obj;
1673 obj_priv->gtt_offset = obj_priv->gtt_space->start;
1676 if (obj_priv->gtt_space == NULL) {
1677 /* If the gtt is empty and we're still having trouble
1678 * fitting our object in, we're out of memory.
1680 #if WATCH_LRU
1681 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1682 #endif
1683 if (list_empty(&dev_priv->mm.inactive_list) &&
1684 list_empty(&dev_priv->mm.flushing_list) &&
1685 list_empty(&dev_priv->mm.active_list)) {
1686 DRM_ERROR("GTT full, but LRU list empty\n");
1687 return -ENOMEM;
1690 ret = i915_gem_evict_something(dev);
1691 if (ret != 0) {
1692 if (ret != -ERESTARTSYS)
1693 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1694 return ret;
1696 goto search_free;
1699 #if WATCH_BUF
1700 DRM_INFO("Binding object of size %d at 0x%08x\n",
1701 obj->size, obj_priv->gtt_offset);
1702 #endif
1703 ret = i915_gem_object_get_page_list(obj);
1704 if (ret) {
1705 drm_mm_put_block(obj_priv->gtt_space);
1706 obj_priv->gtt_space = NULL;
1707 return ret;
1710 page_count = obj->size / PAGE_SIZE;
1711 /* Create an AGP memory structure pointing at our pages, and bind it
1712 * into the GTT.
1714 obj_priv->agp_mem = drm_agp_bind_pages(dev,
1715 obj_priv->page_list,
1716 page_count,
1717 obj_priv->gtt_offset,
1718 obj_priv->agp_type);
1719 if (obj_priv->agp_mem == NULL) {
1720 i915_gem_object_free_page_list(obj);
1721 drm_mm_put_block(obj_priv->gtt_space);
1722 obj_priv->gtt_space = NULL;
1723 return -ENOMEM;
1725 atomic_inc(&dev->gtt_count);
1726 atomic_add(obj->size, &dev->gtt_memory);
1728 /* Assert that the object is not currently in any GPU domain. As it
1729 * wasn't in the GTT, there shouldn't be any way it could have been in
1730 * a GPU cache
1732 BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1733 BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1735 return 0;
1738 void
1739 i915_gem_clflush_object(struct drm_gem_object *obj)
1741 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1743 /* If we don't have a page list set up, then we're not pinned
1744 * to GPU, and we can ignore the cache flush because it'll happen
1745 * again at bind time.
1747 if (obj_priv->page_list == NULL)
1748 return;
1750 drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1753 /** Flushes any GPU write domain for the object if it's dirty. */
1754 static void
1755 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1757 struct drm_device *dev = obj->dev;
1758 uint32_t seqno;
1760 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1761 return;
1763 /* Queue the GPU write cache flushing we need. */
1764 i915_gem_flush(dev, 0, obj->write_domain);
1765 seqno = i915_add_request(dev, obj->write_domain);
1766 obj->write_domain = 0;
1767 i915_gem_object_move_to_active(obj, seqno);
1770 /** Flushes the GTT write domain for the object if it's dirty. */
1771 static void
1772 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1774 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1775 return;
1777 /* No actual flushing is required for the GTT write domain. Writes
1778 * to it immediately go to main memory as far as we know, so there's
1779 * no chipset flush. It also doesn't land in render cache.
1781 obj->write_domain = 0;
1784 /** Flushes the CPU write domain for the object if it's dirty. */
1785 static void
1786 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1788 struct drm_device *dev = obj->dev;
1790 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1791 return;
1793 i915_gem_clflush_object(obj);
1794 drm_agp_chipset_flush(dev);
1795 obj->write_domain = 0;
1799 * Moves a single object to the GTT read, and possibly write domain.
1801 * This function returns when the move is complete, including waiting on
1802 * flushes to occur.
1805 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1807 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1808 int ret;
1810 /* Not valid to be called on unbound objects. */
1811 if (obj_priv->gtt_space == NULL)
1812 return -EINVAL;
1814 i915_gem_object_flush_gpu_write_domain(obj);
1815 /* Wait on any GPU rendering and flushing to occur. */
1816 ret = i915_gem_object_wait_rendering(obj);
1817 if (ret != 0)
1818 return ret;
1820 /* If we're writing through the GTT domain, then CPU and GPU caches
1821 * will need to be invalidated at next use.
1823 if (write)
1824 obj->read_domains &= I915_GEM_DOMAIN_GTT;
1826 i915_gem_object_flush_cpu_write_domain(obj);
1828 /* It should now be out of any other write domains, and we can update
1829 * the domain values for our changes.
1831 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1832 obj->read_domains |= I915_GEM_DOMAIN_GTT;
1833 if (write) {
1834 obj->write_domain = I915_GEM_DOMAIN_GTT;
1835 obj_priv->dirty = 1;
1838 return 0;
1842 * Moves a single object to the CPU read, and possibly write domain.
1844 * This function returns when the move is complete, including waiting on
1845 * flushes to occur.
1847 static int
1848 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1850 struct drm_device *dev = obj->dev;
1851 int ret;
1853 i915_gem_object_flush_gpu_write_domain(obj);
1854 /* Wait on any GPU rendering and flushing to occur. */
1855 ret = i915_gem_object_wait_rendering(obj);
1856 if (ret != 0)
1857 return ret;
1859 i915_gem_object_flush_gtt_write_domain(obj);
1861 /* If we have a partially-valid cache of the object in the CPU,
1862 * finish invalidating it and free the per-page flags.
1864 i915_gem_object_set_to_full_cpu_read_domain(obj);
1866 /* Flush the CPU cache if it's still invalid. */
1867 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1868 i915_gem_clflush_object(obj);
1869 drm_agp_chipset_flush(dev);
1871 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1874 /* It should now be out of any other write domains, and we can update
1875 * the domain values for our changes.
1877 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1879 /* If we're writing through the CPU, then the GPU read domains will
1880 * need to be invalidated at next use.
1882 if (write) {
1883 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1884 obj->write_domain = I915_GEM_DOMAIN_CPU;
1887 return 0;
1891 * Set the next domain for the specified object. This
1892 * may not actually perform the necessary flushing/invaliding though,
1893 * as that may want to be batched with other set_domain operations
1895 * This is (we hope) the only really tricky part of gem. The goal
1896 * is fairly simple -- track which caches hold bits of the object
1897 * and make sure they remain coherent. A few concrete examples may
1898 * help to explain how it works. For shorthand, we use the notation
1899 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1900 * a pair of read and write domain masks.
1902 * Case 1: the batch buffer
1904 * 1. Allocated
1905 * 2. Written by CPU
1906 * 3. Mapped to GTT
1907 * 4. Read by GPU
1908 * 5. Unmapped from GTT
1909 * 6. Freed
1911 * Let's take these a step at a time
1913 * 1. Allocated
1914 * Pages allocated from the kernel may still have
1915 * cache contents, so we set them to (CPU, CPU) always.
1916 * 2. Written by CPU (using pwrite)
1917 * The pwrite function calls set_domain (CPU, CPU) and
1918 * this function does nothing (as nothing changes)
1919 * 3. Mapped by GTT
1920 * This function asserts that the object is not
1921 * currently in any GPU-based read or write domains
1922 * 4. Read by GPU
1923 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1924 * As write_domain is zero, this function adds in the
1925 * current read domains (CPU+COMMAND, 0).
1926 * flush_domains is set to CPU.
1927 * invalidate_domains is set to COMMAND
1928 * clflush is run to get data out of the CPU caches
1929 * then i915_dev_set_domain calls i915_gem_flush to
1930 * emit an MI_FLUSH and drm_agp_chipset_flush
1931 * 5. Unmapped from GTT
1932 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1933 * flush_domains and invalidate_domains end up both zero
1934 * so no flushing/invalidating happens
1935 * 6. Freed
1936 * yay, done
1938 * Case 2: The shared render buffer
1940 * 1. Allocated
1941 * 2. Mapped to GTT
1942 * 3. Read/written by GPU
1943 * 4. set_domain to (CPU,CPU)
1944 * 5. Read/written by CPU
1945 * 6. Read/written by GPU
1947 * 1. Allocated
1948 * Same as last example, (CPU, CPU)
1949 * 2. Mapped to GTT
1950 * Nothing changes (assertions find that it is not in the GPU)
1951 * 3. Read/written by GPU
1952 * execbuffer calls set_domain (RENDER, RENDER)
1953 * flush_domains gets CPU
1954 * invalidate_domains gets GPU
1955 * clflush (obj)
1956 * MI_FLUSH and drm_agp_chipset_flush
1957 * 4. set_domain (CPU, CPU)
1958 * flush_domains gets GPU
1959 * invalidate_domains gets CPU
1960 * wait_rendering (obj) to make sure all drawing is complete.
1961 * This will include an MI_FLUSH to get the data from GPU
1962 * to memory
1963 * clflush (obj) to invalidate the CPU cache
1964 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1965 * 5. Read/written by CPU
1966 * cache lines are loaded and dirtied
1967 * 6. Read written by GPU
1968 * Same as last GPU access
1970 * Case 3: The constant buffer
1972 * 1. Allocated
1973 * 2. Written by CPU
1974 * 3. Read by GPU
1975 * 4. Updated (written) by CPU again
1976 * 5. Read by GPU
1978 * 1. Allocated
1979 * (CPU, CPU)
1980 * 2. Written by CPU
1981 * (CPU, CPU)
1982 * 3. Read by GPU
1983 * (CPU+RENDER, 0)
1984 * flush_domains = CPU
1985 * invalidate_domains = RENDER
1986 * clflush (obj)
1987 * MI_FLUSH
1988 * drm_agp_chipset_flush
1989 * 4. Updated (written) by CPU again
1990 * (CPU, CPU)
1991 * flush_domains = 0 (no previous write domain)
1992 * invalidate_domains = 0 (no new read domains)
1993 * 5. Read by GPU
1994 * (CPU+RENDER, 0)
1995 * flush_domains = CPU
1996 * invalidate_domains = RENDER
1997 * clflush (obj)
1998 * MI_FLUSH
1999 * drm_agp_chipset_flush
2001 static void
2002 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
2003 uint32_t read_domains,
2004 uint32_t write_domain)
2006 struct drm_device *dev = obj->dev;
2007 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2008 uint32_t invalidate_domains = 0;
2009 uint32_t flush_domains = 0;
2011 BUG_ON(read_domains & I915_GEM_DOMAIN_CPU);
2012 BUG_ON(write_domain == I915_GEM_DOMAIN_CPU);
2014 #if WATCH_BUF
2015 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2016 __func__, obj,
2017 obj->read_domains, read_domains,
2018 obj->write_domain, write_domain);
2019 #endif
2021 * If the object isn't moving to a new write domain,
2022 * let the object stay in multiple read domains
2024 if (write_domain == 0)
2025 read_domains |= obj->read_domains;
2026 else
2027 obj_priv->dirty = 1;
2030 * Flush the current write domain if
2031 * the new read domains don't match. Invalidate
2032 * any read domains which differ from the old
2033 * write domain
2035 if (obj->write_domain && obj->write_domain != read_domains) {
2036 flush_domains |= obj->write_domain;
2037 invalidate_domains |= read_domains & ~obj->write_domain;
2040 * Invalidate any read caches which may have
2041 * stale data. That is, any new read domains.
2043 invalidate_domains |= read_domains & ~obj->read_domains;
2044 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2045 #if WATCH_BUF
2046 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2047 __func__, flush_domains, invalidate_domains);
2048 #endif
2049 i915_gem_clflush_object(obj);
2052 if ((write_domain | flush_domains) != 0)
2053 obj->write_domain = write_domain;
2054 obj->read_domains = read_domains;
2056 dev->invalidate_domains |= invalidate_domains;
2057 dev->flush_domains |= flush_domains;
2058 #if WATCH_BUF
2059 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2060 __func__,
2061 obj->read_domains, obj->write_domain,
2062 dev->invalidate_domains, dev->flush_domains);
2063 #endif
2067 * Moves the object from a partially CPU read to a full one.
2069 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2070 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2072 static void
2073 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2075 struct drm_device *dev = obj->dev;
2076 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2078 if (!obj_priv->page_cpu_valid)
2079 return;
2081 /* If we're partially in the CPU read domain, finish moving it in.
2083 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2084 int i;
2086 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2087 if (obj_priv->page_cpu_valid[i])
2088 continue;
2089 drm_clflush_pages(obj_priv->page_list + i, 1);
2091 drm_agp_chipset_flush(dev);
2094 /* Free the page_cpu_valid mappings which are now stale, whether
2095 * or not we've got I915_GEM_DOMAIN_CPU.
2097 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2098 DRM_MEM_DRIVER);
2099 obj_priv->page_cpu_valid = NULL;
2103 * Set the CPU read domain on a range of the object.
2105 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2106 * not entirely valid. The page_cpu_valid member of the object flags which
2107 * pages have been flushed, and will be respected by
2108 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2109 * of the whole object.
2111 * This function returns when the move is complete, including waiting on
2112 * flushes to occur.
2114 static int
2115 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2116 uint64_t offset, uint64_t size)
2118 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2119 int i, ret;
2121 if (offset == 0 && size == obj->size)
2122 return i915_gem_object_set_to_cpu_domain(obj, 0);
2124 i915_gem_object_flush_gpu_write_domain(obj);
2125 /* Wait on any GPU rendering and flushing to occur. */
2126 ret = i915_gem_object_wait_rendering(obj);
2127 if (ret != 0)
2128 return ret;
2129 i915_gem_object_flush_gtt_write_domain(obj);
2131 /* If we're already fully in the CPU read domain, we're done. */
2132 if (obj_priv->page_cpu_valid == NULL &&
2133 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2134 return 0;
2136 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2137 * newly adding I915_GEM_DOMAIN_CPU
2139 if (obj_priv->page_cpu_valid == NULL) {
2140 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2141 DRM_MEM_DRIVER);
2142 if (obj_priv->page_cpu_valid == NULL)
2143 return -ENOMEM;
2144 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2145 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2147 /* Flush the cache on any pages that are still invalid from the CPU's
2148 * perspective.
2150 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2151 i++) {
2152 if (obj_priv->page_cpu_valid[i])
2153 continue;
2155 drm_clflush_pages(obj_priv->page_list + i, 1);
2157 obj_priv->page_cpu_valid[i] = 1;
2160 /* It should now be out of any other write domains, and we can update
2161 * the domain values for our changes.
2163 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2165 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2167 return 0;
2171 * Pin an object to the GTT and evaluate the relocations landing in it.
2173 static int
2174 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2175 struct drm_file *file_priv,
2176 struct drm_i915_gem_exec_object *entry)
2178 struct drm_device *dev = obj->dev;
2179 drm_i915_private_t *dev_priv = dev->dev_private;
2180 struct drm_i915_gem_relocation_entry reloc;
2181 struct drm_i915_gem_relocation_entry __user *relocs;
2182 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2183 int i, ret;
2184 void __iomem *reloc_page;
2186 /* Choose the GTT offset for our buffer and put it there. */
2187 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2188 if (ret)
2189 return ret;
2191 entry->offset = obj_priv->gtt_offset;
2193 relocs = (struct drm_i915_gem_relocation_entry __user *)
2194 (uintptr_t) entry->relocs_ptr;
2195 /* Apply the relocations, using the GTT aperture to avoid cache
2196 * flushing requirements.
2198 for (i = 0; i < entry->relocation_count; i++) {
2199 struct drm_gem_object *target_obj;
2200 struct drm_i915_gem_object *target_obj_priv;
2201 uint32_t reloc_val, reloc_offset;
2202 uint32_t __iomem *reloc_entry;
2204 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
2205 if (ret != 0) {
2206 i915_gem_object_unpin(obj);
2207 return ret;
2210 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2211 reloc.target_handle);
2212 if (target_obj == NULL) {
2213 i915_gem_object_unpin(obj);
2214 return -EBADF;
2216 target_obj_priv = target_obj->driver_private;
2218 /* The target buffer should have appeared before us in the
2219 * exec_object list, so it should have a GTT space bound by now.
2221 if (target_obj_priv->gtt_space == NULL) {
2222 DRM_ERROR("No GTT space found for object %d\n",
2223 reloc.target_handle);
2224 drm_gem_object_unreference(target_obj);
2225 i915_gem_object_unpin(obj);
2226 return -EINVAL;
2229 if (reloc.offset > obj->size - 4) {
2230 DRM_ERROR("Relocation beyond object bounds: "
2231 "obj %p target %d offset %d size %d.\n",
2232 obj, reloc.target_handle,
2233 (int) reloc.offset, (int) obj->size);
2234 drm_gem_object_unreference(target_obj);
2235 i915_gem_object_unpin(obj);
2236 return -EINVAL;
2238 if (reloc.offset & 3) {
2239 DRM_ERROR("Relocation not 4-byte aligned: "
2240 "obj %p target %d offset %d.\n",
2241 obj, reloc.target_handle,
2242 (int) reloc.offset);
2243 drm_gem_object_unreference(target_obj);
2244 i915_gem_object_unpin(obj);
2245 return -EINVAL;
2248 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
2249 reloc.read_domains & I915_GEM_DOMAIN_CPU) {
2250 DRM_ERROR("reloc with read/write CPU domains: "
2251 "obj %p target %d offset %d "
2252 "read %08x write %08x",
2253 obj, reloc.target_handle,
2254 (int) reloc.offset,
2255 reloc.read_domains,
2256 reloc.write_domain);
2257 return -EINVAL;
2260 if (reloc.write_domain && target_obj->pending_write_domain &&
2261 reloc.write_domain != target_obj->pending_write_domain) {
2262 DRM_ERROR("Write domain conflict: "
2263 "obj %p target %d offset %d "
2264 "new %08x old %08x\n",
2265 obj, reloc.target_handle,
2266 (int) reloc.offset,
2267 reloc.write_domain,
2268 target_obj->pending_write_domain);
2269 drm_gem_object_unreference(target_obj);
2270 i915_gem_object_unpin(obj);
2271 return -EINVAL;
2274 #if WATCH_RELOC
2275 DRM_INFO("%s: obj %p offset %08x target %d "
2276 "read %08x write %08x gtt %08x "
2277 "presumed %08x delta %08x\n",
2278 __func__,
2279 obj,
2280 (int) reloc.offset,
2281 (int) reloc.target_handle,
2282 (int) reloc.read_domains,
2283 (int) reloc.write_domain,
2284 (int) target_obj_priv->gtt_offset,
2285 (int) reloc.presumed_offset,
2286 reloc.delta);
2287 #endif
2289 target_obj->pending_read_domains |= reloc.read_domains;
2290 target_obj->pending_write_domain |= reloc.write_domain;
2292 /* If the relocation already has the right value in it, no
2293 * more work needs to be done.
2295 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
2296 drm_gem_object_unreference(target_obj);
2297 continue;
2300 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2301 if (ret != 0) {
2302 drm_gem_object_unreference(target_obj);
2303 i915_gem_object_unpin(obj);
2304 return -EINVAL;
2307 /* Map the page containing the relocation we're going to
2308 * perform.
2310 reloc_offset = obj_priv->gtt_offset + reloc.offset;
2311 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2312 (reloc_offset &
2313 ~(PAGE_SIZE - 1)));
2314 reloc_entry = (uint32_t __iomem *)(reloc_page +
2315 (reloc_offset & (PAGE_SIZE - 1)));
2316 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
2318 #if WATCH_BUF
2319 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2320 obj, (unsigned int) reloc.offset,
2321 readl(reloc_entry), reloc_val);
2322 #endif
2323 writel(reloc_val, reloc_entry);
2324 io_mapping_unmap_atomic(reloc_page);
2326 /* Write the updated presumed offset for this entry back out
2327 * to the user.
2329 reloc.presumed_offset = target_obj_priv->gtt_offset;
2330 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
2331 if (ret != 0) {
2332 drm_gem_object_unreference(target_obj);
2333 i915_gem_object_unpin(obj);
2334 return ret;
2337 drm_gem_object_unreference(target_obj);
2340 #if WATCH_BUF
2341 if (0)
2342 i915_gem_dump_object(obj, 128, __func__, ~0);
2343 #endif
2344 return 0;
2347 /** Dispatch a batchbuffer to the ring
2349 static int
2350 i915_dispatch_gem_execbuffer(struct drm_device *dev,
2351 struct drm_i915_gem_execbuffer *exec,
2352 uint64_t exec_offset)
2354 drm_i915_private_t *dev_priv = dev->dev_private;
2355 struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
2356 (uintptr_t) exec->cliprects_ptr;
2357 int nbox = exec->num_cliprects;
2358 int i = 0, count;
2359 uint32_t exec_start, exec_len;
2360 RING_LOCALS;
2362 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
2363 exec_len = (uint32_t) exec->batch_len;
2365 if ((exec_start | exec_len) & 0x7) {
2366 DRM_ERROR("alignment\n");
2367 return -EINVAL;
2370 if (!exec_start)
2371 return -EINVAL;
2373 count = nbox ? nbox : 1;
2375 for (i = 0; i < count; i++) {
2376 if (i < nbox) {
2377 int ret = i915_emit_box(dev, boxes, i,
2378 exec->DR1, exec->DR4);
2379 if (ret)
2380 return ret;
2383 if (IS_I830(dev) || IS_845G(dev)) {
2384 BEGIN_LP_RING(4);
2385 OUT_RING(MI_BATCH_BUFFER);
2386 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2387 OUT_RING(exec_start + exec_len - 4);
2388 OUT_RING(0);
2389 ADVANCE_LP_RING();
2390 } else {
2391 BEGIN_LP_RING(2);
2392 if (IS_I965G(dev)) {
2393 OUT_RING(MI_BATCH_BUFFER_START |
2394 (2 << 6) |
2395 MI_BATCH_NON_SECURE_I965);
2396 OUT_RING(exec_start);
2397 } else {
2398 OUT_RING(MI_BATCH_BUFFER_START |
2399 (2 << 6));
2400 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2402 ADVANCE_LP_RING();
2406 /* XXX breadcrumb */
2407 return 0;
2410 /* Throttle our rendering by waiting until the ring has completed our requests
2411 * emitted over 20 msec ago.
2413 * This should get us reasonable parallelism between CPU and GPU but also
2414 * relatively low latency when blocking on a particular request to finish.
2416 static int
2417 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
2419 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2420 int ret = 0;
2421 uint32_t seqno;
2423 mutex_lock(&dev->struct_mutex);
2424 seqno = i915_file_priv->mm.last_gem_throttle_seqno;
2425 i915_file_priv->mm.last_gem_throttle_seqno =
2426 i915_file_priv->mm.last_gem_seqno;
2427 if (seqno)
2428 ret = i915_wait_request(dev, seqno);
2429 mutex_unlock(&dev->struct_mutex);
2430 return ret;
2434 i915_gem_execbuffer(struct drm_device *dev, void *data,
2435 struct drm_file *file_priv)
2437 drm_i915_private_t *dev_priv = dev->dev_private;
2438 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2439 struct drm_i915_gem_execbuffer *args = data;
2440 struct drm_i915_gem_exec_object *exec_list = NULL;
2441 struct drm_gem_object **object_list = NULL;
2442 struct drm_gem_object *batch_obj;
2443 int ret, i, pinned = 0;
2444 uint64_t exec_offset;
2445 uint32_t seqno, flush_domains;
2446 int pin_tries;
2448 #if WATCH_EXEC
2449 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2450 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
2451 #endif
2453 if (args->buffer_count < 1) {
2454 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
2455 return -EINVAL;
2457 /* Copy in the exec list from userland */
2458 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
2459 DRM_MEM_DRIVER);
2460 object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
2461 DRM_MEM_DRIVER);
2462 if (exec_list == NULL || object_list == NULL) {
2463 DRM_ERROR("Failed to allocate exec or object list "
2464 "for %d buffers\n",
2465 args->buffer_count);
2466 ret = -ENOMEM;
2467 goto pre_mutex_err;
2469 ret = copy_from_user(exec_list,
2470 (struct drm_i915_relocation_entry __user *)
2471 (uintptr_t) args->buffers_ptr,
2472 sizeof(*exec_list) * args->buffer_count);
2473 if (ret != 0) {
2474 DRM_ERROR("copy %d exec entries failed %d\n",
2475 args->buffer_count, ret);
2476 goto pre_mutex_err;
2479 mutex_lock(&dev->struct_mutex);
2481 i915_verify_inactive(dev, __FILE__, __LINE__);
2483 if (dev_priv->mm.wedged) {
2484 DRM_ERROR("Execbuf while wedged\n");
2485 mutex_unlock(&dev->struct_mutex);
2486 ret = -EIO;
2487 goto pre_mutex_err;
2490 if (dev_priv->mm.suspended) {
2491 DRM_ERROR("Execbuf while VT-switched.\n");
2492 mutex_unlock(&dev->struct_mutex);
2493 ret = -EBUSY;
2494 goto pre_mutex_err;
2497 /* Look up object handles */
2498 for (i = 0; i < args->buffer_count; i++) {
2499 object_list[i] = drm_gem_object_lookup(dev, file_priv,
2500 exec_list[i].handle);
2501 if (object_list[i] == NULL) {
2502 DRM_ERROR("Invalid object handle %d at index %d\n",
2503 exec_list[i].handle, i);
2504 ret = -EBADF;
2505 goto err;
2509 /* Pin and relocate */
2510 for (pin_tries = 0; ; pin_tries++) {
2511 ret = 0;
2512 for (i = 0; i < args->buffer_count; i++) {
2513 object_list[i]->pending_read_domains = 0;
2514 object_list[i]->pending_write_domain = 0;
2515 ret = i915_gem_object_pin_and_relocate(object_list[i],
2516 file_priv,
2517 &exec_list[i]);
2518 if (ret)
2519 break;
2520 pinned = i + 1;
2522 /* success */
2523 if (ret == 0)
2524 break;
2526 /* error other than GTT full, or we've already tried again */
2527 if (ret != -ENOMEM || pin_tries >= 1) {
2528 if (ret != -ERESTARTSYS)
2529 DRM_ERROR("Failed to pin buffers %d\n", ret);
2530 goto err;
2533 /* unpin all of our buffers */
2534 for (i = 0; i < pinned; i++)
2535 i915_gem_object_unpin(object_list[i]);
2536 pinned = 0;
2538 /* evict everyone we can from the aperture */
2539 ret = i915_gem_evict_everything(dev);
2540 if (ret)
2541 goto err;
2544 /* Set the pending read domains for the batch buffer to COMMAND */
2545 batch_obj = object_list[args->buffer_count-1];
2546 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
2547 batch_obj->pending_write_domain = 0;
2549 i915_verify_inactive(dev, __FILE__, __LINE__);
2551 /* Zero the global flush/invalidate flags. These
2552 * will be modified as new domains are computed
2553 * for each object
2555 dev->invalidate_domains = 0;
2556 dev->flush_domains = 0;
2558 for (i = 0; i < args->buffer_count; i++) {
2559 struct drm_gem_object *obj = object_list[i];
2561 /* Compute new gpu domains and update invalidate/flush */
2562 i915_gem_object_set_to_gpu_domain(obj,
2563 obj->pending_read_domains,
2564 obj->pending_write_domain);
2567 i915_verify_inactive(dev, __FILE__, __LINE__);
2569 if (dev->invalidate_domains | dev->flush_domains) {
2570 #if WATCH_EXEC
2571 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2572 __func__,
2573 dev->invalidate_domains,
2574 dev->flush_domains);
2575 #endif
2576 i915_gem_flush(dev,
2577 dev->invalidate_domains,
2578 dev->flush_domains);
2579 if (dev->flush_domains)
2580 (void)i915_add_request(dev, dev->flush_domains);
2583 i915_verify_inactive(dev, __FILE__, __LINE__);
2585 #if WATCH_COHERENCY
2586 for (i = 0; i < args->buffer_count; i++) {
2587 i915_gem_object_check_coherency(object_list[i],
2588 exec_list[i].handle);
2590 #endif
2592 exec_offset = exec_list[args->buffer_count - 1].offset;
2594 #if WATCH_EXEC
2595 i915_gem_dump_object(object_list[args->buffer_count - 1],
2596 args->batch_len,
2597 __func__,
2598 ~0);
2599 #endif
2601 /* Exec the batchbuffer */
2602 ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2603 if (ret) {
2604 DRM_ERROR("dispatch failed %d\n", ret);
2605 goto err;
2609 * Ensure that the commands in the batch buffer are
2610 * finished before the interrupt fires
2612 flush_domains = i915_retire_commands(dev);
2614 i915_verify_inactive(dev, __FILE__, __LINE__);
2617 * Get a seqno representing the execution of the current buffer,
2618 * which we can wait on. We would like to mitigate these interrupts,
2619 * likely by only creating seqnos occasionally (so that we have
2620 * *some* interrupts representing completion of buffers that we can
2621 * wait on when trying to clear up gtt space).
2623 seqno = i915_add_request(dev, flush_domains);
2624 BUG_ON(seqno == 0);
2625 i915_file_priv->mm.last_gem_seqno = seqno;
2626 for (i = 0; i < args->buffer_count; i++) {
2627 struct drm_gem_object *obj = object_list[i];
2629 i915_gem_object_move_to_active(obj, seqno);
2630 #if WATCH_LRU
2631 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2632 #endif
2634 #if WATCH_LRU
2635 i915_dump_lru(dev, __func__);
2636 #endif
2638 i915_verify_inactive(dev, __FILE__, __LINE__);
2640 err:
2641 for (i = 0; i < pinned; i++)
2642 i915_gem_object_unpin(object_list[i]);
2644 for (i = 0; i < args->buffer_count; i++)
2645 drm_gem_object_unreference(object_list[i]);
2647 mutex_unlock(&dev->struct_mutex);
2649 if (!ret) {
2650 /* Copy the new buffer offsets back to the user's exec list. */
2651 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2652 (uintptr_t) args->buffers_ptr,
2653 exec_list,
2654 sizeof(*exec_list) * args->buffer_count);
2655 if (ret)
2656 DRM_ERROR("failed to copy %d exec entries "
2657 "back to user (%d)\n",
2658 args->buffer_count, ret);
2661 pre_mutex_err:
2662 drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2663 DRM_MEM_DRIVER);
2664 drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2665 DRM_MEM_DRIVER);
2667 return ret;
2671 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2673 struct drm_device *dev = obj->dev;
2674 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2675 int ret;
2677 i915_verify_inactive(dev, __FILE__, __LINE__);
2678 if (obj_priv->gtt_space == NULL) {
2679 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2680 if (ret != 0) {
2681 if (ret != -EBUSY && ret != -ERESTARTSYS)
2682 DRM_ERROR("Failure to bind: %d", ret);
2683 return ret;
2686 * Pre-965 chips need a fence register set up in order to
2687 * properly handle tiled surfaces.
2689 if (!IS_I965G(dev) &&
2690 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
2691 obj_priv->tiling_mode != I915_TILING_NONE)
2692 i915_gem_object_get_fence_reg(obj, true);
2694 obj_priv->pin_count++;
2696 /* If the object is not active and not pending a flush,
2697 * remove it from the inactive list
2699 if (obj_priv->pin_count == 1) {
2700 atomic_inc(&dev->pin_count);
2701 atomic_add(obj->size, &dev->pin_memory);
2702 if (!obj_priv->active &&
2703 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2704 I915_GEM_DOMAIN_GTT)) == 0 &&
2705 !list_empty(&obj_priv->list))
2706 list_del_init(&obj_priv->list);
2708 i915_verify_inactive(dev, __FILE__, __LINE__);
2710 return 0;
2713 void
2714 i915_gem_object_unpin(struct drm_gem_object *obj)
2716 struct drm_device *dev = obj->dev;
2717 drm_i915_private_t *dev_priv = dev->dev_private;
2718 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2720 i915_verify_inactive(dev, __FILE__, __LINE__);
2721 obj_priv->pin_count--;
2722 BUG_ON(obj_priv->pin_count < 0);
2723 BUG_ON(obj_priv->gtt_space == NULL);
2725 /* If the object is no longer pinned, and is
2726 * neither active nor being flushed, then stick it on
2727 * the inactive list
2729 if (obj_priv->pin_count == 0) {
2730 if (!obj_priv->active &&
2731 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2732 I915_GEM_DOMAIN_GTT)) == 0)
2733 list_move_tail(&obj_priv->list,
2734 &dev_priv->mm.inactive_list);
2735 atomic_dec(&dev->pin_count);
2736 atomic_sub(obj->size, &dev->pin_memory);
2738 i915_verify_inactive(dev, __FILE__, __LINE__);
2742 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2743 struct drm_file *file_priv)
2745 struct drm_i915_gem_pin *args = data;
2746 struct drm_gem_object *obj;
2747 struct drm_i915_gem_object *obj_priv;
2748 int ret;
2750 mutex_lock(&dev->struct_mutex);
2752 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2753 if (obj == NULL) {
2754 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2755 args->handle);
2756 mutex_unlock(&dev->struct_mutex);
2757 return -EBADF;
2759 obj_priv = obj->driver_private;
2761 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
2762 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2763 args->handle);
2764 drm_gem_object_unreference(obj);
2765 mutex_unlock(&dev->struct_mutex);
2766 return -EINVAL;
2769 obj_priv->user_pin_count++;
2770 obj_priv->pin_filp = file_priv;
2771 if (obj_priv->user_pin_count == 1) {
2772 ret = i915_gem_object_pin(obj, args->alignment);
2773 if (ret != 0) {
2774 drm_gem_object_unreference(obj);
2775 mutex_unlock(&dev->struct_mutex);
2776 return ret;
2780 /* XXX - flush the CPU caches for pinned objects
2781 * as the X server doesn't manage domains yet
2783 i915_gem_object_flush_cpu_write_domain(obj);
2784 args->offset = obj_priv->gtt_offset;
2785 drm_gem_object_unreference(obj);
2786 mutex_unlock(&dev->struct_mutex);
2788 return 0;
2792 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2793 struct drm_file *file_priv)
2795 struct drm_i915_gem_pin *args = data;
2796 struct drm_gem_object *obj;
2797 struct drm_i915_gem_object *obj_priv;
2799 mutex_lock(&dev->struct_mutex);
2801 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2802 if (obj == NULL) {
2803 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2804 args->handle);
2805 mutex_unlock(&dev->struct_mutex);
2806 return -EBADF;
2809 obj_priv = obj->driver_private;
2810 if (obj_priv->pin_filp != file_priv) {
2811 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2812 args->handle);
2813 drm_gem_object_unreference(obj);
2814 mutex_unlock(&dev->struct_mutex);
2815 return -EINVAL;
2817 obj_priv->user_pin_count--;
2818 if (obj_priv->user_pin_count == 0) {
2819 obj_priv->pin_filp = NULL;
2820 i915_gem_object_unpin(obj);
2823 drm_gem_object_unreference(obj);
2824 mutex_unlock(&dev->struct_mutex);
2825 return 0;
2829 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2830 struct drm_file *file_priv)
2832 struct drm_i915_gem_busy *args = data;
2833 struct drm_gem_object *obj;
2834 struct drm_i915_gem_object *obj_priv;
2836 mutex_lock(&dev->struct_mutex);
2837 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2838 if (obj == NULL) {
2839 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2840 args->handle);
2841 mutex_unlock(&dev->struct_mutex);
2842 return -EBADF;
2845 obj_priv = obj->driver_private;
2846 /* Don't count being on the flushing list against the object being
2847 * done. Otherwise, a buffer left on the flushing list but not getting
2848 * flushed (because nobody's flushing that domain) won't ever return
2849 * unbusy and get reused by libdrm's bo cache. The other expected
2850 * consumer of this interface, OpenGL's occlusion queries, also specs
2851 * that the objects get unbusy "eventually" without any interference.
2853 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
2855 drm_gem_object_unreference(obj);
2856 mutex_unlock(&dev->struct_mutex);
2857 return 0;
2861 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv)
2864 return i915_gem_ring_throttle(dev, file_priv);
2867 int i915_gem_init_object(struct drm_gem_object *obj)
2869 struct drm_i915_gem_object *obj_priv;
2871 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2872 if (obj_priv == NULL)
2873 return -ENOMEM;
2876 * We've just allocated pages from the kernel,
2877 * so they've just been written by the CPU with
2878 * zeros. They'll need to be clflushed before we
2879 * use them with the GPU.
2881 obj->write_domain = I915_GEM_DOMAIN_CPU;
2882 obj->read_domains = I915_GEM_DOMAIN_CPU;
2884 obj_priv->agp_type = AGP_USER_MEMORY;
2886 obj->driver_private = obj_priv;
2887 obj_priv->obj = obj;
2888 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2889 INIT_LIST_HEAD(&obj_priv->list);
2891 return 0;
2894 void i915_gem_free_object(struct drm_gem_object *obj)
2896 struct drm_device *dev = obj->dev;
2897 struct drm_gem_mm *mm = dev->mm_private;
2898 struct drm_map_list *list;
2899 struct drm_map *map;
2900 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2902 while (obj_priv->pin_count > 0)
2903 i915_gem_object_unpin(obj);
2905 if (obj_priv->phys_obj)
2906 i915_gem_detach_phys_object(dev, obj);
2908 i915_gem_object_unbind(obj);
2910 list = &obj->map_list;
2911 drm_ht_remove_item(&mm->offset_hash, &list->hash);
2913 if (list->file_offset_node) {
2914 drm_mm_put_block(list->file_offset_node);
2915 list->file_offset_node = NULL;
2918 map = list->map;
2919 if (map) {
2920 drm_free(map, sizeof(*map), DRM_MEM_DRIVER);
2921 list->map = NULL;
2924 drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2925 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2928 /** Unbinds all objects that are on the given buffer list. */
2929 static int
2930 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2932 struct drm_gem_object *obj;
2933 struct drm_i915_gem_object *obj_priv;
2934 int ret;
2936 while (!list_empty(head)) {
2937 obj_priv = list_first_entry(head,
2938 struct drm_i915_gem_object,
2939 list);
2940 obj = obj_priv->obj;
2942 if (obj_priv->pin_count != 0) {
2943 DRM_ERROR("Pinned object in unbind list\n");
2944 mutex_unlock(&dev->struct_mutex);
2945 return -EINVAL;
2948 ret = i915_gem_object_unbind(obj);
2949 if (ret != 0) {
2950 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2951 ret);
2952 mutex_unlock(&dev->struct_mutex);
2953 return ret;
2958 return 0;
2961 static int
2962 i915_gem_idle(struct drm_device *dev)
2964 drm_i915_private_t *dev_priv = dev->dev_private;
2965 uint32_t seqno, cur_seqno, last_seqno;
2966 int stuck, ret;
2968 mutex_lock(&dev->struct_mutex);
2970 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2971 mutex_unlock(&dev->struct_mutex);
2972 return 0;
2975 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2976 * We need to replace this with a semaphore, or something.
2978 dev_priv->mm.suspended = 1;
2980 /* Cancel the retire work handler, wait for it to finish if running
2982 mutex_unlock(&dev->struct_mutex);
2983 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2984 mutex_lock(&dev->struct_mutex);
2986 i915_kernel_lost_context(dev);
2988 /* Flush the GPU along with all non-CPU write domains
2990 i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2991 ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2992 seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
2994 if (seqno == 0) {
2995 mutex_unlock(&dev->struct_mutex);
2996 return -ENOMEM;
2999 dev_priv->mm.waiting_gem_seqno = seqno;
3000 last_seqno = 0;
3001 stuck = 0;
3002 for (;;) {
3003 cur_seqno = i915_get_gem_seqno(dev);
3004 if (i915_seqno_passed(cur_seqno, seqno))
3005 break;
3006 if (last_seqno == cur_seqno) {
3007 if (stuck++ > 100) {
3008 DRM_ERROR("hardware wedged\n");
3009 dev_priv->mm.wedged = 1;
3010 DRM_WAKEUP(&dev_priv->irq_queue);
3011 break;
3014 msleep(10);
3015 last_seqno = cur_seqno;
3017 dev_priv->mm.waiting_gem_seqno = 0;
3019 i915_gem_retire_requests(dev);
3021 if (!dev_priv->mm.wedged) {
3022 /* Active and flushing should now be empty as we've
3023 * waited for a sequence higher than any pending execbuffer
3025 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3026 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3027 /* Request should now be empty as we've also waited
3028 * for the last request in the list
3030 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3033 /* Empty the active and flushing lists to inactive. If there's
3034 * anything left at this point, it means that we're wedged and
3035 * nothing good's going to happen by leaving them there. So strip
3036 * the GPU domains and just stuff them onto inactive.
3038 while (!list_empty(&dev_priv->mm.active_list)) {
3039 struct drm_i915_gem_object *obj_priv;
3041 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3042 struct drm_i915_gem_object,
3043 list);
3044 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3045 i915_gem_object_move_to_inactive(obj_priv->obj);
3048 while (!list_empty(&dev_priv->mm.flushing_list)) {
3049 struct drm_i915_gem_object *obj_priv;
3051 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3052 struct drm_i915_gem_object,
3053 list);
3054 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3055 i915_gem_object_move_to_inactive(obj_priv->obj);
3059 /* Move all inactive buffers out of the GTT. */
3060 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3061 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3062 if (ret) {
3063 mutex_unlock(&dev->struct_mutex);
3064 return ret;
3067 i915_gem_cleanup_ringbuffer(dev);
3068 mutex_unlock(&dev->struct_mutex);
3070 return 0;
3073 static int
3074 i915_gem_init_hws(struct drm_device *dev)
3076 drm_i915_private_t *dev_priv = dev->dev_private;
3077 struct drm_gem_object *obj;
3078 struct drm_i915_gem_object *obj_priv;
3079 int ret;
3081 /* If we need a physical address for the status page, it's already
3082 * initialized at driver load time.
3084 if (!I915_NEED_GFX_HWS(dev))
3085 return 0;
3087 obj = drm_gem_object_alloc(dev, 4096);
3088 if (obj == NULL) {
3089 DRM_ERROR("Failed to allocate status page\n");
3090 return -ENOMEM;
3092 obj_priv = obj->driver_private;
3093 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3095 ret = i915_gem_object_pin(obj, 4096);
3096 if (ret != 0) {
3097 drm_gem_object_unreference(obj);
3098 return ret;
3101 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3103 dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
3104 if (dev_priv->hw_status_page == NULL) {
3105 DRM_ERROR("Failed to map status page.\n");
3106 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3107 drm_gem_object_unreference(obj);
3108 return -EINVAL;
3110 dev_priv->hws_obj = obj;
3111 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3112 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3113 I915_READ(HWS_PGA); /* posting read */
3114 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3116 return 0;
3120 i915_gem_init_ringbuffer(struct drm_device *dev)
3122 drm_i915_private_t *dev_priv = dev->dev_private;
3123 struct drm_gem_object *obj;
3124 struct drm_i915_gem_object *obj_priv;
3125 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
3126 int ret;
3127 u32 head;
3129 ret = i915_gem_init_hws(dev);
3130 if (ret != 0)
3131 return ret;
3133 obj = drm_gem_object_alloc(dev, 128 * 1024);
3134 if (obj == NULL) {
3135 DRM_ERROR("Failed to allocate ringbuffer\n");
3136 return -ENOMEM;
3138 obj_priv = obj->driver_private;
3140 ret = i915_gem_object_pin(obj, 4096);
3141 if (ret != 0) {
3142 drm_gem_object_unreference(obj);
3143 return ret;
3146 /* Set up the kernel mapping for the ring. */
3147 ring->Size = obj->size;
3148 ring->tail_mask = obj->size - 1;
3150 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3151 ring->map.size = obj->size;
3152 ring->map.type = 0;
3153 ring->map.flags = 0;
3154 ring->map.mtrr = 0;
3156 drm_core_ioremap_wc(&ring->map, dev);
3157 if (ring->map.handle == NULL) {
3158 DRM_ERROR("Failed to map ringbuffer.\n");
3159 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3160 drm_gem_object_unreference(obj);
3161 return -EINVAL;
3163 ring->ring_obj = obj;
3164 ring->virtual_start = ring->map.handle;
3166 /* Stop the ring if it's running. */
3167 I915_WRITE(PRB0_CTL, 0);
3168 I915_WRITE(PRB0_TAIL, 0);
3169 I915_WRITE(PRB0_HEAD, 0);
3171 /* Initialize the ring. */
3172 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
3173 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3175 /* G45 ring initialization fails to reset head to zero */
3176 if (head != 0) {
3177 DRM_ERROR("Ring head not reset to zero "
3178 "ctl %08x head %08x tail %08x start %08x\n",
3179 I915_READ(PRB0_CTL),
3180 I915_READ(PRB0_HEAD),
3181 I915_READ(PRB0_TAIL),
3182 I915_READ(PRB0_START));
3183 I915_WRITE(PRB0_HEAD, 0);
3185 DRM_ERROR("Ring head forced to zero "
3186 "ctl %08x head %08x tail %08x start %08x\n",
3187 I915_READ(PRB0_CTL),
3188 I915_READ(PRB0_HEAD),
3189 I915_READ(PRB0_TAIL),
3190 I915_READ(PRB0_START));
3193 I915_WRITE(PRB0_CTL,
3194 ((obj->size - 4096) & RING_NR_PAGES) |
3195 RING_NO_REPORT |
3196 RING_VALID);
3198 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3200 /* If the head is still not zero, the ring is dead */
3201 if (head != 0) {
3202 DRM_ERROR("Ring initialization failed "
3203 "ctl %08x head %08x tail %08x start %08x\n",
3204 I915_READ(PRB0_CTL),
3205 I915_READ(PRB0_HEAD),
3206 I915_READ(PRB0_TAIL),
3207 I915_READ(PRB0_START));
3208 return -EIO;
3211 /* Update our cache of the ring state */
3212 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3213 i915_kernel_lost_context(dev);
3214 else {
3215 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3216 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
3217 ring->space = ring->head - (ring->tail + 8);
3218 if (ring->space < 0)
3219 ring->space += ring->Size;
3222 return 0;
3225 void
3226 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3228 drm_i915_private_t *dev_priv = dev->dev_private;
3230 if (dev_priv->ring.ring_obj == NULL)
3231 return;
3233 drm_core_ioremapfree(&dev_priv->ring.map, dev);
3235 i915_gem_object_unpin(dev_priv->ring.ring_obj);
3236 drm_gem_object_unreference(dev_priv->ring.ring_obj);
3237 dev_priv->ring.ring_obj = NULL;
3238 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3240 if (dev_priv->hws_obj != NULL) {
3241 struct drm_gem_object *obj = dev_priv->hws_obj;
3242 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3244 kunmap(obj_priv->page_list[0]);
3245 i915_gem_object_unpin(obj);
3246 drm_gem_object_unreference(obj);
3247 dev_priv->hws_obj = NULL;
3248 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3249 dev_priv->hw_status_page = NULL;
3251 /* Write high address into HWS_PGA when disabling. */
3252 I915_WRITE(HWS_PGA, 0x1ffff000);
3257 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3258 struct drm_file *file_priv)
3260 drm_i915_private_t *dev_priv = dev->dev_private;
3261 int ret;
3263 if (drm_core_check_feature(dev, DRIVER_MODESET))
3264 return 0;
3266 if (dev_priv->mm.wedged) {
3267 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3268 dev_priv->mm.wedged = 0;
3271 mutex_lock(&dev->struct_mutex);
3272 dev_priv->mm.suspended = 0;
3274 ret = i915_gem_init_ringbuffer(dev);
3275 if (ret != 0)
3276 return ret;
3278 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3279 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3280 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3281 BUG_ON(!list_empty(&dev_priv->mm.request_list));
3282 mutex_unlock(&dev->struct_mutex);
3284 drm_irq_install(dev);
3286 return 0;
3290 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3291 struct drm_file *file_priv)
3293 int ret;
3295 if (drm_core_check_feature(dev, DRIVER_MODESET))
3296 return 0;
3298 ret = i915_gem_idle(dev);
3299 drm_irq_uninstall(dev);
3301 return ret;
3304 void
3305 i915_gem_lastclose(struct drm_device *dev)
3307 int ret;
3309 if (drm_core_check_feature(dev, DRIVER_MODESET))
3310 return;
3312 ret = i915_gem_idle(dev);
3313 if (ret)
3314 DRM_ERROR("failed to idle hardware: %d\n", ret);
3317 void
3318 i915_gem_load(struct drm_device *dev)
3320 drm_i915_private_t *dev_priv = dev->dev_private;
3322 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3323 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3324 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3325 INIT_LIST_HEAD(&dev_priv->mm.request_list);
3326 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3327 i915_gem_retire_work_handler);
3328 dev_priv->mm.next_gem_seqno = 1;
3330 /* Old X drivers will take 0-2 for front, back, depth buffers */
3331 dev_priv->fence_reg_start = 3;
3333 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3334 dev_priv->num_fence_regs = 16;
3335 else
3336 dev_priv->num_fence_regs = 8;
3338 i915_gem_detect_bit_6_swizzle(dev);
3342 * Create a physically contiguous memory object for this object
3343 * e.g. for cursor + overlay regs
3345 int i915_gem_init_phys_object(struct drm_device *dev,
3346 int id, int size)
3348 drm_i915_private_t *dev_priv = dev->dev_private;
3349 struct drm_i915_gem_phys_object *phys_obj;
3350 int ret;
3352 if (dev_priv->mm.phys_objs[id - 1] || !size)
3353 return 0;
3355 phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3356 if (!phys_obj)
3357 return -ENOMEM;
3359 phys_obj->id = id;
3361 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
3362 if (!phys_obj->handle) {
3363 ret = -ENOMEM;
3364 goto kfree_obj;
3366 #ifdef CONFIG_X86
3367 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3368 #endif
3370 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3372 return 0;
3373 kfree_obj:
3374 drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3375 return ret;
3378 void i915_gem_free_phys_object(struct drm_device *dev, int id)
3380 drm_i915_private_t *dev_priv = dev->dev_private;
3381 struct drm_i915_gem_phys_object *phys_obj;
3383 if (!dev_priv->mm.phys_objs[id - 1])
3384 return;
3386 phys_obj = dev_priv->mm.phys_objs[id - 1];
3387 if (phys_obj->cur_obj) {
3388 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3391 #ifdef CONFIG_X86
3392 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3393 #endif
3394 drm_pci_free(dev, phys_obj->handle);
3395 kfree(phys_obj);
3396 dev_priv->mm.phys_objs[id - 1] = NULL;
3399 void i915_gem_free_all_phys_object(struct drm_device *dev)
3401 int i;
3403 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3404 i915_gem_free_phys_object(dev, i);
3407 void i915_gem_detach_phys_object(struct drm_device *dev,
3408 struct drm_gem_object *obj)
3410 struct drm_i915_gem_object *obj_priv;
3411 int i;
3412 int ret;
3413 int page_count;
3415 obj_priv = obj->driver_private;
3416 if (!obj_priv->phys_obj)
3417 return;
3419 ret = i915_gem_object_get_page_list(obj);
3420 if (ret)
3421 goto out;
3423 page_count = obj->size / PAGE_SIZE;
3425 for (i = 0; i < page_count; i++) {
3426 char *dst = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3427 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3429 memcpy(dst, src, PAGE_SIZE);
3430 kunmap_atomic(dst, KM_USER0);
3432 drm_clflush_pages(obj_priv->page_list, page_count);
3433 drm_agp_chipset_flush(dev);
3434 out:
3435 obj_priv->phys_obj->cur_obj = NULL;
3436 obj_priv->phys_obj = NULL;
3440 i915_gem_attach_phys_object(struct drm_device *dev,
3441 struct drm_gem_object *obj, int id)
3443 drm_i915_private_t *dev_priv = dev->dev_private;
3444 struct drm_i915_gem_object *obj_priv;
3445 int ret = 0;
3446 int page_count;
3447 int i;
3449 if (id > I915_MAX_PHYS_OBJECT)
3450 return -EINVAL;
3452 obj_priv = obj->driver_private;
3454 if (obj_priv->phys_obj) {
3455 if (obj_priv->phys_obj->id == id)
3456 return 0;
3457 i915_gem_detach_phys_object(dev, obj);
3461 /* create a new object */
3462 if (!dev_priv->mm.phys_objs[id - 1]) {
3463 ret = i915_gem_init_phys_object(dev, id,
3464 obj->size);
3465 if (ret) {
3466 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
3467 goto out;
3471 /* bind to the object */
3472 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
3473 obj_priv->phys_obj->cur_obj = obj;
3475 ret = i915_gem_object_get_page_list(obj);
3476 if (ret) {
3477 DRM_ERROR("failed to get page list\n");
3478 goto out;
3481 page_count = obj->size / PAGE_SIZE;
3483 for (i = 0; i < page_count; i++) {
3484 char *src = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3485 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3487 memcpy(dst, src, PAGE_SIZE);
3488 kunmap_atomic(src, KM_USER0);
3491 return 0;
3492 out:
3493 return ret;
3496 static int
3497 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
3498 struct drm_i915_gem_pwrite *args,
3499 struct drm_file *file_priv)
3501 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3502 void *obj_addr;
3503 int ret;
3504 char __user *user_data;
3506 user_data = (char __user *) (uintptr_t) args->data_ptr;
3507 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
3509 DRM_ERROR("obj_addr %p, %lld\n", obj_addr, args->size);
3510 ret = copy_from_user(obj_addr, user_data, args->size);
3511 if (ret)
3512 return -EFAULT;
3514 drm_agp_chipset_flush(dev);
3515 return 0;