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ath9k: Fix basic connectivity issue
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath9k / hw.c
blob55ed0830588bcae7aa00b9456c421da965f8afb3
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "core.h"
21 #include "hw.h"
22 #include "reg.h"
23 #include "phy.h"
24 #include "initvals.h"
25
26 static int btcoex_enable;
27 module_param(btcoex_enable, bool, 0);
28 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
29
30 #define ATH9K_CLOCK_RATE_CCK 22
31 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
32 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
33
34 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
35 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
36 enum ath9k_ht_macmode macmode);
37 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
38 struct ar5416_eeprom_def *pEepData,
39 u32 reg, u32 value);
40 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
41 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
42
43 /********************/
44 /* Helper Functions */
45 /********************/
46
47 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
48 {
49 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
50 if (!ah->ah_curchan) /* should really check for CCK instead */
51 return clks / ATH9K_CLOCK_RATE_CCK;
52 if (conf->channel->band == IEEE80211_BAND_2GHZ)
53 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
54 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
55 }
56
57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
58 {
59 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69 if (!ah->ah_curchan) /* should really check for CCK instead */
70 return usecs *ATH9K_CLOCK_RATE_CCK;
71 if (conf->channel->band == IEEE80211_BAND_2GHZ)
72 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
73 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
74 }
75
76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
77 {
78 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
79 if (conf_is_ht40(conf))
80 return ath9k_hw_mac_clks(ah, usecs) * 2;
81 else
82 return ath9k_hw_mac_clks(ah, usecs);
83 }
84
85 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
86 {
87 int i;
88
89 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
90 if ((REG_READ(ah, reg) & mask) == val)
91 return true;
92
93 udelay(AH_TIME_QUANTUM);
94 }
95
96 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
97 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
98 reg, REG_READ(ah, reg), mask, val);
99
100 return false;
101 }
102
103 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
104 {
105 u32 retval;
106 int i;
107
108 for (i = 0, retval = 0; i < n; i++) {
109 retval = (retval << 1) | (val & 1);
110 val >>= 1;
111 }
112 return retval;
113 }
114
115 bool ath9k_get_channel_edges(struct ath_hal *ah,
116 u16 flags, u16 *low,
117 u16 *high)
118 {
119 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
120
121 if (flags & CHANNEL_5GHZ) {
122 *low = pCap->low_5ghz_chan;
123 *high = pCap->high_5ghz_chan;
124 return true;
125 }
126 if ((flags & CHANNEL_2GHZ)) {
127 *low = pCap->low_2ghz_chan;
128 *high = pCap->high_2ghz_chan;
129 return true;
130 }
131 return false;
132 }
133
134 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
135 struct ath_rate_table *rates,
136 u32 frameLen, u16 rateix,
137 bool shortPreamble)
138 {
139 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
140 u32 kbps;
141
142 kbps = rates->info[rateix].ratekbps;
143
144 if (kbps == 0)
145 return 0;
146
147 switch (rates->info[rateix].phy) {
148 case WLAN_RC_PHY_CCK:
149 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
150 if (shortPreamble && rates->info[rateix].short_preamble)
151 phyTime >>= 1;
152 numBits = frameLen << 3;
153 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154 break;
155 case WLAN_RC_PHY_OFDM:
156 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
157 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158 numBits = OFDM_PLCP_BITS + (frameLen << 3);
159 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160 txTime = OFDM_SIFS_TIME_QUARTER
161 + OFDM_PREAMBLE_TIME_QUARTER
162 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
163 } else if (ah->ah_curchan &&
164 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
165 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166 numBits = OFDM_PLCP_BITS + (frameLen << 3);
167 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168 txTime = OFDM_SIFS_TIME_HALF +
169 OFDM_PREAMBLE_TIME_HALF
170 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171 } else {
172 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173 numBits = OFDM_PLCP_BITS + (frameLen << 3);
174 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
175 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
176 + (numSymbols * OFDM_SYMBOL_TIME);
177 }
178 break;
179 default:
180 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
181 "Unknown phy %u (rate ix %u)\n",
182 rates->info[rateix].phy, rateix);
183 txTime = 0;
184 break;
185 }
186
187 return txTime;
188 }
189
190 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
191 {
192 if (flags & CHANNEL_2GHZ) {
193 if (freq == 2484)
194 return 14;
195 if (freq < 2484)
196 return (freq - 2407) / 5;
197 else
198 return 15 + ((freq - 2512) / 20);
199 } else if (flags & CHANNEL_5GHZ) {
200 if (ath9k_regd_is_public_safety_sku(ah) &&
201 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
202 return ((freq * 10) +
203 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
204 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
205 return (freq - 4000) / 5;
206 } else {
207 return (freq - 5000) / 5;
208 }
209 } else {
210 if (freq == 2484)
211 return 14;
212 if (freq < 2484)
213 return (freq - 2407) / 5;
214 if (freq < 5000) {
215 if (ath9k_regd_is_public_safety_sku(ah)
216 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
217 return ((freq * 10) +
218 (((freq % 5) ==
219 2) ? 5 : 0) - 49400) / 5;
220 } else if (freq > 4900) {
221 return (freq - 4000) / 5;
222 } else {
223 return 15 + ((freq - 2512) / 20);
224 }
225 }
226 return (freq - 5000) / 5;
227 }
228 }
229
230 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
231 struct ath9k_channel *chan,
232 struct chan_centers *centers)
233 {
234 int8_t extoff;
235 struct ath_hal_5416 *ahp = AH5416(ah);
236
237 if (!IS_CHAN_HT40(chan)) {
238 centers->ctl_center = centers->ext_center =
239 centers->synth_center = chan->channel;
240 return;
241 }
242
243 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
244 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
245 centers->synth_center =
246 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
247 extoff = 1;
248 } else {
249 centers->synth_center =
250 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
251 extoff = -1;
252 }
253
254 centers->ctl_center =
255 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
256 centers->ext_center =
257 centers->synth_center + (extoff *
258 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
259 HT40_CHANNEL_CENTER_SHIFT : 15));
260
261 }
262
263 /******************/
264 /* Chip Revisions */
265 /******************/
266
267 static void ath9k_hw_read_revisions(struct ath_hal *ah)
268 {
269 u32 val;
270
271 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
272
273 if (val == 0xFF) {
274 val = REG_READ(ah, AR_SREV);
275 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
276 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
277 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
278 } else {
279 if (!AR_SREV_9100(ah))
280 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
281
282 ah->ah_macRev = val & AR_SREV_REVISION;
283
284 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
285 ah->ah_isPciExpress = true;
286 }
287 }
288
289 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
290 {
291 u32 val;
292 int i;
293
294 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
295
296 for (i = 0; i < 8; i++)
297 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
298 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
299 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
300
301 return ath9k_hw_reverse_bits(val, 8);
302 }
303
304 /************************************/
305 /* HW Attach, Detach, Init Routines */
306 /************************************/
307
308 static void ath9k_hw_disablepcie(struct ath_hal *ah)
309 {
310 if (!AR_SREV_9100(ah))
311 return;
312
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
322
323 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
324 }
325
326 static bool ath9k_hw_chip_test(struct ath_hal *ah)
327 {
328 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
329 u32 regHold[2];
330 u32 patternData[4] = { 0x55555555,
331 0xaaaaaaaa,
332 0x66666666,
333 0x99999999 };
334 int i, j;
335
336 for (i = 0; i < 2; i++) {
337 u32 addr = regAddr[i];
338 u32 wrData, rdData;
339
340 regHold[i] = REG_READ(ah, addr);
341 for (j = 0; j < 0x100; j++) {
342 wrData = (j << 16) | j;
343 REG_WRITE(ah, addr, wrData);
344 rdData = REG_READ(ah, addr);
345 if (rdData != wrData) {
346 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
347 "address test failed "
348 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
349 addr, wrData, rdData);
350 return false;
351 }
352 }
353 for (j = 0; j < 4; j++) {
354 wrData = patternData[j];
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (wrData != rdData) {
358 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
359 "address test failed "
360 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
361 addr, wrData, rdData);
362 return false;
363 }
364 }
365 REG_WRITE(ah, regAddr[i], regHold[i]);
366 }
367 udelay(100);
368 return true;
369 }
370
371 static const char *ath9k_hw_devname(u16 devid)
372 {
373 switch (devid) {
374 case AR5416_DEVID_PCI:
375 return "Atheros 5416";
376 case AR5416_DEVID_PCIE:
377 return "Atheros 5418";
378 case AR9160_DEVID_PCI:
379 return "Atheros 9160";
380 case AR9280_DEVID_PCI:
381 case AR9280_DEVID_PCIE:
382 return "Atheros 9280";
383 case AR9285_DEVID_PCIE:
384 return "Atheros 9285";
385 }
386
387 return NULL;
388 }
389
390 static void ath9k_hw_set_defaults(struct ath_hal *ah)
391 {
392 int i;
393
394 ah->ah_config.dma_beacon_response_time = 2;
395 ah->ah_config.sw_beacon_response_time = 10;
396 ah->ah_config.additional_swba_backoff = 0;
397 ah->ah_config.ack_6mb = 0x0;
398 ah->ah_config.cwm_ignore_extcca = 0;
399 ah->ah_config.pcie_powersave_enable = 0;
400 ah->ah_config.pcie_l1skp_enable = 0;
401 ah->ah_config.pcie_clock_req = 0;
402 ah->ah_config.pcie_power_reset = 0x100;
403 ah->ah_config.pcie_restore = 0;
404 ah->ah_config.pcie_waen = 0;
405 ah->ah_config.analog_shiftreg = 1;
406 ah->ah_config.ht_enable = 1;
407 ah->ah_config.ofdm_trig_low = 200;
408 ah->ah_config.ofdm_trig_high = 500;
409 ah->ah_config.cck_trig_high = 200;
410 ah->ah_config.cck_trig_low = 100;
411 ah->ah_config.enable_ani = 1;
412 ah->ah_config.noise_immunity_level = 4;
413 ah->ah_config.ofdm_weaksignal_det = 1;
414 ah->ah_config.cck_weaksignal_thr = 0;
415 ah->ah_config.spur_immunity_level = 2;
416 ah->ah_config.firstep_level = 0;
417 ah->ah_config.rssi_thr_high = 40;
418 ah->ah_config.rssi_thr_low = 7;
419 ah->ah_config.diversity_control = 0;
420 ah->ah_config.antenna_switch_swap = 0;
421
422 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
423 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
424 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
425 }
426
427 ah->ah_config.intr_mitigation = 1;
428 }
429
430 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
431 struct ath_softc *sc,
432 void __iomem *mem,
433 int *status)
434 {
435 static const u8 defbssidmask[ETH_ALEN] =
436 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
437 struct ath_hal_5416 *ahp;
438 struct ath_hal *ah;
439
440 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
441 if (ahp == NULL) {
442 DPRINTF(sc, ATH_DBG_FATAL,
443 "Cannot allocate memory for state block\n");
444 *status = -ENOMEM;
445 return NULL;
446 }
447
448 ah = &ahp->ah;
449 ah->ah_sc = sc;
450 ah->ah_sh = mem;
451 ah->ah_magic = AR5416_MAGIC;
452 ah->ah_countryCode = CTRY_DEFAULT;
453 ah->ah_devid = devid;
454 ah->ah_subvendorid = 0;
455
456 ah->ah_flags = 0;
457 if ((devid == AR5416_AR9100_DEVID))
458 ah->ah_macVersion = AR_SREV_VERSION_9100;
459 if (!AR_SREV_9100(ah))
460 ah->ah_flags = AH_USE_EEPROM;
461
462 ah->ah_powerLimit = MAX_RATE_POWER;
463 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
464 ahp->ah_atimWindow = 0;
465 ahp->ah_diversityControl = ah->ah_config.diversity_control;
466 ahp->ah_antennaSwitchSwap =
467 ah->ah_config.antenna_switch_swap;
468 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
469 ahp->ah_beaconInterval = 100;
470 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
471 ahp->ah_slottime = (u32) -1;
472 ahp->ah_acktimeout = (u32) -1;
473 ahp->ah_ctstimeout = (u32) -1;
474 ahp->ah_globaltxtimeout = (u32) -1;
475 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
476
477 ahp->ah_gBeaconRate = 0;
478
479 return ahp;
480 }
481
482 static int ath9k_hw_rfattach(struct ath_hal *ah)
483 {
484 bool rfStatus = false;
485 int ecode = 0;
486
487 rfStatus = ath9k_hw_init_rf(ah, &ecode);
488 if (!rfStatus) {
489 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
490 "RF setup failed, status %u\n", ecode);
491 return ecode;
492 }
493
494 return 0;
495 }
496
497 static int ath9k_hw_rf_claim(struct ath_hal *ah)
498 {
499 u32 val;
500
501 REG_WRITE(ah, AR_PHY(0), 0x00000007);
502
503 val = ath9k_hw_get_radiorev(ah);
504 switch (val & AR_RADIO_SREV_MAJOR) {
505 case 0:
506 val = AR_RAD5133_SREV_MAJOR;
507 break;
508 case AR_RAD5133_SREV_MAJOR:
509 case AR_RAD5122_SREV_MAJOR:
510 case AR_RAD2133_SREV_MAJOR:
511 case AR_RAD2122_SREV_MAJOR:
512 break;
513 default:
514 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
515 "5G Radio Chip Rev 0x%02X is not "
516 "supported by this driver\n",
517 ah->ah_analog5GhzRev);
518 return -EOPNOTSUPP;
519 }
520
521 ah->ah_analog5GhzRev = val;
522
523 return 0;
524 }
525
526 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
527 {
528 u32 sum;
529 int i;
530 u16 eeval;
531 struct ath_hal_5416 *ahp = AH5416(ah);
532
533 sum = 0;
534 for (i = 0; i < 3; i++) {
535 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
536 sum += eeval;
537 ahp->ah_macaddr[2 * i] = eeval >> 8;
538 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
539 }
540 if (sum == 0 || sum == 0xffff * 3) {
541 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
542 "mac address read failed: %pM\n",
543 ahp->ah_macaddr);
544 return -EADDRNOTAVAIL;
545 }
546
547 return 0;
548 }
549
550 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
551 {
552 u32 rxgain_type;
553 struct ath_hal_5416 *ahp = AH5416(ah);
554
555 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
556 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
557
558 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
559 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
560 ar9280Modes_backoff_13db_rxgain_9280_2,
561 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
562 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
563 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
564 ar9280Modes_backoff_23db_rxgain_9280_2,
565 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
566 else
567 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
568 ar9280Modes_original_rxgain_9280_2,
569 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
570 } else
571 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
572 ar9280Modes_original_rxgain_9280_2,
573 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
574 }
575
576 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
577 {
578 u32 txgain_type;
579 struct ath_hal_5416 *ahp = AH5416(ah);
580
581 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
582 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
583
584 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
585 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
586 ar9280Modes_high_power_tx_gain_9280_2,
587 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
588 else
589 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
590 ar9280Modes_original_tx_gain_9280_2,
591 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
592 } else
593 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
594 ar9280Modes_original_tx_gain_9280_2,
595 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
596 }
597
598 static int ath9k_hw_post_attach(struct ath_hal *ah)
599 {
600 int ecode;
601
602 if (!ath9k_hw_chip_test(ah)) {
603 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
604 "hardware self-test failed\n");
605 return -ENODEV;
606 }
607
608 ecode = ath9k_hw_rf_claim(ah);
609 if (ecode != 0)
610 return ecode;
611
612 ecode = ath9k_hw_eeprom_attach(ah);
613 if (ecode != 0)
614 return ecode;
615 ecode = ath9k_hw_rfattach(ah);
616 if (ecode != 0)
617 return ecode;
618
619 if (!AR_SREV_9100(ah)) {
620 ath9k_hw_ani_setup(ah);
621 ath9k_hw_ani_attach(ah);
622 }
623
624 return 0;
625 }
626
627 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
628 void __iomem *mem, int *status)
629 {
630 struct ath_hal_5416 *ahp;
631 struct ath_hal *ah;
632 int ecode;
633 u32 i, j;
634
635 ahp = ath9k_hw_newstate(devid, sc, mem, status);
636 if (ahp == NULL)
637 return NULL;
638
639 ah = &ahp->ah;
640
641 ath9k_hw_set_defaults(ah);
642
643 if (ah->ah_config.intr_mitigation != 0)
644 ahp->ah_intrMitigation = true;
645
646 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
647 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
648 ecode = -EIO;
649 goto bad;
650 }
651
652 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
653 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
654 ecode = -EIO;
655 goto bad;
656 }
657
658 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
659 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
660 ah->ah_config.serialize_regmode =
661 SER_REG_MODE_ON;
662 } else {
663 ah->ah_config.serialize_regmode =
664 SER_REG_MODE_OFF;
665 }
666 }
667
668 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
669 "serialize_regmode is %d\n",
670 ah->ah_config.serialize_regmode);
671
672 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
673 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
674 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
675 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
676 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
677 "Mac Chip Rev 0x%02x.%x is not supported by "
678 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
679 ecode = -EOPNOTSUPP;
680 goto bad;
681 }
682
683 if (AR_SREV_9100(ah)) {
684 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
685 ahp->ah_suppCals = IQ_MISMATCH_CAL;
686 ah->ah_isPciExpress = false;
687 }
688 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
689
690 if (AR_SREV_9160_10_OR_LATER(ah)) {
691 if (AR_SREV_9280_10_OR_LATER(ah)) {
692 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
693 ahp->ah_adcGainCalData.calData =
694 &adc_gain_cal_single_sample;
695 ahp->ah_adcDcCalData.calData =
696 &adc_dc_cal_single_sample;
697 ahp->ah_adcDcCalInitData.calData =
698 &adc_init_dc_cal;
699 } else {
700 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
701 ahp->ah_adcGainCalData.calData =
702 &adc_gain_cal_multi_sample;
703 ahp->ah_adcDcCalData.calData =
704 &adc_dc_cal_multi_sample;
705 ahp->ah_adcDcCalInitData.calData =
706 &adc_init_dc_cal;
707 }
708 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
709 }
710
711 if (AR_SREV_9160(ah)) {
712 ah->ah_config.enable_ani = 1;
713 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
714 ATH9K_ANI_FIRSTEP_LEVEL);
715 } else {
716 ahp->ah_ani_function = ATH9K_ANI_ALL;
717 if (AR_SREV_9280_10_OR_LATER(ah)) {
718 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
719 }
720 }
721
722 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
723 "This Mac Chip Rev 0x%02x.%x is \n",
724 ah->ah_macVersion, ah->ah_macRev);
725
726 if (AR_SREV_9285_12_OR_LATER(ah)) {
727 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
728 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
729 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
730 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
731
732 if (ah->ah_config.pcie_clock_req) {
733 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
734 ar9285PciePhy_clkreq_off_L1_9285_1_2,
735 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
736 } else {
737 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
738 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
739 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
740 2);
741 }
742 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
743 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
744 ARRAY_SIZE(ar9285Modes_9285), 6);
745 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
746 ARRAY_SIZE(ar9285Common_9285), 2);
747
748 if (ah->ah_config.pcie_clock_req) {
749 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
750 ar9285PciePhy_clkreq_off_L1_9285,
751 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
752 } else {
753 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
754 ar9285PciePhy_clkreq_always_on_L1_9285,
755 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
756 }
757 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
758 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
759 ARRAY_SIZE(ar9280Modes_9280_2), 6);
760 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
761 ARRAY_SIZE(ar9280Common_9280_2), 2);
762
763 if (ah->ah_config.pcie_clock_req) {
764 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
765 ar9280PciePhy_clkreq_off_L1_9280,
766 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
767 } else {
768 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
769 ar9280PciePhy_clkreq_always_on_L1_9280,
770 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
771 }
772 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
773 ar9280Modes_fast_clock_9280_2,
774 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
775 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
776 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
777 ARRAY_SIZE(ar9280Modes_9280), 6);
778 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
779 ARRAY_SIZE(ar9280Common_9280), 2);
780 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
781 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
782 ARRAY_SIZE(ar5416Modes_9160), 6);
783 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
784 ARRAY_SIZE(ar5416Common_9160), 2);
785 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
786 ARRAY_SIZE(ar5416Bank0_9160), 2);
787 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
788 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
789 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
790 ARRAY_SIZE(ar5416Bank1_9160), 2);
791 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
792 ARRAY_SIZE(ar5416Bank2_9160), 2);
793 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
794 ARRAY_SIZE(ar5416Bank3_9160), 3);
795 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
796 ARRAY_SIZE(ar5416Bank6_9160), 3);
797 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
798 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
799 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
800 ARRAY_SIZE(ar5416Bank7_9160), 2);
801 if (AR_SREV_9160_11(ah)) {
802 INIT_INI_ARRAY(&ahp->ah_iniAddac,
803 ar5416Addac_91601_1,
804 ARRAY_SIZE(ar5416Addac_91601_1), 2);
805 } else {
806 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
807 ARRAY_SIZE(ar5416Addac_9160), 2);
808 }
809 } else if (AR_SREV_9100_OR_LATER(ah)) {
810 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
811 ARRAY_SIZE(ar5416Modes_9100), 6);
812 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
813 ARRAY_SIZE(ar5416Common_9100), 2);
814 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
815 ARRAY_SIZE(ar5416Bank0_9100), 2);
816 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
817 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
818 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
819 ARRAY_SIZE(ar5416Bank1_9100), 2);
820 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
821 ARRAY_SIZE(ar5416Bank2_9100), 2);
822 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
823 ARRAY_SIZE(ar5416Bank3_9100), 3);
824 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
825 ARRAY_SIZE(ar5416Bank6_9100), 3);
826 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
827 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
828 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
829 ARRAY_SIZE(ar5416Bank7_9100), 2);
830 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
831 ARRAY_SIZE(ar5416Addac_9100), 2);
832 } else {
833 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
834 ARRAY_SIZE(ar5416Modes), 6);
835 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
836 ARRAY_SIZE(ar5416Common), 2);
837 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
838 ARRAY_SIZE(ar5416Bank0), 2);
839 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
840 ARRAY_SIZE(ar5416BB_RfGain), 3);
841 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
842 ARRAY_SIZE(ar5416Bank1), 2);
843 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
844 ARRAY_SIZE(ar5416Bank2), 2);
845 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
846 ARRAY_SIZE(ar5416Bank3), 3);
847 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
848 ARRAY_SIZE(ar5416Bank6), 3);
849 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
850 ARRAY_SIZE(ar5416Bank6TPC), 3);
851 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
852 ARRAY_SIZE(ar5416Bank7), 2);
853 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
854 ARRAY_SIZE(ar5416Addac), 2);
855 }
856
857 if (ah->ah_isPciExpress)
858 ath9k_hw_configpcipowersave(ah, 0);
859 else
860 ath9k_hw_disablepcie(ah);
861
862 ecode = ath9k_hw_post_attach(ah);
863 if (ecode != 0)
864 goto bad;
865
866 /* rxgain table */
867 if (AR_SREV_9280_20(ah))
868 ath9k_hw_init_rxgain_ini(ah);
869
870 /* txgain table */
871 if (AR_SREV_9280_20(ah))
872 ath9k_hw_init_txgain_ini(ah);
873
874 if (ah->ah_devid == AR9280_DEVID_PCI) {
875 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
876 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
877
878 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
879 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
880
881 INI_RA(&ahp->ah_iniModes, i, j) =
882 ath9k_hw_ini_fixup(ah,
883 &ahp->ah_eeprom.def,
884 reg, val);
885 }
886 }
887 }
888
889 if (!ath9k_hw_fill_cap_info(ah)) {
890 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
891 "failed ath9k_hw_fill_cap_info\n");
892 ecode = -EINVAL;
893 goto bad;
894 }
895
896 ecode = ath9k_hw_init_macaddr(ah);
897 if (ecode != 0) {
898 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
899 "failed initializing mac address\n");
900 goto bad;
901 }
902
903 if (AR_SREV_9285(ah))
904 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
905 else
906 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
907
908 ath9k_init_nfcal_hist_buffer(ah);
909
910 return ah;
911 bad:
912 if (ahp)
913 ath9k_hw_detach((struct ath_hal *) ahp);
914 if (status)
915 *status = ecode;
916
917 return NULL;
918 }
919
920 static void ath9k_hw_init_bb(struct ath_hal *ah,
921 struct ath9k_channel *chan)
922 {
923 u32 synthDelay;
924
925 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
926 if (IS_CHAN_B(chan))
927 synthDelay = (4 * synthDelay) / 22;
928 else
929 synthDelay /= 10;
930
931 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
932
933 udelay(synthDelay + BASE_ACTIVATE_DELAY);
934 }
935
936 static void ath9k_hw_init_qos(struct ath_hal *ah)
937 {
938 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
939 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
940
941 REG_WRITE(ah, AR_QOS_NO_ACK,
942 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
943 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
944 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
945
946 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
947 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
948 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
949 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
950 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
951 }
952
953 static void ath9k_hw_init_pll(struct ath_hal *ah,
954 struct ath9k_channel *chan)
955 {
956 u32 pll;
957
958 if (AR_SREV_9100(ah)) {
959 if (chan && IS_CHAN_5GHZ(chan))
960 pll = 0x1450;
961 else
962 pll = 0x1458;
963 } else {
964 if (AR_SREV_9280_10_OR_LATER(ah)) {
965 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
966
967 if (chan && IS_CHAN_HALF_RATE(chan))
968 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
969 else if (chan && IS_CHAN_QUARTER_RATE(chan))
970 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
971
972 if (chan && IS_CHAN_5GHZ(chan)) {
973 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
974
975
976 if (AR_SREV_9280_20(ah)) {
977 if (((chan->channel % 20) == 0)
978 || ((chan->channel % 10) == 0))
979 pll = 0x2850;
980 else
981 pll = 0x142c;
982 }
983 } else {
984 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
985 }
986
987 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
988
989 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
990
991 if (chan && IS_CHAN_HALF_RATE(chan))
992 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
993 else if (chan && IS_CHAN_QUARTER_RATE(chan))
994 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
995
996 if (chan && IS_CHAN_5GHZ(chan))
997 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
998 else
999 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1000 } else {
1001 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1002
1003 if (chan && IS_CHAN_HALF_RATE(chan))
1004 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1005 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1006 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1007
1008 if (chan && IS_CHAN_5GHZ(chan))
1009 pll |= SM(0xa, AR_RTC_PLL_DIV);
1010 else
1011 pll |= SM(0xb, AR_RTC_PLL_DIV);
1012 }
1013 }
1014 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1015
1016 udelay(RTC_PLL_SETTLE_DELAY);
1017
1018 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1019 }
1020
1021 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1022 {
1023 struct ath_hal_5416 *ahp = AH5416(ah);
1024 int rx_chainmask, tx_chainmask;
1025
1026 rx_chainmask = ahp->ah_rxchainmask;
1027 tx_chainmask = ahp->ah_txchainmask;
1028
1029 switch (rx_chainmask) {
1030 case 0x5:
1031 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1032 AR_PHY_SWAP_ALT_CHAIN);
1033 case 0x3:
1034 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1035 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1036 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1037 break;
1038 }
1039 case 0x1:
1040 case 0x2:
1041 case 0x7:
1042 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1043 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1044 break;
1045 default:
1046 break;
1047 }
1048
1049 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1050 if (tx_chainmask == 0x5) {
1051 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1052 AR_PHY_SWAP_ALT_CHAIN);
1053 }
1054 if (AR_SREV_9100(ah))
1055 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1056 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1057 }
1058
1059 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1060 enum nl80211_iftype opmode)
1061 {
1062 struct ath_hal_5416 *ahp = AH5416(ah);
1063
1064 ahp->ah_maskReg = AR_IMR_TXERR |
1065 AR_IMR_TXURN |
1066 AR_IMR_RXERR |
1067 AR_IMR_RXORN |
1068 AR_IMR_BCNMISC;
1069
1070 if (ahp->ah_intrMitigation)
1071 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1072 else
1073 ahp->ah_maskReg |= AR_IMR_RXOK;
1074
1075 ahp->ah_maskReg |= AR_IMR_TXOK;
1076
1077 if (opmode == NL80211_IFTYPE_AP)
1078 ahp->ah_maskReg |= AR_IMR_MIB;
1079
1080 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1081 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1082
1083 if (!AR_SREV_9100(ah)) {
1084 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1085 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1086 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1087 }
1088 }
1089
1090 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1091 {
1092 struct ath_hal_5416 *ahp = AH5416(ah);
1093
1094 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1095 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1096 ahp->ah_acktimeout = (u32) -1;
1097 return false;
1098 } else {
1099 REG_RMW_FIELD(ah, AR_TIME_OUT,
1100 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1101 ahp->ah_acktimeout = us;
1102 return true;
1103 }
1104 }
1105
1106 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1107 {
1108 struct ath_hal_5416 *ahp = AH5416(ah);
1109
1110 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1111 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1112 ahp->ah_ctstimeout = (u32) -1;
1113 return false;
1114 } else {
1115 REG_RMW_FIELD(ah, AR_TIME_OUT,
1116 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1117 ahp->ah_ctstimeout = us;
1118 return true;
1119 }
1120 }
1121
1122 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1123 {
1124 struct ath_hal_5416 *ahp = AH5416(ah);
1125
1126 if (tu > 0xFFFF) {
1127 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1128 "bad global tx timeout %u\n", tu);
1129 ahp->ah_globaltxtimeout = (u32) -1;
1130 return false;
1131 } else {
1132 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1133 ahp->ah_globaltxtimeout = tu;
1134 return true;
1135 }
1136 }
1137
1138 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1139 {
1140 struct ath_hal_5416 *ahp = AH5416(ah);
1141
1142 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1143 ahp->ah_miscMode);
1144
1145 if (ahp->ah_miscMode != 0)
1146 REG_WRITE(ah, AR_PCU_MISC,
1147 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1148 if (ahp->ah_slottime != (u32) -1)
1149 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1150 if (ahp->ah_acktimeout != (u32) -1)
1151 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1152 if (ahp->ah_ctstimeout != (u32) -1)
1153 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1154 if (ahp->ah_globaltxtimeout != (u32) -1)
1155 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1156 }
1157
1158 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1159 {
1160 return vendorid == ATHEROS_VENDOR_ID ?
1161 ath9k_hw_devname(devid) : NULL;
1162 }
1163
1164 void ath9k_hw_detach(struct ath_hal *ah)
1165 {
1166 if (!AR_SREV_9100(ah))
1167 ath9k_hw_ani_detach(ah);
1168
1169 ath9k_hw_rfdetach(ah);
1170 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1171 kfree(ah);
1172 }
1173
1174 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1175 void __iomem *mem, int *error)
1176 {
1177 struct ath_hal *ah = NULL;
1178
1179 switch (devid) {
1180 case AR5416_DEVID_PCI:
1181 case AR5416_DEVID_PCIE:
1182 case AR9160_DEVID_PCI:
1183 case AR9280_DEVID_PCI:
1184 case AR9280_DEVID_PCIE:
1185 case AR9285_DEVID_PCIE:
1186 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1187 break;
1188 default:
1189 *error = -ENXIO;
1190 break;
1191 }
1192
1193 return ah;
1194 }
1195
1196 /*******/
1197 /* INI */
1198 /*******/
1199
1200 static void ath9k_hw_override_ini(struct ath_hal *ah,
1201 struct ath9k_channel *chan)
1202 {
1203 /*
1204 * Set the RX_ABORT and RX_DIS and clear if off only after
1205 * RXE is set for MAC. This prevents frames with corrupted
1206 * descriptor status.
1207 */
1208 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1209
1210
1211 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1212 AR_SREV_9280_10_OR_LATER(ah))
1213 return;
1214
1215 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1216 }
1217
1218 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1219 struct ar5416_eeprom_def *pEepData,
1220 u32 reg, u32 value)
1221 {
1222 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1223
1224 switch (ah->ah_devid) {
1225 case AR9280_DEVID_PCI:
1226 if (reg == 0x7894) {
1227 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1228 "ini VAL: %x EEPROM: %x\n", value,
1229 (pBase->version & 0xff));
1230
1231 if ((pBase->version & 0xff) > 0x0a) {
1232 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1233 "PWDCLKIND: %d\n",
1234 pBase->pwdclkind);
1235 value &= ~AR_AN_TOP2_PWDCLKIND;
1236 value |= AR_AN_TOP2_PWDCLKIND &
1237 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1238 } else {
1239 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1240 "PWDCLKIND Earlier Rev\n");
1241 }
1242
1243 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1244 "final ini VAL: %x\n", value);
1245 }
1246 break;
1247 }
1248
1249 return value;
1250 }
1251
1252 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1253 struct ar5416_eeprom_def *pEepData,
1254 u32 reg, u32 value)
1255 {
1256 struct ath_hal_5416 *ahp = AH5416(ah);
1257
1258 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1259 return value;
1260 else
1261 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1262 }
1263
1264 static int ath9k_hw_process_ini(struct ath_hal *ah,
1265 struct ath9k_channel *chan,
1266 enum ath9k_ht_macmode macmode)
1267 {
1268 int i, regWrites = 0;
1269 struct ath_hal_5416 *ahp = AH5416(ah);
1270 u32 modesIndex, freqIndex;
1271 int status;
1272
1273 switch (chan->chanmode) {
1274 case CHANNEL_A:
1275 case CHANNEL_A_HT20:
1276 modesIndex = 1;
1277 freqIndex = 1;
1278 break;
1279 case CHANNEL_A_HT40PLUS:
1280 case CHANNEL_A_HT40MINUS:
1281 modesIndex = 2;
1282 freqIndex = 1;
1283 break;
1284 case CHANNEL_G:
1285 case CHANNEL_G_HT20:
1286 case CHANNEL_B:
1287 modesIndex = 4;
1288 freqIndex = 2;
1289 break;
1290 case CHANNEL_G_HT40PLUS:
1291 case CHANNEL_G_HT40MINUS:
1292 modesIndex = 3;
1293 freqIndex = 2;
1294 break;
1295
1296 default:
1297 return -EINVAL;
1298 }
1299
1300 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1301
1302 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1303
1304 ath9k_hw_set_addac(ah, chan);
1305
1306 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1307 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1308 } else {
1309 struct ar5416IniArray temp;
1310 u32 addacSize =
1311 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1312 ahp->ah_iniAddac.ia_columns;
1313
1314 memcpy(ahp->ah_addac5416_21,
1315 ahp->ah_iniAddac.ia_array, addacSize);
1316
1317 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1318
1319 temp.ia_array = ahp->ah_addac5416_21;
1320 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1321 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1322 REG_WRITE_ARRAY(&temp, 1, regWrites);
1323 }
1324
1325 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1326
1327 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1328 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1329 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1330
1331 REG_WRITE(ah, reg, val);
1332
1333 if (reg >= 0x7800 && reg < 0x78a0
1334 && ah->ah_config.analog_shiftreg) {
1335 udelay(100);
1336 }
1337
1338 DO_DELAY(regWrites);
1339 }
1340
1341 if (AR_SREV_9280(ah))
1342 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1343
1344 if (AR_SREV_9280(ah))
1345 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1346
1347 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1348 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1349 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1350
1351 REG_WRITE(ah, reg, val);
1352
1353 if (reg >= 0x7800 && reg < 0x78a0
1354 && ah->ah_config.analog_shiftreg) {
1355 udelay(100);
1356 }
1357
1358 DO_DELAY(regWrites);
1359 }
1360
1361 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1362
1363 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1364 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1365 regWrites);
1366 }
1367
1368 ath9k_hw_override_ini(ah, chan);
1369 ath9k_hw_set_regs(ah, chan, macmode);
1370 ath9k_hw_init_chain_masks(ah);
1371
1372 status = ath9k_hw_set_txpower(ah, chan,
1373 ath9k_regd_get_ctl(ah, chan),
1374 ath9k_regd_get_antenna_allowed(ah,
1375 chan),
1376 chan->maxRegTxPower * 2,
1377 min((u32) MAX_RATE_POWER,
1378 (u32) ah->ah_powerLimit));
1379 if (status != 0) {
1380 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1381 "error init'ing transmit power\n");
1382 return -EIO;
1383 }
1384
1385 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1386 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1387 "ar5416SetRfRegs failed\n");
1388 return -EIO;
1389 }
1390
1391 return 0;
1392 }
1393
1394 /****************************************/
1395 /* Reset and Channel Switching Routines */
1396 /****************************************/
1397
1398 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1399 {
1400 u32 rfMode = 0;
1401
1402 if (chan == NULL)
1403 return;
1404
1405 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1406 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1407
1408 if (!AR_SREV_9280_10_OR_LATER(ah))
1409 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1410 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1411
1412 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1413 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1414
1415 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1416 }
1417
1418 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1419 {
1420 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1421 }
1422
1423 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1424 {
1425 u32 regval;
1426
1427 regval = REG_READ(ah, AR_AHB_MODE);
1428 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1429
1430 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1431 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1432
1433 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1434
1435 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1436 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1437
1438 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1439
1440 if (AR_SREV_9285(ah)) {
1441 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1442 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1443 } else {
1444 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1445 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1446 }
1447 }
1448
1449 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1450 {
1451 u32 val;
1452
1453 val = REG_READ(ah, AR_STA_ID1);
1454 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1455 switch (opmode) {
1456 case NL80211_IFTYPE_AP:
1457 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1458 | AR_STA_ID1_KSRCH_MODE);
1459 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1460 break;
1461 case NL80211_IFTYPE_ADHOC:
1462 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1463 | AR_STA_ID1_KSRCH_MODE);
1464 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1465 break;
1466 case NL80211_IFTYPE_STATION:
1467 case NL80211_IFTYPE_MONITOR:
1468 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1469 break;
1470 }
1471 }
1472
1473 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1474 u32 coef_scaled,
1475 u32 *coef_mantissa,
1476 u32 *coef_exponent)
1477 {
1478 u32 coef_exp, coef_man;
1479
1480 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1481 if ((coef_scaled >> coef_exp) & 0x1)
1482 break;
1483
1484 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1485
1486 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1487
1488 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1489 *coef_exponent = coef_exp - 16;
1490 }
1491
1492 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1493 struct ath9k_channel *chan)
1494 {
1495 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1496 u32 clockMhzScaled = 0x64000000;
1497 struct chan_centers centers;
1498
1499 if (IS_CHAN_HALF_RATE(chan))
1500 clockMhzScaled = clockMhzScaled >> 1;
1501 else if (IS_CHAN_QUARTER_RATE(chan))
1502 clockMhzScaled = clockMhzScaled >> 2;
1503
1504 ath9k_hw_get_channel_centers(ah, chan, &centers);
1505 coef_scaled = clockMhzScaled / centers.synth_center;
1506
1507 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1508 &ds_coef_exp);
1509
1510 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1511 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1512 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1513 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1514
1515 coef_scaled = (9 * coef_scaled) / 10;
1516
1517 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1518 &ds_coef_exp);
1519
1520 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1521 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1522 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1523 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1524 }
1525
1526 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1527 {
1528 u32 rst_flags;
1529 u32 tmpReg;
1530
1531 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1532 AR_RTC_FORCE_WAKE_ON_INT);
1533
1534 if (AR_SREV_9100(ah)) {
1535 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1536 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1537 } else {
1538 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1539 if (tmpReg &
1540 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1541 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1542 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1543 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1544 } else {
1545 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1546 }
1547
1548 rst_flags = AR_RTC_RC_MAC_WARM;
1549 if (type == ATH9K_RESET_COLD)
1550 rst_flags |= AR_RTC_RC_MAC_COLD;
1551 }
1552
1553 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1554 udelay(50);
1555
1556 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1557 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1558 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1559 "RTC stuck in MAC reset\n");
1560 return false;
1561 }
1562
1563 if (!AR_SREV_9100(ah))
1564 REG_WRITE(ah, AR_RC, 0);
1565
1566 ath9k_hw_init_pll(ah, NULL);
1567
1568 if (AR_SREV_9100(ah))
1569 udelay(50);
1570
1571 return true;
1572 }
1573
1574 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1575 {
1576 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1577 AR_RTC_FORCE_WAKE_ON_INT);
1578
1579 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1580 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1581
1582 if (!ath9k_hw_wait(ah,
1583 AR_RTC_STATUS,
1584 AR_RTC_STATUS_M,
1585 AR_RTC_STATUS_ON)) {
1586 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1587 return false;
1588 }
1589
1590 ath9k_hw_read_revisions(ah);
1591
1592 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1593 }
1594
1595 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1596 {
1597 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1598 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1599
1600 switch (type) {
1601 case ATH9K_RESET_POWER_ON:
1602 return ath9k_hw_set_reset_power_on(ah);
1603 break;
1604 case ATH9K_RESET_WARM:
1605 case ATH9K_RESET_COLD:
1606 return ath9k_hw_set_reset(ah, type);
1607 break;
1608 default:
1609 return false;
1610 }
1611 }
1612
1613 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1614 enum ath9k_ht_macmode macmode)
1615 {
1616 u32 phymode;
1617 u32 enableDacFifo = 0;
1618 struct ath_hal_5416 *ahp = AH5416(ah);
1619
1620 if (AR_SREV_9285_10_OR_LATER(ah))
1621 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1622 AR_PHY_FC_ENABLE_DAC_FIFO);
1623
1624 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1625 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1626
1627 if (IS_CHAN_HT40(chan)) {
1628 phymode |= AR_PHY_FC_DYN2040_EN;
1629
1630 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1631 (chan->chanmode == CHANNEL_G_HT40PLUS))
1632 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1633
1634 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1635 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1636 }
1637 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1638
1639 ath9k_hw_set11nmac2040(ah, macmode);
1640
1641 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1642 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1643 }
1644
1645 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1646 struct ath9k_channel *chan)
1647 {
1648 struct ath_hal_5416 *ahp = AH5416(ah);
1649
1650 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1651 return false;
1652
1653 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1654 return false;
1655
1656 ahp->ah_chipFullSleep = false;
1657
1658 ath9k_hw_init_pll(ah, chan);
1659
1660 ath9k_hw_set_rfmode(ah, chan);
1661
1662 return true;
1663 }
1664
1665 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1666 struct ath9k_channel *chan,
1667 enum ath9k_ht_macmode macmode)
1668 {
1669 u32 synthDelay, qnum;
1670
1671 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1672 if (ath9k_hw_numtxpending(ah, qnum)) {
1673 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1674 "Transmit frames pending on queue %d\n", qnum);
1675 return false;
1676 }
1677 }
1678
1679 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1680 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1681 AR_PHY_RFBUS_GRANT_EN)) {
1682 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1683 "Could not kill baseband RX\n");
1684 return false;
1685 }
1686
1687 ath9k_hw_set_regs(ah, chan, macmode);
1688
1689 if (AR_SREV_9280_10_OR_LATER(ah)) {
1690 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1691 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1692 "failed to set channel\n");
1693 return false;
1694 }
1695 } else {
1696 if (!(ath9k_hw_set_channel(ah, chan))) {
1697 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1698 "failed to set channel\n");
1699 return false;
1700 }
1701 }
1702
1703 if (ath9k_hw_set_txpower(ah, chan,
1704 ath9k_regd_get_ctl(ah, chan),
1705 ath9k_regd_get_antenna_allowed(ah, chan),
1706 chan->maxRegTxPower * 2,
1707 min((u32) MAX_RATE_POWER,
1708 (u32) ah->ah_powerLimit)) != 0) {
1709 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1710 "error init'ing transmit power\n");
1711 return false;
1712 }
1713
1714 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1715 if (IS_CHAN_B(chan))
1716 synthDelay = (4 * synthDelay) / 22;
1717 else
1718 synthDelay /= 10;
1719
1720 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1721
1722 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1723
1724 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1725 ath9k_hw_set_delta_slope(ah, chan);
1726
1727 if (AR_SREV_9280_10_OR_LATER(ah))
1728 ath9k_hw_9280_spur_mitigate(ah, chan);
1729 else
1730 ath9k_hw_spur_mitigate(ah, chan);
1731
1732 if (!chan->oneTimeCalsDone)
1733 chan->oneTimeCalsDone = true;
1734
1735 return true;
1736 }
1737
1738 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1739 {
1740 int bb_spur = AR_NO_SPUR;
1741 int freq;
1742 int bin, cur_bin;
1743 int bb_spur_off, spur_subchannel_sd;
1744 int spur_freq_sd;
1745 int spur_delta_phase;
1746 int denominator;
1747 int upper, lower, cur_vit_mask;
1748 int tmp, newVal;
1749 int i;
1750 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1751 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1752 };
1753 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1754 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1755 };
1756 int inc[4] = { 0, 100, 0, 0 };
1757 struct chan_centers centers;
1758
1759 int8_t mask_m[123];
1760 int8_t mask_p[123];
1761 int8_t mask_amt;
1762 int tmp_mask;
1763 int cur_bb_spur;
1764 bool is2GHz = IS_CHAN_2GHZ(chan);
1765
1766 memset(&mask_m, 0, sizeof(int8_t) * 123);
1767 memset(&mask_p, 0, sizeof(int8_t) * 123);
1768
1769 ath9k_hw_get_channel_centers(ah, chan, &centers);
1770 freq = centers.synth_center;
1771
1772 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1773 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1774 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1775
1776 if (is2GHz)
1777 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1778 else
1779 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1780
1781 if (AR_NO_SPUR == cur_bb_spur)
1782 break;
1783 cur_bb_spur = cur_bb_spur - freq;
1784
1785 if (IS_CHAN_HT40(chan)) {
1786 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1787 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1788 bb_spur = cur_bb_spur;
1789 break;
1790 }
1791 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1792 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1793 bb_spur = cur_bb_spur;
1794 break;
1795 }
1796 }
1797
1798 if (AR_NO_SPUR == bb_spur) {
1799 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1800 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1801 return;
1802 } else {
1803 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1804 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1805 }
1806
1807 bin = bb_spur * 320;
1808
1809 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1810
1811 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1812 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1813 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1814 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1815 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1816
1817 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1818 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1819 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1820 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1821 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1822 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1823
1824 if (IS_CHAN_HT40(chan)) {
1825 if (bb_spur < 0) {
1826 spur_subchannel_sd = 1;
1827 bb_spur_off = bb_spur + 10;
1828 } else {
1829 spur_subchannel_sd = 0;
1830 bb_spur_off = bb_spur - 10;
1831 }
1832 } else {
1833 spur_subchannel_sd = 0;
1834 bb_spur_off = bb_spur;
1835 }
1836
1837 if (IS_CHAN_HT40(chan))
1838 spur_delta_phase =
1839 ((bb_spur * 262144) /
1840 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1841 else
1842 spur_delta_phase =
1843 ((bb_spur * 524288) /
1844 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1845
1846 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1847 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1848
1849 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1850 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1851 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1852 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1853
1854 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1855 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1856
1857 cur_bin = -6000;
1858 upper = bin + 100;
1859 lower = bin - 100;
1860
1861 for (i = 0; i < 4; i++) {
1862 int pilot_mask = 0;
1863 int chan_mask = 0;
1864 int bp = 0;
1865 for (bp = 0; bp < 30; bp++) {
1866 if ((cur_bin > lower) && (cur_bin < upper)) {
1867 pilot_mask = pilot_mask | 0x1 << bp;
1868 chan_mask = chan_mask | 0x1 << bp;
1869 }
1870 cur_bin += 100;
1871 }
1872 cur_bin += inc[i];
1873 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1874 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1875 }
1876
1877 cur_vit_mask = 6100;
1878 upper = bin + 120;
1879 lower = bin - 120;
1880
1881 for (i = 0; i < 123; i++) {
1882 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1883
1884 /* workaround for gcc bug #37014 */
1885 volatile int tmp_v = abs(cur_vit_mask - bin);
1886
1887 if (tmp_v < 75)
1888 mask_amt = 1;
1889 else
1890 mask_amt = 0;
1891 if (cur_vit_mask < 0)
1892 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1893 else
1894 mask_p[cur_vit_mask / 100] = mask_amt;
1895 }
1896 cur_vit_mask -= 100;
1897 }
1898
1899 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1900 | (mask_m[48] << 26) | (mask_m[49] << 24)
1901 | (mask_m[50] << 22) | (mask_m[51] << 20)
1902 | (mask_m[52] << 18) | (mask_m[53] << 16)
1903 | (mask_m[54] << 14) | (mask_m[55] << 12)
1904 | (mask_m[56] << 10) | (mask_m[57] << 8)
1905 | (mask_m[58] << 6) | (mask_m[59] << 4)
1906 | (mask_m[60] << 2) | (mask_m[61] << 0);
1907 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1908 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1909
1910 tmp_mask = (mask_m[31] << 28)
1911 | (mask_m[32] << 26) | (mask_m[33] << 24)
1912 | (mask_m[34] << 22) | (mask_m[35] << 20)
1913 | (mask_m[36] << 18) | (mask_m[37] << 16)
1914 | (mask_m[48] << 14) | (mask_m[39] << 12)
1915 | (mask_m[40] << 10) | (mask_m[41] << 8)
1916 | (mask_m[42] << 6) | (mask_m[43] << 4)
1917 | (mask_m[44] << 2) | (mask_m[45] << 0);
1918 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1919 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1920
1921 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1922 | (mask_m[18] << 26) | (mask_m[18] << 24)
1923 | (mask_m[20] << 22) | (mask_m[20] << 20)
1924 | (mask_m[22] << 18) | (mask_m[22] << 16)
1925 | (mask_m[24] << 14) | (mask_m[24] << 12)
1926 | (mask_m[25] << 10) | (mask_m[26] << 8)
1927 | (mask_m[27] << 6) | (mask_m[28] << 4)
1928 | (mask_m[29] << 2) | (mask_m[30] << 0);
1929 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1930 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1931
1932 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1933 | (mask_m[2] << 26) | (mask_m[3] << 24)
1934 | (mask_m[4] << 22) | (mask_m[5] << 20)
1935 | (mask_m[6] << 18) | (mask_m[7] << 16)
1936 | (mask_m[8] << 14) | (mask_m[9] << 12)
1937 | (mask_m[10] << 10) | (mask_m[11] << 8)
1938 | (mask_m[12] << 6) | (mask_m[13] << 4)
1939 | (mask_m[14] << 2) | (mask_m[15] << 0);
1940 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1941 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1942
1943 tmp_mask = (mask_p[15] << 28)
1944 | (mask_p[14] << 26) | (mask_p[13] << 24)
1945 | (mask_p[12] << 22) | (mask_p[11] << 20)
1946 | (mask_p[10] << 18) | (mask_p[9] << 16)
1947 | (mask_p[8] << 14) | (mask_p[7] << 12)
1948 | (mask_p[6] << 10) | (mask_p[5] << 8)
1949 | (mask_p[4] << 6) | (mask_p[3] << 4)
1950 | (mask_p[2] << 2) | (mask_p[1] << 0);
1951 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1952 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1953
1954 tmp_mask = (mask_p[30] << 28)
1955 | (mask_p[29] << 26) | (mask_p[28] << 24)
1956 | (mask_p[27] << 22) | (mask_p[26] << 20)
1957 | (mask_p[25] << 18) | (mask_p[24] << 16)
1958 | (mask_p[23] << 14) | (mask_p[22] << 12)
1959 | (mask_p[21] << 10) | (mask_p[20] << 8)
1960 | (mask_p[19] << 6) | (mask_p[18] << 4)
1961 | (mask_p[17] << 2) | (mask_p[16] << 0);
1962 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1963 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1964
1965 tmp_mask = (mask_p[45] << 28)
1966 | (mask_p[44] << 26) | (mask_p[43] << 24)
1967 | (mask_p[42] << 22) | (mask_p[41] << 20)
1968 | (mask_p[40] << 18) | (mask_p[39] << 16)
1969 | (mask_p[38] << 14) | (mask_p[37] << 12)
1970 | (mask_p[36] << 10) | (mask_p[35] << 8)
1971 | (mask_p[34] << 6) | (mask_p[33] << 4)
1972 | (mask_p[32] << 2) | (mask_p[31] << 0);
1973 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1974 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1975
1976 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1977 | (mask_p[59] << 26) | (mask_p[58] << 24)
1978 | (mask_p[57] << 22) | (mask_p[56] << 20)
1979 | (mask_p[55] << 18) | (mask_p[54] << 16)
1980 | (mask_p[53] << 14) | (mask_p[52] << 12)
1981 | (mask_p[51] << 10) | (mask_p[50] << 8)
1982 | (mask_p[49] << 6) | (mask_p[48] << 4)
1983 | (mask_p[47] << 2) | (mask_p[46] << 0);
1984 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1985 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1986 }
1987
1988 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1989 {
1990 int bb_spur = AR_NO_SPUR;
1991 int bin, cur_bin;
1992 int spur_freq_sd;
1993 int spur_delta_phase;
1994 int denominator;
1995 int upper, lower, cur_vit_mask;
1996 int tmp, new;
1997 int i;
1998 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1999 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2000 };
2001 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2002 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2003 };
2004 int inc[4] = { 0, 100, 0, 0 };
2005
2006 int8_t mask_m[123];
2007 int8_t mask_p[123];
2008 int8_t mask_amt;
2009 int tmp_mask;
2010 int cur_bb_spur;
2011 bool is2GHz = IS_CHAN_2GHZ(chan);
2012
2013 memset(&mask_m, 0, sizeof(int8_t) * 123);
2014 memset(&mask_p, 0, sizeof(int8_t) * 123);
2015
2016 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2017 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2018 if (AR_NO_SPUR == cur_bb_spur)
2019 break;
2020 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2021 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2022 bb_spur = cur_bb_spur;
2023 break;
2024 }
2025 }
2026
2027 if (AR_NO_SPUR == bb_spur)
2028 return;
2029
2030 bin = bb_spur * 32;
2031
2032 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2033 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2034 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2035 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2036 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2037
2038 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2039
2040 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2041 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2042 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2043 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2044 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2045 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2046
2047 spur_delta_phase = ((bb_spur * 524288) / 100) &
2048 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2049
2050 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2051 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2052
2053 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2054 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2055 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2056 REG_WRITE(ah, AR_PHY_TIMING11, new);
2057
2058 cur_bin = -6000;
2059 upper = bin + 100;
2060 lower = bin - 100;
2061
2062 for (i = 0; i < 4; i++) {
2063 int pilot_mask = 0;
2064 int chan_mask = 0;
2065 int bp = 0;
2066 for (bp = 0; bp < 30; bp++) {
2067 if ((cur_bin > lower) && (cur_bin < upper)) {
2068 pilot_mask = pilot_mask | 0x1 << bp;
2069 chan_mask = chan_mask | 0x1 << bp;
2070 }
2071 cur_bin += 100;
2072 }
2073 cur_bin += inc[i];
2074 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2075 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2076 }
2077
2078 cur_vit_mask = 6100;
2079 upper = bin + 120;
2080 lower = bin - 120;
2081
2082 for (i = 0; i < 123; i++) {
2083 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2084
2085 /* workaround for gcc bug #37014 */
2086 volatile int tmp_v = abs(cur_vit_mask - bin);
2087
2088 if (tmp_v < 75)
2089 mask_amt = 1;
2090 else
2091 mask_amt = 0;
2092 if (cur_vit_mask < 0)
2093 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2094 else
2095 mask_p[cur_vit_mask / 100] = mask_amt;
2096 }
2097 cur_vit_mask -= 100;
2098 }
2099
2100 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2101 | (mask_m[48] << 26) | (mask_m[49] << 24)
2102 | (mask_m[50] << 22) | (mask_m[51] << 20)
2103 | (mask_m[52] << 18) | (mask_m[53] << 16)
2104 | (mask_m[54] << 14) | (mask_m[55] << 12)
2105 | (mask_m[56] << 10) | (mask_m[57] << 8)
2106 | (mask_m[58] << 6) | (mask_m[59] << 4)
2107 | (mask_m[60] << 2) | (mask_m[61] << 0);
2108 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2109 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2110
2111 tmp_mask = (mask_m[31] << 28)
2112 | (mask_m[32] << 26) | (mask_m[33] << 24)
2113 | (mask_m[34] << 22) | (mask_m[35] << 20)
2114 | (mask_m[36] << 18) | (mask_m[37] << 16)
2115 | (mask_m[48] << 14) | (mask_m[39] << 12)
2116 | (mask_m[40] << 10) | (mask_m[41] << 8)
2117 | (mask_m[42] << 6) | (mask_m[43] << 4)
2118 | (mask_m[44] << 2) | (mask_m[45] << 0);
2119 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2120 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2121
2122 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2123 | (mask_m[18] << 26) | (mask_m[18] << 24)
2124 | (mask_m[20] << 22) | (mask_m[20] << 20)
2125 | (mask_m[22] << 18) | (mask_m[22] << 16)
2126 | (mask_m[24] << 14) | (mask_m[24] << 12)
2127 | (mask_m[25] << 10) | (mask_m[26] << 8)
2128 | (mask_m[27] << 6) | (mask_m[28] << 4)
2129 | (mask_m[29] << 2) | (mask_m[30] << 0);
2130 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2131 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2132
2133 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2134 | (mask_m[2] << 26) | (mask_m[3] << 24)
2135 | (mask_m[4] << 22) | (mask_m[5] << 20)
2136 | (mask_m[6] << 18) | (mask_m[7] << 16)
2137 | (mask_m[8] << 14) | (mask_m[9] << 12)
2138 | (mask_m[10] << 10) | (mask_m[11] << 8)
2139 | (mask_m[12] << 6) | (mask_m[13] << 4)
2140 | (mask_m[14] << 2) | (mask_m[15] << 0);
2141 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2142 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2143
2144 tmp_mask = (mask_p[15] << 28)
2145 | (mask_p[14] << 26) | (mask_p[13] << 24)
2146 | (mask_p[12] << 22) | (mask_p[11] << 20)
2147 | (mask_p[10] << 18) | (mask_p[9] << 16)
2148 | (mask_p[8] << 14) | (mask_p[7] << 12)
2149 | (mask_p[6] << 10) | (mask_p[5] << 8)
2150 | (mask_p[4] << 6) | (mask_p[3] << 4)
2151 | (mask_p[2] << 2) | (mask_p[1] << 0);
2152 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2153 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2154
2155 tmp_mask = (mask_p[30] << 28)
2156 | (mask_p[29] << 26) | (mask_p[28] << 24)
2157 | (mask_p[27] << 22) | (mask_p[26] << 20)
2158 | (mask_p[25] << 18) | (mask_p[24] << 16)
2159 | (mask_p[23] << 14) | (mask_p[22] << 12)
2160 | (mask_p[21] << 10) | (mask_p[20] << 8)
2161 | (mask_p[19] << 6) | (mask_p[18] << 4)
2162 | (mask_p[17] << 2) | (mask_p[16] << 0);
2163 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2164 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2165
2166 tmp_mask = (mask_p[45] << 28)
2167 | (mask_p[44] << 26) | (mask_p[43] << 24)
2168 | (mask_p[42] << 22) | (mask_p[41] << 20)
2169 | (mask_p[40] << 18) | (mask_p[39] << 16)
2170 | (mask_p[38] << 14) | (mask_p[37] << 12)
2171 | (mask_p[36] << 10) | (mask_p[35] << 8)
2172 | (mask_p[34] << 6) | (mask_p[33] << 4)
2173 | (mask_p[32] << 2) | (mask_p[31] << 0);
2174 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2175 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2176
2177 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2178 | (mask_p[59] << 26) | (mask_p[58] << 24)
2179 | (mask_p[57] << 22) | (mask_p[56] << 20)
2180 | (mask_p[55] << 18) | (mask_p[54] << 16)
2181 | (mask_p[53] << 14) | (mask_p[52] << 12)
2182 | (mask_p[51] << 10) | (mask_p[50] << 8)
2183 | (mask_p[49] << 6) | (mask_p[48] << 4)
2184 | (mask_p[47] << 2) | (mask_p[46] << 0);
2185 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2186 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2187 }
2188
2189 int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2190 bool bChannelChange)
2191 {
2192 u32 saveLedState;
2193 struct ath_softc *sc = ah->ah_sc;
2194 struct ath_hal_5416 *ahp = AH5416(ah);
2195 struct ath9k_channel *curchan = ah->ah_curchan;
2196 u32 saveDefAntenna;
2197 u32 macStaId1;
2198 int i, rx_chainmask, r;
2199
2200 ahp->ah_extprotspacing = sc->sc_ht_extprotspacing;
2201 ahp->ah_txchainmask = sc->sc_tx_chainmask;
2202 ahp->ah_rxchainmask = sc->sc_rx_chainmask;
2203
2204 if (AR_SREV_9280(ah)) {
2205 ahp->ah_txchainmask &= 0x3;
2206 ahp->ah_rxchainmask &= 0x3;
2207 }
2208
2209 if (ath9k_regd_check_channel(ah, chan) == NULL) {
2210 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2211 "invalid channel %u/0x%x; no mapping\n",
2212 chan->channel, chan->channelFlags);
2213 return -EINVAL;
2214 }
2215
2216 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2217 return -EIO;
2218
2219 if (curchan)
2220 ath9k_hw_getnf(ah, curchan);
2221
2222 if (bChannelChange &&
2223 (ahp->ah_chipFullSleep != true) &&
2224 (ah->ah_curchan != NULL) &&
2225 (chan->channel != ah->ah_curchan->channel) &&
2226 ((chan->channelFlags & CHANNEL_ALL) ==
2227 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2228 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2229 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2230
2231 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2232 ath9k_hw_loadnf(ah, ah->ah_curchan);
2233 ath9k_hw_start_nfcal(ah);
2234 return 0;
2235 }
2236 }
2237
2238 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2239 if (saveDefAntenna == 0)
2240 saveDefAntenna = 1;
2241
2242 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2243
2244 saveLedState = REG_READ(ah, AR_CFG_LED) &
2245 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2246 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2247
2248 ath9k_hw_mark_phy_inactive(ah);
2249
2250 if (!ath9k_hw_chip_reset(ah, chan)) {
2251 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2252 return -EINVAL;
2253 }
2254
2255 if (AR_SREV_9280(ah)) {
2256 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2257 AR_GPIO_JTAG_DISABLE);
2258
2259 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2260 if (IS_CHAN_5GHZ(chan))
2261 ath9k_hw_set_gpio(ah, 9, 0);
2262 else
2263 ath9k_hw_set_gpio(ah, 9, 1);
2264 }
2265 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2266 }
2267
2268 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2269 if (r)
2270 return r;
2271
2272 /* Setup MFP options for CCMP */
2273 if (AR_SREV_9280_20_OR_LATER(ah)) {
2274 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2275 * frames when constructing CCMP AAD. */
2276 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2277 0xc7ff);
2278 ah->sw_mgmt_crypto = false;
2279 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2280 /* Disable hardware crypto for management frames */
2281 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2282 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2283 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2284 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2285 ah->sw_mgmt_crypto = true;
2286 } else
2287 ah->sw_mgmt_crypto = true;
2288
2289 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2290 ath9k_hw_set_delta_slope(ah, chan);
2291
2292 if (AR_SREV_9280_10_OR_LATER(ah))
2293 ath9k_hw_9280_spur_mitigate(ah, chan);
2294 else
2295 ath9k_hw_spur_mitigate(ah, chan);
2296
2297 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2298 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2299 "error setting board options\n");
2300 return -EIO;
2301 }
2302
2303 ath9k_hw_decrease_chain_power(ah, chan);
2304
2305 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2306 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2307 | macStaId1
2308 | AR_STA_ID1_RTS_USE_DEF
2309 | (ah->ah_config.
2310 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2311 | ahp->ah_staId1Defaults);
2312 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2313
2314 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2315 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2316
2317 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2318
2319 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2320 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2321 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2322
2323 REG_WRITE(ah, AR_ISR, ~0);
2324
2325 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2326
2327 if (AR_SREV_9280_10_OR_LATER(ah)) {
2328 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2329 return -EIO;
2330 } else {
2331 if (!(ath9k_hw_set_channel(ah, chan)))
2332 return -EIO;
2333 }
2334
2335 for (i = 0; i < AR_NUM_DCU; i++)
2336 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2337
2338 ahp->ah_intrTxqs = 0;
2339 for (i = 0; i < ah->ah_caps.total_queues; i++)
2340 ath9k_hw_resettxqueue(ah, i);
2341
2342 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2343 ath9k_hw_init_qos(ah);
2344
2345 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2346 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2347 ath9k_enable_rfkill(ah);
2348 #endif
2349 ath9k_hw_init_user_settings(ah);
2350
2351 REG_WRITE(ah, AR_STA_ID1,
2352 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2353
2354 ath9k_hw_set_dma(ah);
2355
2356 REG_WRITE(ah, AR_OBS, 8);
2357
2358 if (ahp->ah_intrMitigation) {
2359
2360 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2361 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2362 }
2363
2364 ath9k_hw_init_bb(ah, chan);
2365
2366 if (!ath9k_hw_init_cal(ah, chan))
2367 return -EIO;;
2368
2369 rx_chainmask = ahp->ah_rxchainmask;
2370 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2371 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2372 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2373 }
2374
2375 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2376
2377 if (AR_SREV_9100(ah)) {
2378 u32 mask;
2379 mask = REG_READ(ah, AR_CFG);
2380 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2381 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2382 "CFG Byte Swap Set 0x%x\n", mask);
2383 } else {
2384 mask =
2385 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2386 REG_WRITE(ah, AR_CFG, mask);
2387 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2388 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2389 }
2390 } else {
2391 #ifdef __BIG_ENDIAN
2392 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2393 #endif
2394 }
2395
2396 return 0;
2397 }
2398
2399 /************************/
2400 /* Key Cache Management */
2401 /************************/
2402
2403 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2404 {
2405 u32 keyType;
2406
2407 if (entry >= ah->ah_caps.keycache_size) {
2408 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2409 "entry %u out of range\n", entry);
2410 return false;
2411 }
2412
2413 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2414
2415 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2416 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2417 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2418 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2419 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2420 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2421 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2422 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2423
2424 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2425 u16 micentry = entry + 64;
2426
2427 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2428 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2429 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2430 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2431
2432 }
2433
2434 if (ah->ah_curchan == NULL)
2435 return true;
2436
2437 return true;
2438 }
2439
2440 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2441 {
2442 u32 macHi, macLo;
2443
2444 if (entry >= ah->ah_caps.keycache_size) {
2445 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2446 "entry %u out of range\n", entry);
2447 return false;
2448 }
2449
2450 if (mac != NULL) {
2451 macHi = (mac[5] << 8) | mac[4];
2452 macLo = (mac[3] << 24) |
2453 (mac[2] << 16) |
2454 (mac[1] << 8) |
2455 mac[0];
2456 macLo >>= 1;
2457 macLo |= (macHi & 1) << 31;
2458 macHi >>= 1;
2459 } else {
2460 macLo = macHi = 0;
2461 }
2462 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2463 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2464
2465 return true;
2466 }
2467
2468 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2469 const struct ath9k_keyval *k,
2470 const u8 *mac, int xorKey)
2471 {
2472 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2473 u32 key0, key1, key2, key3, key4;
2474 u32 keyType;
2475 u32 xorMask = xorKey ?
2476 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2477 | ATH9K_KEY_XOR) : 0;
2478 struct ath_hal_5416 *ahp = AH5416(ah);
2479
2480 if (entry >= pCap->keycache_size) {
2481 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2482 "entry %u out of range\n", entry);
2483 return false;
2484 }
2485
2486 switch (k->kv_type) {
2487 case ATH9K_CIPHER_AES_OCB:
2488 keyType = AR_KEYTABLE_TYPE_AES;
2489 break;
2490 case ATH9K_CIPHER_AES_CCM:
2491 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2492 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2493 "AES-CCM not supported by mac rev 0x%x\n",
2494 ah->ah_macRev);
2495 return false;
2496 }
2497 keyType = AR_KEYTABLE_TYPE_CCM;
2498 break;
2499 case ATH9K_CIPHER_TKIP:
2500 keyType = AR_KEYTABLE_TYPE_TKIP;
2501 if (ATH9K_IS_MIC_ENABLED(ah)
2502 && entry + 64 >= pCap->keycache_size) {
2503 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2504 "entry %u inappropriate for TKIP\n", entry);
2505 return false;
2506 }
2507 break;
2508 case ATH9K_CIPHER_WEP:
2509 if (k->kv_len < LEN_WEP40) {
2510 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2511 "WEP key length %u too small\n", k->kv_len);
2512 return false;
2513 }
2514 if (k->kv_len <= LEN_WEP40)
2515 keyType = AR_KEYTABLE_TYPE_40;
2516 else if (k->kv_len <= LEN_WEP104)
2517 keyType = AR_KEYTABLE_TYPE_104;
2518 else
2519 keyType = AR_KEYTABLE_TYPE_128;
2520 break;
2521 case ATH9K_CIPHER_CLR:
2522 keyType = AR_KEYTABLE_TYPE_CLR;
2523 break;
2524 default:
2525 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2526 "cipher %u not supported\n", k->kv_type);
2527 return false;
2528 }
2529
2530 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2531 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2532 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2533 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2534 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2535 if (k->kv_len <= LEN_WEP104)
2536 key4 &= 0xff;
2537
2538 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2539 u16 micentry = entry + 64;
2540
2541 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2542 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2543 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2544 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2545 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2546 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2547 (void) ath9k_hw_keysetmac(ah, entry, mac);
2548
2549 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2550 u32 mic0, mic1, mic2, mic3, mic4;
2551
2552 mic0 = get_unaligned_le32(k->kv_mic + 0);
2553 mic2 = get_unaligned_le32(k->kv_mic + 4);
2554 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2555 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2556 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2557 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2558 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2559 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2560 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2561 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2562 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2563 AR_KEYTABLE_TYPE_CLR);
2564
2565 } else {
2566 u32 mic0, mic2;
2567
2568 mic0 = get_unaligned_le32(k->kv_mic + 0);
2569 mic2 = get_unaligned_le32(k->kv_mic + 4);
2570 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2571 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2572 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2573 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2574 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2575 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2576 AR_KEYTABLE_TYPE_CLR);
2577 }
2578 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2579 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2580 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2581 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2582 } else {
2583 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2584 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2585 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2586 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2587 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2588 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2589
2590 (void) ath9k_hw_keysetmac(ah, entry, mac);
2591 }
2592
2593 if (ah->ah_curchan == NULL)
2594 return true;
2595
2596 return true;
2597 }
2598
2599 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2600 {
2601 if (entry < ah->ah_caps.keycache_size) {
2602 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2603 if (val & AR_KEYTABLE_VALID)
2604 return true;
2605 }
2606 return false;
2607 }
2608
2609 /******************************/
2610 /* Power Management (Chipset) */
2611 /******************************/
2612
2613 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2614 {
2615 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2616 if (setChip) {
2617 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2618 AR_RTC_FORCE_WAKE_EN);
2619 if (!AR_SREV_9100(ah))
2620 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2621
2622 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2623 AR_RTC_RESET_EN);
2624 }
2625 }
2626
2627 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2628 {
2629 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2630 if (setChip) {
2631 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2632
2633 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2634 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2635 AR_RTC_FORCE_WAKE_ON_INT);
2636 } else {
2637 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2638 AR_RTC_FORCE_WAKE_EN);
2639 }
2640 }
2641 }
2642
2643 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2644 int setChip)
2645 {
2646 u32 val;
2647 int i;
2648
2649 if (setChip) {
2650 if ((REG_READ(ah, AR_RTC_STATUS) &
2651 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2652 if (ath9k_hw_set_reset_reg(ah,
2653 ATH9K_RESET_POWER_ON) != true) {
2654 return false;
2655 }
2656 }
2657 if (AR_SREV_9100(ah))
2658 REG_SET_BIT(ah, AR_RTC_RESET,
2659 AR_RTC_RESET_EN);
2660
2661 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2662 AR_RTC_FORCE_WAKE_EN);
2663 udelay(50);
2664
2665 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2666 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2667 if (val == AR_RTC_STATUS_ON)
2668 break;
2669 udelay(50);
2670 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2671 AR_RTC_FORCE_WAKE_EN);
2672 }
2673 if (i == 0) {
2674 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2675 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2676 return false;
2677 }
2678 }
2679
2680 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2681
2682 return true;
2683 }
2684
2685 bool ath9k_hw_setpower(struct ath_hal *ah,
2686 enum ath9k_power_mode mode)
2687 {
2688 struct ath_hal_5416 *ahp = AH5416(ah);
2689 static const char *modes[] = {
2690 "AWAKE",
2691 "FULL-SLEEP",
2692 "NETWORK SLEEP",
2693 "UNDEFINED"
2694 };
2695 int status = true, setChip = true;
2696
2697 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2698 modes[ahp->ah_powerMode], modes[mode],
2699 setChip ? "set chip " : "");
2700
2701 switch (mode) {
2702 case ATH9K_PM_AWAKE:
2703 status = ath9k_hw_set_power_awake(ah, setChip);
2704 break;
2705 case ATH9K_PM_FULL_SLEEP:
2706 ath9k_set_power_sleep(ah, setChip);
2707 ahp->ah_chipFullSleep = true;
2708 break;
2709 case ATH9K_PM_NETWORK_SLEEP:
2710 ath9k_set_power_network_sleep(ah, setChip);
2711 break;
2712 default:
2713 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2714 "Unknown power mode %u\n", mode);
2715 return false;
2716 }
2717 ahp->ah_powerMode = mode;
2718
2719 return status;
2720 }
2721
2722 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2723 {
2724 struct ath_hal_5416 *ahp = AH5416(ah);
2725 u8 i;
2726
2727 if (ah->ah_isPciExpress != true)
2728 return;
2729
2730 if (ah->ah_config.pcie_powersave_enable == 2)
2731 return;
2732
2733 if (restore)
2734 return;
2735
2736 if (AR_SREV_9280_20_OR_LATER(ah)) {
2737 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2738 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2739 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2740 }
2741 udelay(1000);
2742 } else if (AR_SREV_9280(ah) &&
2743 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2744 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2745 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2746
2747 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2748 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2749 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2750
2751 if (ah->ah_config.pcie_clock_req)
2752 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2753 else
2754 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2755
2756 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2757 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2758 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2759
2760 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2761
2762 udelay(1000);
2763 } else {
2764 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2765 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2766 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2767 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2768 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2769 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2770 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2771 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2772 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2773 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2774 }
2775
2776 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2777
2778 if (ah->ah_config.pcie_waen) {
2779 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2780 } else {
2781 if (AR_SREV_9285(ah))
2782 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2783 else if (AR_SREV_9280(ah))
2784 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2785 else
2786 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2787 }
2788
2789 }
2790
2791 /**********************/
2792 /* Interrupt Handling */
2793 /**********************/
2794
2795 bool ath9k_hw_intrpend(struct ath_hal *ah)
2796 {
2797 u32 host_isr;
2798
2799 if (AR_SREV_9100(ah))
2800 return true;
2801
2802 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2803 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2804 return true;
2805
2806 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2807 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2808 && (host_isr != AR_INTR_SPURIOUS))
2809 return true;
2810
2811 return false;
2812 }
2813
2814 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2815 {
2816 u32 isr = 0;
2817 u32 mask2 = 0;
2818 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2819 u32 sync_cause = 0;
2820 bool fatal_int = false;
2821 struct ath_hal_5416 *ahp = AH5416(ah);
2822
2823 if (!AR_SREV_9100(ah)) {
2824 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2825 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2826 == AR_RTC_STATUS_ON) {
2827 isr = REG_READ(ah, AR_ISR);
2828 }
2829 }
2830
2831 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2832 AR_INTR_SYNC_DEFAULT;
2833
2834 *masked = 0;
2835
2836 if (!isr && !sync_cause)
2837 return false;
2838 } else {
2839 *masked = 0;
2840 isr = REG_READ(ah, AR_ISR);
2841 }
2842
2843 if (isr) {
2844 if (isr & AR_ISR_BCNMISC) {
2845 u32 isr2;
2846 isr2 = REG_READ(ah, AR_ISR_S2);
2847 if (isr2 & AR_ISR_S2_TIM)
2848 mask2 |= ATH9K_INT_TIM;
2849 if (isr2 & AR_ISR_S2_DTIM)
2850 mask2 |= ATH9K_INT_DTIM;
2851 if (isr2 & AR_ISR_S2_DTIMSYNC)
2852 mask2 |= ATH9K_INT_DTIMSYNC;
2853 if (isr2 & (AR_ISR_S2_CABEND))
2854 mask2 |= ATH9K_INT_CABEND;
2855 if (isr2 & AR_ISR_S2_GTT)
2856 mask2 |= ATH9K_INT_GTT;
2857 if (isr2 & AR_ISR_S2_CST)
2858 mask2 |= ATH9K_INT_CST;
2859 }
2860
2861 isr = REG_READ(ah, AR_ISR_RAC);
2862 if (isr == 0xffffffff) {
2863 *masked = 0;
2864 return false;
2865 }
2866
2867 *masked = isr & ATH9K_INT_COMMON;
2868
2869 if (ahp->ah_intrMitigation) {
2870 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2871 *masked |= ATH9K_INT_RX;
2872 }
2873
2874 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2875 *masked |= ATH9K_INT_RX;
2876 if (isr &
2877 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2878 AR_ISR_TXEOL)) {
2879 u32 s0_s, s1_s;
2880
2881 *masked |= ATH9K_INT_TX;
2882
2883 s0_s = REG_READ(ah, AR_ISR_S0_S);
2884 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2885 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2886
2887 s1_s = REG_READ(ah, AR_ISR_S1_S);
2888 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2889 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2890 }
2891
2892 if (isr & AR_ISR_RXORN) {
2893 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2894 "receive FIFO overrun interrupt\n");
2895 }
2896
2897 if (!AR_SREV_9100(ah)) {
2898 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2899 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2900 if (isr5 & AR_ISR_S5_TIM_TIMER)
2901 *masked |= ATH9K_INT_TIM_TIMER;
2902 }
2903 }
2904
2905 *masked |= mask2;
2906 }
2907
2908 if (AR_SREV_9100(ah))
2909 return true;
2910
2911 if (sync_cause) {
2912 fatal_int =
2913 (sync_cause &
2914 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2915 ? true : false;
2916
2917 if (fatal_int) {
2918 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2919 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2920 "received PCI FATAL interrupt\n");
2921 }
2922 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2923 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2924 "received PCI PERR interrupt\n");
2925 }
2926 }
2927 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2928 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2929 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2930 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2931 REG_WRITE(ah, AR_RC, 0);
2932 *masked |= ATH9K_INT_FATAL;
2933 }
2934 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2935 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2936 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2937 }
2938
2939 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2940 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2941 }
2942
2943 return true;
2944 }
2945
2946 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2947 {
2948 return AH5416(ah)->ah_maskReg;
2949 }
2950
2951 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2952 {
2953 struct ath_hal_5416 *ahp = AH5416(ah);
2954 u32 omask = ahp->ah_maskReg;
2955 u32 mask, mask2;
2956 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2957
2958 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2959
2960 if (omask & ATH9K_INT_GLOBAL) {
2961 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2962 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2963 (void) REG_READ(ah, AR_IER);
2964 if (!AR_SREV_9100(ah)) {
2965 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2966 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2967
2968 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2969 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2970 }
2971 }
2972
2973 mask = ints & ATH9K_INT_COMMON;
2974 mask2 = 0;
2975
2976 if (ints & ATH9K_INT_TX) {
2977 if (ahp->ah_txOkInterruptMask)
2978 mask |= AR_IMR_TXOK;
2979 if (ahp->ah_txDescInterruptMask)
2980 mask |= AR_IMR_TXDESC;
2981 if (ahp->ah_txErrInterruptMask)
2982 mask |= AR_IMR_TXERR;
2983 if (ahp->ah_txEolInterruptMask)
2984 mask |= AR_IMR_TXEOL;
2985 }
2986 if (ints & ATH9K_INT_RX) {
2987 mask |= AR_IMR_RXERR;
2988 if (ahp->ah_intrMitigation)
2989 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2990 else
2991 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2992 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2993 mask |= AR_IMR_GENTMR;
2994 }
2995
2996 if (ints & (ATH9K_INT_BMISC)) {
2997 mask |= AR_IMR_BCNMISC;
2998 if (ints & ATH9K_INT_TIM)
2999 mask2 |= AR_IMR_S2_TIM;
3000 if (ints & ATH9K_INT_DTIM)
3001 mask2 |= AR_IMR_S2_DTIM;
3002 if (ints & ATH9K_INT_DTIMSYNC)
3003 mask2 |= AR_IMR_S2_DTIMSYNC;
3004 if (ints & ATH9K_INT_CABEND)
3005 mask2 |= (AR_IMR_S2_CABEND);
3006 }
3007
3008 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3009 mask |= AR_IMR_BCNMISC;
3010 if (ints & ATH9K_INT_GTT)
3011 mask2 |= AR_IMR_S2_GTT;
3012 if (ints & ATH9K_INT_CST)
3013 mask2 |= AR_IMR_S2_CST;
3014 }
3015
3016 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3017 REG_WRITE(ah, AR_IMR, mask);
3018 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3019 AR_IMR_S2_DTIM |
3020 AR_IMR_S2_DTIMSYNC |
3021 AR_IMR_S2_CABEND |
3022 AR_IMR_S2_CABTO |
3023 AR_IMR_S2_TSFOOR |
3024 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3025 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3026 ahp->ah_maskReg = ints;
3027
3028 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3029 if (ints & ATH9K_INT_TIM_TIMER)
3030 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3031 else
3032 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3033 }
3034
3035 if (ints & ATH9K_INT_GLOBAL) {
3036 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3037 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3038 if (!AR_SREV_9100(ah)) {
3039 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3040 AR_INTR_MAC_IRQ);
3041 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3042
3043
3044 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3045 AR_INTR_SYNC_DEFAULT);
3046 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3047 AR_INTR_SYNC_DEFAULT);
3048 }
3049 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3050 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3051 }
3052
3053 return omask;
3054 }
3055
3056 /*******************/
3057 /* Beacon Handling */
3058 /*******************/
3059
3060 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3061 {
3062 struct ath_hal_5416 *ahp = AH5416(ah);
3063 int flags = 0;
3064
3065 ahp->ah_beaconInterval = beacon_period;
3066
3067 switch (ah->ah_opmode) {
3068 case NL80211_IFTYPE_STATION:
3069 case NL80211_IFTYPE_MONITOR:
3070 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3071 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3072 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3073 flags |= AR_TBTT_TIMER_EN;
3074 break;
3075 case NL80211_IFTYPE_ADHOC:
3076 REG_SET_BIT(ah, AR_TXCFG,
3077 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3078 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3079 TU_TO_USEC(next_beacon +
3080 (ahp->ah_atimWindow ? ahp->
3081 ah_atimWindow : 1)));
3082 flags |= AR_NDP_TIMER_EN;
3083 case NL80211_IFTYPE_AP:
3084 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3085 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3086 TU_TO_USEC(next_beacon -
3087 ah->ah_config.
3088 dma_beacon_response_time));
3089 REG_WRITE(ah, AR_NEXT_SWBA,
3090 TU_TO_USEC(next_beacon -
3091 ah->ah_config.
3092 sw_beacon_response_time));
3093 flags |=
3094 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3095 break;
3096 default:
3097 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3098 "%s: unsupported opmode: %d\n",
3099 __func__, ah->ah_opmode);
3100 return;
3101 break;
3102 }
3103
3104 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3105 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3106 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3107 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3108
3109 beacon_period &= ~ATH9K_BEACON_ENA;
3110 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3111 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3112 ath9k_hw_reset_tsf(ah);
3113 }
3114
3115 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3116 }
3117
3118 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3119 const struct ath9k_beacon_state *bs)
3120 {
3121 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3122 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3123
3124 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3125
3126 REG_WRITE(ah, AR_BEACON_PERIOD,
3127 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3128 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3129 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3130
3131 REG_RMW_FIELD(ah, AR_RSSI_THR,
3132 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3133
3134 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3135
3136 if (bs->bs_sleepduration > beaconintval)
3137 beaconintval = bs->bs_sleepduration;
3138
3139 dtimperiod = bs->bs_dtimperiod;
3140 if (bs->bs_sleepduration > dtimperiod)
3141 dtimperiod = bs->bs_sleepduration;
3142
3143 if (beaconintval == dtimperiod)
3144 nextTbtt = bs->bs_nextdtim;
3145 else
3146 nextTbtt = bs->bs_nexttbtt;
3147
3148 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3149 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3150 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3151 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3152
3153 REG_WRITE(ah, AR_NEXT_DTIM,
3154 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3155 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3156
3157 REG_WRITE(ah, AR_SLEEP1,
3158 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3159 | AR_SLEEP1_ASSUME_DTIM);
3160
3161 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3162 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3163 else
3164 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3165
3166 REG_WRITE(ah, AR_SLEEP2,
3167 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3168
3169 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3170 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3171
3172 REG_SET_BIT(ah, AR_TIMER_MODE,
3173 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3174 AR_DTIM_TIMER_EN);
3175
3176 }
3177
3178 /*******************/
3179 /* HW Capabilities */
3180 /*******************/
3181
3182 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3183 {
3184 struct ath_hal_5416 *ahp = AH5416(ah);
3185 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3186 u16 capField = 0, eeval;
3187
3188 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3189
3190 ah->ah_currentRD = eeval;
3191
3192 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3193 ah->ah_currentRDExt = eeval;
3194
3195 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3196
3197 if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3198 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3199 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3200 ah->ah_currentRD += 5;
3201 else if (ah->ah_currentRD == 0x41)
3202 ah->ah_currentRD = 0x43;
3203 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3204 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3205 }
3206
3207 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3208 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3209
3210 if (eeval & AR5416_OPFLAGS_11A) {
3211 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3212 if (ah->ah_config.ht_enable) {
3213 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3214 set_bit(ATH9K_MODE_11NA_HT20,
3215 pCap->wireless_modes);
3216 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3217 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3218 pCap->wireless_modes);
3219 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3220 pCap->wireless_modes);
3221 }
3222 }
3223 }
3224
3225 if (eeval & AR5416_OPFLAGS_11G) {
3226 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3227 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3228 if (ah->ah_config.ht_enable) {
3229 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3230 set_bit(ATH9K_MODE_11NG_HT20,
3231 pCap->wireless_modes);
3232 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3233 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3234 pCap->wireless_modes);
3235 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3236 pCap->wireless_modes);
3237 }
3238 }
3239 }
3240
3241 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3242 if ((ah->ah_isPciExpress)
3243 || (eeval & AR5416_OPFLAGS_11A)) {
3244 pCap->rx_chainmask =
3245 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3246 } else {
3247 pCap->rx_chainmask =
3248 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3249 }
3250
3251 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3252 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3253
3254 pCap->low_2ghz_chan = 2312;
3255 pCap->high_2ghz_chan = 2732;
3256
3257 pCap->low_5ghz_chan = 4920;
3258 pCap->high_5ghz_chan = 6100;
3259
3260 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3261 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3262 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3263
3264 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3265 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3266 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3267
3268 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3269
3270 if (ah->ah_config.ht_enable)
3271 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3272 else
3273 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3274
3275 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3276 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3277 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3278 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3279
3280 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3281 pCap->total_queues =
3282 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3283 else
3284 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3285
3286 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3287 pCap->keycache_size =
3288 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3289 else
3290 pCap->keycache_size = AR_KEYTABLE_SIZE;
3291
3292 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3293 pCap->num_mr_retries = 4;
3294 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3295
3296 if (AR_SREV_9285_10_OR_LATER(ah))
3297 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3298 else if (AR_SREV_9280_10_OR_LATER(ah))
3299 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3300 else
3301 pCap->num_gpio_pins = AR_NUM_GPIO;
3302
3303 if (AR_SREV_9280_10_OR_LATER(ah)) {
3304 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3305 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3306 } else {
3307 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3308 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3309 }
3310
3311 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3312 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3313 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3314 } else {
3315 pCap->rts_aggr_limit = (8 * 1024);
3316 }
3317
3318 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3319
3320 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3321 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3322 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3323 ah->ah_rfkill_gpio =
3324 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3325 ah->ah_rfkill_polarity =
3326 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3327
3328 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3329 }
3330 #endif
3331
3332 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3333 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3334 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3335 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3336 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3337 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3338 else
3339 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3340
3341 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3342 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3343 else
3344 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3345
3346 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3347 pCap->reg_cap =
3348 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3349 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3350 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3351 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3352 } else {
3353 pCap->reg_cap =
3354 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3355 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3356 }
3357
3358 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3359
3360 pCap->num_antcfg_5ghz =
3361 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3362 pCap->num_antcfg_2ghz =
3363 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3364
3365 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3366 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3367 ah->ah_btactive_gpio = 6;
3368 ah->ah_wlanactive_gpio = 5;
3369 }
3370
3371 return true;
3372 }
3373
3374 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3375 u32 capability, u32 *result)
3376 {
3377 struct ath_hal_5416 *ahp = AH5416(ah);
3378 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3379
3380 switch (type) {
3381 case ATH9K_CAP_CIPHER:
3382 switch (capability) {
3383 case ATH9K_CIPHER_AES_CCM:
3384 case ATH9K_CIPHER_AES_OCB:
3385 case ATH9K_CIPHER_TKIP:
3386 case ATH9K_CIPHER_WEP:
3387 case ATH9K_CIPHER_MIC:
3388 case ATH9K_CIPHER_CLR:
3389 return true;
3390 default:
3391 return false;
3392 }
3393 case ATH9K_CAP_TKIP_MIC:
3394 switch (capability) {
3395 case 0:
3396 return true;
3397 case 1:
3398 return (ahp->ah_staId1Defaults &
3399 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3400 false;
3401 }
3402 case ATH9K_CAP_TKIP_SPLIT:
3403 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3404 false : true;
3405 case ATH9K_CAP_WME_TKIPMIC:
3406 return 0;
3407 case ATH9K_CAP_PHYCOUNTERS:
3408 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3409 case ATH9K_CAP_DIVERSITY:
3410 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3411 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3412 true : false;
3413 case ATH9K_CAP_PHYDIAG:
3414 return true;
3415 case ATH9K_CAP_MCAST_KEYSRCH:
3416 switch (capability) {
3417 case 0:
3418 return true;
3419 case 1:
3420 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3421 return false;
3422 } else {
3423 return (ahp->ah_staId1Defaults &
3424 AR_STA_ID1_MCAST_KSRCH) ? true :
3425 false;
3426 }
3427 }
3428 return false;
3429 case ATH9K_CAP_TSF_ADJUST:
3430 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3431 true : false;
3432 case ATH9K_CAP_RFSILENT:
3433 if (capability == 3)
3434 return false;
3435 case ATH9K_CAP_ANT_CFG_2GHZ:
3436 *result = pCap->num_antcfg_2ghz;
3437 return true;
3438 case ATH9K_CAP_ANT_CFG_5GHZ:
3439 *result = pCap->num_antcfg_5ghz;
3440 return true;
3441 case ATH9K_CAP_TXPOW:
3442 switch (capability) {
3443 case 0:
3444 return 0;
3445 case 1:
3446 *result = ah->ah_powerLimit;
3447 return 0;
3448 case 2:
3449 *result = ah->ah_maxPowerLevel;
3450 return 0;
3451 case 3:
3452 *result = ah->ah_tpScale;
3453 return 0;
3454 }
3455 return false;
3456 default:
3457 return false;
3458 }
3459 }
3460
3461 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3462 u32 capability, u32 setting, int *status)
3463 {
3464 struct ath_hal_5416 *ahp = AH5416(ah);
3465 u32 v;
3466
3467 switch (type) {
3468 case ATH9K_CAP_TKIP_MIC:
3469 if (setting)
3470 ahp->ah_staId1Defaults |=
3471 AR_STA_ID1_CRPT_MIC_ENABLE;
3472 else
3473 ahp->ah_staId1Defaults &=
3474 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3475 return true;
3476 case ATH9K_CAP_DIVERSITY:
3477 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3478 if (setting)
3479 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3480 else
3481 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3482 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3483 return true;
3484 case ATH9K_CAP_MCAST_KEYSRCH:
3485 if (setting)
3486 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3487 else
3488 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3489 return true;
3490 case ATH9K_CAP_TSF_ADJUST:
3491 if (setting)
3492 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3493 else
3494 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3495 return true;
3496 default:
3497 return false;
3498 }
3499 }
3500
3501 /****************************/
3502 /* GPIO / RFKILL / Antennae */
3503 /****************************/
3504
3505 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3506 u32 gpio, u32 type)
3507 {
3508 int addr;
3509 u32 gpio_shift, tmp;
3510
3511 if (gpio > 11)
3512 addr = AR_GPIO_OUTPUT_MUX3;
3513 else if (gpio > 5)
3514 addr = AR_GPIO_OUTPUT_MUX2;
3515 else
3516 addr = AR_GPIO_OUTPUT_MUX1;
3517
3518 gpio_shift = (gpio % 6) * 5;
3519
3520 if (AR_SREV_9280_20_OR_LATER(ah)
3521 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3522 REG_RMW(ah, addr, (type << gpio_shift),
3523 (0x1f << gpio_shift));
3524 } else {
3525 tmp = REG_READ(ah, addr);
3526 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3527 tmp &= ~(0x1f << gpio_shift);
3528 tmp |= (type << gpio_shift);
3529 REG_WRITE(ah, addr, tmp);
3530 }
3531 }
3532
3533 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3534 {
3535 u32 gpio_shift;
3536
3537 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3538
3539 gpio_shift = gpio << 1;
3540
3541 REG_RMW(ah,
3542 AR_GPIO_OE_OUT,
3543 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3544 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3545 }
3546
3547 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3548 {
3549 #define MS_REG_READ(x, y) \
3550 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3551
3552 if (gpio >= ah->ah_caps.num_gpio_pins)
3553 return 0xffffffff;
3554
3555 if (AR_SREV_9285_10_OR_LATER(ah))
3556 return MS_REG_READ(AR9285, gpio) != 0;
3557 else if (AR_SREV_9280_10_OR_LATER(ah))
3558 return MS_REG_READ(AR928X, gpio) != 0;
3559 else
3560 return MS_REG_READ(AR, gpio) != 0;
3561 }
3562
3563 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3564 u32 ah_signal_type)
3565 {
3566 u32 gpio_shift;
3567
3568 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3569
3570 gpio_shift = 2 * gpio;
3571
3572 REG_RMW(ah,
3573 AR_GPIO_OE_OUT,
3574 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3575 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3576 }
3577
3578 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3579 {
3580 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3581 AR_GPIO_BIT(gpio));
3582 }
3583
3584 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3585 void ath9k_enable_rfkill(struct ath_hal *ah)
3586 {
3587 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3588 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3589
3590 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3591 AR_GPIO_INPUT_MUX2_RFSILENT);
3592
3593 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3594 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3595 }
3596 #endif
3597
3598 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3599 {
3600 struct ath9k_channel *chan = ah->ah_curchan;
3601 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3602 u16 ant_config;
3603 u32 halNumAntConfig;
3604
3605 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3606 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3607
3608 if (cfg < halNumAntConfig) {
3609 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3610 cfg, &ant_config)) {
3611 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3612 return 0;
3613 }
3614 }
3615
3616 return -EINVAL;
3617 }
3618
3619 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3620 {
3621 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3622 }
3623
3624 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3625 {
3626 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3627 }
3628
3629 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3630 enum ath9k_ant_setting settings,
3631 struct ath9k_channel *chan,
3632 u8 *tx_chainmask,
3633 u8 *rx_chainmask,
3634 u8 *antenna_cfgd)
3635 {
3636 struct ath_hal_5416 *ahp = AH5416(ah);
3637 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3638
3639 if (AR_SREV_9280(ah)) {
3640 if (!tx_chainmask_cfg) {
3641
3642 tx_chainmask_cfg = *tx_chainmask;
3643 rx_chainmask_cfg = *rx_chainmask;
3644 }
3645
3646 switch (settings) {
3647 case ATH9K_ANT_FIXED_A:
3648 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3649 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3650 *antenna_cfgd = true;
3651 break;
3652 case ATH9K_ANT_FIXED_B:
3653 if (ah->ah_caps.tx_chainmask >
3654 ATH9K_ANTENNA1_CHAINMASK) {
3655 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3656 }
3657 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3658 *antenna_cfgd = true;
3659 break;
3660 case ATH9K_ANT_VARIABLE:
3661 *tx_chainmask = tx_chainmask_cfg;
3662 *rx_chainmask = rx_chainmask_cfg;
3663 *antenna_cfgd = true;
3664 break;
3665 default:
3666 break;
3667 }
3668 } else {
3669 ahp->ah_diversityControl = settings;
3670 }
3671
3672 return true;
3673 }
3674
3675 /*********************/
3676 /* General Operation */
3677 /*********************/
3678
3679 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3680 {
3681 u32 bits = REG_READ(ah, AR_RX_FILTER);
3682 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3683
3684 if (phybits & AR_PHY_ERR_RADAR)
3685 bits |= ATH9K_RX_FILTER_PHYRADAR;
3686 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3687 bits |= ATH9K_RX_FILTER_PHYERR;
3688
3689 return bits;
3690 }
3691
3692 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3693 {
3694 u32 phybits;
3695
3696 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3697 phybits = 0;
3698 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3699 phybits |= AR_PHY_ERR_RADAR;
3700 if (bits & ATH9K_RX_FILTER_PHYERR)
3701 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3702 REG_WRITE(ah, AR_PHY_ERR, phybits);
3703
3704 if (phybits)
3705 REG_WRITE(ah, AR_RXCFG,
3706 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3707 else
3708 REG_WRITE(ah, AR_RXCFG,
3709 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3710 }
3711
3712 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3713 {
3714 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3715 }
3716
3717 bool ath9k_hw_disable(struct ath_hal *ah)
3718 {
3719 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3720 return false;
3721
3722 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3723 }
3724
3725 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3726 {
3727 struct ath9k_channel *chan = ah->ah_curchan;
3728
3729 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3730
3731 if (ath9k_hw_set_txpower(ah, chan,
3732 ath9k_regd_get_ctl(ah, chan),
3733 ath9k_regd_get_antenna_allowed(ah, chan),
3734 chan->maxRegTxPower * 2,
3735 min((u32) MAX_RATE_POWER,
3736 (u32) ah->ah_powerLimit)) != 0)
3737 return false;
3738
3739 return true;
3740 }
3741
3742 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3743 {
3744 struct ath_hal_5416 *ahp = AH5416(ah);
3745
3746 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3747 }
3748
3749 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3750 {
3751 struct ath_hal_5416 *ahp = AH5416(ah);
3752
3753 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3754
3755 return true;
3756 }
3757
3758 void ath9k_hw_setopmode(struct ath_hal *ah)
3759 {
3760 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3761 }
3762
3763 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3764 {
3765 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3766 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3767 }
3768
3769 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3770 {
3771 struct ath_hal_5416 *ahp = AH5416(ah);
3772
3773 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3774 }
3775
3776 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3777 {
3778 struct ath_hal_5416 *ahp = AH5416(ah);
3779
3780 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3781
3782 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3783 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3784
3785 return true;
3786 }
3787
3788 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3789 {
3790 struct ath_hal_5416 *ahp = AH5416(ah);
3791
3792 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3793 ahp->ah_assocId = assocId;
3794
3795 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3796 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3797 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3798 }
3799
3800 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3801 {
3802 u64 tsf;
3803
3804 tsf = REG_READ(ah, AR_TSF_U32);
3805 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3806
3807 return tsf;
3808 }
3809
3810 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3811 {
3812 int count;
3813
3814 count = 0;
3815 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3816 count++;
3817 if (count > 10) {
3818 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3819 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3820 break;
3821 }
3822 udelay(10);
3823 }
3824 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3825 }
3826
3827 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3828 {
3829 struct ath_hal_5416 *ahp = AH5416(ah);
3830
3831 if (setting)
3832 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3833 else
3834 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3835
3836 return true;
3837 }
3838
3839 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3840 {
3841 struct ath_hal_5416 *ahp = AH5416(ah);
3842
3843 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3844 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3845 ahp->ah_slottime = (u32) -1;
3846 return false;
3847 } else {
3848 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3849 ahp->ah_slottime = us;
3850 return true;
3851 }
3852 }
3853
3854 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3855 {
3856 u32 macmode;
3857
3858 if (mode == ATH9K_HT_MACMODE_2040 &&
3859 !ah->ah_config.cwm_ignore_extcca)
3860 macmode = AR_2040_JOINED_RX_CLEAR;
3861 else
3862 macmode = 0;
3863
3864 REG_WRITE(ah, AR_2040_MODE, macmode);
3865 }
3866
3867 /***************************/
3868 /* Bluetooth Coexistence */
3869 /***************************/
3870
3871 void ath9k_hw_btcoex_enable(struct ath_hal *ah)
3872 {
3873 /* connect bt_active to baseband */
3874 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3875 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3876 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3877
3878 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3879 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3880
3881 /* Set input mux for bt_active to gpio pin */
3882 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3883 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3884 ah->ah_btactive_gpio);
3885
3886 /* Configure the desired gpio port for input */
3887 ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio);
3888
3889 /* Configure the desired GPIO port for TX_FRAME output */
3890 ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio,
3891 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3892 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree