drivers/video/via/viamode.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24
  25 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
  26 {VIASR, SR15, 0x02, 0x02},
  27 {VIASR, SR16, 0xBF, 0x08},
  28 {VIASR, SR17, 0xFF, 0x1F},
  29 {VIASR, SR18, 0xFF, 0x4E},
  30 {VIASR, SR1A, 0xFB, 0x08},
  31 {VIASR, SR1E, 0x0F, 0x01},
  32 {VIASR, SR2A, 0xFF, 0x00},
  33 {VIACR, CR32, 0xFF, 0x00},
  34 {VIACR, CR33, 0xFF, 0x00},
  35 {VIACR, CR35, 0xFF, 0x00},
  36 {VIACR, CR36, 0x08, 0x00},
  37 {VIACR, CR69, 0xFF, 0x00},
  38 {VIACR, CR6A, 0xFF, 0x40},
  39 {VIACR, CR6B, 0xFF, 0x00},
  40 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
  41 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
  42 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
  43 {VIACR, CR8B, 0xFF, 0x69},      /* LCD Power Sequence Control 0        */
  44 {VIACR, CR8C, 0xFF, 0x57},      /* LCD Power Sequence Control 1        */
  45 {VIACR, CR8D, 0xFF, 0x00},      /* LCD Power Sequence Control 2        */
  46 {VIACR, CR8E, 0xFF, 0x7B},      /* LCD Power Sequence Control 3        */
  47 {VIACR, CR8F, 0xFF, 0x03},      /* LCD Power Sequence Control 4        */
  48 {VIACR, CR90, 0xFF, 0x30},      /* LCD Power Sequence Control 5        */
  49 {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off             */
  50 {VIACR, CR96, 0xFF, 0x00},
  51 {VIACR, CR97, 0xFF, 0x00},
  52 {VIACR, CR99, 0xFF, 0x00},
  53 {VIACR, CR9B, 0xFF, 0x00}
  54 };
  55
  56 /* Video Mode Table for VT3314 chipset*/
  57 /* Common Setting for Video Mode */
  58 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
  59 {VIASR, SR15, 0x02, 0x02},
  60 {VIASR, SR16, 0xBF, 0x08},
  61 {VIASR, SR17, 0xFF, 0x1F},
  62 {VIASR, SR18, 0xFF, 0x4E},
  63 {VIASR, SR1A, 0xFB, 0x82},
  64 {VIASR, SR1B, 0xFF, 0xF0},
  65 {VIASR, SR1F, 0xFF, 0x00},
  66 {VIASR, SR1E, 0xFF, 0x01},
  67 {VIASR, SR22, 0xFF, 0x1F},
  68 {VIASR, SR2A, 0x0F, 0x00},
  69 {VIASR, SR2E, 0xFF, 0xFF},
  70 {VIASR, SR3F, 0xFF, 0xFF},
  71 {VIASR, SR40, 0xF7, 0x00},
  72 {VIASR, CR30, 0xFF, 0x04},
  73 {VIACR, CR32, 0xFF, 0x00},
  74 {VIACR, CR33, 0x7F, 0x00},
  75 {VIACR, CR35, 0xFF, 0x00},
  76 {VIACR, CR36, 0xFF, 0x31},
  77 {VIACR, CR41, 0xFF, 0x80},
  78 {VIACR, CR42, 0xFF, 0x00},
  79 {VIACR, CR55, 0x80, 0x00},
  80 {VIACR, CR5D, 0x80, 0x00},      /*Horizontal Retrace Start bit[11] should be 0*/
  81 {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2 */
  82 {VIACR, CR69, 0xFF, 0x00},
  83 {VIACR, CR6A, 0xFD, 0x40},
  84 {VIACR, CR6B, 0xFF, 0x00},
  85 {VIACR, CR77, 0xFF, 0x00},      /* LCD scaling Factor */
  86 {VIACR, CR78, 0xFF, 0x00},      /* LCD scaling Factor */
  87 {VIACR, CR79, 0xFF, 0x00},      /* LCD scaling Factor */
  88 {VIACR, CR9F, 0x03, 0x00},      /* LCD scaling Factor */
  89 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type */
  90 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0 */
  91 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1 */
  92 {VIACR, CR8B, 0xFF, 0x5D},      /* LCD Power Sequence Control 0 */
  93 {VIACR, CR8C, 0xFF, 0x2B},      /* LCD Power Sequence Control 1 */
  94 {VIACR, CR8D, 0xFF, 0x6F},      /* LCD Power Sequence Control 2 */
  95 {VIACR, CR8E, 0xFF, 0x2B},      /* LCD Power Sequence Control 3 */
  96 {VIACR, CR8F, 0xFF, 0x01},      /* LCD Power Sequence Control 4 */
  97 {VIACR, CR90, 0xFF, 0x01},      /* LCD Power Sequence Control 5 */
  98 {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off */
  99 {VIACR, CR96, 0xFF, 0x00},
 100 {VIACR, CR97, 0xFF, 0x00},
 101 {VIACR, CR99, 0xFF, 0x00},
 102 {VIACR, CR9B, 0xFF, 0x00},
 103 {VIACR, CR9D, 0xFF, 0x80},
 104 {VIACR, CR9E, 0xFF, 0x80}
 105 };
 106
 107 struct io_reg KM400_ModeXregs[] = {
 108         {VIASR, SR10, 0xFF, 0x01},      /* Unlock Register                 */
 109         {VIASR, SR16, 0xFF, 0x08},      /* Display FIFO threshold Control  */
 110         {VIASR, SR17, 0xFF, 0x1F},      /* Display FIFO Control            */
 111         {VIASR, SR18, 0xFF, 0x4E},      /* GFX PREQ threshold              */
 112         {VIASR, SR1A, 0xFF, 0x0a},      /* GFX PREQ threshold              */
 113         {VIASR, SR1F, 0xFF, 0x00},      /* Memory Control 0                */
 114         {VIASR, SR1B, 0xFF, 0xF0},      /* Power Management Control 0      */
 115         {VIASR, SR1E, 0xFF, 0x01},      /* Power Management Control        */
 116         {VIASR, SR20, 0xFF, 0x00},      /* Sequencer Arbiter Control 0     */
 117         {VIASR, SR21, 0xFF, 0x00},      /* Sequencer Arbiter Control 1     */
 118         {VIASR, SR22, 0xFF, 0x1F},      /* Display Arbiter Control 1       */
 119         {VIASR, SR2A, 0xFF, 0x00},      /* Power Management Control 5      */
 120         {VIASR, SR2D, 0xFF, 0xFF},      /* Power Management Control 1      */
 121         {VIASR, SR2E, 0xFF, 0xFF},      /* Power Management Control 2      */
 122         {VIACR, CR33, 0xFF, 0x00},
 123         {VIACR, CR55, 0x80, 0x00},
 124         {VIACR, CR5D, 0x80, 0x00},
 125         {VIACR, CR36, 0xFF, 0x01},      /* Power Mangement 3                  */
 126         {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2              */
 127         {VIACR, CR6A, 0x20, 0x20},      /* Extended FIFO On                   */
 128         {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                     */
 129         {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0               */
 130         {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1               */
 131         {VIACR, CR8B, 0xFF, 0x2D},      /* LCD Power Sequence Control 0       */
 132         {VIACR, CR8C, 0xFF, 0x2D},      /* LCD Power Sequence Control 1       */
 133         {VIACR, CR8D, 0xFF, 0xC8},      /* LCD Power Sequence Control 2       */
 134         {VIACR, CR8E, 0xFF, 0x36},      /* LCD Power Sequence Control 3       */
 135         {VIACR, CR8F, 0xFF, 0x00},      /* LCD Power Sequence Control 4       */
 136         {VIACR, CR90, 0xFF, 0x10},      /* LCD Power Sequence Control 5       */
 137         {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off            */
 138         {VIACR, CR96, 0xFF, 0x03},      /* DVP0        ; DVP0 Clock Skew */
 139         {VIACR, CR97, 0xFF, 0x03},      /* DFP high    ; DFPH Clock Skew */
 140         {VIACR, CR99, 0xFF, 0x03},      /* DFP low           ; DFPL Clock Skew*/
 141         {VIACR, CR9B, 0xFF, 0x07}       /* DVI on DVP1       ; DVP1 Clock Skew*/
 142 };
 143
 144 /* For VT3324: Common Setting for Video Mode */
 145 struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 146 {VIASR, SR15, 0x02, 0x02},
 147 {VIASR, SR16, 0xBF, 0x08},
 148 {VIASR, SR17, 0xFF, 0x1F},
 149 {VIASR, SR18, 0xFF, 0x4E},
 150 {VIASR, SR1A, 0xFB, 0x08},
 151 {VIASR, SR1B, 0xFF, 0xF0},
 152 {VIASR, SR1E, 0xFF, 0x01},
 153 {VIASR, SR2A, 0xFF, 0x00},
 154 {VIASR, SR2D, 0xC0, 0xC0},      /* delayed E3_ECK */
 155 {VIACR, CR32, 0xFF, 0x00},
 156 {VIACR, CR33, 0xFF, 0x00},
 157 {VIACR, CR35, 0xFF, 0x00},
 158 {VIACR, CR36, 0x08, 0x00},
 159 {VIACR, CR47, 0xC8, 0x00},      /* Clear VCK Plus. */
 160 {VIACR, CR69, 0xFF, 0x00},
 161 {VIACR, CR6A, 0xFF, 0x40},
 162 {VIACR, CR6B, 0xFF, 0x00},
 163 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
 164 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
 165 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
 166 {VIACR, CRD4, 0xFF, 0x81},      /* Second power sequence control       */
 167 {VIACR, CR8B, 0xFF, 0x5D},      /* LCD Power Sequence Control 0        */
 168 {VIACR, CR8C, 0xFF, 0x2B},      /* LCD Power Sequence Control 1        */
 169 {VIACR, CR8D, 0xFF, 0x6F},      /* LCD Power Sequence Control 2        */
 170 {VIACR, CR8E, 0xFF, 0x2B},      /* LCD Power Sequence Control 3        */
 171 {VIACR, CR8F, 0xFF, 0x01},      /* LCD Power Sequence Control 4        */
 172 {VIACR, CR90, 0xFF, 0x01},      /* LCD Power Sequence Control 5        */
 173 {VIACR, CR91, 0xFF, 0x80},      /* 24/12 bit LVDS Data off             */
 174 {VIACR, CR96, 0xFF, 0x00},
 175 {VIACR, CR97, 0xFF, 0x00},
 176 {VIACR, CR99, 0xFF, 0x00},
 177 {VIACR, CR9B, 0xFF, 0x00}
 178 };
 179
 180 struct io_reg VX855_ModeXregs[] = {
 181 {VIASR, SR10, 0xFF, 0x01},
 182 {VIASR, SR15, 0x02, 0x02},
 183 {VIASR, SR16, 0xBF, 0x08},
 184 {VIASR, SR17, 0xFF, 0x1F},
 185 {VIASR, SR18, 0xFF, 0x4E},
 186 {VIASR, SR1A, 0xFB, 0x08},
 187 {VIASR, SR1B, 0xFF, 0xF0},
 188 {VIASR, SR1E, 0x07, 0x01},
 189 {VIASR, SR2A, 0xF0, 0x00},
 190 {VIASR, SR58, 0xFF, 0x00},
 191 {VIASR, SR59, 0xFF, 0x00},
 192 {VIASR, SR2D, 0xC0, 0xC0},      /* delayed E3_ECK */
 193 {VIACR, CR32, 0xFF, 0x00},
 194 {VIACR, CR33, 0x7F, 0x00},
 195 {VIACR, CR35, 0xFF, 0x00},
 196 {VIACR, CR36, 0x08, 0x00},
 197 {VIACR, CR69, 0xFF, 0x00},
 198 {VIACR, CR6A, 0xFD, 0x60},
 199 {VIACR, CR6B, 0xFF, 0x00},
 200 {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
 201 {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
 202 {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
 203 {VIACR, CRD4, 0xFF, 0x81},          /* Second power sequence control       */
 204 {VIACR, CR91, 0xFF, 0x80},          /* 24/12 bit LVDS Data off             */
 205 {VIACR, CR96, 0xFF, 0x00},
 206 {VIACR, CR97, 0xFF, 0x00},
 207 {VIACR, CR99, 0xFF, 0x00},
 208 {VIACR, CR9B, 0xFF, 0x00},
 209 {VIACR, CRD2, 0xFF, 0xFF}           /* TMDS/LVDS control register.         */
 210 };
 211
 212 /* Video Mode Table */
 213 /* Common Setting for Video Mode */
 214 struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
 215 {VIASR, SR2A, 0x0F, 0x00},
 216 {VIASR, SR15, 0x02, 0x02},
 217 {VIASR, SR16, 0xBF, 0x08},
 218 {VIASR, SR17, 0xFF, 0x1F},
 219 {VIASR, SR18, 0xFF, 0x4E},
 220 {VIASR, SR1A, 0xFB, 0x08},
 221
 222 {VIACR, CR32, 0xFF, 0x00},
 223 {VIACR, CR35, 0xFF, 0x00},
 224 {VIACR, CR36, 0x08, 0x00},
 225 {VIACR, CR6A, 0xFF, 0x80},
 226 {VIACR, CR6A, 0xFF, 0xC0},
 227
 228 {VIACR, CR55, 0x80, 0x00},
 229 {VIACR, CR5D, 0x80, 0x00},
 230
 231 {VIAGR, GR20, 0xFF, 0x00},
 232 {VIAGR, GR21, 0xFF, 0x00},
 233 {VIAGR, GR22, 0xFF, 0x00},
 234
 235 };
 236
 237 /* Mode:1024X768 */
 238 struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
 239 {VIASR, 0x18, 0xFF, 0x4C}
 240 };
 241
 242 struct patch_table res_patch_table[] = {
 243         {ARRAY_SIZE(PM1024x768), PM1024x768}
 244 };
 245
 246 /* struct VPITTable {
 247         unsigned char  Misc;
 248         unsigned char  SR[StdSR];
 249         unsigned char  CR[StdCR];
 250         unsigned char  GR[StdGR];
 251         unsigned char  AR[StdAR];
 252  };*/
 253
 254 struct VPITTable VPIT = {
 255         /* Msic */
 256         0xC7,
 257         /* Sequencer */
 258         {0x01, 0x0F, 0x00, 0x0E},
 259         /* Graphic Controller */
 260         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
 261         /* Attribute Controller */
 262         {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 263          0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 264          0x01, 0x00, 0x0F, 0x00}
 265 };
 266
 267 /********************/
 268 /* Mode Table       */
 269 /********************/
 270
 271 /* 480x640 */
 272 static struct crt_mode_table CRTM480x640[] = {
 273         /* r_rate,              hsp,             vsp   */
 274         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 275         {REFRESH_60, M480X640_R60_HSP, M480X640_R60_VSP,
 276          {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} }     /* GTF*/
 277 };
 278
 279 /* 640x480*/
 280 static struct crt_mode_table CRTM640x480[] = {
 281         /*r_rate,hsp,vsp */
 282         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 283         {REFRESH_60, M640X480_R60_HSP, M640X480_R60_VSP,
 284          {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
 285         {REFRESH_75, M640X480_R75_HSP, M640X480_R75_VSP,
 286          {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
 287         {REFRESH_85, M640X480_R85_HSP, M640X480_R85_VSP,
 288          {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
 289         {REFRESH_100, M640X480_R100_HSP, M640X480_R100_VSP,
 290          {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
 291         {REFRESH_120, M640X480_R120_HSP, M640X480_R120_VSP,
 292          {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3} } /*GTF*/
 293 };
 294
 295 /*720x480 (GTF)*/
 296 static struct crt_mode_table CRTM720x480[] = {
 297         /*r_rate,hsp,vsp      */
 298         /*HT, HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 299         {REFRESH_60, M720X480_R60_HSP, M720X480_R60_VSP,
 300          {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
 301
 302 };
 303
 304 /*720x576 (GTF)*/
 305 static struct crt_mode_table CRTM720x576[] = {
 306         /*r_rate,hsp,vsp */
 307         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 308         {REFRESH_60, M720X576_R60_HSP, M720X576_R60_VSP,
 309          {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
 310 };
 311
 312 /* 800x480 (CVT) */
 313 static struct crt_mode_table CRTM800x480[] = {
 314         /* r_rate,              hsp,             vsp   */
 315         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 316         {REFRESH_60, M800X480_R60_HSP, M800X480_R60_VSP,
 317          {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
 318 };
 319
 320 /* 800x600*/
 321 static struct crt_mode_table CRTM800x600[] = {
 322         /*r_rate,hsp,vsp     */
 323         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 324         {REFRESH_60, M800X600_R60_HSP, M800X600_R60_VSP,
 325          {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
 326         {REFRESH_75, M800X600_R75_HSP, M800X600_R75_VSP,
 327          {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
 328         {REFRESH_85, M800X600_R85_HSP, M800X600_R85_VSP,
 329          {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
 330         {REFRESH_100, M800X600_R100_HSP, M800X600_R100_VSP,
 331          {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
 332         {REFRESH_120, M800X600_R120_HSP, M800X600_R120_VSP,
 333          {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3} }
 334 };
 335
 336 /* 848x480 (CVT) */
 337 static struct crt_mode_table CRTM848x480[] = {
 338         /* r_rate,              hsp,             vsp   */
 339         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 340         {REFRESH_60, M848X480_R60_HSP, M848X480_R60_VSP,
 341          {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
 342 };
 343
 344 /*856x480 (GTF) convert to 852x480*/
 345 static struct crt_mode_table CRTM852x480[] = {
 346         /*r_rate,hsp,vsp     */
 347         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 348         {REFRESH_60, M852X480_R60_HSP, M852X480_R60_VSP,
 349         {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
 350 };
 351
 352 /*1024x512 (GTF)*/
 353 static struct crt_mode_table CRTM1024x512[] = {
 354         /*r_rate,hsp,vsp     */
 355         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 356         {REFRESH_60, M1024X512_R60_HSP, M1024X512_R60_VSP,
 357          {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
 358
 359 };
 360
 361 /* 1024x600*/
 362 static struct crt_mode_table CRTM1024x600[] = {
 363         /*r_rate,hsp,vsp */
 364         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 365         {REFRESH_60, M1024X600_R60_HSP, M1024X600_R60_VSP,
 366          {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
 367 };
 368
 369 /* 1024x768*/
 370 static struct crt_mode_table CRTM1024x768[] = {
 371         /*r_rate,hsp,vsp */
 372         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 373         {REFRESH_60, M1024X768_R60_HSP, M1024X768_R60_VSP,
 374         {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
 375         {REFRESH_75, M1024X768_R75_HSP, M1024X768_R75_VSP,
 376         {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
 377         {REFRESH_85, M1024X768_R85_HSP, M1024X768_R85_VSP,
 378         {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
 379         {REFRESH_100, M1024X768_R100_HSP, M1024X768_R100_VSP,
 380         {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
 381 };
 382
 383 /* 1152x864*/
 384 static struct crt_mode_table CRTM1152x864[] = {
 385         /*r_rate,hsp,vsp      */
 386         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 387         {REFRESH_75, M1152X864_R75_HSP, M1152X864_R75_VSP,
 388          {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
 389
 390 };
 391
 392 /* 1280x720 (HDMI 720P)*/
 393 static struct crt_mode_table CRTM1280x720[] = {
 394         /*r_rate,hsp,vsp */
 395         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE      */
 396         {REFRESH_60, M1280X720_R60_HSP, M1280X720_R60_VSP,
 397          {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
 398         {REFRESH_50, M1280X720_R50_HSP, M1280X720_R50_VSP,
 399          {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
 400 };
 401
 402 /*1280x768 (GTF)*/
 403 static struct crt_mode_table CRTM1280x768[] = {
 404         /*r_rate,hsp,vsp     */
 405         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 406         {REFRESH_60, M1280X768_R60_HSP, M1280X768_R60_VSP,
 407          {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
 408         {REFRESH_50, M1280X768_R50_HSP, M1280X768_R50_VSP,
 409          {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
 410 };
 411
 412 /* 1280x800 (CVT) */
 413 static struct crt_mode_table CRTM1280x800[] = {
 414         /* r_rate,              hsp,             vsp   */
 415         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 416         {REFRESH_60, M1280X800_R60_HSP, M1280X800_R60_VSP,
 417          {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
 418 };
 419
 420 /*1280x960*/
 421 static struct crt_mode_table CRTM1280x960[] = {
 422         /*r_rate,hsp,vsp */
 423         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 424         {REFRESH_60, M1280X960_R60_HSP, M1280X960_R60_VSP,
 425          {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
 426 };
 427
 428 /* 1280x1024*/
 429 static struct crt_mode_table CRTM1280x1024[] = {
 430         /*r_rate,hsp,vsp */
 431         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 432         {REFRESH_60, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
 433          {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
 434           3} },
 435         {REFRESH_75, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
 436          {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
 437           3} },
 438         {REFRESH_85, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
 439          {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
 440 };
 441
 442 /* 1368x768 (GTF) */
 443 static struct crt_mode_table CRTM1368x768[] = {
 444         /* r_rate,  hsp, vsp */
 445         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 446         {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
 447          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
 448 };
 449
 450 /*1440x1050 (GTF)*/
 451 static struct crt_mode_table CRTM1440x1050[] = {
 452         /*r_rate,hsp,vsp      */
 453         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 454         {REFRESH_60, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
 455          {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
 456 };
 457
 458 /* 1600x1200*/
 459 static struct crt_mode_table CRTM1600x1200[] = {
 460         /*r_rate,hsp,vsp */
 461         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 462         {REFRESH_60, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
 463          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
 464           3} },
 465         {REFRESH_75, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
 466          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
 467
 468 };
 469
 470 /* 1680x1050 (CVT) */
 471 static struct crt_mode_table CRTM1680x1050[] = {
 472         /* r_rate,              hsp,             vsp  */
 473         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
 474         {REFRESH_60, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
 475          {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
 476           6} },
 477         {REFRESH_75, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
 478          {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
 479 };
 480
 481 /* 1680x1050 (CVT Reduce Blanking) */
 482 static struct crt_mode_table CRTM1680x1050_RB[] = {
 483         /* r_rate,              hsp,             vsp   */
 484         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
 485         {REFRESH_60, M1680x1050_RB_R60_HSP, M1680x1050_RB_R60_VSP,
 486          {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
 487 };
 488
 489 /* 1920x1080 (CVT)*/
 490 static struct crt_mode_table CRTM1920x1080[] = {
 491         /*r_rate,hsp,vsp */
 492         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 493         {REFRESH_60, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
 494          {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
 495 };
 496
 497 /* 1920x1080 (CVT with Reduce Blanking) */
 498 static struct crt_mode_table CRTM1920x1080_RB[] = {
 499         /* r_rate,              hsp,             vsp   */
 500         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 501         {REFRESH_60, M1920X1080_RB_R60_HSP, M1920X1080_RB_R60_VSP,
 502          {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
 503 };
 504
 505 /* 1920x1440*/
 506 static struct crt_mode_table CRTM1920x1440[] = {
 507         /*r_rate,hsp,vsp */
 508         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 509         {REFRESH_60, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
 510          {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
 511           3} },
 512         {REFRESH_75, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
 513          {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
 514 };
 515
 516 /* 1400x1050 (CVT) */
 517 static struct crt_mode_table CRTM1400x1050[] = {
 518         /* r_rate,              hsp,             vsp   */
 519         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 520         {REFRESH_60, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
 521          {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
 522           4} },
 523         {REFRESH_75, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
 524          {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
 525 };
 526
 527 /* 1400x1050 (CVT Reduce Blanking) */
 528 static struct crt_mode_table CRTM1400x1050_RB[] = {
 529         /* r_rate,              hsp,             vsp   */
 530         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 531         {REFRESH_60, M1400X1050_RB_R60_HSP, M1400X1050_RB_R60_VSP,
 532          {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
 533 };
 534
 535 /* 960x600 (CVT) */
 536 static struct crt_mode_table CRTM960x600[] = {
 537         /* r_rate,          hsp,             vsp   */
 538         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 539         {REFRESH_60, M960X600_R60_HSP, M960X600_R60_VSP,
 540          {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
 541 };
 542
 543 /* 1000x600 (GTF) */
 544 static struct crt_mode_table CRTM1000x600[] = {
 545         /* r_rate,              hsp,             vsp   */
 546         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 547         {REFRESH_60, M1000X600_R60_HSP, M1000X600_R60_VSP,
 548          {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
 549 };
 550
 551 /* 1024x576 (GTF) */
 552 static struct crt_mode_table CRTM1024x576[] = {
 553         /* r_rate,              hsp,             vsp   */
 554         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 555         {REFRESH_60, M1024X576_R60_HSP, M1024X576_R60_VSP,
 556          {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
 557 };
 558
 559 /* 1088x612 (CVT) */
 560 static struct crt_mode_table CRTM1088x612[] = {
 561         /* r_rate,              hsp,             vsp   */
 562         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 563         {REFRESH_60, M1088X612_R60_HSP, M1088X612_R60_VSP,
 564          {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
 565 };
 566
 567 /* 1152x720 (CVT) */
 568 static struct crt_mode_table CRTM1152x720[] = {
 569         /* r_rate,              hsp,             vsp   */
 570         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 571         {REFRESH_60, M1152X720_R60_HSP, M1152X720_R60_VSP,
 572          {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
 573 };
 574
 575 /* 1200x720 (GTF) */
 576 static struct crt_mode_table CRTM1200x720[] = {
 577         /* r_rate,              hsp,             vsp   */
 578         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 579         {REFRESH_60, M1200X720_R60_HSP, M1200X720_R60_VSP,
 580          {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
 581 };
 582
 583 /* 1200x900 (DCON) */
 584 static struct crt_mode_table DCON1200x900[] = {
 585         /* r_rate,               hsp,               vsp   */
 586         {REFRESH_49, M1200X900_R60_HSP, M1200X900_R60_VSP,
 587         /* The correct htotal is 1240, but this doesn't raster on VX855. */
 588         /* Via suggested changing to a multiple of 16, hence 1264.       */
 589         /*  HT,   HA,  HBS, HBE,  HSS, HSE,  VT,  VA, VBS, VBE, VSS, VSE */
 590          {1264, 1200, 1200,  64, 1211,  32, 912, 900, 900,  12, 901, 10} }
 591 };
 592
 593 /* 1280x600 (GTF) */
 594 static struct crt_mode_table CRTM1280x600[] = {
 595         /* r_rate,              hsp,             vsp   */
 596         /* HT,  HA,  HBS, HBE,  HSS, HSE, VT,  VA,  VBS, VBE,  VSS, VSE */
 597         {REFRESH_60, M1280x600_R60_HSP, M1280x600_R60_VSP,
 598          {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
 599 };
 600
 601 /* 1360x768 (CVT) */
 602 static struct crt_mode_table CRTM1360x768[] = {
 603         /* r_rate,              hsp,             vsp   */
 604         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 605         {REFRESH_60, M1360X768_R60_HSP, M1360X768_R60_VSP,
 606          {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
 607 };
 608
 609 /* 1360x768 (CVT Reduce Blanking) */
 610 static struct crt_mode_table CRTM1360x768_RB[] = {
 611         /* r_rate,              hsp,             vsp   */
 612         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 613         {REFRESH_60, M1360X768_RB_R60_HSP, M1360X768_RB_R60_VSP,
 614          {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
 615 };
 616
 617 /* 1366x768 (GTF) */
 618 static struct crt_mode_table CRTM1366x768[] = {
 619         /* r_rate,          hsp,             vsp   */
 620         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 621         {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
 622          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
 623         {REFRESH_50, M1368X768_R50_HSP, M1368X768_R50_VSP,
 624          {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
 625 };
 626
 627 /* 1440x900 (CVT) */
 628 static struct crt_mode_table CRTM1440x900[] = {
 629         /* r_rate,              hsp,             vsp   */
 630         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 631         {REFRESH_60, M1440X900_R60_HSP, M1440X900_R60_VSP,
 632          {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
 633         {REFRESH_75, M1440X900_R75_HSP, M1440X900_R75_VSP,
 634          {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
 635 };
 636
 637 /* 1440x900 (CVT Reduce Blanking) */
 638 static struct crt_mode_table CRTM1440x900_RB[] = {
 639         /* r_rate,              hsp,             vsp   */
 640         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 641         {REFRESH_60, M1440X900_RB_R60_HSP, M1440X900_RB_R60_VSP,
 642          {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
 643 };
 644
 645 /* 1600x900 (CVT) */
 646 static struct crt_mode_table CRTM1600x900[] = {
 647         /* r_rate,          hsp,             vsp   */
 648         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 649         {REFRESH_60, M1600X900_R60_HSP, M1600X900_R60_VSP,
 650          {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
 651 };
 652
 653 /* 1600x900 (CVT Reduce Blanking) */
 654 static struct crt_mode_table CRTM1600x900_RB[] = {
 655         /* r_rate,           hsp,        vsp   */
 656         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 657         {REFRESH_60, M1600X900_RB_R60_HSP, M1600X900_RB_R60_VSP,
 658          {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
 659 };
 660
 661 /* 1600x1024 (GTF) */
 662 static struct crt_mode_table CRTM1600x1024[] = {
 663         /* r_rate,          hsp,             vsp   */
 664         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 665         {REFRESH_60, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
 666          {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
 667 };
 668
 669 /* 1792x1344 (DMT) */
 670 static struct crt_mode_table CRTM1792x1344[] = {
 671         /* r_rate,              hsp,             vsp   */
 672         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 673         {REFRESH_60, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
 674          {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
 675 };
 676
 677 /* 1856x1392 (DMT) */
 678 static struct crt_mode_table CRTM1856x1392[] = {
 679         /* r_rate,              hsp,             vsp   */
 680         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 681         {REFRESH_60, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
 682          {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
 683 };
 684
 685 /* 1920x1200 (CVT) */
 686 static struct crt_mode_table CRTM1920x1200[] = {
 687         /* r_rate,              hsp,             vsp   */
 688         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 689         {REFRESH_60, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
 690          {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
 691 };
 692
 693 /* 1920x1200 (CVT with Reduce Blanking) */
 694 static struct crt_mode_table CRTM1920x1200_RB[] = {
 695         /* r_rate,              hsp,             vsp   */
 696         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 697         {REFRESH_60, M1920X1200_RB_R60_HSP, M1920X1200_RB_R60_VSP,
 698          {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
 699 };
 700
 701 /* 2048x1536 (CVT) */
 702 static struct crt_mode_table CRTM2048x1536[] = {
 703         /* r_rate,              hsp,             vsp   */
 704         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 705         {REFRESH_60, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
 706          {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
 707 };
 708
 709 static struct VideoModeTable viafb_modes[] = {
 710         /* Display : 480x640 (GTF) */
 711         {CRTM480x640, ARRAY_SIZE(CRTM480x640)},
 712
 713         /* Display : 640x480 */
 714         {CRTM640x480, ARRAY_SIZE(CRTM640x480)},
 715
 716         /* Display : 720x480 (GTF) */
 717         {CRTM720x480, ARRAY_SIZE(CRTM720x480)},
 718
 719         /* Display : 720x576 (GTF) */
 720         {CRTM720x576, ARRAY_SIZE(CRTM720x576)},
 721
 722         /* Display : 800x600 */
 723         {CRTM800x600, ARRAY_SIZE(CRTM800x600)},
 724
 725         /* Display : 800x480 (CVT) */
 726         {CRTM800x480, ARRAY_SIZE(CRTM800x480)},
 727
 728         /* Display : 848x480 (CVT) */
 729         {CRTM848x480, ARRAY_SIZE(CRTM848x480)},
 730
 731         /* Display : 852x480 (GTF) */
 732         {CRTM852x480, ARRAY_SIZE(CRTM852x480)},
 733
 734         /* Display : 1024x512 (GTF) */
 735         {CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
 736
 737         /* Display : 1024x600 */
 738         {CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
 739
 740         /* Display : 1024x768 */
 741         {CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
 742
 743         /* Display : 1152x864 */
 744         {CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
 745
 746         /* Display : 1280x768 (GTF) */
 747         {CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
 748
 749         /* Display : 960x600 (CVT) */
 750         {CRTM960x600, ARRAY_SIZE(CRTM960x600)},
 751
 752         /* Display : 1000x600 (GTF) */
 753         {CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
 754
 755         /* Display : 1024x576 (GTF) */
 756         {CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
 757
 758         /* Display : 1088x612 (GTF) */
 759         {CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
 760
 761         /* Display : 1152x720 (CVT) */
 762         {CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
 763
 764         /* Display : 1200x720 (GTF) */
 765         {CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
 766
 767         /* Display : 1200x900 (DCON) */
 768         {DCON1200x900, ARRAY_SIZE(DCON1200x900)},
 769
 770         /* Display : 1280x600 (GTF) */
 771         {CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
 772
 773         /* Display : 1280x800 (CVT) */
 774         {CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
 775
 776         /* Display : 1280x960 */
 777         {CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
 778
 779         /* Display : 1280x1024 */
 780         {CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
 781
 782         /* Display : 1360x768 (CVT) */
 783         {CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
 784
 785         /* Display : 1366x768 */
 786         {CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
 787
 788         /* Display : 1368x768 (GTF) */
 789         {CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
 790
 791         /* Display : 1440x900 (CVT) */
 792         {CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
 793
 794         /* Display : 1440x1050 (GTF) */
 795         {CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
 796
 797         /* Display : 1600x900 (CVT) */
 798         {CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
 799
 800         /* Display : 1600x1024 (GTF) */
 801         {CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
 802
 803         /* Display : 1600x1200 */
 804         {CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
 805
 806         /* Display : 1680x1050 (CVT) */
 807         {CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
 808
 809         /* Display : 1792x1344 (DMT) */
 810         {CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
 811
 812         /* Display : 1856x1392 (DMT) */
 813         {CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
 814
 815         /* Display : 1920x1440 */
 816         {CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
 817
 818         /* Display : 2048x1536 */
 819         {CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
 820
 821         /* Display : 1280x720 */
 822         {CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
 823
 824         /* Display : 1920x1080 (CVT) */
 825         {CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
 826
 827         /* Display : 1920x1200 (CVT) */
 828         {CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
 829
 830         /* Display : 1400x1050 (CVT) */
 831         {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
 832 };
 833
 834 static struct VideoModeTable viafb_rb_modes[] = {
 835         /* Display : 1360x768 (CVT Reduce Blanking) */
 836         {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)},
 837
 838         /* Display : 1440x900 (CVT Reduce Blanking) */
 839         {CRTM1440x900_RB, ARRAY_SIZE(CRTM1440x900_RB)},
 840
 841         /* Display : 1400x1050 (CVT Reduce Blanking) */
 842         {CRTM1400x1050_RB, ARRAY_SIZE(CRTM1400x1050_RB)},
 843
 844         /* Display : 1600x900 (CVT Reduce Blanking) */
 845         {CRTM1600x900_RB, ARRAY_SIZE(CRTM1600x900_RB)},
 846
 847         /* Display : 1680x1050 (CVT Reduce Blanking) */
 848         {CRTM1680x1050_RB, ARRAY_SIZE(CRTM1680x1050_RB)},
 849
 850         /* Display : 1920x1080 (CVT Reduce Blanking) */
 851         {CRTM1920x1080_RB, ARRAY_SIZE(CRTM1920x1080_RB)},
 852
 853         /* Display : 1920x1200 (CVT Reduce Blanking) */
 854         {CRTM1920x1200_RB, ARRAY_SIZE(CRTM1920x1200_RB)}
 855 };
 856
 857 int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
 858 int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
 859 int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
 860 int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
 861 int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
 862 int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
 863 int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
 864
 865
 866 struct VideoModeTable *viafb_get_mode(int hres, int vres)
 867 {
 868         u32 i;
 869         for (i = 0; i < ARRAY_SIZE(viafb_modes); i++)
 870                 if (viafb_modes[i].mode_array &&
 871                         viafb_modes[i].crtc[0].crtc.hor_addr == hres &&
 872                         viafb_modes[i].crtc[0].crtc.ver_addr == vres)
 873                         return &viafb_modes[i];
 874
 875         return NULL;
 876 }
 877
 878 struct VideoModeTable *viafb_get_rb_mode(int hres, int vres)
 879 {
 880         u32 i;
 881         for (i = 0; i < ARRAY_SIZE(viafb_rb_modes); i++)
 882                 if (viafb_rb_modes[i].mode_array &&
 883                         viafb_rb_modes[i].crtc[0].crtc.hor_addr == hres &&
 884                         viafb_rb_modes[i].crtc[0].crtc.ver_addr == vres)
 885                         return &viafb_rb_modes[i];
 886
 887         return NULL;
 888 }