drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h

   1 #ifndef __RTL8712_SYSCFG_BITDEF_H__
   2 #define __RTL8712_SYSCFG_BITDEF_H__
   3
   4 /*SYS_PWR_CTRL*/
   5 /*SRCTRL0*/
   6 /*SRCTRL1*/
   7 /*SYS_CLKR*/
   8
   9 /*SYS_IOS_CTRL*/
  10 #define iso_LDR2RP_SHT          8 /* EE Loader to Retention Path*/
  11 #define iso_LDR2RP              BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/
  12
  13 /*SYS_CTRL*/
  14 #define FEN_DIO_SDIO_SHT        0
  15 #define FEN_DIO_SDIO            BIT(FEN_DIO_SDIO_SHT)
  16 #define FEN_SDIO_SHT            1
  17 #define FEN_SDIO                BIT(FEN_SDIO_SHT)
  18 #define FEN_USBA_SHT            2
  19 #define FEN_USBA                BIT(FEN_USBA_SHT)
  20 #define FEN_UPLL_SHT            3
  21 #define FEN_UPLL                BIT(FEN_UPLL_SHT)
  22 #define FEN_USBD_SHT            4
  23 #define FEN_USBD                BIT(FEN_USBD_SHT)
  24 #define FEN_DIO_PCIE_SHT        5
  25 #define FEN_DIO_PCIE            BIT(FEN_DIO_PCIE_SHT)
  26 #define FEN_PCIEA_SHT           6
  27 #define FEN_PCIEA               BIT(FEN_PCIEA_SHT)
  28 #define FEN_PPLL_SHT            7
  29 #define FEN_PPLL                BIT(FEN_PPLL_SHT)
  30 #define FEN_PCIED_SHT           8
  31 #define FEN_PCIED               BIT(FEN_PCIED_SHT)
  32 #define FEN_CPUEN_SHT           10
  33 #define FEN_CPUEN               BIT(FEN_CPUEN_SHT)
  34 #define FEN_DCORE_SHT           11
  35 #define FEN_DCORE               BIT(FEN_DCORE_SHT)
  36 #define FEN_ELDR_SHT            12
  37 #define FEN_ELDR                BIT(FEN_ELDR_SHT)
  38 #define PWC_DV2LDR_SHT          13
  39 #define PWC_DV2LDR              BIT(PWC_DV2LDR_SHT) /* Loader Power Enable*/
  40
  41 /*=== SYS_CLKR ===*/
  42 #define SYS_CLKSEL_SHT          0
  43 #define SYS_CLKSEL              BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/
  44 #define PS_CLKSEL_SHT           1
  45 #define PS_CLKSEL               BIT(PS_CLKSEL_SHT) /*System power save
  46                                                     * clock select.*/
  47 #define CPU_CLKSEL_SHT          2
  48 #define CPU_CLKSEL              BIT(CPU_CLKSEL_SHT) /* System Clock select,
  49                                                      * 1: AFE source,
  50                                                      * 0: System clock(L-Bus)*/
  51 #define INT32K_EN_SHT           3
  52 #define INT32K_EN               BIT(INT32K_EN_SHT)
  53 #define MACSLP_SHT              4
  54 #define MACSLP                  BIT(MACSLP_SHT)
  55 #define MAC_CLK_EN_SHT          11
  56 #define MAC_CLK_EN              BIT(MAC_CLK_EN_SHT) /* MAC Clock Enable.*/
  57 #define SYS_CLK_EN_SHT          12
  58 #define SYS_CLK_EN              BIT(SYS_CLK_EN_SHT)
  59 #define RING_CLK_EN_SHT         13
  60 #define RING_CLK_EN             BIT(RING_CLK_EN_SHT)
  61 #define SWHW_SEL_SHT            14
  62 #define SWHW_SEL                BIT(SWHW_SEL_SHT) /* Load done,
  63                                                    * control path switch.*/
  64 #define FWHW_SEL_SHT            15
  65 #define FWHW_SEL                BIT(FWHW_SEL_SHT) /* Sleep exit,
  66                                                    * control path switch.*/
  67
  68 /*9346CR*/
  69 #define _VPDIDX_MSK             0xFF00
  70 #define _VPDIDX_SHT             8
  71 #define _EEM_MSK                0x00C0
  72 #define _EEM_SHT                6
  73 #define _EEM0                   BIT(6)
  74 #define _EEM1                   BIT(7)
  75 #define _EEPROM_EN              BIT(5)
  76 #define _9356SEL                BIT(4)
  77 #define _EECS                   BIT(3)
  78 #define _EESK                   BIT(2)
  79 #define _EEDI                   BIT(1)
  80 #define _EEDO                   BIT(0)
  81
  82 /*AFE_MISC*/
  83 #define AFE_MISC_USB_MBEN_SHT   7
  84 #define AFE_MISC_USB_MBEN       BIT(AFE_MISC_USB_MBEN_SHT)
  85 #define AFE_MISC_USB_BGEN_SHT   6
  86 #define AFE_MISC_USB_BGEN       BIT(AFE_MISC_USB_BGEN_SHT)
  87 #define AFE_MISC_LD12_VDAJ_SHT  4
  88 #define AFE_MISC_LD12_VDAJ_MSK  0X0030
  89 #define AFE_MISC_LD12_VDAJ      BIT(AFE_MISC_LD12_VDAJ_SHT)
  90 #define AFE_MISC_I32_EN_SHT     3
  91 #define AFE_MISC_I32_EN         BIT(AFE_MISC_I32_EN_SHT)
  92 #define AFE_MISC_E32_EN_SHT     2
  93 #define AFE_MISC_E32_EN         BIT(AFE_MISC_E32_EN_SHT)
  94 #define AFE_MISC_MBEN_SHT       1
  95 #define AFE_MISC_MBEN           BIT(AFE_MISC_MBEN_SHT)/* Enable AFE Macro
  96                                                        * Block's Mbias.*/
  97 #define AFE_MISC_BGEN_SHT       0
  98 #define AFE_MISC_BGEN           BIT(AFE_MISC_BGEN_SHT)/* Enable AFE Macro
  99                                                        * Block's Bandgap.*/
 100
 101
 102 /*--------------------------------------------------------------------------*/
 103 /*       SPS1_CTRL bits                         (Offset 0x18-1E, 56bits)*/
 104 /*--------------------------------------------------------------------------*/
 105 #define SPS1_SWEN               BIT(1)  /* Enable vsps18 SW Macro Block.*/
 106 #define SPS1_LDEN               BIT(0)  /* Enable VSPS12 LDO Macro block.*/
 107
 108
 109 /*----------------------------------------------------------------------------*/
 110 /*       LDOA15_CTRL bits               (Offset 0x20, 8bits)*/
 111 /*----------------------------------------------------------------------------*/
 112 #define LDA15_EN                BIT(0)  /* Enable LDOA15 Macro Block*/
 113
 114
 115 /*----------------------------------------------------------------------------*/
 116 /*       8192S LDOV12D_CTRL bit         (Offset 0x21, 8bits)*/
 117 /*----------------------------------------------------------------------------*/
 118 #define LDV12_EN                BIT(0)  /* Enable LDOVD12 Macro Block*/
 119 #define LDV12_SDBY              BIT(1)  /* LDOVD12 standby mode*/
 120
 121 /*CLK_PS_CTRL*/
 122 #define _CLK_GATE_EN            BIT(0)
 123
 124
 125 /* EFUSE_CTRL*/
 126 #define EF_FLAG                 BIT(31)         /* Access Flag, Write:1;
 127                                                  *              Read:0*/
 128 #define EF_PGPD                 0x70000000      /* E-fuse Program time*/
 129 #define EF_RDT                  0x0F000000      /* E-fuse read time: in the
 130                                                  * unit of cycle time*/
 131 #define EF_PDN_EN               BIT(19)         /* EFuse Power down enable*/
 132 #define ALD_EN                  BIT(18)         /* Autoload Enable*/
 133 #define EF_ADDR                 0x0003FF00      /* Access Address*/
 134 #define EF_DATA                 0x000000FF      /* Access Data*/
 135
 136 /* EFUSE_TEST*/
 137 #define LDOE25_EN               BIT(31)         /* Enable LDOE25 Macro Block*/
 138
 139 /* EFUSE_CLK_CTRL*/
 140 #define EFUSE_CLK_EN            BIT(1)          /* E-Fuse Clock Enable*/
 141 #define EFUSE_CLK_SEL           BIT(0)          /* E-Fuse Clock Select,
 142                                                  * 0:500K, 1:40M*/
 143
 144 #endif  /*__RTL8712_SYSCFG_BITDEF_H__*/
 145