drivers/staging/et131x/et1310_mac.c

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_mac.c - All code and routines pertaining to the MAC
  12  *
  13  *------------------------------------------------------------------------------
  14  *
  15  * SOFTWARE LICENSE
  16  *
  17  * This software is provided subject to the following terms and conditions,
  18  * which you should read carefully before using the software.  Using this
  19  * software indicates your acceptance of these terms and conditions.  If you do
  20  * not agree with these terms and conditions, do not use the software.
  21  *
  22  * Copyright © 2005 Agere Systems Inc.
  23  * All rights reserved.
  24  *
  25  * Redistribution and use in source or binary forms, with or without
  26  * modifications, are permitted provided that the following conditions are met:
  27  *
  28  * . Redistributions of source code must retain the above copyright notice, this
  29  *    list of conditions and the following Disclaimer as comments in the code as
  30  *    well as in the documentation and/or other materials provided with the
  31  *    distribution.
  32  *
  33  * . Redistributions in binary form must reproduce the above copyright notice,
  34  *    this list of conditions and the following Disclaimer in the documentation
  35  *    and/or other materials provided with the distribution.
  36  *
  37  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38  *    may be used to endorse or promote products derived from this software
  39  *    without specific prior written permission.
  40  *
  41  * Disclaimer
  42  *
  43  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54  * DAMAGE.
  55  *
  56  */
  57
  58 #include "et131x_version.h"
  59 #include "et131x_defs.h"
  60
  61 #include <linux/init.h>
  62 #include <linux/module.h>
  63 #include <linux/types.h>
  64 #include <linux/kernel.h>
  65
  66 #include <linux/sched.h>
  67 #include <linux/ptrace.h>
  68 #include <linux/ctype.h>
  69 #include <linux/string.h>
  70 #include <linux/timer.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/in.h>
  73 #include <linux/delay.h>
  74 #include <linux/io.h>
  75 #include <linux/bitops.h>
  76 #include <linux/pci.h>
  77 #include <asm/system.h>
  78
  79 #include <linux/netdevice.h>
  80 #include <linux/etherdevice.h>
  81 #include <linux/skbuff.h>
  82 #include <linux/if_arp.h>
  83 #include <linux/ioport.h>
  84 #include <linux/crc32.h>
  85
  86 #include "et1310_phy.h"
  87 #include "et131x_adapter.h"
  88 #include "et131x.h"
  89
  90
  91 #define COUNTER_WRAP_28_BIT 0x10000000
  92 #define COUNTER_WRAP_22_BIT 0x400000
  93 #define COUNTER_WRAP_16_BIT 0x10000
  94 #define COUNTER_WRAP_12_BIT 0x1000
  95
  96 #define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1)
  97 #define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1)
  98 #define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
  99 #define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
 100
 101 /**
 102  * ConfigMacRegs1 - Initialize the first part of MAC regs
 103  * @pAdpater: pointer to our adapter structure
 104  */
 105 void ConfigMACRegs1(struct et131x_adapter *etdev)
 106 {
 107         struct mac_regs __iomem *pMac = &etdev->regs->mac;
 108         u32 station1;
 109         u32 station2;
 110         u32 ipg;
 111
 112         /* First we need to reset everything.  Write to MAC configuration
 113          * register 1 to perform reset.
 114          */
 115         writel(0xC00F0000, &pMac->cfg1);
 116
 117         /* Next lets configure the MAC Inter-packet gap register */
 118         ipg = 0x38005860;               /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
 119         ipg |= 0x50 << 8;               /* ifg enforce 0x50 */
 120         writel(ipg, &pMac->ipg);
 121
 122         /* Next lets configure the MAC Half Duplex register */
 123         /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
 124         writel(0x00A1F037, &pMac->hfdp);
 125
 126         /* Next lets configure the MAC Interface Control register */
 127         writel(0, &pMac->if_ctrl);
 128
 129         /* Let's move on to setting up the mii management configuration */
 130         writel(0x07, &pMac->mii_mgmt_cfg);      /* Clock reset 0x7 */
 131
 132         /* Next lets configure the MAC Station Address register.  These
 133          * values are read from the EEPROM during initialization and stored
 134          * in the adapter structure.  We write what is stored in the adapter
 135          * structure to the MAC Station Address registers high and low.  This
 136          * station address is used for generating and checking pause control
 137          * packets.
 138          */
 139         station2 = (etdev->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
 140                    (etdev->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
 141         station1 = (etdev->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
 142                    (etdev->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
 143                    (etdev->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
 144                     etdev->addr[2];
 145         writel(station1, &pMac->station_addr_1);
 146         writel(station2, &pMac->station_addr_2);
 147
 148         /* Max ethernet packet in bytes that will passed by the mac without
 149          * being truncated.  Allow the MAC to pass 4 more than our max packet
 150          * size.  This is 4 for the Ethernet CRC.
 151          *
 152          * Packets larger than (RegistryJumboPacket) that do not contain a
 153          * VLAN ID will be dropped by the Rx function.
 154          */
 155         writel(etdev->RegistryJumboPacket + 4, &pMac->max_fm_len);
 156
 157         /* clear out MAC config reset */
 158         writel(0, &pMac->cfg1);
 159 }
 160
 161 /**
 162  * ConfigMacRegs2 - Initialize the second part of MAC regs
 163  * @pAdpater: pointer to our adapter structure
 164  */
 165 void ConfigMACRegs2(struct et131x_adapter *etdev)
 166 {
 167         int32_t delay = 0;
 168         struct mac_regs __iomem *pMac = &etdev->regs->mac;
 169         u32 cfg1;
 170         u32 cfg2;
 171         u32 ifctrl;
 172         u32 ctl;
 173
 174         ctl = readl(&etdev->regs->txmac.ctl);
 175         cfg1 = readl(&pMac->cfg1);
 176         cfg2 = readl(&pMac->cfg2);
 177         ifctrl = readl(&pMac->if_ctrl);
 178
 179         /* Set up the if mode bits */
 180         cfg2 &= ~0x300;
 181         if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
 182                 cfg2 |= 0x200;
 183                 /* Phy mode bit */
 184                 ifctrl &= ~(1 << 24);
 185         } else {
 186                 cfg2 |= 0x100;
 187                 ifctrl |= (1 << 24);
 188         }
 189
 190         /* We need to enable Rx/Tx */
 191         cfg1 |= CFG1_RX_ENABLE|CFG1_TX_ENABLE|CFG1_TX_FLOW;
 192         /* Initialize loop back to off */
 193         cfg1 &= ~(CFG1_LOOPBACK|CFG1_RX_FLOW);
 194         if (etdev->flowcontrol == FLOW_RXONLY || etdev->flowcontrol == FLOW_BOTH)
 195                 cfg1 |= CFG1_RX_FLOW;
 196         writel(cfg1, &pMac->cfg1);
 197
 198         /* Now we need to initialize the MAC Configuration 2 register */
 199         /* preamble 7, check length, huge frame off, pad crc, crc enable
 200            full duplex off */
 201         cfg2 |= 0x7016;
 202         cfg2 &= ~0x0021;
 203
 204         /* Turn on duplex if needed */
 205         if (etdev->duplex_mode)
 206                 cfg2 |= 0x01;
 207
 208         ifctrl &= ~(1 << 26);
 209         if (!etdev->duplex_mode)
 210                 ifctrl |= (1<<26);      /* Enable ghd */
 211
 212         writel(ifctrl, &pMac->if_ctrl);
 213         writel(cfg2, &pMac->cfg2);
 214
 215         do {
 216                 udelay(10);
 217                 delay++;
 218                 cfg1 = readl(&pMac->cfg1);
 219         } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
 220
 221         if (delay == 100) {
 222                 dev_warn(&etdev->pdev->dev,
 223                     "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
 224                         cfg1);
 225         }
 226
 227         /* Enable TXMAC */
 228         ctl |= 0x09;    /* TX mac enable, FC disable */
 229         writel(ctl, &etdev->regs->txmac.ctl);
 230
 231         /* Ready to start the RXDMA/TXDMA engine */
 232         if (etdev->flags & fMP_ADAPTER_LOWER_POWER) {
 233                 et131x_rx_dma_enable(etdev);
 234                 et131x_tx_dma_enable(etdev);
 235         }
 236 }
 237
 238 void ConfigRxMacRegs(struct et131x_adapter *etdev)
 239 {
 240         struct rxmac_regs __iomem *pRxMac = &etdev->regs->rxmac;
 241         u32 sa_lo;
 242         u32 sa_hi = 0;
 243         u32 pf_ctrl = 0;
 244
 245         /* Disable the MAC while it is being configured (also disable WOL) */
 246         writel(0x8, &pRxMac->ctrl);
 247
 248         /* Initialize WOL to disabled. */
 249         writel(0, &pRxMac->crc0);
 250         writel(0, &pRxMac->crc12);
 251         writel(0, &pRxMac->crc34);
 252
 253         /* We need to set the WOL mask0 - mask4 next.  We initialize it to
 254          * its default Values of 0x00000000 because there are not WOL masks
 255          * as of this time.
 256          */
 257         writel(0, &pRxMac->mask0_word0);
 258         writel(0, &pRxMac->mask0_word1);
 259         writel(0, &pRxMac->mask0_word2);
 260         writel(0, &pRxMac->mask0_word3);
 261
 262         writel(0, &pRxMac->mask1_word0);
 263         writel(0, &pRxMac->mask1_word1);
 264         writel(0, &pRxMac->mask1_word2);
 265         writel(0, &pRxMac->mask1_word3);
 266
 267         writel(0, &pRxMac->mask2_word0);
 268         writel(0, &pRxMac->mask2_word1);
 269         writel(0, &pRxMac->mask2_word2);
 270         writel(0, &pRxMac->mask2_word3);
 271
 272         writel(0, &pRxMac->mask3_word0);
 273         writel(0, &pRxMac->mask3_word1);
 274         writel(0, &pRxMac->mask3_word2);
 275         writel(0, &pRxMac->mask3_word3);
 276
 277         writel(0, &pRxMac->mask4_word0);
 278         writel(0, &pRxMac->mask4_word1);
 279         writel(0, &pRxMac->mask4_word2);
 280         writel(0, &pRxMac->mask4_word3);
 281
 282         /* Lets setup the WOL Source Address */
 283         sa_lo = (etdev->addr[2] << ET_WOL_LO_SA3_SHIFT) |
 284                 (etdev->addr[3] << ET_WOL_LO_SA4_SHIFT) |
 285                 (etdev->addr[4] << ET_WOL_LO_SA5_SHIFT) |
 286                  etdev->addr[5];
 287         writel(sa_lo, &pRxMac->sa_lo);
 288
 289         sa_hi = (u32) (etdev->addr[0] << ET_WOL_HI_SA1_SHIFT) |
 290                        etdev->addr[1];
 291         writel(sa_hi, &pRxMac->sa_hi);
 292
 293         /* Disable all Packet Filtering */
 294         writel(0, &pRxMac->pf_ctrl);
 295
 296         /* Let's initialize the Unicast Packet filtering address */
 297         if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
 298                 SetupDeviceForUnicast(etdev);
 299                 pf_ctrl |= 4;   /* Unicast filter */
 300         } else {
 301                 writel(0, &pRxMac->uni_pf_addr1);
 302                 writel(0, &pRxMac->uni_pf_addr2);
 303                 writel(0, &pRxMac->uni_pf_addr3);
 304         }
 305
 306         /* Let's initialize the Multicast hash */
 307         if (!(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
 308                 pf_ctrl |= 2;   /* Multicast filter */
 309                 SetupDeviceForMulticast(etdev);
 310         }
 311
 312         /* Runt packet filtering.  Didn't work in version A silicon. */
 313         pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
 314         pf_ctrl |= 8;   /* Fragment filter */
 315
 316         if (etdev->RegistryJumboPacket > 8192)
 317                 /* In order to transmit jumbo packets greater than 8k, the
 318                  * FIFO between RxMAC and RxDMA needs to be reduced in size
 319                  * to (16k - Jumbo packet size).  In order to implement this,
 320                  * we must use "cut through" mode in the RxMAC, which chops
 321                  * packets down into segments which are (max_size * 16).  In
 322                  * this case we selected 256 bytes, since this is the size of
 323                  * the PCI-Express TLP's that the 1310 uses.
 324                  *
 325                  * seg_en on, fc_en off, size 0x10
 326                  */
 327                 writel(0x41, &pRxMac->mcif_ctrl_max_seg);
 328         else
 329                 writel(0, &pRxMac->mcif_ctrl_max_seg);
 330
 331         /* Initialize the MCIF water marks */
 332         writel(0, &pRxMac->mcif_water_mark);
 333
 334         /*  Initialize the MIF control */
 335         writel(0, &pRxMac->mif_ctrl);
 336
 337         /* Initialize the Space Available Register */
 338         writel(0, &pRxMac->space_avail);
 339
 340         /* Initialize the the mif_ctrl register
 341          * bit 3:  Receive code error. One or more nibbles were signaled as
 342          *         errors  during the reception of the packet.  Clear this
 343          *         bit in Gigabit, set it in 100Mbit.  This was derived
 344          *         experimentally at UNH.
 345          * bit 4:  Receive CRC error. The packet's CRC did not match the
 346          *         internally generated CRC.
 347          * bit 5:  Receive length check error. Indicates that frame length
 348          *         field value in the packet does not match the actual data
 349          *         byte length and is not a type field.
 350          * bit 16: Receive frame truncated.
 351          * bit 17: Drop packet enable
 352          */
 353         if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS)
 354                 writel(0x30038, &pRxMac->mif_ctrl);
 355         else
 356                 writel(0x30030, &pRxMac->mif_ctrl);
 357
 358         /* Finally we initialize RxMac to be enabled & WOL disabled.  Packet
 359          * filter is always enabled since it is where the runt packets are
 360          * supposed to be dropped.  For version A silicon, runt packet
 361          * dropping doesn't work, so it is disabled in the pf_ctrl register,
 362          * but we still leave the packet filter on.
 363          */
 364         writel(pf_ctrl, &pRxMac->pf_ctrl);
 365         writel(0x9, &pRxMac->ctrl);
 366 }
 367
 368 void ConfigTxMacRegs(struct et131x_adapter *etdev)
 369 {
 370         struct txmac_regs *txmac = &etdev->regs->txmac;
 371
 372         /* We need to update the Control Frame Parameters
 373          * cfpt - control frame pause timer set to 64 (0x40)
 374          * cfep - control frame extended pause timer set to 0x0
 375          */
 376         if (etdev->flowcontrol == FLOW_NONE)
 377                 writel(0, &txmac->cf_param);
 378         else
 379                 writel(0x40, &txmac->cf_param);
 380 }
 381
 382 void ConfigMacStatRegs(struct et131x_adapter *etdev)
 383 {
 384         struct macstat_regs __iomem *macstat =
 385                 &etdev->regs->macstat;
 386
 387         /* Next we need to initialize all the macstat registers to zero on
 388          * the device.
 389          */
 390         writel(0, &macstat->txrx_0_64_byte_frames);
 391         writel(0, &macstat->txrx_65_127_byte_frames);
 392         writel(0, &macstat->txrx_128_255_byte_frames);
 393         writel(0, &macstat->txrx_256_511_byte_frames);
 394         writel(0, &macstat->txrx_512_1023_byte_frames);
 395         writel(0, &macstat->txrx_1024_1518_byte_frames);
 396         writel(0, &macstat->txrx_1519_1522_gvln_frames);
 397
 398         writel(0, &macstat->rx_bytes);
 399         writel(0, &macstat->rx_packets);
 400         writel(0, &macstat->rx_fcs_errs);
 401         writel(0, &macstat->rx_multicast_packets);
 402         writel(0, &macstat->rx_broadcast_packets);
 403         writel(0, &macstat->rx_control_frames);
 404         writel(0, &macstat->rx_pause_frames);
 405         writel(0, &macstat->rx_unknown_opcodes);
 406         writel(0, &macstat->rx_align_errs);
 407         writel(0, &macstat->rx_frame_len_errs);
 408         writel(0, &macstat->rx_code_errs);
 409         writel(0, &macstat->rx_carrier_sense_errs);
 410         writel(0, &macstat->rx_undersize_packets);
 411         writel(0, &macstat->rx_oversize_packets);
 412         writel(0, &macstat->rx_fragment_packets);
 413         writel(0, &macstat->rx_jabbers);
 414         writel(0, &macstat->rx_drops);
 415
 416         writel(0, &macstat->tx_bytes);
 417         writel(0, &macstat->tx_packets);
 418         writel(0, &macstat->tx_multicast_packets);
 419         writel(0, &macstat->tx_broadcast_packets);
 420         writel(0, &macstat->tx_pause_frames);
 421         writel(0, &macstat->tx_deferred);
 422         writel(0, &macstat->tx_excessive_deferred);
 423         writel(0, &macstat->tx_single_collisions);
 424         writel(0, &macstat->tx_multiple_collisions);
 425         writel(0, &macstat->tx_late_collisions);
 426         writel(0, &macstat->tx_excessive_collisions);
 427         writel(0, &macstat->tx_total_collisions);
 428         writel(0, &macstat->tx_pause_honored_frames);
 429         writel(0, &macstat->tx_drops);
 430         writel(0, &macstat->tx_jabbers);
 431         writel(0, &macstat->tx_fcs_errs);
 432         writel(0, &macstat->tx_control_frames);
 433         writel(0, &macstat->tx_oversize_frames);
 434         writel(0, &macstat->tx_undersize_frames);
 435         writel(0, &macstat->tx_fragments);
 436         writel(0, &macstat->carry_reg1);
 437         writel(0, &macstat->carry_reg2);
 438
 439         /* Unmask any counters that we want to track the overflow of.
 440          * Initially this will be all counters.  It may become clear later
 441          * that we do not need to track all counters.
 442          */
 443         writel(0xFFFFBE32, &macstat->carry_reg1_mask);
 444         writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
 445 }
 446
 447 void ConfigFlowControl(struct et131x_adapter *etdev)
 448 {
 449         if (etdev->duplex_mode == 0) {
 450                 etdev->flowcontrol = FLOW_NONE;
 451         } else {
 452                 char remote_pause, remote_async_pause;
 453
 454                 ET1310_PhyAccessMiBit(etdev,
 455                                       TRUEPHY_BIT_READ, 5, 10, &remote_pause);
 456                 ET1310_PhyAccessMiBit(etdev,
 457                                       TRUEPHY_BIT_READ, 5, 11,
 458                                       &remote_async_pause);
 459
 460                 if ((remote_pause == TRUEPHY_BIT_SET) &&
 461                     (remote_async_pause == TRUEPHY_BIT_SET)) {
 462                         etdev->flowcontrol = etdev->wanted_flow;
 463                 } else if ((remote_pause == TRUEPHY_BIT_SET) &&
 464                            (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
 465                         if (etdev->wanted_flow == FLOW_BOTH)
 466                                 etdev->flowcontrol = FLOW_BOTH;
 467                         else
 468                                 etdev->flowcontrol = FLOW_NONE;
 469                 } else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
 470                            (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
 471                         etdev->flowcontrol = FLOW_NONE;
 472                 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
 473                                remote_async_pause == TRUEPHY_SET_BIT) */
 474                         if (etdev->wanted_flow == FLOW_BOTH)
 475                                 etdev->flowcontrol = FLOW_RXONLY;
 476                         else
 477                                 etdev->flowcontrol = FLOW_NONE;
 478                 }
 479         }
 480 }
 481
 482 /**
 483  * UpdateMacStatHostCounters - Update the local copy of the statistics
 484  * @etdev: pointer to the adapter structure
 485  */
 486 void UpdateMacStatHostCounters(struct et131x_adapter *etdev)
 487 {
 488         struct ce_stats *stats = &etdev->stats;
 489         struct macstat_regs __iomem *macstat =
 490                 &etdev->regs->macstat;
 491
 492         stats->collisions += readl(&macstat->tx_total_collisions);
 493         stats->first_collision += readl(&macstat->tx_single_collisions);
 494         stats->tx_deferred += readl(&macstat->tx_deferred);
 495         stats->excessive_collisions += readl(&macstat->tx_multiple_collisions);
 496         stats->late_collisions += readl(&macstat->tx_late_collisions);
 497         stats->tx_uflo += readl(&macstat->tx_undersize_frames);
 498         stats->max_pkt_error += readl(&macstat->tx_oversize_frames);
 499
 500         stats->alignment_err += readl(&macstat->rx_align_errs);
 501         stats->crc_err += readl(&macstat->rx_code_errs);
 502         stats->norcvbuf += readl(&macstat->rx_drops);
 503         stats->rx_ov_flow += readl(&macstat->rx_oversize_packets);
 504         stats->code_violations += readl(&macstat->rx_fcs_errs);
 505         stats->length_err += readl(&macstat->rx_frame_len_errs);
 506
 507         stats->other_errors += readl(&macstat->rx_fragment_packets);
 508 }
 509
 510 /**
 511  * HandleMacStatInterrupt
 512  * @etdev: pointer to the adapter structure
 513  *
 514  * One of the MACSTAT counters has wrapped.  Update the local copy of
 515  * the statistics held in the adapter structure, checking the "wrap"
 516  * bit for each counter.
 517  */
 518 void HandleMacStatInterrupt(struct et131x_adapter *etdev)
 519 {
 520         u32 carry_reg1;
 521         u32 carry_reg2;
 522
 523         /* Read the interrupt bits from the register(s).  These are Clear On
 524          * Write.
 525          */
 526         carry_reg1 = readl(&etdev->regs->macstat.carry_reg1);
 527         carry_reg2 = readl(&etdev->regs->macstat.carry_reg2);
 528
 529         writel(carry_reg2, &etdev->regs->macstat.carry_reg1);
 530         writel(carry_reg2, &etdev->regs->macstat.carry_reg2);
 531
 532         /* We need to do update the host copy of all the MAC_STAT counters.
 533          * For each counter, check it's overflow bit.  If the overflow bit is
 534          * set, then increment the host version of the count by one complete
 535          * revolution of the counter.  This routine is called when the counter
 536          * block indicates that one of the counters has wrapped.
 537          */
 538         if (carry_reg1 & (1 << 14))
 539                 etdev->stats.code_violations += COUNTER_WRAP_16_BIT;
 540         if (carry_reg1 & (1 << 8))
 541                 etdev->stats.alignment_err += COUNTER_WRAP_12_BIT;
 542         if (carry_reg1 & (1 << 7))
 543                 etdev->stats.length_err += COUNTER_WRAP_16_BIT;
 544         if (carry_reg1 & (1 << 2))
 545                 etdev->stats.other_errors += COUNTER_WRAP_16_BIT;
 546         if (carry_reg1 & (1 << 6))
 547                 etdev->stats.crc_err += COUNTER_WRAP_16_BIT;
 548         if (carry_reg1 & (1 << 3))
 549                 etdev->stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
 550         if (carry_reg1 & (1 << 0))
 551                 etdev->stats.norcvbuf += COUNTER_WRAP_16_BIT;
 552         if (carry_reg2 & (1 << 16))
 553                 etdev->stats.max_pkt_error += COUNTER_WRAP_12_BIT;
 554         if (carry_reg2 & (1 << 15))
 555                 etdev->stats.tx_uflo += COUNTER_WRAP_12_BIT;
 556         if (carry_reg2 & (1 << 6))
 557                 etdev->stats.first_collision += COUNTER_WRAP_12_BIT;
 558         if (carry_reg2 & (1 << 8))
 559                 etdev->stats.tx_deferred += COUNTER_WRAP_12_BIT;
 560         if (carry_reg2 & (1 << 5))
 561                 etdev->stats.excessive_collisions += COUNTER_WRAP_12_BIT;
 562         if (carry_reg2 & (1 << 4))
 563                 etdev->stats.late_collisions += COUNTER_WRAP_12_BIT;
 564         if (carry_reg2 & (1 << 2))
 565                 etdev->stats.collisions += COUNTER_WRAP_12_BIT;
 566 }
 567
 568 void SetupDeviceForMulticast(struct et131x_adapter *etdev)
 569 {
 570         struct rxmac_regs __iomem *rxmac = &etdev->regs->rxmac;
 571         uint32_t nIndex;
 572         uint32_t result;
 573         uint32_t hash1 = 0;
 574         uint32_t hash2 = 0;
 575         uint32_t hash3 = 0;
 576         uint32_t hash4 = 0;
 577         u32 pm_csr;
 578
 579         /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
 580          * the multi-cast LIST.  If it is NOT specified, (and "ALL" is not
 581          * specified) then we should pass NO multi-cast addresses to the
 582          * driver.
 583          */
 584         if (etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {
 585                 /* Loop through our multicast array and set up the device */
 586                 for (nIndex = 0; nIndex < etdev->MCAddressCount; nIndex++) {
 587                         result = ether_crc(6, etdev->MCList[nIndex]);
 588
 589                         result = (result & 0x3F800000) >> 23;
 590
 591                         if (result < 32) {
 592                                 hash1 |= (1 << result);
 593                         } else if ((31 < result) && (result < 64)) {
 594                                 result -= 32;
 595                                 hash2 |= (1 << result);
 596                         } else if ((63 < result) && (result < 96)) {
 597                                 result -= 64;
 598                                 hash3 |= (1 << result);
 599                         } else {
 600                                 result -= 96;
 601                                 hash4 |= (1 << result);
 602                         }
 603                 }
 604         }
 605
 606         /* Write out the new hash to the device */
 607         pm_csr = readl(&etdev->regs->global.pm_csr);
 608         if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
 609                 writel(hash1, &rxmac->multi_hash1);
 610                 writel(hash2, &rxmac->multi_hash2);
 611                 writel(hash3, &rxmac->multi_hash3);
 612                 writel(hash4, &rxmac->multi_hash4);
 613         }
 614 }
 615
 616 void SetupDeviceForUnicast(struct et131x_adapter *etdev)
 617 {
 618         struct rxmac_regs __iomem *rxmac = &etdev->regs->rxmac;
 619         u32 uni_pf1;
 620         u32 uni_pf2;
 621         u32 uni_pf3;
 622         u32 pm_csr;
 623
 624         /* Set up unicast packet filter reg 3 to be the first two octets of
 625          * the MAC address for both address
 626          *
 627          * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
 628          * MAC address for second address
 629          *
 630          * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
 631          * MAC address for first address
 632          */
 633         uni_pf3 = (etdev->addr[0] << ET_UNI_PF_ADDR2_1_SHIFT) |
 634                   (etdev->addr[1] << ET_UNI_PF_ADDR2_2_SHIFT) |
 635                   (etdev->addr[0] << ET_UNI_PF_ADDR1_1_SHIFT) |
 636                    etdev->addr[1];
 637
 638         uni_pf2 = (etdev->addr[2] << ET_UNI_PF_ADDR2_3_SHIFT) |
 639                   (etdev->addr[3] << ET_UNI_PF_ADDR2_4_SHIFT) |
 640                   (etdev->addr[4] << ET_UNI_PF_ADDR2_5_SHIFT) |
 641                    etdev->addr[5];
 642
 643         uni_pf1 = (etdev->addr[2] << ET_UNI_PF_ADDR1_3_SHIFT) |
 644                   (etdev->addr[3] << ET_UNI_PF_ADDR1_4_SHIFT) |
 645                   (etdev->addr[4] << ET_UNI_PF_ADDR1_5_SHIFT) |
 646                    etdev->addr[5];
 647
 648         pm_csr = readl(&etdev->regs->global.pm_csr);
 649         if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
 650                 writel(uni_pf1, &rxmac->uni_pf_addr1);
 651                 writel(uni_pf2, &rxmac->uni_pf_addr2);
 652                 writel(uni_pf3, &rxmac->uni_pf_addr3);
 653         }
 654 }