?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] 3c59x: use mii_check_media
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / 8139too.c
blobfeae7832fc846b3daef50d83d5cf0184561b9484
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
94
95
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/kernel.h>
99 #include <linux/compiler.h>
100 #include <linux/pci.h>
101 #include <linux/init.h>
102 #include <linux/ioport.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <asm/io.h>
112 #include <asm/uaccess.h>
113 #include <asm/irq.h>
114
115 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
116 #define PFX DRV_NAME ": "
117
118 /* Default Message level */
119 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
120 NETIF_MSG_PROBE | \
121 NETIF_MSG_LINK)
122
123
124 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
125 #ifdef CONFIG_8139TOO_PIO
126 #define USE_IO_OPS 1
127 #endif
128
129 /* define to 1, 2 or 3 to enable copious debugging info */
130 #define RTL8139_DEBUG 0
131
132 /* define to 1 to disable lightweight runtime debugging checks */
133 #undef RTL8139_NDEBUG
134
135
136 #if RTL8139_DEBUG
137 /* note: prints function name for you */
138 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
139 #else
140 # define DPRINTK(fmt, args...)
141 #endif
142
143 #ifdef RTL8139_NDEBUG
144 # define assert(expr) do {} while (0)
145 #else
146 # define assert(expr) \
147 if(unlikely(!(expr))) { \
148 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
149 #expr,__FILE__,__FUNCTION__,__LINE__); \
150 }
151 #endif
152
153
154 /* A few user-configurable values. */
155 /* media options */
156 #define MAX_UNITS 8
157 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 1 /* 16K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static const struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 FlashReg = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 PARA7c = 0x7c, /* Magic transceiver parameter register. */
329 Config5 = 0xD8, /* absent on RTL-8139A */
330 };
331
332 enum ClearBitMasks {
333 MultiIntrClear = 0xF000,
334 ChipCmdClear = 0xE2,
335 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
336 };
337
338 enum ChipCmdBits {
339 CmdReset = 0x10,
340 CmdRxEnb = 0x08,
341 CmdTxEnb = 0x04,
342 RxBufEmpty = 0x01,
343 };
344
345 /* Interrupt register bits, using my own meaningful names. */
346 enum IntrStatusBits {
347 PCIErr = 0x8000,
348 PCSTimeout = 0x4000,
349 RxFIFOOver = 0x40,
350 RxUnderrun = 0x20,
351 RxOverflow = 0x10,
352 TxErr = 0x08,
353 TxOK = 0x04,
354 RxErr = 0x02,
355 RxOK = 0x01,
356
357 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
358 };
359
360 enum TxStatusBits {
361 TxHostOwns = 0x2000,
362 TxUnderrun = 0x4000,
363 TxStatOK = 0x8000,
364 TxOutOfWindow = 0x20000000,
365 TxAborted = 0x40000000,
366 TxCarrierLost = 0x80000000,
367 };
368 enum RxStatusBits {
369 RxMulticast = 0x8000,
370 RxPhysical = 0x4000,
371 RxBroadcast = 0x2000,
372 RxBadSymbol = 0x0020,
373 RxRunt = 0x0010,
374 RxTooLong = 0x0008,
375 RxCRCErr = 0x0004,
376 RxBadAlign = 0x0002,
377 RxStatusOK = 0x0001,
378 };
379
380 /* Bits in RxConfig. */
381 enum rx_mode_bits {
382 AcceptErr = 0x20,
383 AcceptRunt = 0x10,
384 AcceptBroadcast = 0x08,
385 AcceptMulticast = 0x04,
386 AcceptMyPhys = 0x02,
387 AcceptAllPhys = 0x01,
388 };
389
390 /* Bits in TxConfig. */
391 enum tx_config_bits {
392
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 static const struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasHltClk /* XXX undocumented? */
556 | HasLWake,
557 },
558
559 { "RTL-8101",
560 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 HasLWake,
562 },
563 };
564
565 struct rtl_extra_stats {
566 unsigned long early_rx;
567 unsigned long tx_buf_mapped;
568 unsigned long tx_timeouts;
569 unsigned long rx_lost_in_ring;
570 };
571
572 struct rtl8139_private {
573 void __iomem *mmio_addr;
574 int drv_flags;
575 struct pci_dev *pci_dev;
576 u32 msg_enable;
577 struct net_device_stats stats;
578 unsigned char *rx_ring;
579 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
580 unsigned int tx_flag;
581 unsigned long cur_tx;
582 unsigned long dirty_tx;
583 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
584 unsigned char *tx_bufs; /* Tx bounce buffer region. */
585 dma_addr_t rx_ring_dma;
586 dma_addr_t tx_bufs_dma;
587 signed char phys[4]; /* MII device addresses. */
588 char twistie, twist_row, twist_col; /* Twister tune state. */
589 unsigned int watchdog_fired : 1;
590 unsigned int default_port : 4; /* Last dev->if_port value. */
591 unsigned int have_thread : 1;
592 spinlock_t lock;
593 spinlock_t rx_lock;
594 chip_t chipset;
595 u32 rx_config;
596 struct rtl_extra_stats xstats;
597
598 struct work_struct thread;
599
600 struct mii_if_info mii;
601 unsigned int regs_len;
602 unsigned long fifo_copy_timeout;
603 };
604
605 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
606 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
607 MODULE_LICENSE("GPL");
608 MODULE_VERSION(DRV_VERSION);
609
610 module_param(multicast_filter_limit, int, 0);
611 module_param_array(media, int, NULL, 0);
612 module_param_array(full_duplex, int, NULL, 0);
613 module_param(debug, int, 0);
614 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
615 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
616 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
617 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
618
619 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
620 static int rtl8139_open (struct net_device *dev);
621 static int mdio_read (struct net_device *dev, int phy_id, int location);
622 static void mdio_write (struct net_device *dev, int phy_id, int location,
623 int val);
624 static void rtl8139_start_thread(struct rtl8139_private *tp);
625 static void rtl8139_tx_timeout (struct net_device *dev);
626 static void rtl8139_init_ring (struct net_device *dev);
627 static int rtl8139_start_xmit (struct sk_buff *skb,
628 struct net_device *dev);
629 static int rtl8139_poll(struct net_device *dev, int *budget);
630 #ifdef CONFIG_NET_POLL_CONTROLLER
631 static void rtl8139_poll_controller(struct net_device *dev);
632 #endif
633 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
634 struct pt_regs *regs);
635 static int rtl8139_close (struct net_device *dev);
636 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
637 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
638 static void rtl8139_set_rx_mode (struct net_device *dev);
639 static void __set_rx_mode (struct net_device *dev);
640 static void rtl8139_hw_start (struct net_device *dev);
641 static void rtl8139_thread (void *_data);
642 static void rtl8139_tx_timeout_task(void *_data);
643 static struct ethtool_ops rtl8139_ethtool_ops;
644
645 /* write MMIO register, with flush */
646 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
647 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
648 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
649 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
650
651
652 #define MMIO_FLUSH_AUDIT_COMPLETE 1
653 #if MMIO_FLUSH_AUDIT_COMPLETE
654
655 /* write MMIO register */
656 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
657 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
658 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
659
660 #else
661
662 /* write MMIO register, then flush */
663 #define RTL_W8 RTL_W8_F
664 #define RTL_W16 RTL_W16_F
665 #define RTL_W32 RTL_W32_F
666
667 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
668
669 /* read MMIO register */
670 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
671 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
672 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
673
674
675 static const u16 rtl8139_intr_mask =
676 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
677 TxErr | TxOK | RxErr | RxOK;
678
679 static const u16 rtl8139_norx_intr_mask =
680 PCIErr | PCSTimeout | RxUnderrun |
681 TxErr | TxOK | RxErr ;
682
683 #if RX_BUF_IDX == 0
684 static const unsigned int rtl8139_rx_config =
685 RxCfgRcv8K | RxNoWrap |
686 (RX_FIFO_THRESH << RxCfgFIFOShift) |
687 (RX_DMA_BURST << RxCfgDMAShift);
688 #elif RX_BUF_IDX == 1
689 static const unsigned int rtl8139_rx_config =
690 RxCfgRcv16K | RxNoWrap |
691 (RX_FIFO_THRESH << RxCfgFIFOShift) |
692 (RX_DMA_BURST << RxCfgDMAShift);
693 #elif RX_BUF_IDX == 2
694 static const unsigned int rtl8139_rx_config =
695 RxCfgRcv32K | RxNoWrap |
696 (RX_FIFO_THRESH << RxCfgFIFOShift) |
697 (RX_DMA_BURST << RxCfgDMAShift);
698 #elif RX_BUF_IDX == 3
699 static const unsigned int rtl8139_rx_config =
700 RxCfgRcv64K |
701 (RX_FIFO_THRESH << RxCfgFIFOShift) |
702 (RX_DMA_BURST << RxCfgDMAShift);
703 #else
704 #error "Invalid configuration for 8139_RXBUF_IDX"
705 #endif
706
707 static const unsigned int rtl8139_tx_config =
708 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
709
710 static void __rtl8139_cleanup_dev (struct net_device *dev)
711 {
712 struct rtl8139_private *tp = netdev_priv(dev);
713 struct pci_dev *pdev;
714
715 assert (dev != NULL);
716 assert (tp->pci_dev != NULL);
717 pdev = tp->pci_dev;
718
719 #ifdef USE_IO_OPS
720 if (tp->mmio_addr)
721 ioport_unmap (tp->mmio_addr);
722 #else
723 if (tp->mmio_addr)
724 pci_iounmap (pdev, tp->mmio_addr);
725 #endif /* USE_IO_OPS */
726
727 /* it's ok to call this even if we have no regions to free */
728 pci_release_regions (pdev);
729
730 free_netdev(dev);
731 pci_set_drvdata (pdev, NULL);
732 }
733
734
735 static void rtl8139_chip_reset (void __iomem *ioaddr)
736 {
737 int i;
738
739 /* Soft reset the chip. */
740 RTL_W8 (ChipCmd, CmdReset);
741
742 /* Check that the chip has finished the reset. */
743 for (i = 1000; i > 0; i--) {
744 barrier();
745 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
746 break;
747 udelay (10);
748 }
749 }
750
751
752 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
753 struct net_device **dev_out)
754 {
755 void __iomem *ioaddr;
756 struct net_device *dev;
757 struct rtl8139_private *tp;
758 u8 tmp8;
759 int rc, disable_dev_on_err = 0;
760 unsigned int i;
761 unsigned long pio_start, pio_end, pio_flags, pio_len;
762 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
763 u32 version;
764
765 assert (pdev != NULL);
766
767 *dev_out = NULL;
768
769 /* dev and priv zeroed in alloc_etherdev */
770 dev = alloc_etherdev (sizeof (*tp));
771 if (dev == NULL) {
772 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
773 return -ENOMEM;
774 }
775 SET_MODULE_OWNER(dev);
776 SET_NETDEV_DEV(dev, &pdev->dev);
777
778 tp = netdev_priv(dev);
779 tp->pci_dev = pdev;
780
781 /* enable device (incl. PCI PM wakeup and hotplug setup) */
782 rc = pci_enable_device (pdev);
783 if (rc)
784 goto err_out;
785
786 pio_start = pci_resource_start (pdev, 0);
787 pio_end = pci_resource_end (pdev, 0);
788 pio_flags = pci_resource_flags (pdev, 0);
789 pio_len = pci_resource_len (pdev, 0);
790
791 mmio_start = pci_resource_start (pdev, 1);
792 mmio_end = pci_resource_end (pdev, 1);
793 mmio_flags = pci_resource_flags (pdev, 1);
794 mmio_len = pci_resource_len (pdev, 1);
795
796 /* set this immediately, we need to know before
797 * we talk to the chip directly */
798 DPRINTK("PIO region size == 0x%02X\n", pio_len);
799 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
800
801 #ifdef USE_IO_OPS
802 /* make sure PCI base addr 0 is PIO */
803 if (!(pio_flags & IORESOURCE_IO)) {
804 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
805 rc = -ENODEV;
806 goto err_out;
807 }
808 /* check for weird/broken PCI region reporting */
809 if (pio_len < RTL_MIN_IO_SIZE) {
810 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
811 rc = -ENODEV;
812 goto err_out;
813 }
814 #else
815 /* make sure PCI base addr 1 is MMIO */
816 if (!(mmio_flags & IORESOURCE_MEM)) {
817 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
818 rc = -ENODEV;
819 goto err_out;
820 }
821 if (mmio_len < RTL_MIN_IO_SIZE) {
822 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
823 rc = -ENODEV;
824 goto err_out;
825 }
826 #endif
827
828 rc = pci_request_regions (pdev, "8139too");
829 if (rc)
830 goto err_out;
831 disable_dev_on_err = 1;
832
833 /* enable PCI bus-mastering */
834 pci_set_master (pdev);
835
836 #ifdef USE_IO_OPS
837 ioaddr = ioport_map(pio_start, pio_len);
838 if (!ioaddr) {
839 printk (KERN_ERR PFX "%s: cannot map PIO, aborting\n", pci_name(pdev));
840 rc = -EIO;
841 goto err_out;
842 }
843 dev->base_addr = pio_start;
844 tp->mmio_addr = ioaddr;
845 tp->regs_len = pio_len;
846 #else
847 /* ioremap MMIO region */
848 ioaddr = pci_iomap(pdev, 1, 0);
849 if (ioaddr == NULL) {
850 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
851 rc = -EIO;
852 goto err_out;
853 }
854 dev->base_addr = (long) ioaddr;
855 tp->mmio_addr = ioaddr;
856 tp->regs_len = mmio_len;
857 #endif /* USE_IO_OPS */
858
859 /* Bring old chips out of low-power mode. */
860 RTL_W8 (HltClk, 'R');
861
862 /* check for missing/broken hardware */
863 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
864 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
865 pci_name(pdev));
866 rc = -EIO;
867 goto err_out;
868 }
869
870 /* identify chip attached to board */
871 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
872 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
873 if (version == rtl_chip_info[i].version) {
874 tp->chipset = i;
875 goto match;
876 }
877
878 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
879 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
880 pci_name(pdev));
881 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
882 tp->chipset = 0;
883
884 match:
885 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
886 version, i, rtl_chip_info[i].name);
887
888 if (tp->chipset >= CH_8139B) {
889 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
890 DPRINTK("PCI PM wakeup\n");
891 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
892 (tmp8 & LWAKE))
893 new_tmp8 &= ~LWAKE;
894 new_tmp8 |= Cfg1_PM_Enable;
895 if (new_tmp8 != tmp8) {
896 RTL_W8 (Cfg9346, Cfg9346_Unlock);
897 RTL_W8 (Config1, tmp8);
898 RTL_W8 (Cfg9346, Cfg9346_Lock);
899 }
900 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
901 tmp8 = RTL_R8 (Config4);
902 if (tmp8 & LWPTN) {
903 RTL_W8 (Cfg9346, Cfg9346_Unlock);
904 RTL_W8 (Config4, tmp8 & ~LWPTN);
905 RTL_W8 (Cfg9346, Cfg9346_Lock);
906 }
907 }
908 } else {
909 DPRINTK("Old chip wakeup\n");
910 tmp8 = RTL_R8 (Config1);
911 tmp8 &= ~(SLEEP | PWRDN);
912 RTL_W8 (Config1, tmp8);
913 }
914
915 rtl8139_chip_reset (ioaddr);
916
917 *dev_out = dev;
918 return 0;
919
920 err_out:
921 __rtl8139_cleanup_dev (dev);
922 if (disable_dev_on_err)
923 pci_disable_device (pdev);
924 return rc;
925 }
926
927
928 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
929 const struct pci_device_id *ent)
930 {
931 struct net_device *dev = NULL;
932 struct rtl8139_private *tp;
933 int i, addr_len, option;
934 void __iomem *ioaddr;
935 static int board_idx = -1;
936 u8 pci_rev;
937
938 assert (pdev != NULL);
939 assert (ent != NULL);
940
941 board_idx++;
942
943 /* when we're built into the kernel, the driver version message
944 * is only printed if at least one 8139 board has been found
945 */
946 #ifndef MODULE
947 {
948 static int printed_version;
949 if (!printed_version++)
950 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
951 }
952 #endif
953
954 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
955
956 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
957 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
958 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
959 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
960 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
961 }
962
963 i = rtl8139_init_board (pdev, &dev);
964 if (i < 0)
965 return i;
966
967 assert (dev != NULL);
968 tp = netdev_priv(dev);
969
970 ioaddr = tp->mmio_addr;
971 assert (ioaddr != NULL);
972
973 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
974 for (i = 0; i < 3; i++)
975 ((u16 *) (dev->dev_addr))[i] =
976 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
977 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
978
979 /* The Rtl8139-specific entries in the device structure. */
980 dev->open = rtl8139_open;
981 dev->hard_start_xmit = rtl8139_start_xmit;
982 dev->poll = rtl8139_poll;
983 dev->weight = 64;
984 dev->stop = rtl8139_close;
985 dev->get_stats = rtl8139_get_stats;
986 dev->set_multicast_list = rtl8139_set_rx_mode;
987 dev->do_ioctl = netdev_ioctl;
988 dev->ethtool_ops = &rtl8139_ethtool_ops;
989 dev->tx_timeout = rtl8139_tx_timeout;
990 dev->watchdog_timeo = TX_TIMEOUT;
991 #ifdef CONFIG_NET_POLL_CONTROLLER
992 dev->poll_controller = rtl8139_poll_controller;
993 #endif
994
995 /* note: the hardware is not capable of sg/csum/highdma, however
996 * through the use of skb_copy_and_csum_dev we enable these
997 * features
998 */
999 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1000
1001 dev->irq = pdev->irq;
1002
1003 /* tp zeroed and aligned in alloc_etherdev */
1004 tp = netdev_priv(dev);
1005
1006 /* note: tp->chipset set in rtl8139_init_board */
1007 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1008 tp->mmio_addr = ioaddr;
1009 tp->msg_enable =
1010 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1011 spin_lock_init (&tp->lock);
1012 spin_lock_init (&tp->rx_lock);
1013 INIT_WORK(&tp->thread, rtl8139_thread, dev);
1014 tp->mii.dev = dev;
1015 tp->mii.mdio_read = mdio_read;
1016 tp->mii.mdio_write = mdio_write;
1017 tp->mii.phy_id_mask = 0x3f;
1018 tp->mii.reg_num_mask = 0x1f;
1019
1020 /* dev is fully set up and ready to use now */
1021 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1022 i = register_netdev (dev);
1023 if (i) goto err_out;
1024
1025 pci_set_drvdata (pdev, dev);
1026
1027 printk (KERN_INFO "%s: %s at 0x%lx, "
1028 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1029 "IRQ %d\n",
1030 dev->name,
1031 board_info[ent->driver_data].name,
1032 dev->base_addr,
1033 dev->dev_addr[0], dev->dev_addr[1],
1034 dev->dev_addr[2], dev->dev_addr[3],
1035 dev->dev_addr[4], dev->dev_addr[5],
1036 dev->irq);
1037
1038 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1039 dev->name, rtl_chip_info[tp->chipset].name);
1040
1041 /* Find the connected MII xcvrs.
1042 Doing this in open() would allow detecting external xcvrs later, but
1043 takes too much time. */
1044 #ifdef CONFIG_8139TOO_8129
1045 if (tp->drv_flags & HAS_MII_XCVR) {
1046 int phy, phy_idx = 0;
1047 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1048 int mii_status = mdio_read(dev, phy, 1);
1049 if (mii_status != 0xffff && mii_status != 0x0000) {
1050 u16 advertising = mdio_read(dev, phy, 4);
1051 tp->phys[phy_idx++] = phy;
1052 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1053 "advertising %4.4x.\n",
1054 dev->name, phy, mii_status, advertising);
1055 }
1056 }
1057 if (phy_idx == 0) {
1058 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1059 "transceiver.\n",
1060 dev->name);
1061 tp->phys[0] = 32;
1062 }
1063 } else
1064 #endif
1065 tp->phys[0] = 32;
1066 tp->mii.phy_id = tp->phys[0];
1067
1068 /* The lower four bits are the media type. */
1069 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1070 if (option > 0) {
1071 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1072 tp->default_port = option & 0xFF;
1073 if (tp->default_port)
1074 tp->mii.force_media = 1;
1075 }
1076 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1077 tp->mii.full_duplex = full_duplex[board_idx];
1078 if (tp->mii.full_duplex) {
1079 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1080 /* Changing the MII-advertised media because might prevent
1081 re-connection. */
1082 tp->mii.force_media = 1;
1083 }
1084 if (tp->default_port) {
1085 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1086 (option & 0x20 ? 100 : 10),
1087 (option & 0x10 ? "full" : "half"));
1088 mdio_write(dev, tp->phys[0], 0,
1089 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1090 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1091 }
1092
1093 /* Put the chip into low-power mode. */
1094 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1095 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1096
1097 return 0;
1098
1099 err_out:
1100 __rtl8139_cleanup_dev (dev);
1101 pci_disable_device (pdev);
1102 return i;
1103 }
1104
1105
1106 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1107 {
1108 struct net_device *dev = pci_get_drvdata (pdev);
1109
1110 assert (dev != NULL);
1111
1112 unregister_netdev (dev);
1113
1114 __rtl8139_cleanup_dev (dev);
1115 pci_disable_device (pdev);
1116 }
1117
1118
1119 /* Serial EEPROM section. */
1120
1121 /* EEPROM_Ctrl bits. */
1122 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1123 #define EE_CS 0x08 /* EEPROM chip select. */
1124 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1125 #define EE_WRITE_0 0x00
1126 #define EE_WRITE_1 0x02
1127 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1128 #define EE_ENB (0x80 | EE_CS)
1129
1130 /* Delay between EEPROM clock transitions.
1131 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1132 */
1133
1134 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1135
1136 /* The EEPROM commands include the alway-set leading bit. */
1137 #define EE_WRITE_CMD (5)
1138 #define EE_READ_CMD (6)
1139 #define EE_ERASE_CMD (7)
1140
1141 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1142 {
1143 int i;
1144 unsigned retval = 0;
1145 int read_cmd = location | (EE_READ_CMD << addr_len);
1146
1147 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1148 RTL_W8 (Cfg9346, EE_ENB);
1149 eeprom_delay ();
1150
1151 /* Shift the read command bits out. */
1152 for (i = 4 + addr_len; i >= 0; i--) {
1153 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1154 RTL_W8 (Cfg9346, EE_ENB | dataval);
1155 eeprom_delay ();
1156 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1157 eeprom_delay ();
1158 }
1159 RTL_W8 (Cfg9346, EE_ENB);
1160 eeprom_delay ();
1161
1162 for (i = 16; i > 0; i--) {
1163 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1164 eeprom_delay ();
1165 retval =
1166 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1167 0);
1168 RTL_W8 (Cfg9346, EE_ENB);
1169 eeprom_delay ();
1170 }
1171
1172 /* Terminate the EEPROM access. */
1173 RTL_W8 (Cfg9346, ~EE_CS);
1174 eeprom_delay ();
1175
1176 return retval;
1177 }
1178
1179 /* MII serial management: mostly bogus for now. */
1180 /* Read and write the MII management registers using software-generated
1181 serial MDIO protocol.
1182 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1183 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1184 "overclocking" issues. */
1185 #define MDIO_DIR 0x80
1186 #define MDIO_DATA_OUT 0x04
1187 #define MDIO_DATA_IN 0x02
1188 #define MDIO_CLK 0x01
1189 #define MDIO_WRITE0 (MDIO_DIR)
1190 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1191
1192 #define mdio_delay() RTL_R8(Config4)
1193
1194
1195 static const char mii_2_8139_map[8] = {
1196 BasicModeCtrl,
1197 BasicModeStatus,
1198 0,
1199 0,
1200 NWayAdvert,
1201 NWayLPAR,
1202 NWayExpansion,
1203 0
1204 };
1205
1206
1207 #ifdef CONFIG_8139TOO_8129
1208 /* Syncronize the MII management interface by shifting 32 one bits out. */
1209 static void mdio_sync (void __iomem *ioaddr)
1210 {
1211 int i;
1212
1213 for (i = 32; i >= 0; i--) {
1214 RTL_W8 (Config4, MDIO_WRITE1);
1215 mdio_delay ();
1216 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1217 mdio_delay ();
1218 }
1219 }
1220 #endif
1221
1222 static int mdio_read (struct net_device *dev, int phy_id, int location)
1223 {
1224 struct rtl8139_private *tp = netdev_priv(dev);
1225 int retval = 0;
1226 #ifdef CONFIG_8139TOO_8129
1227 void __iomem *ioaddr = tp->mmio_addr;
1228 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1229 int i;
1230 #endif
1231
1232 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1233 void __iomem *ioaddr = tp->mmio_addr;
1234 return location < 8 && mii_2_8139_map[location] ?
1235 RTL_R16 (mii_2_8139_map[location]) : 0;
1236 }
1237
1238 #ifdef CONFIG_8139TOO_8129
1239 mdio_sync (ioaddr);
1240 /* Shift the read command bits out. */
1241 for (i = 15; i >= 0; i--) {
1242 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1243
1244 RTL_W8 (Config4, MDIO_DIR | dataval);
1245 mdio_delay ();
1246 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1247 mdio_delay ();
1248 }
1249
1250 /* Read the two transition, 16 data, and wire-idle bits. */
1251 for (i = 19; i > 0; i--) {
1252 RTL_W8 (Config4, 0);
1253 mdio_delay ();
1254 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1255 RTL_W8 (Config4, MDIO_CLK);
1256 mdio_delay ();
1257 }
1258 #endif
1259
1260 return (retval >> 1) & 0xffff;
1261 }
1262
1263
1264 static void mdio_write (struct net_device *dev, int phy_id, int location,
1265 int value)
1266 {
1267 struct rtl8139_private *tp = netdev_priv(dev);
1268 #ifdef CONFIG_8139TOO_8129
1269 void __iomem *ioaddr = tp->mmio_addr;
1270 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1271 int i;
1272 #endif
1273
1274 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1275 void __iomem *ioaddr = tp->mmio_addr;
1276 if (location == 0) {
1277 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1278 RTL_W16 (BasicModeCtrl, value);
1279 RTL_W8 (Cfg9346, Cfg9346_Lock);
1280 } else if (location < 8 && mii_2_8139_map[location])
1281 RTL_W16 (mii_2_8139_map[location], value);
1282 return;
1283 }
1284
1285 #ifdef CONFIG_8139TOO_8129
1286 mdio_sync (ioaddr);
1287
1288 /* Shift the command bits out. */
1289 for (i = 31; i >= 0; i--) {
1290 int dataval =
1291 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1292 RTL_W8 (Config4, dataval);
1293 mdio_delay ();
1294 RTL_W8 (Config4, dataval | MDIO_CLK);
1295 mdio_delay ();
1296 }
1297 /* Clear out extra bits. */
1298 for (i = 2; i > 0; i--) {
1299 RTL_W8 (Config4, 0);
1300 mdio_delay ();
1301 RTL_W8 (Config4, MDIO_CLK);
1302 mdio_delay ();
1303 }
1304 #endif
1305 }
1306
1307
1308 static int rtl8139_open (struct net_device *dev)
1309 {
1310 struct rtl8139_private *tp = netdev_priv(dev);
1311 int retval;
1312 void __iomem *ioaddr = tp->mmio_addr;
1313
1314 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1315 if (retval)
1316 return retval;
1317
1318 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1319 &tp->tx_bufs_dma);
1320 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1321 &tp->rx_ring_dma);
1322 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1323 free_irq(dev->irq, dev);
1324
1325 if (tp->tx_bufs)
1326 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1327 tp->tx_bufs, tp->tx_bufs_dma);
1328 if (tp->rx_ring)
1329 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1330 tp->rx_ring, tp->rx_ring_dma);
1331
1332 return -ENOMEM;
1333
1334 }
1335
1336 tp->mii.full_duplex = tp->mii.force_media;
1337 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1338
1339 rtl8139_init_ring (dev);
1340 rtl8139_hw_start (dev);
1341 netif_start_queue (dev);
1342
1343 if (netif_msg_ifup(tp))
1344 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1345 " GP Pins %2.2x %s-duplex.\n",
1346 dev->name, pci_resource_start (tp->pci_dev, 1),
1347 dev->irq, RTL_R8 (MediaStatus),
1348 tp->mii.full_duplex ? "full" : "half");
1349
1350 rtl8139_start_thread(tp);
1351
1352 return 0;
1353 }
1354
1355
1356 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1357 {
1358 struct rtl8139_private *tp = netdev_priv(dev);
1359
1360 if (tp->phys[0] >= 0) {
1361 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1362 }
1363 }
1364
1365 /* Start the hardware at open or resume. */
1366 static void rtl8139_hw_start (struct net_device *dev)
1367 {
1368 struct rtl8139_private *tp = netdev_priv(dev);
1369 void __iomem *ioaddr = tp->mmio_addr;
1370 u32 i;
1371 u8 tmp;
1372
1373 /* Bring old chips out of low-power mode. */
1374 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1375 RTL_W8 (HltClk, 'R');
1376
1377 rtl8139_chip_reset (ioaddr);
1378
1379 /* unlock Config[01234] and BMCR register writes */
1380 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1381 /* Restore our idea of the MAC address. */
1382 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1383 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1384
1385 /* Must enable Tx/Rx before setting transfer thresholds! */
1386 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1387
1388 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1389 RTL_W32 (RxConfig, tp->rx_config);
1390 RTL_W32 (TxConfig, rtl8139_tx_config);
1391
1392 tp->cur_rx = 0;
1393
1394 rtl_check_media (dev, 1);
1395
1396 if (tp->chipset >= CH_8139B) {
1397 /* Disable magic packet scanning, which is enabled
1398 * when PM is enabled in Config1. It can be reenabled
1399 * via ETHTOOL_SWOL if desired. */
1400 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1401 }
1402
1403 DPRINTK("init buffer addresses\n");
1404
1405 /* Lock Config[01234] and BMCR register writes */
1406 RTL_W8 (Cfg9346, Cfg9346_Lock);
1407
1408 /* init Rx ring buffer DMA address */
1409 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1410
1411 /* init Tx buffer DMA addresses */
1412 for (i = 0; i < NUM_TX_DESC; i++)
1413 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1414
1415 RTL_W32 (RxMissed, 0);
1416
1417 rtl8139_set_rx_mode (dev);
1418
1419 /* no early-rx interrupts */
1420 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1421
1422 /* make sure RxTx has started */
1423 tmp = RTL_R8 (ChipCmd);
1424 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1425 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1426
1427 /* Enable all known interrupts by setting the interrupt mask. */
1428 RTL_W16 (IntrMask, rtl8139_intr_mask);
1429 }
1430
1431
1432 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1433 static void rtl8139_init_ring (struct net_device *dev)
1434 {
1435 struct rtl8139_private *tp = netdev_priv(dev);
1436 int i;
1437
1438 tp->cur_rx = 0;
1439 tp->cur_tx = 0;
1440 tp->dirty_tx = 0;
1441
1442 for (i = 0; i < NUM_TX_DESC; i++)
1443 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1444 }
1445
1446
1447 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1448 static int next_tick = 3 * HZ;
1449
1450 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1451 static inline void rtl8139_tune_twister (struct net_device *dev,
1452 struct rtl8139_private *tp) {}
1453 #else
1454 enum TwisterParamVals {
1455 PARA78_default = 0x78fa8388,
1456 PARA7c_default = 0xcb38de43, /* param[0][3] */
1457 PARA7c_xxx = 0xcb38de43,
1458 };
1459
1460 static const unsigned long param[4][4] = {
1461 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1462 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1463 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1464 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1465 };
1466
1467 static void rtl8139_tune_twister (struct net_device *dev,
1468 struct rtl8139_private *tp)
1469 {
1470 int linkcase;
1471 void __iomem *ioaddr = tp->mmio_addr;
1472
1473 /* This is a complicated state machine to configure the "twister" for
1474 impedance/echos based on the cable length.
1475 All of this is magic and undocumented.
1476 */
1477 switch (tp->twistie) {
1478 case 1:
1479 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1480 /* We have link beat, let us tune the twister. */
1481 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1482 tp->twistie = 2; /* Change to state 2. */
1483 next_tick = HZ / 10;
1484 } else {
1485 /* Just put in some reasonable defaults for when beat returns. */
1486 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1487 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1488 RTL_W32 (PARA78, PARA78_default);
1489 RTL_W32 (PARA7c, PARA7c_default);
1490 tp->twistie = 0; /* Bail from future actions. */
1491 }
1492 break;
1493 case 2:
1494 /* Read how long it took to hear the echo. */
1495 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1496 if (linkcase == 0x7000)
1497 tp->twist_row = 3;
1498 else if (linkcase == 0x3000)
1499 tp->twist_row = 2;
1500 else if (linkcase == 0x1000)
1501 tp->twist_row = 1;
1502 else
1503 tp->twist_row = 0;
1504 tp->twist_col = 0;
1505 tp->twistie = 3; /* Change to state 2. */
1506 next_tick = HZ / 10;
1507 break;
1508 case 3:
1509 /* Put out four tuning parameters, one per 100msec. */
1510 if (tp->twist_col == 0)
1511 RTL_W16 (FIFOTMS, 0);
1512 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1513 [(int) tp->twist_col]);
1514 next_tick = HZ / 10;
1515 if (++tp->twist_col >= 4) {
1516 /* For short cables we are done.
1517 For long cables (row == 3) check for mistune. */
1518 tp->twistie =
1519 (tp->twist_row == 3) ? 4 : 0;
1520 }
1521 break;
1522 case 4:
1523 /* Special case for long cables: check for mistune. */
1524 if ((RTL_R16 (CSCR) &
1525 CSCR_LinkStatusBits) == 0x7000) {
1526 tp->twistie = 0;
1527 break;
1528 } else {
1529 RTL_W32 (PARA7c, 0xfb38de03);
1530 tp->twistie = 5;
1531 next_tick = HZ / 10;
1532 }
1533 break;
1534 case 5:
1535 /* Retune for shorter cable (column 2). */
1536 RTL_W32 (FIFOTMS, 0x20);
1537 RTL_W32 (PARA78, PARA78_default);
1538 RTL_W32 (PARA7c, PARA7c_default);
1539 RTL_W32 (FIFOTMS, 0x00);
1540 tp->twist_row = 2;
1541 tp->twist_col = 0;
1542 tp->twistie = 3;
1543 next_tick = HZ / 10;
1544 break;
1545
1546 default:
1547 /* do nothing */
1548 break;
1549 }
1550 }
1551 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1552
1553 static inline void rtl8139_thread_iter (struct net_device *dev,
1554 struct rtl8139_private *tp,
1555 void __iomem *ioaddr)
1556 {
1557 int mii_lpa;
1558
1559 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1560
1561 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1562 int duplex = (mii_lpa & LPA_100FULL)
1563 || (mii_lpa & 0x01C0) == 0x0040;
1564 if (tp->mii.full_duplex != duplex) {
1565 tp->mii.full_duplex = duplex;
1566
1567 if (mii_lpa) {
1568 printk (KERN_INFO
1569 "%s: Setting %s-duplex based on MII #%d link"
1570 " partner ability of %4.4x.\n",
1571 dev->name,
1572 tp->mii.full_duplex ? "full" : "half",
1573 tp->phys[0], mii_lpa);
1574 } else {
1575 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1576 dev->name);
1577 }
1578 #if 0
1579 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1580 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1581 RTL_W8 (Cfg9346, Cfg9346_Lock);
1582 #endif
1583 }
1584 }
1585
1586 next_tick = HZ * 60;
1587
1588 rtl8139_tune_twister (dev, tp);
1589
1590 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1591 dev->name, RTL_R16 (NWayLPAR));
1592 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1593 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1594 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1595 dev->name, RTL_R8 (Config0),
1596 RTL_R8 (Config1));
1597 }
1598
1599 static void rtl8139_thread (void *_data)
1600 {
1601 struct net_device *dev = _data;
1602 struct rtl8139_private *tp = netdev_priv(dev);
1603 unsigned long thr_delay = next_tick;
1604
1605 if (tp->watchdog_fired) {
1606 tp->watchdog_fired = 0;
1607 rtl8139_tx_timeout_task(_data);
1608 } else if (rtnl_trylock()) {
1609 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1610 rtnl_unlock ();
1611 } else {
1612 /* unlikely race. mitigate with fast poll. */
1613 thr_delay = HZ / 2;
1614 }
1615
1616 schedule_delayed_work(&tp->thread, thr_delay);
1617 }
1618
1619 static void rtl8139_start_thread(struct rtl8139_private *tp)
1620 {
1621 tp->twistie = 0;
1622 if (tp->chipset == CH_8139_K)
1623 tp->twistie = 1;
1624 else if (tp->drv_flags & HAS_LNK_CHNG)
1625 return;
1626
1627 tp->have_thread = 1;
1628
1629 schedule_delayed_work(&tp->thread, next_tick);
1630 }
1631
1632 static void rtl8139_stop_thread(struct rtl8139_private *tp)
1633 {
1634 if (tp->have_thread) {
1635 cancel_rearming_delayed_work(&tp->thread);
1636 tp->have_thread = 0;
1637 } else
1638 flush_scheduled_work();
1639 }
1640
1641 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1642 {
1643 tp->cur_tx = 0;
1644 tp->dirty_tx = 0;
1645
1646 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1647 }
1648
1649 static void rtl8139_tx_timeout_task (void *_data)
1650 {
1651 struct net_device *dev = _data;
1652 struct rtl8139_private *tp = netdev_priv(dev);
1653 void __iomem *ioaddr = tp->mmio_addr;
1654 int i;
1655 u8 tmp8;
1656
1657 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1658 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1659 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1660 /* Emit info to figure out what went wrong. */
1661 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1662 dev->name, tp->cur_tx, tp->dirty_tx);
1663 for (i = 0; i < NUM_TX_DESC; i++)
1664 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1665 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1666 i == tp->dirty_tx % NUM_TX_DESC ?
1667 " (queue head)" : "");
1668
1669 tp->xstats.tx_timeouts++;
1670
1671 /* disable Tx ASAP, if not already */
1672 tmp8 = RTL_R8 (ChipCmd);
1673 if (tmp8 & CmdTxEnb)
1674 RTL_W8 (ChipCmd, CmdRxEnb);
1675
1676 spin_lock_bh(&tp->rx_lock);
1677 /* Disable interrupts by clearing the interrupt mask. */
1678 RTL_W16 (IntrMask, 0x0000);
1679
1680 /* Stop a shared interrupt from scavenging while we are. */
1681 spin_lock_irq(&tp->lock);
1682 rtl8139_tx_clear (tp);
1683 spin_unlock_irq(&tp->lock);
1684
1685 /* ...and finally, reset everything */
1686 if (netif_running(dev)) {
1687 rtl8139_hw_start (dev);
1688 netif_wake_queue (dev);
1689 }
1690 spin_unlock_bh(&tp->rx_lock);
1691 }
1692
1693 static void rtl8139_tx_timeout (struct net_device *dev)
1694 {
1695 struct rtl8139_private *tp = netdev_priv(dev);
1696
1697 if (!tp->have_thread) {
1698 INIT_WORK(&tp->thread, rtl8139_tx_timeout_task, dev);
1699 schedule_delayed_work(&tp->thread, next_tick);
1700 } else
1701 tp->watchdog_fired = 1;
1702
1703 }
1704
1705 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1706 {
1707 struct rtl8139_private *tp = netdev_priv(dev);
1708 void __iomem *ioaddr = tp->mmio_addr;
1709 unsigned int entry;
1710 unsigned int len = skb->len;
1711
1712 /* Calculate the next Tx descriptor entry. */
1713 entry = tp->cur_tx % NUM_TX_DESC;
1714
1715 /* Note: the chip doesn't have auto-pad! */
1716 if (likely(len < TX_BUF_SIZE)) {
1717 if (len < ETH_ZLEN)
1718 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1719 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1720 dev_kfree_skb(skb);
1721 } else {
1722 dev_kfree_skb(skb);
1723 tp->stats.tx_dropped++;
1724 return 0;
1725 }
1726
1727 spin_lock_irq(&tp->lock);
1728 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1729 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1730
1731 dev->trans_start = jiffies;
1732
1733 tp->cur_tx++;
1734 wmb();
1735
1736 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1737 netif_stop_queue (dev);
1738 spin_unlock_irq(&tp->lock);
1739
1740 if (netif_msg_tx_queued(tp))
1741 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1742 dev->name, len, entry);
1743
1744 return 0;
1745 }
1746
1747
1748 static void rtl8139_tx_interrupt (struct net_device *dev,
1749 struct rtl8139_private *tp,
1750 void __iomem *ioaddr)
1751 {
1752 unsigned long dirty_tx, tx_left;
1753
1754 assert (dev != NULL);
1755 assert (ioaddr != NULL);
1756
1757 dirty_tx = tp->dirty_tx;
1758 tx_left = tp->cur_tx - dirty_tx;
1759 while (tx_left > 0) {
1760 int entry = dirty_tx % NUM_TX_DESC;
1761 int txstatus;
1762
1763 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1764
1765 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1766 break; /* It still hasn't been Txed */
1767
1768 /* Note: TxCarrierLost is always asserted at 100mbps. */
1769 if (txstatus & (TxOutOfWindow | TxAborted)) {
1770 /* There was an major error, log it. */
1771 if (netif_msg_tx_err(tp))
1772 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1773 dev->name, txstatus);
1774 tp->stats.tx_errors++;
1775 if (txstatus & TxAborted) {
1776 tp->stats.tx_aborted_errors++;
1777 RTL_W32 (TxConfig, TxClearAbt);
1778 RTL_W16 (IntrStatus, TxErr);
1779 wmb();
1780 }
1781 if (txstatus & TxCarrierLost)
1782 tp->stats.tx_carrier_errors++;
1783 if (txstatus & TxOutOfWindow)
1784 tp->stats.tx_window_errors++;
1785 } else {
1786 if (txstatus & TxUnderrun) {
1787 /* Add 64 to the Tx FIFO threshold. */
1788 if (tp->tx_flag < 0x00300000)
1789 tp->tx_flag += 0x00020000;
1790 tp->stats.tx_fifo_errors++;
1791 }
1792 tp->stats.collisions += (txstatus >> 24) & 15;
1793 tp->stats.tx_bytes += txstatus & 0x7ff;
1794 tp->stats.tx_packets++;
1795 }
1796
1797 dirty_tx++;
1798 tx_left--;
1799 }
1800
1801 #ifndef RTL8139_NDEBUG
1802 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1803 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1804 dev->name, dirty_tx, tp->cur_tx);
1805 dirty_tx += NUM_TX_DESC;
1806 }
1807 #endif /* RTL8139_NDEBUG */
1808
1809 /* only wake the queue if we did work, and the queue is stopped */
1810 if (tp->dirty_tx != dirty_tx) {
1811 tp->dirty_tx = dirty_tx;
1812 mb();
1813 netif_wake_queue (dev);
1814 }
1815 }
1816
1817
1818 /* TODO: clean this up! Rx reset need not be this intensive */
1819 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1820 struct rtl8139_private *tp, void __iomem *ioaddr)
1821 {
1822 u8 tmp8;
1823 #ifdef CONFIG_8139_OLD_RX_RESET
1824 int tmp_work;
1825 #endif
1826
1827 if (netif_msg_rx_err (tp))
1828 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1829 dev->name, rx_status);
1830 tp->stats.rx_errors++;
1831 if (!(rx_status & RxStatusOK)) {
1832 if (rx_status & RxTooLong) {
1833 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1834 dev->name, rx_status);
1835 /* A.C.: The chip hangs here. */
1836 }
1837 if (rx_status & (RxBadSymbol | RxBadAlign))
1838 tp->stats.rx_frame_errors++;
1839 if (rx_status & (RxRunt | RxTooLong))
1840 tp->stats.rx_length_errors++;
1841 if (rx_status & RxCRCErr)
1842 tp->stats.rx_crc_errors++;
1843 } else {
1844 tp->xstats.rx_lost_in_ring++;
1845 }
1846
1847 #ifndef CONFIG_8139_OLD_RX_RESET
1848 tmp8 = RTL_R8 (ChipCmd);
1849 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1850 RTL_W8 (ChipCmd, tmp8);
1851 RTL_W32 (RxConfig, tp->rx_config);
1852 tp->cur_rx = 0;
1853 #else
1854 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1855
1856 /* disable receive */
1857 RTL_W8_F (ChipCmd, CmdTxEnb);
1858 tmp_work = 200;
1859 while (--tmp_work > 0) {
1860 udelay(1);
1861 tmp8 = RTL_R8 (ChipCmd);
1862 if (!(tmp8 & CmdRxEnb))
1863 break;
1864 }
1865 if (tmp_work <= 0)
1866 printk (KERN_WARNING PFX "rx stop wait too long\n");
1867 /* restart receive */
1868 tmp_work = 200;
1869 while (--tmp_work > 0) {
1870 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1871 udelay(1);
1872 tmp8 = RTL_R8 (ChipCmd);
1873 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1874 break;
1875 }
1876 if (tmp_work <= 0)
1877 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1878
1879 /* and reinitialize all rx related registers */
1880 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1881 /* Must enable Tx/Rx before setting transfer thresholds! */
1882 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1883
1884 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1885 RTL_W32 (RxConfig, tp->rx_config);
1886 tp->cur_rx = 0;
1887
1888 DPRINTK("init buffer addresses\n");
1889
1890 /* Lock Config[01234] and BMCR register writes */
1891 RTL_W8 (Cfg9346, Cfg9346_Lock);
1892
1893 /* init Rx ring buffer DMA address */
1894 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1895
1896 /* A.C.: Reset the multicast list. */
1897 __set_rx_mode (dev);
1898 #endif
1899 }
1900
1901 #if RX_BUF_IDX == 3
1902 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1903 u32 offset, unsigned int size)
1904 {
1905 u32 left = RX_BUF_LEN - offset;
1906
1907 if (size > left) {
1908 memcpy(skb->data, ring + offset, left);
1909 memcpy(skb->data+left, ring, size - left);
1910 } else
1911 memcpy(skb->data, ring + offset, size);
1912 }
1913 #endif
1914
1915 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1916 {
1917 void __iomem *ioaddr = tp->mmio_addr;
1918 u16 status;
1919
1920 status = RTL_R16 (IntrStatus) & RxAckBits;
1921
1922 /* Clear out errors and receive interrupts */
1923 if (likely(status != 0)) {
1924 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1925 tp->stats.rx_errors++;
1926 if (status & RxFIFOOver)
1927 tp->stats.rx_fifo_errors++;
1928 }
1929 RTL_W16_F (IntrStatus, RxAckBits);
1930 }
1931 }
1932
1933 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1934 int budget)
1935 {
1936 void __iomem *ioaddr = tp->mmio_addr;
1937 int received = 0;
1938 unsigned char *rx_ring = tp->rx_ring;
1939 unsigned int cur_rx = tp->cur_rx;
1940 unsigned int rx_size = 0;
1941
1942 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1943 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1944 RTL_R16 (RxBufAddr),
1945 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1946
1947 while (netif_running(dev) && received < budget
1948 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1949 u32 ring_offset = cur_rx % RX_BUF_LEN;
1950 u32 rx_status;
1951 unsigned int pkt_size;
1952 struct sk_buff *skb;
1953
1954 rmb();
1955
1956 /* read size+status of next frame from DMA ring buffer */
1957 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1958 rx_size = rx_status >> 16;
1959 pkt_size = rx_size - 4;
1960
1961 if (netif_msg_rx_status(tp))
1962 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1963 " cur %4.4x.\n", dev->name, rx_status,
1964 rx_size, cur_rx);
1965 #if RTL8139_DEBUG > 2
1966 {
1967 int i;
1968 DPRINTK ("%s: Frame contents ", dev->name);
1969 for (i = 0; i < 70; i++)
1970 printk (" %2.2x",
1971 rx_ring[ring_offset + i]);
1972 printk (".\n");
1973 }
1974 #endif
1975
1976 /* Packet copy from FIFO still in progress.
1977 * Theoretically, this should never happen
1978 * since EarlyRx is disabled.
1979 */
1980 if (unlikely(rx_size == 0xfff0)) {
1981 if (!tp->fifo_copy_timeout)
1982 tp->fifo_copy_timeout = jiffies + 2;
1983 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1984 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1985 rx_size = 0;
1986 goto no_early_rx;
1987 }
1988 if (netif_msg_intr(tp)) {
1989 printk(KERN_DEBUG "%s: fifo copy in progress.",
1990 dev->name);
1991 }
1992 tp->xstats.early_rx++;
1993 break;
1994 }
1995
1996 no_early_rx:
1997 tp->fifo_copy_timeout = 0;
1998
1999 /* If Rx err or invalid rx_size/rx_status received
2000 * (which happens if we get lost in the ring),
2001 * Rx process gets reset, so we abort any further
2002 * Rx processing.
2003 */
2004 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2005 (rx_size < 8) ||
2006 (!(rx_status & RxStatusOK)))) {
2007 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2008 received = -1;
2009 goto out;
2010 }
2011
2012 /* Malloc up new buffer, compatible with net-2e. */
2013 /* Omit the four octet CRC from the length. */
2014
2015 skb = dev_alloc_skb (pkt_size + 2);
2016 if (likely(skb)) {
2017 skb->dev = dev;
2018 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2019 #if RX_BUF_IDX == 3
2020 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2021 #else
2022 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2023 #endif
2024 skb_put (skb, pkt_size);
2025
2026 skb->protocol = eth_type_trans (skb, dev);
2027
2028 dev->last_rx = jiffies;
2029 tp->stats.rx_bytes += pkt_size;
2030 tp->stats.rx_packets++;
2031
2032 netif_receive_skb (skb);
2033 } else {
2034 if (net_ratelimit())
2035 printk (KERN_WARNING
2036 "%s: Memory squeeze, dropping packet.\n",
2037 dev->name);
2038 tp->stats.rx_dropped++;
2039 }
2040 received++;
2041
2042 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2043 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2044
2045 rtl8139_isr_ack(tp);
2046 }
2047
2048 if (unlikely(!received || rx_size == 0xfff0))
2049 rtl8139_isr_ack(tp);
2050
2051 #if RTL8139_DEBUG > 1
2052 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2053 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2054 RTL_R16 (RxBufAddr),
2055 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2056 #endif
2057
2058 tp->cur_rx = cur_rx;
2059
2060 /*
2061 * The receive buffer should be mostly empty.
2062 * Tell NAPI to reenable the Rx irq.
2063 */
2064 if (tp->fifo_copy_timeout)
2065 received = budget;
2066
2067 out:
2068 return received;
2069 }
2070
2071
2072 static void rtl8139_weird_interrupt (struct net_device *dev,
2073 struct rtl8139_private *tp,
2074 void __iomem *ioaddr,
2075 int status, int link_changed)
2076 {
2077 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2078 dev->name, status);
2079
2080 assert (dev != NULL);
2081 assert (tp != NULL);
2082 assert (ioaddr != NULL);
2083
2084 /* Update the error count. */
2085 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2086 RTL_W32 (RxMissed, 0);
2087
2088 if ((status & RxUnderrun) && link_changed &&
2089 (tp->drv_flags & HAS_LNK_CHNG)) {
2090 rtl_check_media(dev, 0);
2091 status &= ~RxUnderrun;
2092 }
2093
2094 if (status & (RxUnderrun | RxErr))
2095 tp->stats.rx_errors++;
2096
2097 if (status & PCSTimeout)
2098 tp->stats.rx_length_errors++;
2099 if (status & RxUnderrun)
2100 tp->stats.rx_fifo_errors++;
2101 if (status & PCIErr) {
2102 u16 pci_cmd_status;
2103 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2104 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2105
2106 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2107 dev->name, pci_cmd_status);
2108 }
2109 }
2110
2111 static int rtl8139_poll(struct net_device *dev, int *budget)
2112 {
2113 struct rtl8139_private *tp = netdev_priv(dev);
2114 void __iomem *ioaddr = tp->mmio_addr;
2115 int orig_budget = min(*budget, dev->quota);
2116 int done = 1;
2117
2118 spin_lock(&tp->rx_lock);
2119 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2120 int work_done;
2121
2122 work_done = rtl8139_rx(dev, tp, orig_budget);
2123 if (likely(work_done > 0)) {
2124 *budget -= work_done;
2125 dev->quota -= work_done;
2126 done = (work_done < orig_budget);
2127 }
2128 }
2129
2130 if (done) {
2131 /*
2132 * Order is important since data can get interrupted
2133 * again when we think we are done.
2134 */
2135 local_irq_disable();
2136 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2137 __netif_rx_complete(dev);
2138 local_irq_enable();
2139 }
2140 spin_unlock(&tp->rx_lock);
2141
2142 return !done;
2143 }
2144
2145 /* The interrupt handler does all of the Rx thread work and cleans up
2146 after the Tx thread. */
2147 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2148 struct pt_regs *regs)
2149 {
2150 struct net_device *dev = (struct net_device *) dev_instance;
2151 struct rtl8139_private *tp = netdev_priv(dev);
2152 void __iomem *ioaddr = tp->mmio_addr;
2153 u16 status, ackstat;
2154 int link_changed = 0; /* avoid bogus "uninit" warning */
2155 int handled = 0;
2156
2157 spin_lock (&tp->lock);
2158 status = RTL_R16 (IntrStatus);
2159
2160 /* shared irq? */
2161 if (unlikely((status & rtl8139_intr_mask) == 0))
2162 goto out;
2163
2164 handled = 1;
2165
2166 /* h/w no longer present (hotplug?) or major error, bail */
2167 if (unlikely(status == 0xFFFF))
2168 goto out;
2169
2170 /* close possible race's with dev_close */
2171 if (unlikely(!netif_running(dev))) {
2172 RTL_W16 (IntrMask, 0);
2173 goto out;
2174 }
2175
2176 /* Acknowledge all of the current interrupt sources ASAP, but
2177 an first get an additional status bit from CSCR. */
2178 if (unlikely(status & RxUnderrun))
2179 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2180
2181 ackstat = status & ~(RxAckBits | TxErr);
2182 if (ackstat)
2183 RTL_W16 (IntrStatus, ackstat);
2184
2185 /* Receive packets are processed by poll routine.
2186 If not running start it now. */
2187 if (status & RxAckBits){
2188 if (netif_rx_schedule_prep(dev)) {
2189 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2190 __netif_rx_schedule (dev);
2191 }
2192 }
2193
2194 /* Check uncommon events with one test. */
2195 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2196 rtl8139_weird_interrupt (dev, tp, ioaddr,
2197 status, link_changed);
2198
2199 if (status & (TxOK | TxErr)) {
2200 rtl8139_tx_interrupt (dev, tp, ioaddr);
2201 if (status & TxErr)
2202 RTL_W16 (IntrStatus, TxErr);
2203 }
2204 out:
2205 spin_unlock (&tp->lock);
2206
2207 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2208 dev->name, RTL_R16 (IntrStatus));
2209 return IRQ_RETVAL(handled);
2210 }
2211
2212 #ifdef CONFIG_NET_POLL_CONTROLLER
2213 /*
2214 * Polling receive - used by netconsole and other diagnostic tools
2215 * to allow network i/o with interrupts disabled.
2216 */
2217 static void rtl8139_poll_controller(struct net_device *dev)
2218 {
2219 disable_irq(dev->irq);
2220 rtl8139_interrupt(dev->irq, dev, NULL);
2221 enable_irq(dev->irq);
2222 }
2223 #endif
2224
2225 static int rtl8139_close (struct net_device *dev)
2226 {
2227 struct rtl8139_private *tp = netdev_priv(dev);
2228 void __iomem *ioaddr = tp->mmio_addr;
2229 unsigned long flags;
2230
2231 netif_stop_queue (dev);
2232
2233 rtl8139_stop_thread(tp);
2234
2235 if (netif_msg_ifdown(tp))
2236 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2237 dev->name, RTL_R16 (IntrStatus));
2238
2239 spin_lock_irqsave (&tp->lock, flags);
2240
2241 /* Stop the chip's Tx and Rx DMA processes. */
2242 RTL_W8 (ChipCmd, 0);
2243
2244 /* Disable interrupts by clearing the interrupt mask. */
2245 RTL_W16 (IntrMask, 0);
2246
2247 /* Update the error counts. */
2248 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2249 RTL_W32 (RxMissed, 0);
2250
2251 spin_unlock_irqrestore (&tp->lock, flags);
2252
2253 synchronize_irq (dev->irq); /* racy, but that's ok here */
2254 free_irq (dev->irq, dev);
2255
2256 rtl8139_tx_clear (tp);
2257
2258 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2259 tp->rx_ring, tp->rx_ring_dma);
2260 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2261 tp->tx_bufs, tp->tx_bufs_dma);
2262 tp->rx_ring = NULL;
2263 tp->tx_bufs = NULL;
2264
2265 /* Green! Put the chip in low-power mode. */
2266 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2267
2268 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2269 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2270
2271 return 0;
2272 }
2273
2274
2275 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2276 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2277 other threads or interrupts aren't messing with the 8139. */
2278 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2279 {
2280 struct rtl8139_private *np = netdev_priv(dev);
2281 void __iomem *ioaddr = np->mmio_addr;
2282
2283 spin_lock_irq(&np->lock);
2284 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2285 u8 cfg3 = RTL_R8 (Config3);
2286 u8 cfg5 = RTL_R8 (Config5);
2287
2288 wol->supported = WAKE_PHY | WAKE_MAGIC
2289 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2290
2291 wol->wolopts = 0;
2292 if (cfg3 & Cfg3_LinkUp)
2293 wol->wolopts |= WAKE_PHY;
2294 if (cfg3 & Cfg3_Magic)
2295 wol->wolopts |= WAKE_MAGIC;
2296 /* (KON)FIXME: See how netdev_set_wol() handles the
2297 following constants. */
2298 if (cfg5 & Cfg5_UWF)
2299 wol->wolopts |= WAKE_UCAST;
2300 if (cfg5 & Cfg5_MWF)
2301 wol->wolopts |= WAKE_MCAST;
2302 if (cfg5 & Cfg5_BWF)
2303 wol->wolopts |= WAKE_BCAST;
2304 }
2305 spin_unlock_irq(&np->lock);
2306 }
2307
2308
2309 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2310 that wol points to kernel memory and other threads or interrupts
2311 aren't messing with the 8139. */
2312 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2313 {
2314 struct rtl8139_private *np = netdev_priv(dev);
2315 void __iomem *ioaddr = np->mmio_addr;
2316 u32 support;
2317 u8 cfg3, cfg5;
2318
2319 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2320 ? (WAKE_PHY | WAKE_MAGIC
2321 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2322 : 0);
2323 if (wol->wolopts & ~support)
2324 return -EINVAL;
2325
2326 spin_lock_irq(&np->lock);
2327 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2328 if (wol->wolopts & WAKE_PHY)
2329 cfg3 |= Cfg3_LinkUp;
2330 if (wol->wolopts & WAKE_MAGIC)
2331 cfg3 |= Cfg3_Magic;
2332 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2333 RTL_W8 (Config3, cfg3);
2334 RTL_W8 (Cfg9346, Cfg9346_Lock);
2335
2336 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2337 /* (KON)FIXME: These are untested. We may have to set the
2338 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2339 documentation. */
2340 if (wol->wolopts & WAKE_UCAST)
2341 cfg5 |= Cfg5_UWF;
2342 if (wol->wolopts & WAKE_MCAST)
2343 cfg5 |= Cfg5_MWF;
2344 if (wol->wolopts & WAKE_BCAST)
2345 cfg5 |= Cfg5_BWF;
2346 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2347 spin_unlock_irq(&np->lock);
2348
2349 return 0;
2350 }
2351
2352 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2353 {
2354 struct rtl8139_private *np = netdev_priv(dev);
2355 strcpy(info->driver, DRV_NAME);
2356 strcpy(info->version, DRV_VERSION);
2357 strcpy(info->bus_info, pci_name(np->pci_dev));
2358 info->regdump_len = np->regs_len;
2359 }
2360
2361 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2362 {
2363 struct rtl8139_private *np = netdev_priv(dev);
2364 spin_lock_irq(&np->lock);
2365 mii_ethtool_gset(&np->mii, cmd);
2366 spin_unlock_irq(&np->lock);
2367 return 0;
2368 }
2369
2370 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2371 {
2372 struct rtl8139_private *np = netdev_priv(dev);
2373 int rc;
2374 spin_lock_irq(&np->lock);
2375 rc = mii_ethtool_sset(&np->mii, cmd);
2376 spin_unlock_irq(&np->lock);
2377 return rc;
2378 }
2379
2380 static int rtl8139_nway_reset(struct net_device *dev)
2381 {
2382 struct rtl8139_private *np = netdev_priv(dev);
2383 return mii_nway_restart(&np->mii);
2384 }
2385
2386 static u32 rtl8139_get_link(struct net_device *dev)
2387 {
2388 struct rtl8139_private *np = netdev_priv(dev);
2389 return mii_link_ok(&np->mii);
2390 }
2391
2392 static u32 rtl8139_get_msglevel(struct net_device *dev)
2393 {
2394 struct rtl8139_private *np = netdev_priv(dev);
2395 return np->msg_enable;
2396 }
2397
2398 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2399 {
2400 struct rtl8139_private *np = netdev_priv(dev);
2401 np->msg_enable = datum;
2402 }
2403
2404 /* TODO: we are too slack to do reg dumping for pio, for now */
2405 #ifdef CONFIG_8139TOO_PIO
2406 #define rtl8139_get_regs_len NULL
2407 #define rtl8139_get_regs NULL
2408 #else
2409 static int rtl8139_get_regs_len(struct net_device *dev)
2410 {
2411 struct rtl8139_private *np = netdev_priv(dev);
2412 return np->regs_len;
2413 }
2414
2415 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2416 {
2417 struct rtl8139_private *np = netdev_priv(dev);
2418
2419 regs->version = RTL_REGS_VER;
2420
2421 spin_lock_irq(&np->lock);
2422 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2423 spin_unlock_irq(&np->lock);
2424 }
2425 #endif /* CONFIG_8139TOO_MMIO */
2426
2427 static int rtl8139_get_stats_count(struct net_device *dev)
2428 {
2429 return RTL_NUM_STATS;
2430 }
2431
2432 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2433 {
2434 struct rtl8139_private *np = netdev_priv(dev);
2435
2436 data[0] = np->xstats.early_rx;
2437 data[1] = np->xstats.tx_buf_mapped;
2438 data[2] = np->xstats.tx_timeouts;
2439 data[3] = np->xstats.rx_lost_in_ring;
2440 }
2441
2442 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2443 {
2444 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2445 }
2446
2447 static struct ethtool_ops rtl8139_ethtool_ops = {
2448 .get_drvinfo = rtl8139_get_drvinfo,
2449 .get_settings = rtl8139_get_settings,
2450 .set_settings = rtl8139_set_settings,
2451 .get_regs_len = rtl8139_get_regs_len,
2452 .get_regs = rtl8139_get_regs,
2453 .nway_reset = rtl8139_nway_reset,
2454 .get_link = rtl8139_get_link,
2455 .get_msglevel = rtl8139_get_msglevel,
2456 .set_msglevel = rtl8139_set_msglevel,
2457 .get_wol = rtl8139_get_wol,
2458 .set_wol = rtl8139_set_wol,
2459 .get_strings = rtl8139_get_strings,
2460 .get_stats_count = rtl8139_get_stats_count,
2461 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2462 .get_perm_addr = ethtool_op_get_perm_addr,
2463 };
2464
2465 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2466 {
2467 struct rtl8139_private *np = netdev_priv(dev);
2468 int rc;
2469
2470 if (!netif_running(dev))
2471 return -EINVAL;
2472
2473 spin_lock_irq(&np->lock);
2474 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2475 spin_unlock_irq(&np->lock);
2476
2477 return rc;
2478 }
2479
2480
2481 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2482 {
2483 struct rtl8139_private *tp = netdev_priv(dev);
2484 void __iomem *ioaddr = tp->mmio_addr;
2485 unsigned long flags;
2486
2487 if (netif_running(dev)) {
2488 spin_lock_irqsave (&tp->lock, flags);
2489 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2490 RTL_W32 (RxMissed, 0);
2491 spin_unlock_irqrestore (&tp->lock, flags);
2492 }
2493
2494 return &tp->stats;
2495 }
2496
2497 /* Set or clear the multicast filter for this adaptor.
2498 This routine is not state sensitive and need not be SMP locked. */
2499
2500 static void __set_rx_mode (struct net_device *dev)
2501 {
2502 struct rtl8139_private *tp = netdev_priv(dev);
2503 void __iomem *ioaddr = tp->mmio_addr;
2504 u32 mc_filter[2]; /* Multicast hash filter */
2505 int i, rx_mode;
2506 u32 tmp;
2507
2508 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2509 dev->name, dev->flags, RTL_R32 (RxConfig));
2510
2511 /* Note: do not reorder, GCC is clever about common statements. */
2512 if (dev->flags & IFF_PROMISC) {
2513 /* Unconditionally log net taps. */
2514 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2515 dev->name);
2516 rx_mode =
2517 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2518 AcceptAllPhys;
2519 mc_filter[1] = mc_filter[0] = 0xffffffff;
2520 } else if ((dev->mc_count > multicast_filter_limit)
2521 || (dev->flags & IFF_ALLMULTI)) {
2522 /* Too many to filter perfectly -- accept all multicasts. */
2523 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2524 mc_filter[1] = mc_filter[0] = 0xffffffff;
2525 } else {
2526 struct dev_mc_list *mclist;
2527 rx_mode = AcceptBroadcast | AcceptMyPhys;
2528 mc_filter[1] = mc_filter[0] = 0;
2529 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2530 i++, mclist = mclist->next) {
2531 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2532
2533 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2534 rx_mode |= AcceptMulticast;
2535 }
2536 }
2537
2538 /* We can safely update without stopping the chip. */
2539 tmp = rtl8139_rx_config | rx_mode;
2540 if (tp->rx_config != tmp) {
2541 RTL_W32_F (RxConfig, tmp);
2542 tp->rx_config = tmp;
2543 }
2544 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2545 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2546 }
2547
2548 static void rtl8139_set_rx_mode (struct net_device *dev)
2549 {
2550 unsigned long flags;
2551 struct rtl8139_private *tp = netdev_priv(dev);
2552
2553 spin_lock_irqsave (&tp->lock, flags);
2554 __set_rx_mode(dev);
2555 spin_unlock_irqrestore (&tp->lock, flags);
2556 }
2557
2558 #ifdef CONFIG_PM
2559
2560 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2561 {
2562 struct net_device *dev = pci_get_drvdata (pdev);
2563 struct rtl8139_private *tp = netdev_priv(dev);
2564 void __iomem *ioaddr = tp->mmio_addr;
2565 unsigned long flags;
2566
2567 pci_save_state (pdev);
2568
2569 if (!netif_running (dev))
2570 return 0;
2571
2572 netif_device_detach (dev);
2573
2574 spin_lock_irqsave (&tp->lock, flags);
2575
2576 /* Disable interrupts, stop Tx and Rx. */
2577 RTL_W16 (IntrMask, 0);
2578 RTL_W8 (ChipCmd, 0);
2579
2580 /* Update the error counts. */
2581 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2582 RTL_W32 (RxMissed, 0);
2583
2584 spin_unlock_irqrestore (&tp->lock, flags);
2585
2586 pci_set_power_state (pdev, PCI_D3hot);
2587
2588 return 0;
2589 }
2590
2591
2592 static int rtl8139_resume (struct pci_dev *pdev)
2593 {
2594 struct net_device *dev = pci_get_drvdata (pdev);
2595
2596 pci_restore_state (pdev);
2597 if (!netif_running (dev))
2598 return 0;
2599 pci_set_power_state (pdev, PCI_D0);
2600 rtl8139_init_ring (dev);
2601 rtl8139_hw_start (dev);
2602 netif_device_attach (dev);
2603 return 0;
2604 }
2605
2606 #endif /* CONFIG_PM */
2607
2608
2609 static struct pci_driver rtl8139_pci_driver = {
2610 .name = DRV_NAME,
2611 .id_table = rtl8139_pci_tbl,
2612 .probe = rtl8139_init_one,
2613 .remove = __devexit_p(rtl8139_remove_one),
2614 #ifdef CONFIG_PM
2615 .suspend = rtl8139_suspend,
2616 .resume = rtl8139_resume,
2617 #endif /* CONFIG_PM */
2618 };
2619
2620
2621 static int __init rtl8139_init_module (void)
2622 {
2623 /* when we're a module, we always print a version message,
2624 * even if no 8139 board is found.
2625 */
2626 #ifdef MODULE
2627 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2628 #endif
2629
2630 return pci_module_init (&rtl8139_pci_driver);
2631 }
2632
2633
2634 static void __exit rtl8139_cleanup_module (void)
2635 {
2636 pci_unregister_driver (&rtl8139_pci_driver);
2637 }
2638
2639
2640 module_init(rtl8139_init_module);
2641 module_exit(rtl8139_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree