arch/arm/plat-omap/dmtimer.c

   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * OMAP2 support by Juha Yrjola
   8  * API improvements and OMAP2 clock framework support by Timo Teras
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  * You should have received a copy of the  GNU General Public License along
  25  * with this program; if not, write  to the Free Software Foundation, Inc.,
  26  * 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/init.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/errno.h>
  32 #include <linux/list.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <asm/hardware.h>
  36 #include <asm/arch/dmtimer.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/irqs.h>
  39
  40 /* register offsets */
  41 #define OMAP_TIMER_ID_REG               0x00
  42 #define OMAP_TIMER_OCP_CFG_REG          0x10
  43 #define OMAP_TIMER_SYS_STAT_REG         0x14
  44 #define OMAP_TIMER_STAT_REG             0x18
  45 #define OMAP_TIMER_INT_EN_REG           0x1c
  46 #define OMAP_TIMER_WAKEUP_EN_REG        0x20
  47 #define OMAP_TIMER_CTRL_REG             0x24
  48 #define OMAP_TIMER_COUNTER_REG          0x28
  49 #define OMAP_TIMER_LOAD_REG             0x2c
  50 #define OMAP_TIMER_TRIGGER_REG          0x30
  51 #define OMAP_TIMER_WRITE_PEND_REG       0x34
  52 #define OMAP_TIMER_MATCH_REG            0x38
  53 #define OMAP_TIMER_CAPTURE_REG          0x3c
  54 #define OMAP_TIMER_IF_CTRL_REG          0x40
  55
  56 /* timer control reg bits */
  57 #define OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
  58 #define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
  59 #define OMAP_TIMER_CTRL_PT              (1 << 12)
  60 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
  61 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
  62 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
  63 #define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
  64 #define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
  65 #define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
  66 #define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
  67 #define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
  68 #define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
  69
  70 struct omap_dm_timer {
  71         unsigned long phys_base;
  72         int irq;
  73 #ifdef CONFIG_ARCH_OMAP2
  74         struct clk *iclk, *fclk;
  75 #endif
  76         void __iomem *io_base;
  77         unsigned reserved:1;
  78         unsigned enabled:1;
  79 };
  80
  81 #ifdef CONFIG_ARCH_OMAP1
  82
  83 #define omap_dm_clk_enable(x)
  84 #define omap_dm_clk_disable(x)
  85
  86 static struct omap_dm_timer dm_timers[] = {
  87         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
  88         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
  89         { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
  90         { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
  91         { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
  92         { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
  93         { .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
  94         { .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
  95 };
  96
  97 #elif defined(CONFIG_ARCH_OMAP2)
  98
  99 #define omap_dm_clk_enable(x) clk_enable(x)
 100 #define omap_dm_clk_disable(x) clk_disable(x)
 101
 102 static struct omap_dm_timer dm_timers[] = {
 103         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
 104         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
 105         { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
 106         { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
 107         { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
 108         { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
 109         { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
 110         { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
 111         { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
 112         { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
 113         { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
 114         { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
 115 };
 116
 117 static const char *dm_source_names[] = {
 118         "sys_ck",
 119         "func_32k_ck",
 120         "alt_ck"
 121 };
 122
 123 static struct clk *dm_source_clocks[3];
 124
 125 #else
 126
 127 #error OMAP architecture not supported!
 128
 129 #endif
 130
 131 static const int dm_timer_count = ARRAY_SIZE(dm_timers);
 132 static spinlock_t dm_timer_lock;
 133
 134 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
 135 {
 136         return readl(timer->io_base + reg);
 137 }
 138
 139 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
 140 {
 141         writel(value, timer->io_base + reg);
 142         while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
 143                 ;
 144 }
 145
 146 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 147 {
 148         int c;
 149
 150         c = 0;
 151         while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
 152                 c++;
 153                 if (c > 100000) {
 154                         printk(KERN_ERR "Timer failed to reset\n");
 155                         return;
 156                 }
 157         }
 158 }
 159
 160 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 161 {
 162         u32 l;
 163
 164         if (timer != &dm_timers[0]) {
 165                 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 166                 omap_dm_timer_wait_for_reset(timer);
 167         }
 168         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 169
 170         /* Set to smart-idle mode */
 171         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
 172         l |= 0x02 << 3;
 173         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
 174 }
 175
 176 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
 177 {
 178         omap_dm_timer_enable(timer);
 179         omap_dm_timer_reset(timer);
 180 }
 181
 182 struct omap_dm_timer *omap_dm_timer_request(void)
 183 {
 184         struct omap_dm_timer *timer = NULL;
 185         unsigned long flags;
 186         int i;
 187
 188         spin_lock_irqsave(&dm_timer_lock, flags);
 189         for (i = 0; i < dm_timer_count; i++) {
 190                 if (dm_timers[i].reserved)
 191                         continue;
 192
 193                 timer = &dm_timers[i];
 194                 timer->reserved = 1;
 195                 break;
 196         }
 197         spin_unlock_irqrestore(&dm_timer_lock, flags);
 198
 199         if (timer != NULL)
 200                 omap_dm_timer_prepare(timer);
 201
 202         return timer;
 203 }
 204
 205 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 206 {
 207         struct omap_dm_timer *timer;
 208         unsigned long flags;
 209
 210         spin_lock_irqsave(&dm_timer_lock, flags);
 211         if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
 212                 spin_unlock_irqrestore(&dm_timer_lock, flags);
 213                 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
 214                        __FILE__, __LINE__, __FUNCTION__, id);
 215                 dump_stack();
 216                 return NULL;
 217         }
 218
 219         timer = &dm_timers[id-1];
 220         timer->reserved = 1;
 221         spin_unlock_irqrestore(&dm_timer_lock, flags);
 222
 223         omap_dm_timer_prepare(timer);
 224
 225         return timer;
 226 }
 227
 228 void omap_dm_timer_free(struct omap_dm_timer *timer)
 229 {
 230         omap_dm_timer_enable(timer);
 231         omap_dm_timer_reset(timer);
 232         omap_dm_timer_disable(timer);
 233
 234         WARN_ON(!timer->reserved);
 235         timer->reserved = 0;
 236 }
 237
 238 void omap_dm_timer_enable(struct omap_dm_timer *timer)
 239 {
 240         if (timer->enabled)
 241                 return;
 242
 243         omap_dm_clk_enable(timer->fclk);
 244         omap_dm_clk_enable(timer->iclk);
 245
 246         timer->enabled = 1;
 247 }
 248
 249 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 250 {
 251         if (!timer->enabled)
 252                 return;
 253
 254         omap_dm_clk_disable(timer->iclk);
 255         omap_dm_clk_disable(timer->fclk);
 256
 257         timer->enabled = 0;
 258 }
 259
 260 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 261 {
 262         return timer->irq;
 263 }
 264
 265 #if defined(CONFIG_ARCH_OMAP1)
 266
 267 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 268 {
 269         BUG();
 270 }
 271
 272 /**
 273  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 274  * @inputmask: current value of idlect mask
 275  */
 276 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 277 {
 278         int i;
 279
 280         /* If ARMXOR cannot be idled this function call is unnecessary */
 281         if (!(inputmask & (1 << 1)))
 282                 return inputmask;
 283
 284         /* If any active timer is using ARMXOR return modified mask */
 285         for (i = 0; i < dm_timer_count; i++) {
 286                 u32 l;
 287
 288                 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
 289                 if (l & OMAP_TIMER_CTRL_ST) {
 290                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 291                                 inputmask &= ~(1 << 1);
 292                         else
 293                                 inputmask &= ~(1 << 2);
 294                 }
 295         }
 296
 297         return inputmask;
 298 }
 299
 300 #elif defined(CONFIG_ARCH_OMAP2)
 301
 302 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 303 {
 304         return timer->fclk;
 305 }
 306
 307 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 308 {
 309         BUG();
 310 }
 311
 312 #endif
 313
 314 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
 315 {
 316         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 317 }
 318
 319 void omap_dm_timer_start(struct omap_dm_timer *timer)
 320 {
 321         u32 l;
 322
 323         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 324         if (!(l & OMAP_TIMER_CTRL_ST)) {
 325                 l |= OMAP_TIMER_CTRL_ST;
 326                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 327         }
 328 }
 329
 330 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 331 {
 332         u32 l;
 333
 334         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 335         if (l & OMAP_TIMER_CTRL_ST) {
 336                 l &= ~0x1;
 337                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 338         }
 339 }
 340
 341 #ifdef CONFIG_ARCH_OMAP1
 342
 343 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 344 {
 345         int n = (timer - dm_timers) << 1;
 346         u32 l;
 347
 348         l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
 349         l |= source << n;
 350         omap_writel(l, MOD_CONF_CTRL_1);
 351 }
 352
 353 #else
 354
 355 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 356 {
 357         if (source < 0 || source >= 3)
 358                 return;
 359
 360         clk_disable(timer->fclk);
 361         clk_set_parent(timer->fclk, dm_source_clocks[source]);
 362         clk_enable(timer->fclk);
 363
 364         /* When the functional clock disappears, too quick writes seem to
 365          * cause an abort. */
 366         __delay(15000);
 367 }
 368
 369 #endif
 370
 371 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 372                             unsigned int load)
 373 {
 374         u32 l;
 375
 376         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 377         if (autoreload)
 378                 l |= OMAP_TIMER_CTRL_AR;
 379         else
 380                 l &= ~OMAP_TIMER_CTRL_AR;
 381         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 382         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 383         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 384 }
 385
 386 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 387                              unsigned int match)
 388 {
 389         u32 l;
 390
 391         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 392         if (enable)
 393                 l |= OMAP_TIMER_CTRL_CE;
 394         else
 395                 l &= ~OMAP_TIMER_CTRL_CE;
 396         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 397         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 398 }
 399
 400
 401 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 402                            int toggle, int trigger)
 403 {
 404         u32 l;
 405
 406         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 407         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 408                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 409         if (def_on)
 410                 l |= OMAP_TIMER_CTRL_SCPWM;
 411         if (toggle)
 412                 l |= OMAP_TIMER_CTRL_PT;
 413         l |= trigger << 10;
 414         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 415 }
 416
 417 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 418 {
 419         u32 l;
 420
 421         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 422         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 423         if (prescaler >= 0x00 && prescaler <= 0x07) {
 424                 l |= OMAP_TIMER_CTRL_PRE;
 425                 l |= prescaler << 2;
 426         }
 427         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 428 }
 429
 430 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 431                                   unsigned int value)
 432 {
 433         omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
 434 }
 435
 436 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 437 {
 438         unsigned int l;
 439
 440         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
 441
 442         return l;
 443 }
 444
 445 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 446 {
 447         omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
 448 }
 449
 450 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 451 {
 452         unsigned int l;
 453
 454         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
 455
 456         return l;
 457 }
 458
 459 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 460 {
 461         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 462 }
 463
 464 int omap_dm_timers_active(void)
 465 {
 466         int i;
 467
 468         for (i = 0; i < dm_timer_count; i++) {
 469                 struct omap_dm_timer *timer;
 470
 471                 timer = &dm_timers[i];
 472
 473                 if (!timer->enabled)
 474                         continue;
 475
 476                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 477                     OMAP_TIMER_CTRL_ST) {
 478                         return 1;
 479                 }
 480         }
 481         return 0;
 482 }
 483
 484 int omap_dm_timer_init(void)
 485 {
 486         struct omap_dm_timer *timer;
 487         int i;
 488
 489         if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
 490                 return -ENODEV;
 491
 492         spin_lock_init(&dm_timer_lock);
 493 #ifdef CONFIG_ARCH_OMAP2
 494         for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
 495                 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
 496                 BUG_ON(dm_source_clocks[i] == NULL);
 497         }
 498 #endif
 499
 500         for (i = 0; i < dm_timer_count; i++) {
 501 #ifdef CONFIG_ARCH_OMAP2
 502                 char clk_name[16];
 503 #endif
 504
 505                 timer = &dm_timers[i];
 506                 timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
 507 #ifdef CONFIG_ARCH_OMAP2
 508                 sprintf(clk_name, "gpt%d_ick", i + 1);
 509                 timer->iclk = clk_get(NULL, clk_name);
 510                 sprintf(clk_name, "gpt%d_fck", i + 1);
 511                 timer->fclk = clk_get(NULL, clk_name);
 512 #endif
 513         }
 514
 515         return 0;
 516 }