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ixgb: fix unload race with timers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / mv643xx_eth.c
blob83a877f3a553ee94611dced9e87d28f2222aecaf
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
53 #include <asm/io.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
56
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.1";
59
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
63
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66 #else
67 #define MAX_DESCS_PER_SKB 1
68 #endif
69
70 /*
71 * Registers shared between all ports.
72 */
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
80
81 /*
82 * Per-port registers.
83 */
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
96 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
97 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
98 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
99 #define INT_TX_END 0x07f80000
100 #define INT_RX 0x0007fbfc
101 #define INT_EXT 0x00000002
102 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
103 #define INT_EXT_LINK 0x00100000
104 #define INT_EXT_PHY 0x00010000
105 #define INT_EXT_TX_ERROR_0 0x00000100
106 #define INT_EXT_TX_0 0x00000001
107 #define INT_EXT_TX 0x0000ffff
108 #define INT_MASK(p) (0x0468 + ((p) << 10))
109 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
110 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
111 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
112 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
113 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
114 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
115 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
116 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
117 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
118 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
119 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
120 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
121 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
122 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
123 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
124 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
125
126
127 /*
128 * SDMA configuration register.
129 */
130 #define RX_BURST_SIZE_4_64BIT (2 << 1)
131 #define BLM_RX_NO_SWAP (1 << 4)
132 #define BLM_TX_NO_SWAP (1 << 5)
133 #define TX_BURST_SIZE_4_64BIT (2 << 22)
134
135 #if defined(__BIG_ENDIAN)
136 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
137 RX_BURST_SIZE_4_64BIT | \
138 TX_BURST_SIZE_4_64BIT
139 #elif defined(__LITTLE_ENDIAN)
140 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
141 RX_BURST_SIZE_4_64BIT | \
142 BLM_RX_NO_SWAP | \
143 BLM_TX_NO_SWAP | \
144 TX_BURST_SIZE_4_64BIT
145 #else
146 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
147 #endif
148
149
150 /*
151 * Port serial control register.
152 */
153 #define SET_MII_SPEED_TO_100 (1 << 24)
154 #define SET_GMII_SPEED_TO_1000 (1 << 23)
155 #define SET_FULL_DUPLEX_MODE (1 << 21)
156 #define MAX_RX_PACKET_1522BYTE (1 << 17)
157 #define MAX_RX_PACKET_9700BYTE (5 << 17)
158 #define MAX_RX_PACKET_MASK (7 << 17)
159 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
160 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
161 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
162 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
163 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
164 #define FORCE_LINK_PASS (1 << 1)
165 #define SERIAL_PORT_ENABLE (1 << 0)
166
167 #define DEFAULT_RX_QUEUE_SIZE 400
168 #define DEFAULT_TX_QUEUE_SIZE 800
169
170
171 /*
172 * RX/TX descriptors.
173 */
174 #if defined(__BIG_ENDIAN)
175 struct rx_desc {
176 u16 byte_cnt; /* Descriptor buffer byte count */
177 u16 buf_size; /* Buffer size */
178 u32 cmd_sts; /* Descriptor command status */
179 u32 next_desc_ptr; /* Next descriptor pointer */
180 u32 buf_ptr; /* Descriptor buffer pointer */
181 };
182
183 struct tx_desc {
184 u16 byte_cnt; /* buffer byte count */
185 u16 l4i_chk; /* CPU provided TCP checksum */
186 u32 cmd_sts; /* Command/status field */
187 u32 next_desc_ptr; /* Pointer to next descriptor */
188 u32 buf_ptr; /* pointer to buffer for this descriptor*/
189 };
190 #elif defined(__LITTLE_ENDIAN)
191 struct rx_desc {
192 u32 cmd_sts; /* Descriptor command status */
193 u16 buf_size; /* Buffer size */
194 u16 byte_cnt; /* Descriptor buffer byte count */
195 u32 buf_ptr; /* Descriptor buffer pointer */
196 u32 next_desc_ptr; /* Next descriptor pointer */
197 };
198
199 struct tx_desc {
200 u32 cmd_sts; /* Command/status field */
201 u16 l4i_chk; /* CPU provided TCP checksum */
202 u16 byte_cnt; /* buffer byte count */
203 u32 buf_ptr; /* pointer to buffer for this descriptor*/
204 u32 next_desc_ptr; /* Pointer to next descriptor */
205 };
206 #else
207 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
208 #endif
209
210 /* RX & TX descriptor command */
211 #define BUFFER_OWNED_BY_DMA 0x80000000
212
213 /* RX & TX descriptor status */
214 #define ERROR_SUMMARY 0x00000001
215
216 /* RX descriptor status */
217 #define LAYER_4_CHECKSUM_OK 0x40000000
218 #define RX_ENABLE_INTERRUPT 0x20000000
219 #define RX_FIRST_DESC 0x08000000
220 #define RX_LAST_DESC 0x04000000
221
222 /* TX descriptor command */
223 #define TX_ENABLE_INTERRUPT 0x00800000
224 #define GEN_CRC 0x00400000
225 #define TX_FIRST_DESC 0x00200000
226 #define TX_LAST_DESC 0x00100000
227 #define ZERO_PADDING 0x00080000
228 #define GEN_IP_V4_CHECKSUM 0x00040000
229 #define GEN_TCP_UDP_CHECKSUM 0x00020000
230 #define UDP_FRAME 0x00010000
231
232 #define TX_IHL_SHIFT 11
233
234
235 /* global *******************************************************************/
236 struct mv643xx_eth_shared_private {
237 /*
238 * Ethernet controller base address.
239 */
240 void __iomem *base;
241
242 /*
243 * Protects access to SMI_REG, which is shared between ports.
244 */
245 spinlock_t phy_lock;
246
247 /*
248 * Per-port MBUS window access register value.
249 */
250 u32 win_protect;
251
252 /*
253 * Hardware-specific parameters.
254 */
255 unsigned int t_clk;
256 int extended_rx_coal_limit;
257 int tx_bw_control_moved;
258 };
259
260
261 /* per-port *****************************************************************/
262 struct mib_counters {
263 u64 good_octets_received;
264 u32 bad_octets_received;
265 u32 internal_mac_transmit_err;
266 u32 good_frames_received;
267 u32 bad_frames_received;
268 u32 broadcast_frames_received;
269 u32 multicast_frames_received;
270 u32 frames_64_octets;
271 u32 frames_65_to_127_octets;
272 u32 frames_128_to_255_octets;
273 u32 frames_256_to_511_octets;
274 u32 frames_512_to_1023_octets;
275 u32 frames_1024_to_max_octets;
276 u64 good_octets_sent;
277 u32 good_frames_sent;
278 u32 excessive_collision;
279 u32 multicast_frames_sent;
280 u32 broadcast_frames_sent;
281 u32 unrec_mac_control_received;
282 u32 fc_sent;
283 u32 good_fc_received;
284 u32 bad_fc_received;
285 u32 undersize_received;
286 u32 fragments_received;
287 u32 oversize_received;
288 u32 jabber_received;
289 u32 mac_receive_error;
290 u32 bad_crc_event;
291 u32 collision;
292 u32 late_collision;
293 };
294
295 struct rx_queue {
296 int index;
297
298 int rx_ring_size;
299
300 int rx_desc_count;
301 int rx_curr_desc;
302 int rx_used_desc;
303
304 struct rx_desc *rx_desc_area;
305 dma_addr_t rx_desc_dma;
306 int rx_desc_area_size;
307 struct sk_buff **rx_skb;
308
309 struct timer_list rx_oom;
310 };
311
312 struct tx_queue {
313 int index;
314
315 int tx_ring_size;
316
317 int tx_desc_count;
318 int tx_curr_desc;
319 int tx_used_desc;
320
321 struct tx_desc *tx_desc_area;
322 dma_addr_t tx_desc_dma;
323 int tx_desc_area_size;
324 struct sk_buff **tx_skb;
325 };
326
327 struct mv643xx_eth_private {
328 struct mv643xx_eth_shared_private *shared;
329 int port_num;
330
331 struct net_device *dev;
332
333 struct mv643xx_eth_shared_private *shared_smi;
334 int phy_addr;
335
336 spinlock_t lock;
337
338 struct mib_counters mib_counters;
339 struct work_struct tx_timeout_task;
340 struct mii_if_info mii;
341
342 /*
343 * RX state.
344 */
345 int default_rx_ring_size;
346 unsigned long rx_desc_sram_addr;
347 int rx_desc_sram_size;
348 u8 rxq_mask;
349 int rxq_primary;
350 struct napi_struct napi;
351 struct rx_queue rxq[8];
352
353 /*
354 * TX state.
355 */
356 int default_tx_ring_size;
357 unsigned long tx_desc_sram_addr;
358 int tx_desc_sram_size;
359 u8 txq_mask;
360 int txq_primary;
361 struct tx_queue txq[8];
362 #ifdef MV643XX_ETH_TX_FAST_REFILL
363 int tx_clean_threshold;
364 #endif
365 };
366
367
368 /* port register accessors **************************************************/
369 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
370 {
371 return readl(mp->shared->base + offset);
372 }
373
374 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
375 {
376 writel(data, mp->shared->base + offset);
377 }
378
379
380 /* rxq/txq helper functions *************************************************/
381 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
382 {
383 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
384 }
385
386 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
387 {
388 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
389 }
390
391 static void rxq_enable(struct rx_queue *rxq)
392 {
393 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
394 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
395 }
396
397 static void rxq_disable(struct rx_queue *rxq)
398 {
399 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
400 u8 mask = 1 << rxq->index;
401
402 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
403 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
404 udelay(10);
405 }
406
407 static void txq_enable(struct tx_queue *txq)
408 {
409 struct mv643xx_eth_private *mp = txq_to_mp(txq);
410 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
411 }
412
413 static void txq_disable(struct tx_queue *txq)
414 {
415 struct mv643xx_eth_private *mp = txq_to_mp(txq);
416 u8 mask = 1 << txq->index;
417
418 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
419 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
420 udelay(10);
421 }
422
423 static void __txq_maybe_wake(struct tx_queue *txq)
424 {
425 struct mv643xx_eth_private *mp = txq_to_mp(txq);
426
427 /*
428 * netif_{stop,wake}_queue() flow control only applies to
429 * the primary queue.
430 */
431 BUG_ON(txq->index != mp->txq_primary);
432
433 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
434 netif_wake_queue(mp->dev);
435 }
436
437
438 /* rx ***********************************************************************/
439 static void txq_reclaim(struct tx_queue *txq, int force);
440
441 static void rxq_refill(struct rx_queue *rxq)
442 {
443 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
444 unsigned long flags;
445
446 spin_lock_irqsave(&mp->lock, flags);
447
448 while (rxq->rx_desc_count < rxq->rx_ring_size) {
449 int skb_size;
450 struct sk_buff *skb;
451 int unaligned;
452 int rx;
453
454 /*
455 * Reserve 2+14 bytes for an ethernet header (the
456 * hardware automatically prepends 2 bytes of dummy
457 * data to each received packet), 4 bytes for a VLAN
458 * header, and 4 bytes for the trailing FCS -- 24
459 * bytes total.
460 */
461 skb_size = mp->dev->mtu + 24;
462
463 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
464 if (skb == NULL)
465 break;
466
467 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
468 if (unaligned)
469 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
470
471 rxq->rx_desc_count++;
472 rx = rxq->rx_used_desc;
473 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
474
475 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
476 skb_size, DMA_FROM_DEVICE);
477 rxq->rx_desc_area[rx].buf_size = skb_size;
478 rxq->rx_skb[rx] = skb;
479 wmb();
480 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
481 RX_ENABLE_INTERRUPT;
482 wmb();
483
484 /*
485 * The hardware automatically prepends 2 bytes of
486 * dummy data to each received packet, so that the
487 * IP header ends up 16-byte aligned.
488 */
489 skb_reserve(skb, 2);
490 }
491
492 if (rxq->rx_desc_count != rxq->rx_ring_size) {
493 rxq->rx_oom.expires = jiffies + (HZ / 10);
494 add_timer(&rxq->rx_oom);
495 }
496
497 spin_unlock_irqrestore(&mp->lock, flags);
498 }
499
500 static inline void rxq_refill_timer_wrapper(unsigned long data)
501 {
502 rxq_refill((struct rx_queue *)data);
503 }
504
505 static int rxq_process(struct rx_queue *rxq, int budget)
506 {
507 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
508 struct net_device_stats *stats = &mp->dev->stats;
509 int rx;
510
511 rx = 0;
512 while (rx < budget) {
513 struct rx_desc *rx_desc;
514 unsigned int cmd_sts;
515 struct sk_buff *skb;
516 unsigned long flags;
517
518 spin_lock_irqsave(&mp->lock, flags);
519
520 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
521
522 cmd_sts = rx_desc->cmd_sts;
523 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
524 spin_unlock_irqrestore(&mp->lock, flags);
525 break;
526 }
527 rmb();
528
529 skb = rxq->rx_skb[rxq->rx_curr_desc];
530 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
531
532 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
533
534 spin_unlock_irqrestore(&mp->lock, flags);
535
536 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
537 mp->dev->mtu + 24, DMA_FROM_DEVICE);
538 rxq->rx_desc_count--;
539 rx++;
540
541 /*
542 * Update statistics.
543 *
544 * Note that the descriptor byte count includes 2 dummy
545 * bytes automatically inserted by the hardware at the
546 * start of the packet (which we don't count), and a 4
547 * byte CRC at the end of the packet (which we do count).
548 */
549 stats->rx_packets++;
550 stats->rx_bytes += rx_desc->byte_cnt - 2;
551
552 /*
553 * In case we received a packet without first / last bits
554 * on, or the error summary bit is set, the packet needs
555 * to be dropped.
556 */
557 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
558 (RX_FIRST_DESC | RX_LAST_DESC))
559 || (cmd_sts & ERROR_SUMMARY)) {
560 stats->rx_dropped++;
561
562 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
563 (RX_FIRST_DESC | RX_LAST_DESC)) {
564 if (net_ratelimit())
565 dev_printk(KERN_ERR, &mp->dev->dev,
566 "received packet spanning "
567 "multiple descriptors\n");
568 }
569
570 if (cmd_sts & ERROR_SUMMARY)
571 stats->rx_errors++;
572
573 dev_kfree_skb_irq(skb);
574 } else {
575 /*
576 * The -4 is for the CRC in the trailer of the
577 * received packet
578 */
579 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
580
581 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
582 skb->ip_summed = CHECKSUM_UNNECESSARY;
583 skb->csum = htons(
584 (cmd_sts & 0x0007fff8) >> 3);
585 }
586 skb->protocol = eth_type_trans(skb, mp->dev);
587 #ifdef MV643XX_ETH_NAPI
588 netif_receive_skb(skb);
589 #else
590 netif_rx(skb);
591 #endif
592 }
593
594 mp->dev->last_rx = jiffies;
595 }
596
597 rxq_refill(rxq);
598
599 return rx;
600 }
601
602 #ifdef MV643XX_ETH_NAPI
603 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
604 {
605 struct mv643xx_eth_private *mp;
606 int rx;
607 int i;
608
609 mp = container_of(napi, struct mv643xx_eth_private, napi);
610
611 #ifdef MV643XX_ETH_TX_FAST_REFILL
612 if (++mp->tx_clean_threshold > 5) {
613 mp->tx_clean_threshold = 0;
614 for (i = 0; i < 8; i++)
615 if (mp->txq_mask & (1 << i))
616 txq_reclaim(mp->txq + i, 0);
617 }
618 #endif
619
620 rx = 0;
621 for (i = 7; rx < budget && i >= 0; i--)
622 if (mp->rxq_mask & (1 << i))
623 rx += rxq_process(mp->rxq + i, budget - rx);
624
625 if (rx < budget) {
626 netif_rx_complete(mp->dev, napi);
627 wrl(mp, INT_CAUSE(mp->port_num), 0);
628 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
629 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
630 }
631
632 return rx;
633 }
634 #endif
635
636
637 /* tx ***********************************************************************/
638 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
639 {
640 int frag;
641
642 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
643 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
644 if (fragp->size <= 8 && fragp->page_offset & 7)
645 return 1;
646 }
647
648 return 0;
649 }
650
651 static int txq_alloc_desc_index(struct tx_queue *txq)
652 {
653 int tx_desc_curr;
654
655 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
656
657 tx_desc_curr = txq->tx_curr_desc;
658 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
659
660 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
661
662 return tx_desc_curr;
663 }
664
665 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
666 {
667 int nr_frags = skb_shinfo(skb)->nr_frags;
668 int frag;
669
670 for (frag = 0; frag < nr_frags; frag++) {
671 skb_frag_t *this_frag;
672 int tx_index;
673 struct tx_desc *desc;
674
675 this_frag = &skb_shinfo(skb)->frags[frag];
676 tx_index = txq_alloc_desc_index(txq);
677 desc = &txq->tx_desc_area[tx_index];
678
679 /*
680 * The last fragment will generate an interrupt
681 * which will free the skb on TX completion.
682 */
683 if (frag == nr_frags - 1) {
684 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
685 ZERO_PADDING | TX_LAST_DESC |
686 TX_ENABLE_INTERRUPT;
687 txq->tx_skb[tx_index] = skb;
688 } else {
689 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
690 txq->tx_skb[tx_index] = NULL;
691 }
692
693 desc->l4i_chk = 0;
694 desc->byte_cnt = this_frag->size;
695 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
696 this_frag->page_offset,
697 this_frag->size,
698 DMA_TO_DEVICE);
699 }
700 }
701
702 static inline __be16 sum16_as_be(__sum16 sum)
703 {
704 return (__force __be16)sum;
705 }
706
707 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
708 {
709 int nr_frags = skb_shinfo(skb)->nr_frags;
710 int tx_index;
711 struct tx_desc *desc;
712 u32 cmd_sts;
713 int length;
714
715 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
716
717 tx_index = txq_alloc_desc_index(txq);
718 desc = &txq->tx_desc_area[tx_index];
719
720 if (nr_frags) {
721 txq_submit_frag_skb(txq, skb);
722
723 length = skb_headlen(skb);
724 txq->tx_skb[tx_index] = NULL;
725 } else {
726 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
727 length = skb->len;
728 txq->tx_skb[tx_index] = skb;
729 }
730
731 desc->byte_cnt = length;
732 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
733
734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
735 BUG_ON(skb->protocol != htons(ETH_P_IP));
736
737 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
738 GEN_IP_V4_CHECKSUM |
739 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
740
741 switch (ip_hdr(skb)->protocol) {
742 case IPPROTO_UDP:
743 cmd_sts |= UDP_FRAME;
744 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
745 break;
746 case IPPROTO_TCP:
747 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
748 break;
749 default:
750 BUG();
751 }
752 } else {
753 /* Errata BTS #50, IHL must be 5 if no HW checksum */
754 cmd_sts |= 5 << TX_IHL_SHIFT;
755 desc->l4i_chk = 0;
756 }
757
758 /* ensure all other descriptors are written before first cmd_sts */
759 wmb();
760 desc->cmd_sts = cmd_sts;
761
762 /* ensure all descriptors are written before poking hardware */
763 wmb();
764 txq_enable(txq);
765
766 txq->tx_desc_count += nr_frags + 1;
767 }
768
769 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
770 {
771 struct mv643xx_eth_private *mp = netdev_priv(dev);
772 struct net_device_stats *stats = &dev->stats;
773 struct tx_queue *txq;
774 unsigned long flags;
775
776 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
777 stats->tx_dropped++;
778 dev_printk(KERN_DEBUG, &dev->dev,
779 "failed to linearize skb with tiny "
780 "unaligned fragment\n");
781 return NETDEV_TX_BUSY;
782 }
783
784 spin_lock_irqsave(&mp->lock, flags);
785
786 txq = mp->txq + mp->txq_primary;
787
788 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
789 spin_unlock_irqrestore(&mp->lock, flags);
790 if (txq->index == mp->txq_primary && net_ratelimit())
791 dev_printk(KERN_ERR, &dev->dev,
792 "primary tx queue full?!\n");
793 kfree_skb(skb);
794 return NETDEV_TX_OK;
795 }
796
797 txq_submit_skb(txq, skb);
798 stats->tx_bytes += skb->len;
799 stats->tx_packets++;
800 dev->trans_start = jiffies;
801
802 if (txq->index == mp->txq_primary) {
803 int entries_left;
804
805 entries_left = txq->tx_ring_size - txq->tx_desc_count;
806 if (entries_left < MAX_DESCS_PER_SKB)
807 netif_stop_queue(dev);
808 }
809
810 spin_unlock_irqrestore(&mp->lock, flags);
811
812 return NETDEV_TX_OK;
813 }
814
815
816 /* tx rate control **********************************************************/
817 /*
818 * Set total maximum TX rate (shared by all TX queues for this port)
819 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
820 */
821 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
822 {
823 int token_rate;
824 int mtu;
825 int bucket_size;
826
827 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
828 if (token_rate > 1023)
829 token_rate = 1023;
830
831 mtu = (mp->dev->mtu + 255) >> 8;
832 if (mtu > 63)
833 mtu = 63;
834
835 bucket_size = (burst + 255) >> 8;
836 if (bucket_size > 65535)
837 bucket_size = 65535;
838
839 if (mp->shared->tx_bw_control_moved) {
840 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
841 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
842 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
843 } else {
844 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
845 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
846 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
847 }
848 }
849
850 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
851 {
852 struct mv643xx_eth_private *mp = txq_to_mp(txq);
853 int token_rate;
854 int bucket_size;
855
856 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
857 if (token_rate > 1023)
858 token_rate = 1023;
859
860 bucket_size = (burst + 255) >> 8;
861 if (bucket_size > 65535)
862 bucket_size = 65535;
863
864 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
865 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
866 (bucket_size << 10) | token_rate);
867 }
868
869 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
870 {
871 struct mv643xx_eth_private *mp = txq_to_mp(txq);
872 int off;
873 u32 val;
874
875 /*
876 * Turn on fixed priority mode.
877 */
878 if (mp->shared->tx_bw_control_moved)
879 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
880 else
881 off = TXQ_FIX_PRIO_CONF(mp->port_num);
882
883 val = rdl(mp, off);
884 val |= 1 << txq->index;
885 wrl(mp, off, val);
886 }
887
888 static void txq_set_wrr(struct tx_queue *txq, int weight)
889 {
890 struct mv643xx_eth_private *mp = txq_to_mp(txq);
891 int off;
892 u32 val;
893
894 /*
895 * Turn off fixed priority mode.
896 */
897 if (mp->shared->tx_bw_control_moved)
898 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
899 else
900 off = TXQ_FIX_PRIO_CONF(mp->port_num);
901
902 val = rdl(mp, off);
903 val &= ~(1 << txq->index);
904 wrl(mp, off, val);
905
906 /*
907 * Configure WRR weight for this queue.
908 */
909 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
910
911 val = rdl(mp, off);
912 val = (val & ~0xff) | (weight & 0xff);
913 wrl(mp, off, val);
914 }
915
916
917 /* mii management interface *************************************************/
918 #define SMI_BUSY 0x10000000
919 #define SMI_READ_VALID 0x08000000
920 #define SMI_OPCODE_READ 0x04000000
921 #define SMI_OPCODE_WRITE 0x00000000
922
923 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
924 unsigned int reg, unsigned int *value)
925 {
926 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
927 unsigned long flags;
928 int i;
929
930 /* the SMI register is a shared resource */
931 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
932
933 /* wait for the SMI register to become available */
934 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
935 if (i == 1000) {
936 printk("%s: PHY busy timeout\n", mp->dev->name);
937 goto out;
938 }
939 udelay(10);
940 }
941
942 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
943
944 /* now wait for the data to be valid */
945 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
946 if (i == 1000) {
947 printk("%s: PHY read timeout\n", mp->dev->name);
948 goto out;
949 }
950 udelay(10);
951 }
952
953 *value = readl(smi_reg) & 0xffff;
954 out:
955 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
956 }
957
958 static void smi_reg_write(struct mv643xx_eth_private *mp,
959 unsigned int addr,
960 unsigned int reg, unsigned int value)
961 {
962 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
963 unsigned long flags;
964 int i;
965
966 /* the SMI register is a shared resource */
967 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
968
969 /* wait for the SMI register to become available */
970 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
971 if (i == 1000) {
972 printk("%s: PHY busy timeout\n", mp->dev->name);
973 goto out;
974 }
975 udelay(10);
976 }
977
978 writel(SMI_OPCODE_WRITE | (reg << 21) |
979 (addr << 16) | (value & 0xffff), smi_reg);
980 out:
981 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
982 }
983
984
985 /* mib counters *************************************************************/
986 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
987 {
988 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
989 }
990
991 static void mib_counters_clear(struct mv643xx_eth_private *mp)
992 {
993 int i;
994
995 for (i = 0; i < 0x80; i += 4)
996 mib_read(mp, i);
997 }
998
999 static void mib_counters_update(struct mv643xx_eth_private *mp)
1000 {
1001 struct mib_counters *p = &mp->mib_counters;
1002
1003 p->good_octets_received += mib_read(mp, 0x00);
1004 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1005 p->bad_octets_received += mib_read(mp, 0x08);
1006 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1007 p->good_frames_received += mib_read(mp, 0x10);
1008 p->bad_frames_received += mib_read(mp, 0x14);
1009 p->broadcast_frames_received += mib_read(mp, 0x18);
1010 p->multicast_frames_received += mib_read(mp, 0x1c);
1011 p->frames_64_octets += mib_read(mp, 0x20);
1012 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1013 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1014 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1015 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1016 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1017 p->good_octets_sent += mib_read(mp, 0x38);
1018 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1019 p->good_frames_sent += mib_read(mp, 0x40);
1020 p->excessive_collision += mib_read(mp, 0x44);
1021 p->multicast_frames_sent += mib_read(mp, 0x48);
1022 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1023 p->unrec_mac_control_received += mib_read(mp, 0x50);
1024 p->fc_sent += mib_read(mp, 0x54);
1025 p->good_fc_received += mib_read(mp, 0x58);
1026 p->bad_fc_received += mib_read(mp, 0x5c);
1027 p->undersize_received += mib_read(mp, 0x60);
1028 p->fragments_received += mib_read(mp, 0x64);
1029 p->oversize_received += mib_read(mp, 0x68);
1030 p->jabber_received += mib_read(mp, 0x6c);
1031 p->mac_receive_error += mib_read(mp, 0x70);
1032 p->bad_crc_event += mib_read(mp, 0x74);
1033 p->collision += mib_read(mp, 0x78);
1034 p->late_collision += mib_read(mp, 0x7c);
1035 }
1036
1037
1038 /* ethtool ******************************************************************/
1039 struct mv643xx_eth_stats {
1040 char stat_string[ETH_GSTRING_LEN];
1041 int sizeof_stat;
1042 int netdev_off;
1043 int mp_off;
1044 };
1045
1046 #define SSTAT(m) \
1047 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1048 offsetof(struct net_device, stats.m), -1 }
1049
1050 #define MIBSTAT(m) \
1051 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1052 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1053
1054 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1055 SSTAT(rx_packets),
1056 SSTAT(tx_packets),
1057 SSTAT(rx_bytes),
1058 SSTAT(tx_bytes),
1059 SSTAT(rx_errors),
1060 SSTAT(tx_errors),
1061 SSTAT(rx_dropped),
1062 SSTAT(tx_dropped),
1063 MIBSTAT(good_octets_received),
1064 MIBSTAT(bad_octets_received),
1065 MIBSTAT(internal_mac_transmit_err),
1066 MIBSTAT(good_frames_received),
1067 MIBSTAT(bad_frames_received),
1068 MIBSTAT(broadcast_frames_received),
1069 MIBSTAT(multicast_frames_received),
1070 MIBSTAT(frames_64_octets),
1071 MIBSTAT(frames_65_to_127_octets),
1072 MIBSTAT(frames_128_to_255_octets),
1073 MIBSTAT(frames_256_to_511_octets),
1074 MIBSTAT(frames_512_to_1023_octets),
1075 MIBSTAT(frames_1024_to_max_octets),
1076 MIBSTAT(good_octets_sent),
1077 MIBSTAT(good_frames_sent),
1078 MIBSTAT(excessive_collision),
1079 MIBSTAT(multicast_frames_sent),
1080 MIBSTAT(broadcast_frames_sent),
1081 MIBSTAT(unrec_mac_control_received),
1082 MIBSTAT(fc_sent),
1083 MIBSTAT(good_fc_received),
1084 MIBSTAT(bad_fc_received),
1085 MIBSTAT(undersize_received),
1086 MIBSTAT(fragments_received),
1087 MIBSTAT(oversize_received),
1088 MIBSTAT(jabber_received),
1089 MIBSTAT(mac_receive_error),
1090 MIBSTAT(bad_crc_event),
1091 MIBSTAT(collision),
1092 MIBSTAT(late_collision),
1093 };
1094
1095 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1096 {
1097 struct mv643xx_eth_private *mp = netdev_priv(dev);
1098 int err;
1099
1100 spin_lock_irq(&mp->lock);
1101 err = mii_ethtool_gset(&mp->mii, cmd);
1102 spin_unlock_irq(&mp->lock);
1103
1104 /*
1105 * The MAC does not support 1000baseT_Half.
1106 */
1107 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1108 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1109
1110 return err;
1111 }
1112
1113 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1114 {
1115 cmd->supported = SUPPORTED_MII;
1116 cmd->advertising = ADVERTISED_MII;
1117 cmd->speed = SPEED_1000;
1118 cmd->duplex = DUPLEX_FULL;
1119 cmd->port = PORT_MII;
1120 cmd->phy_address = 0;
1121 cmd->transceiver = XCVR_INTERNAL;
1122 cmd->autoneg = AUTONEG_DISABLE;
1123 cmd->maxtxpkt = 1;
1124 cmd->maxrxpkt = 1;
1125
1126 return 0;
1127 }
1128
1129 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1130 {
1131 struct mv643xx_eth_private *mp = netdev_priv(dev);
1132 int err;
1133
1134 /*
1135 * The MAC does not support 1000baseT_Half.
1136 */
1137 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1138
1139 spin_lock_irq(&mp->lock);
1140 err = mii_ethtool_sset(&mp->mii, cmd);
1141 spin_unlock_irq(&mp->lock);
1142
1143 return err;
1144 }
1145
1146 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1147 {
1148 return -EINVAL;
1149 }
1150
1151 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1152 struct ethtool_drvinfo *drvinfo)
1153 {
1154 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1155 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1156 strncpy(drvinfo->fw_version, "N/A", 32);
1157 strncpy(drvinfo->bus_info, "platform", 32);
1158 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1159 }
1160
1161 static int mv643xx_eth_nway_reset(struct net_device *dev)
1162 {
1163 struct mv643xx_eth_private *mp = netdev_priv(dev);
1164
1165 return mii_nway_restart(&mp->mii);
1166 }
1167
1168 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1169 {
1170 return -EINVAL;
1171 }
1172
1173 static u32 mv643xx_eth_get_link(struct net_device *dev)
1174 {
1175 struct mv643xx_eth_private *mp = netdev_priv(dev);
1176
1177 return mii_link_ok(&mp->mii);
1178 }
1179
1180 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1181 {
1182 return 1;
1183 }
1184
1185 static void mv643xx_eth_get_strings(struct net_device *dev,
1186 uint32_t stringset, uint8_t *data)
1187 {
1188 int i;
1189
1190 if (stringset == ETH_SS_STATS) {
1191 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1192 memcpy(data + i * ETH_GSTRING_LEN,
1193 mv643xx_eth_stats[i].stat_string,
1194 ETH_GSTRING_LEN);
1195 }
1196 }
1197 }
1198
1199 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1200 struct ethtool_stats *stats,
1201 uint64_t *data)
1202 {
1203 struct mv643xx_eth_private *mp = dev->priv;
1204 int i;
1205
1206 mib_counters_update(mp);
1207
1208 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1209 const struct mv643xx_eth_stats *stat;
1210 void *p;
1211
1212 stat = mv643xx_eth_stats + i;
1213
1214 if (stat->netdev_off >= 0)
1215 p = ((void *)mp->dev) + stat->netdev_off;
1216 else
1217 p = ((void *)mp) + stat->mp_off;
1218
1219 data[i] = (stat->sizeof_stat == 8) ?
1220 *(uint64_t *)p : *(uint32_t *)p;
1221 }
1222 }
1223
1224 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1225 {
1226 if (sset == ETH_SS_STATS)
1227 return ARRAY_SIZE(mv643xx_eth_stats);
1228
1229 return -EOPNOTSUPP;
1230 }
1231
1232 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1233 .get_settings = mv643xx_eth_get_settings,
1234 .set_settings = mv643xx_eth_set_settings,
1235 .get_drvinfo = mv643xx_eth_get_drvinfo,
1236 .nway_reset = mv643xx_eth_nway_reset,
1237 .get_link = mv643xx_eth_get_link,
1238 .set_sg = ethtool_op_set_sg,
1239 .get_strings = mv643xx_eth_get_strings,
1240 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1241 .get_sset_count = mv643xx_eth_get_sset_count,
1242 };
1243
1244 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1245 .get_settings = mv643xx_eth_get_settings_phyless,
1246 .set_settings = mv643xx_eth_set_settings_phyless,
1247 .get_drvinfo = mv643xx_eth_get_drvinfo,
1248 .nway_reset = mv643xx_eth_nway_reset_phyless,
1249 .get_link = mv643xx_eth_get_link_phyless,
1250 .set_sg = ethtool_op_set_sg,
1251 .get_strings = mv643xx_eth_get_strings,
1252 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1253 .get_sset_count = mv643xx_eth_get_sset_count,
1254 };
1255
1256
1257 /* address handling *********************************************************/
1258 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1259 {
1260 unsigned int mac_h;
1261 unsigned int mac_l;
1262
1263 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1264 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1265
1266 addr[0] = (mac_h >> 24) & 0xff;
1267 addr[1] = (mac_h >> 16) & 0xff;
1268 addr[2] = (mac_h >> 8) & 0xff;
1269 addr[3] = mac_h & 0xff;
1270 addr[4] = (mac_l >> 8) & 0xff;
1271 addr[5] = mac_l & 0xff;
1272 }
1273
1274 static void init_mac_tables(struct mv643xx_eth_private *mp)
1275 {
1276 int i;
1277
1278 for (i = 0; i < 0x100; i += 4) {
1279 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1280 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1281 }
1282
1283 for (i = 0; i < 0x10; i += 4)
1284 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1285 }
1286
1287 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1288 int table, unsigned char entry)
1289 {
1290 unsigned int table_reg;
1291
1292 /* Set "accepts frame bit" at specified table entry */
1293 table_reg = rdl(mp, table + (entry & 0xfc));
1294 table_reg |= 0x01 << (8 * (entry & 3));
1295 wrl(mp, table + (entry & 0xfc), table_reg);
1296 }
1297
1298 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1299 {
1300 unsigned int mac_h;
1301 unsigned int mac_l;
1302 int table;
1303
1304 mac_l = (addr[4] << 8) | addr[5];
1305 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1306
1307 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1308 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1309
1310 table = UNICAST_TABLE(mp->port_num);
1311 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1312 }
1313
1314 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1315 {
1316 struct mv643xx_eth_private *mp = netdev_priv(dev);
1317
1318 /* +2 is for the offset of the HW addr type */
1319 memcpy(dev->dev_addr, addr + 2, 6);
1320
1321 init_mac_tables(mp);
1322 uc_addr_set(mp, dev->dev_addr);
1323
1324 return 0;
1325 }
1326
1327 static int addr_crc(unsigned char *addr)
1328 {
1329 int crc = 0;
1330 int i;
1331
1332 for (i = 0; i < 6; i++) {
1333 int j;
1334
1335 crc = (crc ^ addr[i]) << 8;
1336 for (j = 7; j >= 0; j--) {
1337 if (crc & (0x100 << j))
1338 crc ^= 0x107 << j;
1339 }
1340 }
1341
1342 return crc;
1343 }
1344
1345 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1346 {
1347 struct mv643xx_eth_private *mp = netdev_priv(dev);
1348 u32 port_config;
1349 struct dev_addr_list *addr;
1350 int i;
1351
1352 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1353 if (dev->flags & IFF_PROMISC)
1354 port_config |= UNICAST_PROMISCUOUS_MODE;
1355 else
1356 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1357 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1358
1359 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1360 int port_num = mp->port_num;
1361 u32 accept = 0x01010101;
1362
1363 for (i = 0; i < 0x100; i += 4) {
1364 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1365 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1366 }
1367 return;
1368 }
1369
1370 for (i = 0; i < 0x100; i += 4) {
1371 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1372 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1373 }
1374
1375 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1376 u8 *a = addr->da_addr;
1377 int table;
1378
1379 if (addr->da_addrlen != 6)
1380 continue;
1381
1382 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1383 table = SPECIAL_MCAST_TABLE(mp->port_num);
1384 set_filter_table_entry(mp, table, a[5]);
1385 } else {
1386 int crc = addr_crc(a);
1387
1388 table = OTHER_MCAST_TABLE(mp->port_num);
1389 set_filter_table_entry(mp, table, crc);
1390 }
1391 }
1392 }
1393
1394
1395 /* rx/tx queue initialisation ***********************************************/
1396 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1397 {
1398 struct rx_queue *rxq = mp->rxq + index;
1399 struct rx_desc *rx_desc;
1400 int size;
1401 int i;
1402
1403 rxq->index = index;
1404
1405 rxq->rx_ring_size = mp->default_rx_ring_size;
1406
1407 rxq->rx_desc_count = 0;
1408 rxq->rx_curr_desc = 0;
1409 rxq->rx_used_desc = 0;
1410
1411 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1412
1413 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1414 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1415 mp->rx_desc_sram_size);
1416 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1417 } else {
1418 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1419 &rxq->rx_desc_dma,
1420 GFP_KERNEL);
1421 }
1422
1423 if (rxq->rx_desc_area == NULL) {
1424 dev_printk(KERN_ERR, &mp->dev->dev,
1425 "can't allocate rx ring (%d bytes)\n", size);
1426 goto out;
1427 }
1428 memset(rxq->rx_desc_area, 0, size);
1429
1430 rxq->rx_desc_area_size = size;
1431 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1432 GFP_KERNEL);
1433 if (rxq->rx_skb == NULL) {
1434 dev_printk(KERN_ERR, &mp->dev->dev,
1435 "can't allocate rx skb ring\n");
1436 goto out_free;
1437 }
1438
1439 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1440 for (i = 0; i < rxq->rx_ring_size; i++) {
1441 int nexti = (i + 1) % rxq->rx_ring_size;
1442 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1443 nexti * sizeof(struct rx_desc);
1444 }
1445
1446 init_timer(&rxq->rx_oom);
1447 rxq->rx_oom.data = (unsigned long)rxq;
1448 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1449
1450 return 0;
1451
1452
1453 out_free:
1454 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1455 iounmap(rxq->rx_desc_area);
1456 else
1457 dma_free_coherent(NULL, size,
1458 rxq->rx_desc_area,
1459 rxq->rx_desc_dma);
1460
1461 out:
1462 return -ENOMEM;
1463 }
1464
1465 static void rxq_deinit(struct rx_queue *rxq)
1466 {
1467 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1468 int i;
1469
1470 rxq_disable(rxq);
1471
1472 del_timer_sync(&rxq->rx_oom);
1473
1474 for (i = 0; i < rxq->rx_ring_size; i++) {
1475 if (rxq->rx_skb[i]) {
1476 dev_kfree_skb(rxq->rx_skb[i]);
1477 rxq->rx_desc_count--;
1478 }
1479 }
1480
1481 if (rxq->rx_desc_count) {
1482 dev_printk(KERN_ERR, &mp->dev->dev,
1483 "error freeing rx ring -- %d skbs stuck\n",
1484 rxq->rx_desc_count);
1485 }
1486
1487 if (rxq->index == mp->rxq_primary &&
1488 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1489 iounmap(rxq->rx_desc_area);
1490 else
1491 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1492 rxq->rx_desc_area, rxq->rx_desc_dma);
1493
1494 kfree(rxq->rx_skb);
1495 }
1496
1497 static int txq_init(struct mv643xx_eth_private *mp, int index)
1498 {
1499 struct tx_queue *txq = mp->txq + index;
1500 struct tx_desc *tx_desc;
1501 int size;
1502 int i;
1503
1504 txq->index = index;
1505
1506 txq->tx_ring_size = mp->default_tx_ring_size;
1507
1508 txq->tx_desc_count = 0;
1509 txq->tx_curr_desc = 0;
1510 txq->tx_used_desc = 0;
1511
1512 size = txq->tx_ring_size * sizeof(struct tx_desc);
1513
1514 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1515 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1516 mp->tx_desc_sram_size);
1517 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1518 } else {
1519 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1520 &txq->tx_desc_dma,
1521 GFP_KERNEL);
1522 }
1523
1524 if (txq->tx_desc_area == NULL) {
1525 dev_printk(KERN_ERR, &mp->dev->dev,
1526 "can't allocate tx ring (%d bytes)\n", size);
1527 goto out;
1528 }
1529 memset(txq->tx_desc_area, 0, size);
1530
1531 txq->tx_desc_area_size = size;
1532 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1533 GFP_KERNEL);
1534 if (txq->tx_skb == NULL) {
1535 dev_printk(KERN_ERR, &mp->dev->dev,
1536 "can't allocate tx skb ring\n");
1537 goto out_free;
1538 }
1539
1540 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1541 for (i = 0; i < txq->tx_ring_size; i++) {
1542 int nexti = (i + 1) % txq->tx_ring_size;
1543 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1544 nexti * sizeof(struct tx_desc);
1545 }
1546
1547 return 0;
1548
1549
1550 out_free:
1551 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1552 iounmap(txq->tx_desc_area);
1553 else
1554 dma_free_coherent(NULL, size,
1555 txq->tx_desc_area,
1556 txq->tx_desc_dma);
1557
1558 out:
1559 return -ENOMEM;
1560 }
1561
1562 static void txq_reclaim(struct tx_queue *txq, int force)
1563 {
1564 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1565 unsigned long flags;
1566
1567 spin_lock_irqsave(&mp->lock, flags);
1568 while (txq->tx_desc_count > 0) {
1569 int tx_index;
1570 struct tx_desc *desc;
1571 u32 cmd_sts;
1572 struct sk_buff *skb;
1573 dma_addr_t addr;
1574 int count;
1575
1576 tx_index = txq->tx_used_desc;
1577 desc = &txq->tx_desc_area[tx_index];
1578 cmd_sts = desc->cmd_sts;
1579
1580 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1581 break;
1582
1583 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1584 txq->tx_desc_count--;
1585
1586 addr = desc->buf_ptr;
1587 count = desc->byte_cnt;
1588 skb = txq->tx_skb[tx_index];
1589 txq->tx_skb[tx_index] = NULL;
1590
1591 if (cmd_sts & ERROR_SUMMARY) {
1592 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1593 mp->dev->stats.tx_errors++;
1594 }
1595
1596 /*
1597 * Drop mp->lock while we free the skb.
1598 */
1599 spin_unlock_irqrestore(&mp->lock, flags);
1600
1601 if (cmd_sts & TX_FIRST_DESC)
1602 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1603 else
1604 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1605
1606 if (skb)
1607 dev_kfree_skb_irq(skb);
1608
1609 spin_lock_irqsave(&mp->lock, flags);
1610 }
1611 spin_unlock_irqrestore(&mp->lock, flags);
1612 }
1613
1614 static void txq_deinit(struct tx_queue *txq)
1615 {
1616 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1617
1618 txq_disable(txq);
1619 txq_reclaim(txq, 1);
1620
1621 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1622
1623 if (txq->index == mp->txq_primary &&
1624 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1625 iounmap(txq->tx_desc_area);
1626 else
1627 dma_free_coherent(NULL, txq->tx_desc_area_size,
1628 txq->tx_desc_area, txq->tx_desc_dma);
1629
1630 kfree(txq->tx_skb);
1631 }
1632
1633
1634 /* netdev ops and related ***************************************************/
1635 static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1636 {
1637 u32 pscr_o;
1638 u32 pscr_n;
1639
1640 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1641
1642 /* clear speed, duplex and rx buffer size fields */
1643 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1644 SET_GMII_SPEED_TO_1000 |
1645 SET_FULL_DUPLEX_MODE |
1646 MAX_RX_PACKET_MASK);
1647
1648 if (speed == SPEED_1000) {
1649 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1650 } else {
1651 if (speed == SPEED_100)
1652 pscr_n |= SET_MII_SPEED_TO_100;
1653 pscr_n |= MAX_RX_PACKET_1522BYTE;
1654 }
1655
1656 if (duplex == DUPLEX_FULL)
1657 pscr_n |= SET_FULL_DUPLEX_MODE;
1658
1659 if (pscr_n != pscr_o) {
1660 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1661 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1662 else {
1663 int i;
1664
1665 for (i = 0; i < 8; i++)
1666 if (mp->txq_mask & (1 << i))
1667 txq_disable(mp->txq + i);
1668
1669 pscr_o &= ~SERIAL_PORT_ENABLE;
1670 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1671 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1672 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1673
1674 for (i = 0; i < 8; i++)
1675 if (mp->txq_mask & (1 << i))
1676 txq_enable(mp->txq + i);
1677 }
1678 }
1679 }
1680
1681 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1682 {
1683 struct net_device *dev = (struct net_device *)dev_id;
1684 struct mv643xx_eth_private *mp = netdev_priv(dev);
1685 u32 int_cause;
1686 u32 int_cause_ext;
1687 u32 txq_active;
1688
1689 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1690 (INT_TX_END | INT_RX | INT_EXT);
1691 if (int_cause == 0)
1692 return IRQ_NONE;
1693
1694 int_cause_ext = 0;
1695 if (int_cause & INT_EXT) {
1696 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1697 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1698 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1699 }
1700
1701 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1702 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
1703 int i;
1704
1705 if (mp->phy_addr != -1) {
1706 struct ethtool_cmd cmd;
1707
1708 mii_ethtool_gset(&mp->mii, &cmd);
1709 update_pscr(mp, cmd.speed, cmd.duplex);
1710 }
1711
1712 for (i = 0; i < 8; i++)
1713 if (mp->txq_mask & (1 << i))
1714 txq_enable(mp->txq + i);
1715
1716 if (!netif_carrier_ok(dev)) {
1717 netif_carrier_on(dev);
1718 __txq_maybe_wake(mp->txq + mp->txq_primary);
1719 }
1720 } else if (netif_carrier_ok(dev)) {
1721 netif_stop_queue(dev);
1722 netif_carrier_off(dev);
1723 }
1724 }
1725
1726 /*
1727 * RxBuffer or RxError set for any of the 8 queues?
1728 */
1729 #ifdef MV643XX_ETH_NAPI
1730 if (int_cause & INT_RX) {
1731 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1732 rdl(mp, INT_MASK(mp->port_num));
1733
1734 netif_rx_schedule(dev, &mp->napi);
1735 }
1736 #else
1737 if (int_cause & INT_RX) {
1738 int i;
1739
1740 for (i = 7; i >= 0; i--)
1741 if (mp->rxq_mask & (1 << i))
1742 rxq_process(mp->rxq + i, INT_MAX);
1743 }
1744 #endif
1745
1746 txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
1747
1748 /*
1749 * TxBuffer or TxError set for any of the 8 queues?
1750 */
1751 if (int_cause_ext & INT_EXT_TX) {
1752 int i;
1753
1754 for (i = 0; i < 8; i++)
1755 if (mp->txq_mask & (1 << i))
1756 txq_reclaim(mp->txq + i, 0);
1757 }
1758
1759 /*
1760 * Any TxEnd interrupts?
1761 */
1762 if (int_cause & INT_TX_END) {
1763 int i;
1764
1765 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1766 for (i = 0; i < 8; i++) {
1767 struct tx_queue *txq = mp->txq + i;
1768 if (txq->tx_desc_count && !((txq_active >> i) & 1))
1769 txq_enable(txq);
1770 }
1771 }
1772
1773 /*
1774 * Enough space again in the primary TX queue for a full packet?
1775 */
1776 if (int_cause_ext & INT_EXT_TX) {
1777 struct tx_queue *txq = mp->txq + mp->txq_primary;
1778 __txq_maybe_wake(txq);
1779 }
1780
1781 return IRQ_HANDLED;
1782 }
1783
1784 static void phy_reset(struct mv643xx_eth_private *mp)
1785 {
1786 unsigned int data;
1787
1788 smi_reg_read(mp, mp->phy_addr, 0, &data);
1789 data |= 0x8000;
1790 smi_reg_write(mp, mp->phy_addr, 0, data);
1791
1792 do {
1793 udelay(1);
1794 smi_reg_read(mp, mp->phy_addr, 0, &data);
1795 } while (data & 0x8000);
1796 }
1797
1798 static void port_start(struct mv643xx_eth_private *mp)
1799 {
1800 u32 pscr;
1801 int i;
1802
1803 /*
1804 * Configure basic link parameters.
1805 */
1806 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1807 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1808 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1809 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1810 DISABLE_AUTO_NEG_SPEED_GMII |
1811 DISABLE_AUTO_NEG_FOR_DUPLEX |
1812 DO_NOT_FORCE_LINK_FAIL |
1813 SERIAL_PORT_CONTROL_RESERVED;
1814 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1815 pscr |= SERIAL_PORT_ENABLE;
1816 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1817
1818 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1819
1820 /*
1821 * Perform PHY reset, if there is a PHY.
1822 */
1823 if (mp->phy_addr != -1) {
1824 struct ethtool_cmd cmd;
1825
1826 mv643xx_eth_get_settings(mp->dev, &cmd);
1827 phy_reset(mp);
1828 mv643xx_eth_set_settings(mp->dev, &cmd);
1829 }
1830
1831 /*
1832 * Configure TX path and queues.
1833 */
1834 tx_set_rate(mp, 1000000000, 16777216);
1835 for (i = 0; i < 8; i++) {
1836 struct tx_queue *txq = mp->txq + i;
1837 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
1838 u32 addr;
1839
1840 if ((mp->txq_mask & (1 << i)) == 0)
1841 continue;
1842
1843 addr = (u32)txq->tx_desc_dma;
1844 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1845 wrl(mp, off, addr);
1846
1847 txq_set_rate(txq, 1000000000, 16777216);
1848 txq_set_fixed_prio_mode(txq);
1849 }
1850
1851 /*
1852 * Add configured unicast address to address filter table.
1853 */
1854 uc_addr_set(mp, mp->dev->dev_addr);
1855
1856 /*
1857 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1858 * frames to RX queue #0.
1859 */
1860 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1861
1862 /*
1863 * Treat BPDUs as normal multicasts, and disable partition mode.
1864 */
1865 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1866
1867 /*
1868 * Enable the receive queues.
1869 */
1870 for (i = 0; i < 8; i++) {
1871 struct rx_queue *rxq = mp->rxq + i;
1872 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1873 u32 addr;
1874
1875 if ((mp->rxq_mask & (1 << i)) == 0)
1876 continue;
1877
1878 addr = (u32)rxq->rx_desc_dma;
1879 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1880 wrl(mp, off, addr);
1881
1882 rxq_enable(rxq);
1883 }
1884 }
1885
1886 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1887 {
1888 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1889 u32 val;
1890
1891 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1892 if (mp->shared->extended_rx_coal_limit) {
1893 if (coal > 0xffff)
1894 coal = 0xffff;
1895 val &= ~0x023fff80;
1896 val |= (coal & 0x8000) << 10;
1897 val |= (coal & 0x7fff) << 7;
1898 } else {
1899 if (coal > 0x3fff)
1900 coal = 0x3fff;
1901 val &= ~0x003fff00;
1902 val |= (coal & 0x3fff) << 8;
1903 }
1904 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1905 }
1906
1907 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1908 {
1909 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1910
1911 if (coal > 0x3fff)
1912 coal = 0x3fff;
1913 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1914 }
1915
1916 static int mv643xx_eth_open(struct net_device *dev)
1917 {
1918 struct mv643xx_eth_private *mp = netdev_priv(dev);
1919 int err;
1920 int i;
1921
1922 wrl(mp, INT_CAUSE(mp->port_num), 0);
1923 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1924 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1925
1926 err = request_irq(dev->irq, mv643xx_eth_irq,
1927 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1928 dev->name, dev);
1929 if (err) {
1930 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1931 return -EAGAIN;
1932 }
1933
1934 init_mac_tables(mp);
1935
1936 for (i = 0; i < 8; i++) {
1937 if ((mp->rxq_mask & (1 << i)) == 0)
1938 continue;
1939
1940 err = rxq_init(mp, i);
1941 if (err) {
1942 while (--i >= 0)
1943 if (mp->rxq_mask & (1 << i))
1944 rxq_deinit(mp->rxq + i);
1945 goto out;
1946 }
1947
1948 rxq_refill(mp->rxq + i);
1949 }
1950
1951 for (i = 0; i < 8; i++) {
1952 if ((mp->txq_mask & (1 << i)) == 0)
1953 continue;
1954
1955 err = txq_init(mp, i);
1956 if (err) {
1957 while (--i >= 0)
1958 if (mp->txq_mask & (1 << i))
1959 txq_deinit(mp->txq + i);
1960 goto out_free;
1961 }
1962 }
1963
1964 #ifdef MV643XX_ETH_NAPI
1965 napi_enable(&mp->napi);
1966 #endif
1967
1968 port_start(mp);
1969
1970 set_rx_coal(mp, 0);
1971 set_tx_coal(mp, 0);
1972
1973 wrl(mp, INT_MASK_EXT(mp->port_num),
1974 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1975
1976 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1977
1978 return 0;
1979
1980
1981 out_free:
1982 for (i = 0; i < 8; i++)
1983 if (mp->rxq_mask & (1 << i))
1984 rxq_deinit(mp->rxq + i);
1985 out:
1986 free_irq(dev->irq, dev);
1987
1988 return err;
1989 }
1990
1991 static void port_reset(struct mv643xx_eth_private *mp)
1992 {
1993 unsigned int data;
1994 int i;
1995
1996 for (i = 0; i < 8; i++) {
1997 if (mp->rxq_mask & (1 << i))
1998 rxq_disable(mp->rxq + i);
1999 if (mp->txq_mask & (1 << i))
2000 txq_disable(mp->txq + i);
2001 }
2002 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
2003 udelay(10);
2004
2005 /* Reset the Enable bit in the Configuration Register */
2006 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2007 data &= ~(SERIAL_PORT_ENABLE |
2008 DO_NOT_FORCE_LINK_FAIL |
2009 FORCE_LINK_PASS);
2010 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2011 }
2012
2013 static int mv643xx_eth_stop(struct net_device *dev)
2014 {
2015 struct mv643xx_eth_private *mp = netdev_priv(dev);
2016 int i;
2017
2018 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2019 rdl(mp, INT_MASK(mp->port_num));
2020
2021 #ifdef MV643XX_ETH_NAPI
2022 napi_disable(&mp->napi);
2023 #endif
2024 netif_carrier_off(dev);
2025 netif_stop_queue(dev);
2026
2027 free_irq(dev->irq, dev);
2028
2029 port_reset(mp);
2030 mib_counters_update(mp);
2031
2032 for (i = 0; i < 8; i++) {
2033 if (mp->rxq_mask & (1 << i))
2034 rxq_deinit(mp->rxq + i);
2035 if (mp->txq_mask & (1 << i))
2036 txq_deinit(mp->txq + i);
2037 }
2038
2039 return 0;
2040 }
2041
2042 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2043 {
2044 struct mv643xx_eth_private *mp = netdev_priv(dev);
2045
2046 if (mp->phy_addr != -1)
2047 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2048
2049 return -EOPNOTSUPP;
2050 }
2051
2052 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2053 {
2054 struct mv643xx_eth_private *mp = netdev_priv(dev);
2055
2056 if (new_mtu < 64 || new_mtu > 9500)
2057 return -EINVAL;
2058
2059 dev->mtu = new_mtu;
2060 tx_set_rate(mp, 1000000000, 16777216);
2061
2062 if (!netif_running(dev))
2063 return 0;
2064
2065 /*
2066 * Stop and then re-open the interface. This will allocate RX
2067 * skbs of the new MTU.
2068 * There is a possible danger that the open will not succeed,
2069 * due to memory being full.
2070 */
2071 mv643xx_eth_stop(dev);
2072 if (mv643xx_eth_open(dev)) {
2073 dev_printk(KERN_ERR, &dev->dev,
2074 "fatal error on re-opening device after "
2075 "MTU change\n");
2076 }
2077
2078 return 0;
2079 }
2080
2081 static void tx_timeout_task(struct work_struct *ugly)
2082 {
2083 struct mv643xx_eth_private *mp;
2084
2085 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2086 if (netif_running(mp->dev)) {
2087 netif_stop_queue(mp->dev);
2088
2089 port_reset(mp);
2090 port_start(mp);
2091
2092 __txq_maybe_wake(mp->txq + mp->txq_primary);
2093 }
2094 }
2095
2096 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2097 {
2098 struct mv643xx_eth_private *mp = netdev_priv(dev);
2099
2100 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2101
2102 schedule_work(&mp->tx_timeout_task);
2103 }
2104
2105 #ifdef CONFIG_NET_POLL_CONTROLLER
2106 static void mv643xx_eth_netpoll(struct net_device *dev)
2107 {
2108 struct mv643xx_eth_private *mp = netdev_priv(dev);
2109
2110 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2111 rdl(mp, INT_MASK(mp->port_num));
2112
2113 mv643xx_eth_irq(dev->irq, dev);
2114
2115 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
2116 }
2117 #endif
2118
2119 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2120 {
2121 struct mv643xx_eth_private *mp = netdev_priv(dev);
2122 int val;
2123
2124 smi_reg_read(mp, addr, reg, &val);
2125
2126 return val;
2127 }
2128
2129 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2130 {
2131 struct mv643xx_eth_private *mp = netdev_priv(dev);
2132 smi_reg_write(mp, addr, reg, val);
2133 }
2134
2135
2136 /* platform glue ************************************************************/
2137 static void
2138 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2139 struct mbus_dram_target_info *dram)
2140 {
2141 void __iomem *base = msp->base;
2142 u32 win_enable;
2143 u32 win_protect;
2144 int i;
2145
2146 for (i = 0; i < 6; i++) {
2147 writel(0, base + WINDOW_BASE(i));
2148 writel(0, base + WINDOW_SIZE(i));
2149 if (i < 4)
2150 writel(0, base + WINDOW_REMAP_HIGH(i));
2151 }
2152
2153 win_enable = 0x3f;
2154 win_protect = 0;
2155
2156 for (i = 0; i < dram->num_cs; i++) {
2157 struct mbus_dram_window *cs = dram->cs + i;
2158
2159 writel((cs->base & 0xffff0000) |
2160 (cs->mbus_attr << 8) |
2161 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2162 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2163
2164 win_enable &= ~(1 << i);
2165 win_protect |= 3 << (2 * i);
2166 }
2167
2168 writel(win_enable, base + WINDOW_BAR_ENABLE);
2169 msp->win_protect = win_protect;
2170 }
2171
2172 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2173 {
2174 /*
2175 * Check whether we have a 14-bit coal limit field in bits
2176 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2177 * SDMA config register.
2178 */
2179 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2180 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2181 msp->extended_rx_coal_limit = 1;
2182 else
2183 msp->extended_rx_coal_limit = 0;
2184
2185 /*
2186 * Check whether the TX rate control registers are in the
2187 * old or the new place.
2188 */
2189 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2190 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2191 msp->tx_bw_control_moved = 1;
2192 else
2193 msp->tx_bw_control_moved = 0;
2194 }
2195
2196 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2197 {
2198 static int mv643xx_eth_version_printed = 0;
2199 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2200 struct mv643xx_eth_shared_private *msp;
2201 struct resource *res;
2202 int ret;
2203
2204 if (!mv643xx_eth_version_printed++)
2205 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2206
2207 ret = -EINVAL;
2208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2209 if (res == NULL)
2210 goto out;
2211
2212 ret = -ENOMEM;
2213 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2214 if (msp == NULL)
2215 goto out;
2216 memset(msp, 0, sizeof(*msp));
2217
2218 msp->base = ioremap(res->start, res->end - res->start + 1);
2219 if (msp->base == NULL)
2220 goto out_free;
2221
2222 spin_lock_init(&msp->phy_lock);
2223
2224 /*
2225 * (Re-)program MBUS remapping windows if we are asked to.
2226 */
2227 if (pd != NULL && pd->dram != NULL)
2228 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2229
2230 /*
2231 * Detect hardware parameters.
2232 */
2233 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2234 infer_hw_params(msp);
2235
2236 platform_set_drvdata(pdev, msp);
2237
2238 return 0;
2239
2240 out_free:
2241 kfree(msp);
2242 out:
2243 return ret;
2244 }
2245
2246 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2247 {
2248 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2249
2250 iounmap(msp->base);
2251 kfree(msp);
2252
2253 return 0;
2254 }
2255
2256 static struct platform_driver mv643xx_eth_shared_driver = {
2257 .probe = mv643xx_eth_shared_probe,
2258 .remove = mv643xx_eth_shared_remove,
2259 .driver = {
2260 .name = MV643XX_ETH_SHARED_NAME,
2261 .owner = THIS_MODULE,
2262 },
2263 };
2264
2265 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2266 {
2267 int addr_shift = 5 * mp->port_num;
2268 u32 data;
2269
2270 data = rdl(mp, PHY_ADDR);
2271 data &= ~(0x1f << addr_shift);
2272 data |= (phy_addr & 0x1f) << addr_shift;
2273 wrl(mp, PHY_ADDR, data);
2274 }
2275
2276 static int phy_addr_get(struct mv643xx_eth_private *mp)
2277 {
2278 unsigned int data;
2279
2280 data = rdl(mp, PHY_ADDR);
2281
2282 return (data >> (5 * mp->port_num)) & 0x1f;
2283 }
2284
2285 static void set_params(struct mv643xx_eth_private *mp,
2286 struct mv643xx_eth_platform_data *pd)
2287 {
2288 struct net_device *dev = mp->dev;
2289
2290 if (is_valid_ether_addr(pd->mac_addr))
2291 memcpy(dev->dev_addr, pd->mac_addr, 6);
2292 else
2293 uc_addr_get(mp, dev->dev_addr);
2294
2295 if (pd->phy_addr == -1) {
2296 mp->shared_smi = NULL;
2297 mp->phy_addr = -1;
2298 } else {
2299 mp->shared_smi = mp->shared;
2300 if (pd->shared_smi != NULL)
2301 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2302
2303 if (pd->force_phy_addr || pd->phy_addr) {
2304 mp->phy_addr = pd->phy_addr & 0x3f;
2305 phy_addr_set(mp, mp->phy_addr);
2306 } else {
2307 mp->phy_addr = phy_addr_get(mp);
2308 }
2309 }
2310
2311 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2312 if (pd->rx_queue_size)
2313 mp->default_rx_ring_size = pd->rx_queue_size;
2314 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2315 mp->rx_desc_sram_size = pd->rx_sram_size;
2316
2317 if (pd->rx_queue_mask)
2318 mp->rxq_mask = pd->rx_queue_mask;
2319 else
2320 mp->rxq_mask = 0x01;
2321 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2322
2323 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2324 if (pd->tx_queue_size)
2325 mp->default_tx_ring_size = pd->tx_queue_size;
2326 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2327 mp->tx_desc_sram_size = pd->tx_sram_size;
2328
2329 if (pd->tx_queue_mask)
2330 mp->txq_mask = pd->tx_queue_mask;
2331 else
2332 mp->txq_mask = 0x01;
2333 mp->txq_primary = fls(mp->txq_mask) - 1;
2334 }
2335
2336 static int phy_detect(struct mv643xx_eth_private *mp)
2337 {
2338 unsigned int data;
2339 unsigned int data2;
2340
2341 smi_reg_read(mp, mp->phy_addr, 0, &data);
2342 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
2343
2344 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2345 if (((data ^ data2) & 0x1000) == 0)
2346 return -ENODEV;
2347
2348 smi_reg_write(mp, mp->phy_addr, 0, data);
2349
2350 return 0;
2351 }
2352
2353 static int phy_init(struct mv643xx_eth_private *mp,
2354 struct mv643xx_eth_platform_data *pd)
2355 {
2356 struct ethtool_cmd cmd;
2357 int err;
2358
2359 err = phy_detect(mp);
2360 if (err) {
2361 dev_printk(KERN_INFO, &mp->dev->dev,
2362 "no PHY detected at addr %d\n", mp->phy_addr);
2363 return err;
2364 }
2365 phy_reset(mp);
2366
2367 mp->mii.phy_id = mp->phy_addr;
2368 mp->mii.phy_id_mask = 0x3f;
2369 mp->mii.reg_num_mask = 0x1f;
2370 mp->mii.dev = mp->dev;
2371 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2372 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2373
2374 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2375
2376 memset(&cmd, 0, sizeof(cmd));
2377
2378 cmd.port = PORT_MII;
2379 cmd.transceiver = XCVR_INTERNAL;
2380 cmd.phy_address = mp->phy_addr;
2381 if (pd->speed == 0) {
2382 cmd.autoneg = AUTONEG_ENABLE;
2383 cmd.speed = SPEED_100;
2384 cmd.advertising = ADVERTISED_10baseT_Half |
2385 ADVERTISED_10baseT_Full |
2386 ADVERTISED_100baseT_Half |
2387 ADVERTISED_100baseT_Full;
2388 if (mp->mii.supports_gmii)
2389 cmd.advertising |= ADVERTISED_1000baseT_Full;
2390 } else {
2391 cmd.autoneg = AUTONEG_DISABLE;
2392 cmd.speed = pd->speed;
2393 cmd.duplex = pd->duplex;
2394 }
2395
2396 update_pscr(mp, cmd.speed, cmd.duplex);
2397 mv643xx_eth_set_settings(mp->dev, &cmd);
2398
2399 return 0;
2400 }
2401
2402 static int mv643xx_eth_probe(struct platform_device *pdev)
2403 {
2404 struct mv643xx_eth_platform_data *pd;
2405 struct mv643xx_eth_private *mp;
2406 struct net_device *dev;
2407 struct resource *res;
2408 DECLARE_MAC_BUF(mac);
2409 int err;
2410
2411 pd = pdev->dev.platform_data;
2412 if (pd == NULL) {
2413 dev_printk(KERN_ERR, &pdev->dev,
2414 "no mv643xx_eth_platform_data\n");
2415 return -ENODEV;
2416 }
2417
2418 if (pd->shared == NULL) {
2419 dev_printk(KERN_ERR, &pdev->dev,
2420 "no mv643xx_eth_platform_data->shared\n");
2421 return -ENODEV;
2422 }
2423
2424 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2425 if (!dev)
2426 return -ENOMEM;
2427
2428 mp = netdev_priv(dev);
2429 platform_set_drvdata(pdev, mp);
2430
2431 mp->shared = platform_get_drvdata(pd->shared);
2432 mp->port_num = pd->port_number;
2433
2434 mp->dev = dev;
2435 #ifdef MV643XX_ETH_NAPI
2436 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2437 #endif
2438
2439 set_params(mp, pd);
2440
2441 spin_lock_init(&mp->lock);
2442
2443 mib_counters_clear(mp);
2444 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2445
2446 if (mp->phy_addr != -1) {
2447 err = phy_init(mp, pd);
2448 if (err)
2449 goto out;
2450
2451 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2452 } else {
2453 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2454 }
2455
2456
2457 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2458 BUG_ON(!res);
2459 dev->irq = res->start;
2460
2461 dev->hard_start_xmit = mv643xx_eth_xmit;
2462 dev->open = mv643xx_eth_open;
2463 dev->stop = mv643xx_eth_stop;
2464 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2465 dev->set_mac_address = mv643xx_eth_set_mac_address;
2466 dev->do_ioctl = mv643xx_eth_ioctl;
2467 dev->change_mtu = mv643xx_eth_change_mtu;
2468 dev->tx_timeout = mv643xx_eth_tx_timeout;
2469 #ifdef CONFIG_NET_POLL_CONTROLLER
2470 dev->poll_controller = mv643xx_eth_netpoll;
2471 #endif
2472 dev->watchdog_timeo = 2 * HZ;
2473 dev->base_addr = 0;
2474
2475 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2476 /*
2477 * Zero copy can only work if we use Discovery II memory. Else, we will
2478 * have to map the buffers to ISA memory which is only 16 MB
2479 */
2480 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2481 #endif
2482
2483 SET_NETDEV_DEV(dev, &pdev->dev);
2484
2485 if (mp->shared->win_protect)
2486 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2487
2488 err = register_netdev(dev);
2489 if (err)
2490 goto out;
2491
2492 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2493 mp->port_num, print_mac(mac, dev->dev_addr));
2494
2495 if (dev->features & NETIF_F_SG)
2496 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2497
2498 if (dev->features & NETIF_F_IP_CSUM)
2499 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2500
2501 #ifdef MV643XX_ETH_NAPI
2502 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2503 #endif
2504
2505 if (mp->tx_desc_sram_size > 0)
2506 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2507
2508 return 0;
2509
2510 out:
2511 free_netdev(dev);
2512
2513 return err;
2514 }
2515
2516 static int mv643xx_eth_remove(struct platform_device *pdev)
2517 {
2518 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2519
2520 unregister_netdev(mp->dev);
2521 flush_scheduled_work();
2522 free_netdev(mp->dev);
2523
2524 platform_set_drvdata(pdev, NULL);
2525
2526 return 0;
2527 }
2528
2529 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2530 {
2531 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2532
2533 /* Mask all interrupts on ethernet port */
2534 wrl(mp, INT_MASK(mp->port_num), 0);
2535 rdl(mp, INT_MASK(mp->port_num));
2536
2537 if (netif_running(mp->dev))
2538 port_reset(mp);
2539 }
2540
2541 static struct platform_driver mv643xx_eth_driver = {
2542 .probe = mv643xx_eth_probe,
2543 .remove = mv643xx_eth_remove,
2544 .shutdown = mv643xx_eth_shutdown,
2545 .driver = {
2546 .name = MV643XX_ETH_NAME,
2547 .owner = THIS_MODULE,
2548 },
2549 };
2550
2551 static int __init mv643xx_eth_init_module(void)
2552 {
2553 int rc;
2554
2555 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2556 if (!rc) {
2557 rc = platform_driver_register(&mv643xx_eth_driver);
2558 if (rc)
2559 platform_driver_unregister(&mv643xx_eth_shared_driver);
2560 }
2561
2562 return rc;
2563 }
2564 module_init(mv643xx_eth_init_module);
2565
2566 static void __exit mv643xx_eth_cleanup_module(void)
2567 {
2568 platform_driver_unregister(&mv643xx_eth_driver);
2569 platform_driver_unregister(&mv643xx_eth_shared_driver);
2570 }
2571 module_exit(mv643xx_eth_cleanup_module);
2572
2573 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2574 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2575 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2576 MODULE_LICENSE("GPL");
2577 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2578 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree