?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ixgb: fix unload race with timers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / 8139too.c
blob75317a14ad1cb26d6d3e030f48f0357dc6928789
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <linux/io.h>
111 #include <linux/uaccess.h>
112 #include <asm/irq.h>
113
114 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
115 #define PFX DRV_NAME ": "
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
124 #ifdef CONFIG_8139TOO_PIO
125 #define USE_IO_OPS 1
126 #endif
127
128 /* define to 1, 2 or 3 to enable copious debugging info */
129 #define RTL8139_DEBUG 0
130
131 /* define to 1 to disable lightweight runtime debugging checks */
132 #undef RTL8139_NDEBUG
133
134
135 #if RTL8139_DEBUG
136 /* note: prints function name for you */
137 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
138 #else
139 # define DPRINTK(fmt, args...)
140 #endif
141
142 #ifdef RTL8139_NDEBUG
143 # define assert(expr) do {} while (0)
144 #else
145 # define assert(expr) \
146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr, __FILE__, __func__, __LINE__); \
149 }
150 #endif
151
152
153 /* A few user-configurable values. */
154 /* media options */
155 #define MAX_UNITS 8
156 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /*
167 * Receive ring size
168 * Warning: 64K ring has hardware issues and may lock up.
169 */
170 #if defined(CONFIG_SH_DREAMCAST)
171 #define RX_BUF_IDX 0 /* 8K ring */
172 #else
173 #define RX_BUF_IDX 2 /* 32K ring */
174 #endif
175 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
176 #define RX_BUF_PAD 16
177 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
178
179 #if RX_BUF_LEN == 65536
180 #define RX_BUF_TOT_LEN RX_BUF_LEN
181 #else
182 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
183 #endif
184
185 /* Number of Tx descriptor registers. */
186 #define NUM_TX_DESC 4
187
188 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
189 #define MAX_ETH_FRAME_SIZE 1536
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] __devinitdata = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
392 TxIFGShift = 24,
393 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
394 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
395 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
396 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
397
398 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
399 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
400 TxClearAbt = (1 << 0), /* Clear abort (WO) */
401 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
402 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
403
404 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
405 };
406
407 /* Bits in Config1 */
408 enum Config1Bits {
409 Cfg1_PM_Enable = 0x01,
410 Cfg1_VPD_Enable = 0x02,
411 Cfg1_PIO = 0x04,
412 Cfg1_MMIO = 0x08,
413 LWAKE = 0x10, /* not on 8139, 8139A */
414 Cfg1_Driver_Load = 0x20,
415 Cfg1_LED0 = 0x40,
416 Cfg1_LED1 = 0x80,
417 SLEEP = (1 << 1), /* only on 8139, 8139A */
418 PWRDN = (1 << 0), /* only on 8139, 8139A */
419 };
420
421 /* Bits in Config3 */
422 enum Config3Bits {
423 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
424 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
425 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
426 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
427 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
428 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
429 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
430 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
431 };
432
433 /* Bits in Config4 */
434 enum Config4Bits {
435 LWPTN = (1 << 2), /* not on 8139, 8139A */
436 };
437
438 /* Bits in Config5 */
439 enum Config5Bits {
440 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
441 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
442 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
443 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
444 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
445 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
446 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
447 };
448
449 enum RxConfigBits {
450 /* rx fifo threshold */
451 RxCfgFIFOShift = 13,
452 RxCfgFIFONone = (7 << RxCfgFIFOShift),
453
454 /* Max DMA burst */
455 RxCfgDMAShift = 8,
456 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
457
458 /* rx ring buffer length */
459 RxCfgRcv8K = 0,
460 RxCfgRcv16K = (1 << 11),
461 RxCfgRcv32K = (1 << 12),
462 RxCfgRcv64K = (1 << 11) | (1 << 12),
463
464 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
465 RxNoWrap = (1 << 7),
466 };
467
468 /* Twister tuning parameters from RealTek.
469 Completely undocumented, but required to tune bad links on some boards. */
470 enum CSCRBits {
471 CSCR_LinkOKBit = 0x0400,
472 CSCR_LinkChangeBit = 0x0800,
473 CSCR_LinkStatusBits = 0x0f000,
474 CSCR_LinkDownOffCmd = 0x003c0,
475 CSCR_LinkDownCmd = 0x0f3c0,
476 };
477
478 enum Cfg9346Bits {
479 Cfg9346_Lock = 0x00,
480 Cfg9346_Unlock = 0xC0,
481 };
482
483 typedef enum {
484 CH_8139 = 0,
485 CH_8139_K,
486 CH_8139A,
487 CH_8139A_G,
488 CH_8139B,
489 CH_8130,
490 CH_8139C,
491 CH_8100,
492 CH_8100B_8139D,
493 CH_8101,
494 } chip_t;
495
496 enum chip_flags {
497 HasHltClk = (1 << 0),
498 HasLWake = (1 << 1),
499 };
500
501 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
502 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
503 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
504
505 /* directly indexed by chip_t, above */
506 static const struct {
507 const char *name;
508 u32 version; /* from RTL8139C/RTL8139D docs */
509 u32 flags;
510 } rtl_chip_info[] = {
511 { "RTL-8139",
512 HW_REVID(1, 0, 0, 0, 0, 0, 0),
513 HasHltClk,
514 },
515
516 { "RTL-8139 rev K",
517 HW_REVID(1, 1, 0, 0, 0, 0, 0),
518 HasHltClk,
519 },
520
521 { "RTL-8139A",
522 HW_REVID(1, 1, 1, 0, 0, 0, 0),
523 HasHltClk, /* XXX undocumented? */
524 },
525
526 { "RTL-8139A rev G",
527 HW_REVID(1, 1, 1, 0, 0, 1, 0),
528 HasHltClk, /* XXX undocumented? */
529 },
530
531 { "RTL-8139B",
532 HW_REVID(1, 1, 1, 1, 0, 0, 0),
533 HasLWake,
534 },
535
536 { "RTL-8130",
537 HW_REVID(1, 1, 1, 1, 1, 0, 0),
538 HasLWake,
539 },
540
541 { "RTL-8139C",
542 HW_REVID(1, 1, 1, 0, 1, 0, 0),
543 HasLWake,
544 },
545
546 { "RTL-8100",
547 HW_REVID(1, 1, 1, 1, 0, 1, 0),
548 HasLWake,
549 },
550
551 { "RTL-8100B/8139D",
552 HW_REVID(1, 1, 1, 0, 1, 0, 1),
553 HasHltClk /* XXX undocumented? */
554 | HasLWake,
555 },
556
557 { "RTL-8101",
558 HW_REVID(1, 1, 1, 0, 1, 1, 1),
559 HasLWake,
560 },
561 };
562
563 struct rtl_extra_stats {
564 unsigned long early_rx;
565 unsigned long tx_buf_mapped;
566 unsigned long tx_timeouts;
567 unsigned long rx_lost_in_ring;
568 };
569
570 struct rtl8139_private {
571 void __iomem *mmio_addr;
572 int drv_flags;
573 struct pci_dev *pci_dev;
574 u32 msg_enable;
575 struct napi_struct napi;
576 struct net_device *dev;
577
578 unsigned char *rx_ring;
579 unsigned int cur_rx; /* RX buf index of next pkt */
580 dma_addr_t rx_ring_dma;
581
582 unsigned int tx_flag;
583 unsigned long cur_tx;
584 unsigned long dirty_tx;
585 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
586 unsigned char *tx_bufs; /* Tx bounce buffer region. */
587 dma_addr_t tx_bufs_dma;
588
589 signed char phys[4]; /* MII device addresses. */
590
591 /* Twister tune state. */
592 char twistie, twist_row, twist_col;
593
594 unsigned int watchdog_fired : 1;
595 unsigned int default_port : 4; /* Last dev->if_port value. */
596 unsigned int have_thread : 1;
597
598 spinlock_t lock;
599 spinlock_t rx_lock;
600
601 chip_t chipset;
602 u32 rx_config;
603 struct rtl_extra_stats xstats;
604
605 struct delayed_work thread;
606
607 struct mii_if_info mii;
608 unsigned int regs_len;
609 unsigned long fifo_copy_timeout;
610 };
611
612 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
613 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
614 MODULE_LICENSE("GPL");
615 MODULE_VERSION(DRV_VERSION);
616
617 module_param(multicast_filter_limit, int, 0);
618 module_param_array(media, int, NULL, 0);
619 module_param_array(full_duplex, int, NULL, 0);
620 module_param(debug, int, 0);
621 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
622 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
623 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
624 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
625
626 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
627 static int rtl8139_open (struct net_device *dev);
628 static int mdio_read (struct net_device *dev, int phy_id, int location);
629 static void mdio_write (struct net_device *dev, int phy_id, int location,
630 int val);
631 static void rtl8139_start_thread(struct rtl8139_private *tp);
632 static void rtl8139_tx_timeout (struct net_device *dev);
633 static void rtl8139_init_ring (struct net_device *dev);
634 static int rtl8139_start_xmit (struct sk_buff *skb,
635 struct net_device *dev);
636 #ifdef CONFIG_NET_POLL_CONTROLLER
637 static void rtl8139_poll_controller(struct net_device *dev);
638 #endif
639 static int rtl8139_poll(struct napi_struct *napi, int budget);
640 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
641 static int rtl8139_close (struct net_device *dev);
642 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
643 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
644 static void rtl8139_set_rx_mode (struct net_device *dev);
645 static void __set_rx_mode (struct net_device *dev);
646 static void rtl8139_hw_start (struct net_device *dev);
647 static void rtl8139_thread (struct work_struct *work);
648 static void rtl8139_tx_timeout_task(struct work_struct *work);
649 static const struct ethtool_ops rtl8139_ethtool_ops;
650
651 /* write MMIO register, with flush */
652 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
653 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
654 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
655 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
656
657 /* write MMIO register */
658 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
659 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
660 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
661
662 /* read MMIO register */
663 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
664 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
665 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
666
667
668 static const u16 rtl8139_intr_mask =
669 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
670 TxErr | TxOK | RxErr | RxOK;
671
672 static const u16 rtl8139_norx_intr_mask =
673 PCIErr | PCSTimeout | RxUnderrun |
674 TxErr | TxOK | RxErr ;
675
676 #if RX_BUF_IDX == 0
677 static const unsigned int rtl8139_rx_config =
678 RxCfgRcv8K | RxNoWrap |
679 (RX_FIFO_THRESH << RxCfgFIFOShift) |
680 (RX_DMA_BURST << RxCfgDMAShift);
681 #elif RX_BUF_IDX == 1
682 static const unsigned int rtl8139_rx_config =
683 RxCfgRcv16K | RxNoWrap |
684 (RX_FIFO_THRESH << RxCfgFIFOShift) |
685 (RX_DMA_BURST << RxCfgDMAShift);
686 #elif RX_BUF_IDX == 2
687 static const unsigned int rtl8139_rx_config =
688 RxCfgRcv32K | RxNoWrap |
689 (RX_FIFO_THRESH << RxCfgFIFOShift) |
690 (RX_DMA_BURST << RxCfgDMAShift);
691 #elif RX_BUF_IDX == 3
692 static const unsigned int rtl8139_rx_config =
693 RxCfgRcv64K |
694 (RX_FIFO_THRESH << RxCfgFIFOShift) |
695 (RX_DMA_BURST << RxCfgDMAShift);
696 #else
697 #error "Invalid configuration for 8139_RXBUF_IDX"
698 #endif
699
700 static const unsigned int rtl8139_tx_config =
701 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
702
703 static void __rtl8139_cleanup_dev (struct net_device *dev)
704 {
705 struct rtl8139_private *tp = netdev_priv(dev);
706 struct pci_dev *pdev;
707
708 assert (dev != NULL);
709 assert (tp->pci_dev != NULL);
710 pdev = tp->pci_dev;
711
712 #ifdef USE_IO_OPS
713 if (tp->mmio_addr)
714 ioport_unmap (tp->mmio_addr);
715 #else
716 if (tp->mmio_addr)
717 pci_iounmap (pdev, tp->mmio_addr);
718 #endif /* USE_IO_OPS */
719
720 /* it's ok to call this even if we have no regions to free */
721 pci_release_regions (pdev);
722
723 free_netdev(dev);
724 pci_set_drvdata (pdev, NULL);
725 }
726
727
728 static void rtl8139_chip_reset (void __iomem *ioaddr)
729 {
730 int i;
731
732 /* Soft reset the chip. */
733 RTL_W8 (ChipCmd, CmdReset);
734
735 /* Check that the chip has finished the reset. */
736 for (i = 1000; i > 0; i--) {
737 barrier();
738 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
739 break;
740 udelay (10);
741 }
742 }
743
744
745 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
746 struct net_device **dev_out)
747 {
748 void __iomem *ioaddr;
749 struct net_device *dev;
750 struct rtl8139_private *tp;
751 u8 tmp8;
752 int rc, disable_dev_on_err = 0;
753 unsigned int i;
754 unsigned long pio_start, pio_end, pio_flags, pio_len;
755 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
756 u32 version;
757
758 assert (pdev != NULL);
759
760 *dev_out = NULL;
761
762 /* dev and priv zeroed in alloc_etherdev */
763 dev = alloc_etherdev (sizeof (*tp));
764 if (dev == NULL) {
765 dev_err(&pdev->dev, "Unable to alloc new net device\n");
766 return -ENOMEM;
767 }
768 SET_NETDEV_DEV(dev, &pdev->dev);
769
770 tp = netdev_priv(dev);
771 tp->pci_dev = pdev;
772
773 /* enable device (incl. PCI PM wakeup and hotplug setup) */
774 rc = pci_enable_device (pdev);
775 if (rc)
776 goto err_out;
777
778 pio_start = pci_resource_start (pdev, 0);
779 pio_end = pci_resource_end (pdev, 0);
780 pio_flags = pci_resource_flags (pdev, 0);
781 pio_len = pci_resource_len (pdev, 0);
782
783 mmio_start = pci_resource_start (pdev, 1);
784 mmio_end = pci_resource_end (pdev, 1);
785 mmio_flags = pci_resource_flags (pdev, 1);
786 mmio_len = pci_resource_len (pdev, 1);
787
788 /* set this immediately, we need to know before
789 * we talk to the chip directly */
790 DPRINTK("PIO region size == 0x%02X\n", pio_len);
791 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
792
793 #ifdef USE_IO_OPS
794 /* make sure PCI base addr 0 is PIO */
795 if (!(pio_flags & IORESOURCE_IO)) {
796 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
797 rc = -ENODEV;
798 goto err_out;
799 }
800 /* check for weird/broken PCI region reporting */
801 if (pio_len < RTL_MIN_IO_SIZE) {
802 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
803 rc = -ENODEV;
804 goto err_out;
805 }
806 #else
807 /* make sure PCI base addr 1 is MMIO */
808 if (!(mmio_flags & IORESOURCE_MEM)) {
809 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
810 rc = -ENODEV;
811 goto err_out;
812 }
813 if (mmio_len < RTL_MIN_IO_SIZE) {
814 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
815 rc = -ENODEV;
816 goto err_out;
817 }
818 #endif
819
820 rc = pci_request_regions (pdev, DRV_NAME);
821 if (rc)
822 goto err_out;
823 disable_dev_on_err = 1;
824
825 /* enable PCI bus-mastering */
826 pci_set_master (pdev);
827
828 #ifdef USE_IO_OPS
829 ioaddr = ioport_map(pio_start, pio_len);
830 if (!ioaddr) {
831 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
832 rc = -EIO;
833 goto err_out;
834 }
835 dev->base_addr = pio_start;
836 tp->mmio_addr = ioaddr;
837 tp->regs_len = pio_len;
838 #else
839 /* ioremap MMIO region */
840 ioaddr = pci_iomap(pdev, 1, 0);
841 if (ioaddr == NULL) {
842 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
843 rc = -EIO;
844 goto err_out;
845 }
846 dev->base_addr = (long) ioaddr;
847 tp->mmio_addr = ioaddr;
848 tp->regs_len = mmio_len;
849 #endif /* USE_IO_OPS */
850
851 /* Bring old chips out of low-power mode. */
852 RTL_W8 (HltClk, 'R');
853
854 /* check for missing/broken hardware */
855 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
856 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
857 rc = -EIO;
858 goto err_out;
859 }
860
861 /* identify chip attached to board */
862 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
863 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
864 if (version == rtl_chip_info[i].version) {
865 tp->chipset = i;
866 goto match;
867 }
868
869 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
870 dev_printk (KERN_DEBUG, &pdev->dev,
871 "unknown chip version, assuming RTL-8139\n");
872 dev_printk (KERN_DEBUG, &pdev->dev,
873 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
874 tp->chipset = 0;
875
876 match:
877 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
878 version, i, rtl_chip_info[i].name);
879
880 if (tp->chipset >= CH_8139B) {
881 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
882 DPRINTK("PCI PM wakeup\n");
883 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
884 (tmp8 & LWAKE))
885 new_tmp8 &= ~LWAKE;
886 new_tmp8 |= Cfg1_PM_Enable;
887 if (new_tmp8 != tmp8) {
888 RTL_W8 (Cfg9346, Cfg9346_Unlock);
889 RTL_W8 (Config1, tmp8);
890 RTL_W8 (Cfg9346, Cfg9346_Lock);
891 }
892 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
893 tmp8 = RTL_R8 (Config4);
894 if (tmp8 & LWPTN) {
895 RTL_W8 (Cfg9346, Cfg9346_Unlock);
896 RTL_W8 (Config4, tmp8 & ~LWPTN);
897 RTL_W8 (Cfg9346, Cfg9346_Lock);
898 }
899 }
900 } else {
901 DPRINTK("Old chip wakeup\n");
902 tmp8 = RTL_R8 (Config1);
903 tmp8 &= ~(SLEEP | PWRDN);
904 RTL_W8 (Config1, tmp8);
905 }
906
907 rtl8139_chip_reset (ioaddr);
908
909 *dev_out = dev;
910 return 0;
911
912 err_out:
913 __rtl8139_cleanup_dev (dev);
914 if (disable_dev_on_err)
915 pci_disable_device (pdev);
916 return rc;
917 }
918
919
920 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
921 const struct pci_device_id *ent)
922 {
923 struct net_device *dev = NULL;
924 struct rtl8139_private *tp;
925 int i, addr_len, option;
926 void __iomem *ioaddr;
927 static int board_idx = -1;
928 DECLARE_MAC_BUF(mac);
929
930 assert (pdev != NULL);
931 assert (ent != NULL);
932
933 board_idx++;
934
935 /* when we're built into the kernel, the driver version message
936 * is only printed if at least one 8139 board has been found
937 */
938 #ifndef MODULE
939 {
940 static int printed_version;
941 if (!printed_version++)
942 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
943 }
944 #endif
945
946 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
947 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
948 dev_info(&pdev->dev,
949 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
950 pdev->vendor, pdev->device, pdev->revision);
951 dev_info(&pdev->dev,
952 "Use the \"8139cp\" driver for improved performance and stability.\n");
953 }
954
955 i = rtl8139_init_board (pdev, &dev);
956 if (i < 0)
957 return i;
958
959 assert (dev != NULL);
960 tp = netdev_priv(dev);
961 tp->dev = dev;
962
963 ioaddr = tp->mmio_addr;
964 assert (ioaddr != NULL);
965
966 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
967 for (i = 0; i < 3; i++)
968 ((__le16 *) (dev->dev_addr))[i] =
969 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
970 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
971
972 /* The Rtl8139-specific entries in the device structure. */
973 dev->open = rtl8139_open;
974 dev->hard_start_xmit = rtl8139_start_xmit;
975 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
976 dev->stop = rtl8139_close;
977 dev->get_stats = rtl8139_get_stats;
978 dev->set_multicast_list = rtl8139_set_rx_mode;
979 dev->do_ioctl = netdev_ioctl;
980 dev->ethtool_ops = &rtl8139_ethtool_ops;
981 dev->tx_timeout = rtl8139_tx_timeout;
982 dev->watchdog_timeo = TX_TIMEOUT;
983 #ifdef CONFIG_NET_POLL_CONTROLLER
984 dev->poll_controller = rtl8139_poll_controller;
985 #endif
986
987 /* note: the hardware is not capable of sg/csum/highdma, however
988 * through the use of skb_copy_and_csum_dev we enable these
989 * features
990 */
991 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
992
993 dev->irq = pdev->irq;
994
995 /* tp zeroed and aligned in alloc_etherdev */
996 tp = netdev_priv(dev);
997
998 /* note: tp->chipset set in rtl8139_init_board */
999 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1000 tp->mmio_addr = ioaddr;
1001 tp->msg_enable =
1002 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1003 spin_lock_init (&tp->lock);
1004 spin_lock_init (&tp->rx_lock);
1005 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1006 tp->mii.dev = dev;
1007 tp->mii.mdio_read = mdio_read;
1008 tp->mii.mdio_write = mdio_write;
1009 tp->mii.phy_id_mask = 0x3f;
1010 tp->mii.reg_num_mask = 0x1f;
1011
1012 /* dev is fully set up and ready to use now */
1013 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1014 i = register_netdev (dev);
1015 if (i) goto err_out;
1016
1017 pci_set_drvdata (pdev, dev);
1018
1019 printk (KERN_INFO "%s: %s at 0x%lx, "
1020 "%s, IRQ %d\n",
1021 dev->name,
1022 board_info[ent->driver_data].name,
1023 dev->base_addr,
1024 print_mac(mac, dev->dev_addr),
1025 dev->irq);
1026
1027 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1028 dev->name, rtl_chip_info[tp->chipset].name);
1029
1030 /* Find the connected MII xcvrs.
1031 Doing this in open() would allow detecting external xcvrs later, but
1032 takes too much time. */
1033 #ifdef CONFIG_8139TOO_8129
1034 if (tp->drv_flags & HAS_MII_XCVR) {
1035 int phy, phy_idx = 0;
1036 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1037 int mii_status = mdio_read(dev, phy, 1);
1038 if (mii_status != 0xffff && mii_status != 0x0000) {
1039 u16 advertising = mdio_read(dev, phy, 4);
1040 tp->phys[phy_idx++] = phy;
1041 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1042 "advertising %4.4x.\n",
1043 dev->name, phy, mii_status, advertising);
1044 }
1045 }
1046 if (phy_idx == 0) {
1047 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1048 "transceiver.\n",
1049 dev->name);
1050 tp->phys[0] = 32;
1051 }
1052 } else
1053 #endif
1054 tp->phys[0] = 32;
1055 tp->mii.phy_id = tp->phys[0];
1056
1057 /* The lower four bits are the media type. */
1058 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1059 if (option > 0) {
1060 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1061 tp->default_port = option & 0xFF;
1062 if (tp->default_port)
1063 tp->mii.force_media = 1;
1064 }
1065 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1066 tp->mii.full_duplex = full_duplex[board_idx];
1067 if (tp->mii.full_duplex) {
1068 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1069 /* Changing the MII-advertised media because might prevent
1070 re-connection. */
1071 tp->mii.force_media = 1;
1072 }
1073 if (tp->default_port) {
1074 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1075 (option & 0x20 ? 100 : 10),
1076 (option & 0x10 ? "full" : "half"));
1077 mdio_write(dev, tp->phys[0], 0,
1078 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1079 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1080 }
1081
1082 /* Put the chip into low-power mode. */
1083 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1084 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1085
1086 return 0;
1087
1088 err_out:
1089 __rtl8139_cleanup_dev (dev);
1090 pci_disable_device (pdev);
1091 return i;
1092 }
1093
1094
1095 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1096 {
1097 struct net_device *dev = pci_get_drvdata (pdev);
1098
1099 assert (dev != NULL);
1100
1101 flush_scheduled_work();
1102
1103 unregister_netdev (dev);
1104
1105 __rtl8139_cleanup_dev (dev);
1106 pci_disable_device (pdev);
1107 }
1108
1109
1110 /* Serial EEPROM section. */
1111
1112 /* EEPROM_Ctrl bits. */
1113 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1114 #define EE_CS 0x08 /* EEPROM chip select. */
1115 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1116 #define EE_WRITE_0 0x00
1117 #define EE_WRITE_1 0x02
1118 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1119 #define EE_ENB (0x80 | EE_CS)
1120
1121 /* Delay between EEPROM clock transitions.
1122 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1123 */
1124
1125 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1126
1127 /* The EEPROM commands include the alway-set leading bit. */
1128 #define EE_WRITE_CMD (5)
1129 #define EE_READ_CMD (6)
1130 #define EE_ERASE_CMD (7)
1131
1132 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1133 {
1134 int i;
1135 unsigned retval = 0;
1136 int read_cmd = location | (EE_READ_CMD << addr_len);
1137
1138 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1139 RTL_W8 (Cfg9346, EE_ENB);
1140 eeprom_delay ();
1141
1142 /* Shift the read command bits out. */
1143 for (i = 4 + addr_len; i >= 0; i--) {
1144 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1145 RTL_W8 (Cfg9346, EE_ENB | dataval);
1146 eeprom_delay ();
1147 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1148 eeprom_delay ();
1149 }
1150 RTL_W8 (Cfg9346, EE_ENB);
1151 eeprom_delay ();
1152
1153 for (i = 16; i > 0; i--) {
1154 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1155 eeprom_delay ();
1156 retval =
1157 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1158 0);
1159 RTL_W8 (Cfg9346, EE_ENB);
1160 eeprom_delay ();
1161 }
1162
1163 /* Terminate the EEPROM access. */
1164 RTL_W8 (Cfg9346, ~EE_CS);
1165 eeprom_delay ();
1166
1167 return retval;
1168 }
1169
1170 /* MII serial management: mostly bogus for now. */
1171 /* Read and write the MII management registers using software-generated
1172 serial MDIO protocol.
1173 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1174 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1175 "overclocking" issues. */
1176 #define MDIO_DIR 0x80
1177 #define MDIO_DATA_OUT 0x04
1178 #define MDIO_DATA_IN 0x02
1179 #define MDIO_CLK 0x01
1180 #define MDIO_WRITE0 (MDIO_DIR)
1181 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1182
1183 #define mdio_delay() RTL_R8(Config4)
1184
1185
1186 static const char mii_2_8139_map[8] = {
1187 BasicModeCtrl,
1188 BasicModeStatus,
1189 0,
1190 0,
1191 NWayAdvert,
1192 NWayLPAR,
1193 NWayExpansion,
1194 0
1195 };
1196
1197
1198 #ifdef CONFIG_8139TOO_8129
1199 /* Syncronize the MII management interface by shifting 32 one bits out. */
1200 static void mdio_sync (void __iomem *ioaddr)
1201 {
1202 int i;
1203
1204 for (i = 32; i >= 0; i--) {
1205 RTL_W8 (Config4, MDIO_WRITE1);
1206 mdio_delay ();
1207 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1208 mdio_delay ();
1209 }
1210 }
1211 #endif
1212
1213 static int mdio_read (struct net_device *dev, int phy_id, int location)
1214 {
1215 struct rtl8139_private *tp = netdev_priv(dev);
1216 int retval = 0;
1217 #ifdef CONFIG_8139TOO_8129
1218 void __iomem *ioaddr = tp->mmio_addr;
1219 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1220 int i;
1221 #endif
1222
1223 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1224 void __iomem *ioaddr = tp->mmio_addr;
1225 return location < 8 && mii_2_8139_map[location] ?
1226 RTL_R16 (mii_2_8139_map[location]) : 0;
1227 }
1228
1229 #ifdef CONFIG_8139TOO_8129
1230 mdio_sync (ioaddr);
1231 /* Shift the read command bits out. */
1232 for (i = 15; i >= 0; i--) {
1233 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1234
1235 RTL_W8 (Config4, MDIO_DIR | dataval);
1236 mdio_delay ();
1237 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1238 mdio_delay ();
1239 }
1240
1241 /* Read the two transition, 16 data, and wire-idle bits. */
1242 for (i = 19; i > 0; i--) {
1243 RTL_W8 (Config4, 0);
1244 mdio_delay ();
1245 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1246 RTL_W8 (Config4, MDIO_CLK);
1247 mdio_delay ();
1248 }
1249 #endif
1250
1251 return (retval >> 1) & 0xffff;
1252 }
1253
1254
1255 static void mdio_write (struct net_device *dev, int phy_id, int location,
1256 int value)
1257 {
1258 struct rtl8139_private *tp = netdev_priv(dev);
1259 #ifdef CONFIG_8139TOO_8129
1260 void __iomem *ioaddr = tp->mmio_addr;
1261 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1262 int i;
1263 #endif
1264
1265 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1266 void __iomem *ioaddr = tp->mmio_addr;
1267 if (location == 0) {
1268 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1269 RTL_W16 (BasicModeCtrl, value);
1270 RTL_W8 (Cfg9346, Cfg9346_Lock);
1271 } else if (location < 8 && mii_2_8139_map[location])
1272 RTL_W16 (mii_2_8139_map[location], value);
1273 return;
1274 }
1275
1276 #ifdef CONFIG_8139TOO_8129
1277 mdio_sync (ioaddr);
1278
1279 /* Shift the command bits out. */
1280 for (i = 31; i >= 0; i--) {
1281 int dataval =
1282 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1283 RTL_W8 (Config4, dataval);
1284 mdio_delay ();
1285 RTL_W8 (Config4, dataval | MDIO_CLK);
1286 mdio_delay ();
1287 }
1288 /* Clear out extra bits. */
1289 for (i = 2; i > 0; i--) {
1290 RTL_W8 (Config4, 0);
1291 mdio_delay ();
1292 RTL_W8 (Config4, MDIO_CLK);
1293 mdio_delay ();
1294 }
1295 #endif
1296 }
1297
1298
1299 static int rtl8139_open (struct net_device *dev)
1300 {
1301 struct rtl8139_private *tp = netdev_priv(dev);
1302 int retval;
1303 void __iomem *ioaddr = tp->mmio_addr;
1304
1305 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1306 if (retval)
1307 return retval;
1308
1309 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1310 &tp->tx_bufs_dma, GFP_KERNEL);
1311 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1312 &tp->rx_ring_dma, GFP_KERNEL);
1313 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1314 free_irq(dev->irq, dev);
1315
1316 if (tp->tx_bufs)
1317 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1318 tp->tx_bufs, tp->tx_bufs_dma);
1319 if (tp->rx_ring)
1320 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1321 tp->rx_ring, tp->rx_ring_dma);
1322
1323 return -ENOMEM;
1324
1325 }
1326
1327 napi_enable(&tp->napi);
1328
1329 tp->mii.full_duplex = tp->mii.force_media;
1330 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1331
1332 rtl8139_init_ring (dev);
1333 rtl8139_hw_start (dev);
1334 netif_start_queue (dev);
1335
1336 if (netif_msg_ifup(tp))
1337 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1338 " GP Pins %2.2x %s-duplex.\n", dev->name,
1339 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1340 dev->irq, RTL_R8 (MediaStatus),
1341 tp->mii.full_duplex ? "full" : "half");
1342
1343 rtl8139_start_thread(tp);
1344
1345 return 0;
1346 }
1347
1348
1349 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1350 {
1351 struct rtl8139_private *tp = netdev_priv(dev);
1352
1353 if (tp->phys[0] >= 0) {
1354 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1355 }
1356 }
1357
1358 /* Start the hardware at open or resume. */
1359 static void rtl8139_hw_start (struct net_device *dev)
1360 {
1361 struct rtl8139_private *tp = netdev_priv(dev);
1362 void __iomem *ioaddr = tp->mmio_addr;
1363 u32 i;
1364 u8 tmp;
1365
1366 /* Bring old chips out of low-power mode. */
1367 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1368 RTL_W8 (HltClk, 'R');
1369
1370 rtl8139_chip_reset (ioaddr);
1371
1372 /* unlock Config[01234] and BMCR register writes */
1373 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1374 /* Restore our idea of the MAC address. */
1375 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1376 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1377
1378 /* Must enable Tx/Rx before setting transfer thresholds! */
1379 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1380
1381 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1382 RTL_W32 (RxConfig, tp->rx_config);
1383 RTL_W32 (TxConfig, rtl8139_tx_config);
1384
1385 tp->cur_rx = 0;
1386
1387 rtl_check_media (dev, 1);
1388
1389 if (tp->chipset >= CH_8139B) {
1390 /* Disable magic packet scanning, which is enabled
1391 * when PM is enabled in Config1. It can be reenabled
1392 * via ETHTOOL_SWOL if desired. */
1393 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1394 }
1395
1396 DPRINTK("init buffer addresses\n");
1397
1398 /* Lock Config[01234] and BMCR register writes */
1399 RTL_W8 (Cfg9346, Cfg9346_Lock);
1400
1401 /* init Rx ring buffer DMA address */
1402 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1403
1404 /* init Tx buffer DMA addresses */
1405 for (i = 0; i < NUM_TX_DESC; i++)
1406 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1407
1408 RTL_W32 (RxMissed, 0);
1409
1410 rtl8139_set_rx_mode (dev);
1411
1412 /* no early-rx interrupts */
1413 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1414
1415 /* make sure RxTx has started */
1416 tmp = RTL_R8 (ChipCmd);
1417 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1418 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1419
1420 /* Enable all known interrupts by setting the interrupt mask. */
1421 RTL_W16 (IntrMask, rtl8139_intr_mask);
1422 }
1423
1424
1425 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1426 static void rtl8139_init_ring (struct net_device *dev)
1427 {
1428 struct rtl8139_private *tp = netdev_priv(dev);
1429 int i;
1430
1431 tp->cur_rx = 0;
1432 tp->cur_tx = 0;
1433 tp->dirty_tx = 0;
1434
1435 for (i = 0; i < NUM_TX_DESC; i++)
1436 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1437 }
1438
1439
1440 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1441 static int next_tick = 3 * HZ;
1442
1443 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1444 static inline void rtl8139_tune_twister (struct net_device *dev,
1445 struct rtl8139_private *tp) {}
1446 #else
1447 enum TwisterParamVals {
1448 PARA78_default = 0x78fa8388,
1449 PARA7c_default = 0xcb38de43, /* param[0][3] */
1450 PARA7c_xxx = 0xcb38de43,
1451 };
1452
1453 static const unsigned long param[4][4] = {
1454 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1455 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1456 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1457 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1458 };
1459
1460 static void rtl8139_tune_twister (struct net_device *dev,
1461 struct rtl8139_private *tp)
1462 {
1463 int linkcase;
1464 void __iomem *ioaddr = tp->mmio_addr;
1465
1466 /* This is a complicated state machine to configure the "twister" for
1467 impedance/echos based on the cable length.
1468 All of this is magic and undocumented.
1469 */
1470 switch (tp->twistie) {
1471 case 1:
1472 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1473 /* We have link beat, let us tune the twister. */
1474 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1475 tp->twistie = 2; /* Change to state 2. */
1476 next_tick = HZ / 10;
1477 } else {
1478 /* Just put in some reasonable defaults for when beat returns. */
1479 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1480 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1481 RTL_W32 (PARA78, PARA78_default);
1482 RTL_W32 (PARA7c, PARA7c_default);
1483 tp->twistie = 0; /* Bail from future actions. */
1484 }
1485 break;
1486 case 2:
1487 /* Read how long it took to hear the echo. */
1488 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1489 if (linkcase == 0x7000)
1490 tp->twist_row = 3;
1491 else if (linkcase == 0x3000)
1492 tp->twist_row = 2;
1493 else if (linkcase == 0x1000)
1494 tp->twist_row = 1;
1495 else
1496 tp->twist_row = 0;
1497 tp->twist_col = 0;
1498 tp->twistie = 3; /* Change to state 2. */
1499 next_tick = HZ / 10;
1500 break;
1501 case 3:
1502 /* Put out four tuning parameters, one per 100msec. */
1503 if (tp->twist_col == 0)
1504 RTL_W16 (FIFOTMS, 0);
1505 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1506 [(int) tp->twist_col]);
1507 next_tick = HZ / 10;
1508 if (++tp->twist_col >= 4) {
1509 /* For short cables we are done.
1510 For long cables (row == 3) check for mistune. */
1511 tp->twistie =
1512 (tp->twist_row == 3) ? 4 : 0;
1513 }
1514 break;
1515 case 4:
1516 /* Special case for long cables: check for mistune. */
1517 if ((RTL_R16 (CSCR) &
1518 CSCR_LinkStatusBits) == 0x7000) {
1519 tp->twistie = 0;
1520 break;
1521 } else {
1522 RTL_W32 (PARA7c, 0xfb38de03);
1523 tp->twistie = 5;
1524 next_tick = HZ / 10;
1525 }
1526 break;
1527 case 5:
1528 /* Retune for shorter cable (column 2). */
1529 RTL_W32 (FIFOTMS, 0x20);
1530 RTL_W32 (PARA78, PARA78_default);
1531 RTL_W32 (PARA7c, PARA7c_default);
1532 RTL_W32 (FIFOTMS, 0x00);
1533 tp->twist_row = 2;
1534 tp->twist_col = 0;
1535 tp->twistie = 3;
1536 next_tick = HZ / 10;
1537 break;
1538
1539 default:
1540 /* do nothing */
1541 break;
1542 }
1543 }
1544 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1545
1546 static inline void rtl8139_thread_iter (struct net_device *dev,
1547 struct rtl8139_private *tp,
1548 void __iomem *ioaddr)
1549 {
1550 int mii_lpa;
1551
1552 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1553
1554 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1555 int duplex = (mii_lpa & LPA_100FULL)
1556 || (mii_lpa & 0x01C0) == 0x0040;
1557 if (tp->mii.full_duplex != duplex) {
1558 tp->mii.full_duplex = duplex;
1559
1560 if (mii_lpa) {
1561 printk (KERN_INFO
1562 "%s: Setting %s-duplex based on MII #%d link"
1563 " partner ability of %4.4x.\n",
1564 dev->name,
1565 tp->mii.full_duplex ? "full" : "half",
1566 tp->phys[0], mii_lpa);
1567 } else {
1568 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1569 dev->name);
1570 }
1571 #if 0
1572 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1573 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1574 RTL_W8 (Cfg9346, Cfg9346_Lock);
1575 #endif
1576 }
1577 }
1578
1579 next_tick = HZ * 60;
1580
1581 rtl8139_tune_twister (dev, tp);
1582
1583 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1584 dev->name, RTL_R16 (NWayLPAR));
1585 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1586 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1587 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1588 dev->name, RTL_R8 (Config0),
1589 RTL_R8 (Config1));
1590 }
1591
1592 static void rtl8139_thread (struct work_struct *work)
1593 {
1594 struct rtl8139_private *tp =
1595 container_of(work, struct rtl8139_private, thread.work);
1596 struct net_device *dev = tp->mii.dev;
1597 unsigned long thr_delay = next_tick;
1598
1599 rtnl_lock();
1600
1601 if (!netif_running(dev))
1602 goto out_unlock;
1603
1604 if (tp->watchdog_fired) {
1605 tp->watchdog_fired = 0;
1606 rtl8139_tx_timeout_task(work);
1607 } else
1608 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1609
1610 if (tp->have_thread)
1611 schedule_delayed_work(&tp->thread, thr_delay);
1612 out_unlock:
1613 rtnl_unlock ();
1614 }
1615
1616 static void rtl8139_start_thread(struct rtl8139_private *tp)
1617 {
1618 tp->twistie = 0;
1619 if (tp->chipset == CH_8139_K)
1620 tp->twistie = 1;
1621 else if (tp->drv_flags & HAS_LNK_CHNG)
1622 return;
1623
1624 tp->have_thread = 1;
1625 tp->watchdog_fired = 0;
1626
1627 schedule_delayed_work(&tp->thread, next_tick);
1628 }
1629
1630 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1631 {
1632 tp->cur_tx = 0;
1633 tp->dirty_tx = 0;
1634
1635 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1636 }
1637
1638 static void rtl8139_tx_timeout_task (struct work_struct *work)
1639 {
1640 struct rtl8139_private *tp =
1641 container_of(work, struct rtl8139_private, thread.work);
1642 struct net_device *dev = tp->mii.dev;
1643 void __iomem *ioaddr = tp->mmio_addr;
1644 int i;
1645 u8 tmp8;
1646
1647 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1648 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1649 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1650 /* Emit info to figure out what went wrong. */
1651 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1652 dev->name, tp->cur_tx, tp->dirty_tx);
1653 for (i = 0; i < NUM_TX_DESC; i++)
1654 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1655 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1656 i == tp->dirty_tx % NUM_TX_DESC ?
1657 " (queue head)" : "");
1658
1659 tp->xstats.tx_timeouts++;
1660
1661 /* disable Tx ASAP, if not already */
1662 tmp8 = RTL_R8 (ChipCmd);
1663 if (tmp8 & CmdTxEnb)
1664 RTL_W8 (ChipCmd, CmdRxEnb);
1665
1666 spin_lock_bh(&tp->rx_lock);
1667 /* Disable interrupts by clearing the interrupt mask. */
1668 RTL_W16 (IntrMask, 0x0000);
1669
1670 /* Stop a shared interrupt from scavenging while we are. */
1671 spin_lock_irq(&tp->lock);
1672 rtl8139_tx_clear (tp);
1673 spin_unlock_irq(&tp->lock);
1674
1675 /* ...and finally, reset everything */
1676 if (netif_running(dev)) {
1677 rtl8139_hw_start (dev);
1678 netif_wake_queue (dev);
1679 }
1680 spin_unlock_bh(&tp->rx_lock);
1681 }
1682
1683 static void rtl8139_tx_timeout (struct net_device *dev)
1684 {
1685 struct rtl8139_private *tp = netdev_priv(dev);
1686
1687 tp->watchdog_fired = 1;
1688 if (!tp->have_thread) {
1689 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1690 schedule_delayed_work(&tp->thread, next_tick);
1691 }
1692 }
1693
1694 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1695 {
1696 struct rtl8139_private *tp = netdev_priv(dev);
1697 void __iomem *ioaddr = tp->mmio_addr;
1698 unsigned int entry;
1699 unsigned int len = skb->len;
1700 unsigned long flags;
1701
1702 /* Calculate the next Tx descriptor entry. */
1703 entry = tp->cur_tx % NUM_TX_DESC;
1704
1705 /* Note: the chip doesn't have auto-pad! */
1706 if (likely(len < TX_BUF_SIZE)) {
1707 if (len < ETH_ZLEN)
1708 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1709 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1710 dev_kfree_skb(skb);
1711 } else {
1712 dev_kfree_skb(skb);
1713 dev->stats.tx_dropped++;
1714 return 0;
1715 }
1716
1717 spin_lock_irqsave(&tp->lock, flags);
1718 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1719 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1720
1721 dev->trans_start = jiffies;
1722
1723 tp->cur_tx++;
1724 wmb();
1725
1726 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1727 netif_stop_queue (dev);
1728 spin_unlock_irqrestore(&tp->lock, flags);
1729
1730 if (netif_msg_tx_queued(tp))
1731 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1732 dev->name, len, entry);
1733
1734 return 0;
1735 }
1736
1737
1738 static void rtl8139_tx_interrupt (struct net_device *dev,
1739 struct rtl8139_private *tp,
1740 void __iomem *ioaddr)
1741 {
1742 unsigned long dirty_tx, tx_left;
1743
1744 assert (dev != NULL);
1745 assert (ioaddr != NULL);
1746
1747 dirty_tx = tp->dirty_tx;
1748 tx_left = tp->cur_tx - dirty_tx;
1749 while (tx_left > 0) {
1750 int entry = dirty_tx % NUM_TX_DESC;
1751 int txstatus;
1752
1753 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1754
1755 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1756 break; /* It still hasn't been Txed */
1757
1758 /* Note: TxCarrierLost is always asserted at 100mbps. */
1759 if (txstatus & (TxOutOfWindow | TxAborted)) {
1760 /* There was an major error, log it. */
1761 if (netif_msg_tx_err(tp))
1762 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1763 dev->name, txstatus);
1764 dev->stats.tx_errors++;
1765 if (txstatus & TxAborted) {
1766 dev->stats.tx_aborted_errors++;
1767 RTL_W32 (TxConfig, TxClearAbt);
1768 RTL_W16 (IntrStatus, TxErr);
1769 wmb();
1770 }
1771 if (txstatus & TxCarrierLost)
1772 dev->stats.tx_carrier_errors++;
1773 if (txstatus & TxOutOfWindow)
1774 dev->stats.tx_window_errors++;
1775 } else {
1776 if (txstatus & TxUnderrun) {
1777 /* Add 64 to the Tx FIFO threshold. */
1778 if (tp->tx_flag < 0x00300000)
1779 tp->tx_flag += 0x00020000;
1780 dev->stats.tx_fifo_errors++;
1781 }
1782 dev->stats.collisions += (txstatus >> 24) & 15;
1783 dev->stats.tx_bytes += txstatus & 0x7ff;
1784 dev->stats.tx_packets++;
1785 }
1786
1787 dirty_tx++;
1788 tx_left--;
1789 }
1790
1791 #ifndef RTL8139_NDEBUG
1792 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1793 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1794 dev->name, dirty_tx, tp->cur_tx);
1795 dirty_tx += NUM_TX_DESC;
1796 }
1797 #endif /* RTL8139_NDEBUG */
1798
1799 /* only wake the queue if we did work, and the queue is stopped */
1800 if (tp->dirty_tx != dirty_tx) {
1801 tp->dirty_tx = dirty_tx;
1802 mb();
1803 netif_wake_queue (dev);
1804 }
1805 }
1806
1807
1808 /* TODO: clean this up! Rx reset need not be this intensive */
1809 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1810 struct rtl8139_private *tp, void __iomem *ioaddr)
1811 {
1812 u8 tmp8;
1813 #ifdef CONFIG_8139_OLD_RX_RESET
1814 int tmp_work;
1815 #endif
1816
1817 if (netif_msg_rx_err (tp))
1818 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1819 dev->name, rx_status);
1820 dev->stats.rx_errors++;
1821 if (!(rx_status & RxStatusOK)) {
1822 if (rx_status & RxTooLong) {
1823 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1824 dev->name, rx_status);
1825 /* A.C.: The chip hangs here. */
1826 }
1827 if (rx_status & (RxBadSymbol | RxBadAlign))
1828 dev->stats.rx_frame_errors++;
1829 if (rx_status & (RxRunt | RxTooLong))
1830 dev->stats.rx_length_errors++;
1831 if (rx_status & RxCRCErr)
1832 dev->stats.rx_crc_errors++;
1833 } else {
1834 tp->xstats.rx_lost_in_ring++;
1835 }
1836
1837 #ifndef CONFIG_8139_OLD_RX_RESET
1838 tmp8 = RTL_R8 (ChipCmd);
1839 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1840 RTL_W8 (ChipCmd, tmp8);
1841 RTL_W32 (RxConfig, tp->rx_config);
1842 tp->cur_rx = 0;
1843 #else
1844 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1845
1846 /* disable receive */
1847 RTL_W8_F (ChipCmd, CmdTxEnb);
1848 tmp_work = 200;
1849 while (--tmp_work > 0) {
1850 udelay(1);
1851 tmp8 = RTL_R8 (ChipCmd);
1852 if (!(tmp8 & CmdRxEnb))
1853 break;
1854 }
1855 if (tmp_work <= 0)
1856 printk (KERN_WARNING PFX "rx stop wait too long\n");
1857 /* restart receive */
1858 tmp_work = 200;
1859 while (--tmp_work > 0) {
1860 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1861 udelay(1);
1862 tmp8 = RTL_R8 (ChipCmd);
1863 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1864 break;
1865 }
1866 if (tmp_work <= 0)
1867 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1868
1869 /* and reinitialize all rx related registers */
1870 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1871 /* Must enable Tx/Rx before setting transfer thresholds! */
1872 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1873
1874 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1875 RTL_W32 (RxConfig, tp->rx_config);
1876 tp->cur_rx = 0;
1877
1878 DPRINTK("init buffer addresses\n");
1879
1880 /* Lock Config[01234] and BMCR register writes */
1881 RTL_W8 (Cfg9346, Cfg9346_Lock);
1882
1883 /* init Rx ring buffer DMA address */
1884 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1885
1886 /* A.C.: Reset the multicast list. */
1887 __set_rx_mode (dev);
1888 #endif
1889 }
1890
1891 #if RX_BUF_IDX == 3
1892 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1893 u32 offset, unsigned int size)
1894 {
1895 u32 left = RX_BUF_LEN - offset;
1896
1897 if (size > left) {
1898 skb_copy_to_linear_data(skb, ring + offset, left);
1899 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1900 } else
1901 skb_copy_to_linear_data(skb, ring + offset, size);
1902 }
1903 #endif
1904
1905 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1906 {
1907 void __iomem *ioaddr = tp->mmio_addr;
1908 u16 status;
1909
1910 status = RTL_R16 (IntrStatus) & RxAckBits;
1911
1912 /* Clear out errors and receive interrupts */
1913 if (likely(status != 0)) {
1914 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1915 tp->dev->stats.rx_errors++;
1916 if (status & RxFIFOOver)
1917 tp->dev->stats.rx_fifo_errors++;
1918 }
1919 RTL_W16_F (IntrStatus, RxAckBits);
1920 }
1921 }
1922
1923 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1924 int budget)
1925 {
1926 void __iomem *ioaddr = tp->mmio_addr;
1927 int received = 0;
1928 unsigned char *rx_ring = tp->rx_ring;
1929 unsigned int cur_rx = tp->cur_rx;
1930 unsigned int rx_size = 0;
1931
1932 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1933 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1934 RTL_R16 (RxBufAddr),
1935 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1936
1937 while (netif_running(dev) && received < budget
1938 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1939 u32 ring_offset = cur_rx % RX_BUF_LEN;
1940 u32 rx_status;
1941 unsigned int pkt_size;
1942 struct sk_buff *skb;
1943
1944 rmb();
1945
1946 /* read size+status of next frame from DMA ring buffer */
1947 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1948 rx_size = rx_status >> 16;
1949 pkt_size = rx_size - 4;
1950
1951 if (netif_msg_rx_status(tp))
1952 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1953 " cur %4.4x.\n", dev->name, rx_status,
1954 rx_size, cur_rx);
1955 #if RTL8139_DEBUG > 2
1956 {
1957 int i;
1958 DPRINTK ("%s: Frame contents ", dev->name);
1959 for (i = 0; i < 70; i++)
1960 printk (" %2.2x",
1961 rx_ring[ring_offset + i]);
1962 printk (".\n");
1963 }
1964 #endif
1965
1966 /* Packet copy from FIFO still in progress.
1967 * Theoretically, this should never happen
1968 * since EarlyRx is disabled.
1969 */
1970 if (unlikely(rx_size == 0xfff0)) {
1971 if (!tp->fifo_copy_timeout)
1972 tp->fifo_copy_timeout = jiffies + 2;
1973 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1974 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1975 rx_size = 0;
1976 goto no_early_rx;
1977 }
1978 if (netif_msg_intr(tp)) {
1979 printk(KERN_DEBUG "%s: fifo copy in progress.",
1980 dev->name);
1981 }
1982 tp->xstats.early_rx++;
1983 break;
1984 }
1985
1986 no_early_rx:
1987 tp->fifo_copy_timeout = 0;
1988
1989 /* If Rx err or invalid rx_size/rx_status received
1990 * (which happens if we get lost in the ring),
1991 * Rx process gets reset, so we abort any further
1992 * Rx processing.
1993 */
1994 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1995 (rx_size < 8) ||
1996 (!(rx_status & RxStatusOK)))) {
1997 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1998 received = -1;
1999 goto out;
2000 }
2001
2002 /* Malloc up new buffer, compatible with net-2e. */
2003 /* Omit the four octet CRC from the length. */
2004
2005 skb = dev_alloc_skb (pkt_size + 2);
2006 if (likely(skb)) {
2007 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2008 #if RX_BUF_IDX == 3
2009 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2010 #else
2011 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2012 #endif
2013 skb_put (skb, pkt_size);
2014
2015 skb->protocol = eth_type_trans (skb, dev);
2016
2017 dev->last_rx = jiffies;
2018 dev->stats.rx_bytes += pkt_size;
2019 dev->stats.rx_packets++;
2020
2021 netif_receive_skb (skb);
2022 } else {
2023 if (net_ratelimit())
2024 printk (KERN_WARNING
2025 "%s: Memory squeeze, dropping packet.\n",
2026 dev->name);
2027 dev->stats.rx_dropped++;
2028 }
2029 received++;
2030
2031 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2032 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2033
2034 rtl8139_isr_ack(tp);
2035 }
2036
2037 if (unlikely(!received || rx_size == 0xfff0))
2038 rtl8139_isr_ack(tp);
2039
2040 #if RTL8139_DEBUG > 1
2041 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2042 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2043 RTL_R16 (RxBufAddr),
2044 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2045 #endif
2046
2047 tp->cur_rx = cur_rx;
2048
2049 /*
2050 * The receive buffer should be mostly empty.
2051 * Tell NAPI to reenable the Rx irq.
2052 */
2053 if (tp->fifo_copy_timeout)
2054 received = budget;
2055
2056 out:
2057 return received;
2058 }
2059
2060
2061 static void rtl8139_weird_interrupt (struct net_device *dev,
2062 struct rtl8139_private *tp,
2063 void __iomem *ioaddr,
2064 int status, int link_changed)
2065 {
2066 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2067 dev->name, status);
2068
2069 assert (dev != NULL);
2070 assert (tp != NULL);
2071 assert (ioaddr != NULL);
2072
2073 /* Update the error count. */
2074 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2075 RTL_W32 (RxMissed, 0);
2076
2077 if ((status & RxUnderrun) && link_changed &&
2078 (tp->drv_flags & HAS_LNK_CHNG)) {
2079 rtl_check_media(dev, 0);
2080 status &= ~RxUnderrun;
2081 }
2082
2083 if (status & (RxUnderrun | RxErr))
2084 dev->stats.rx_errors++;
2085
2086 if (status & PCSTimeout)
2087 dev->stats.rx_length_errors++;
2088 if (status & RxUnderrun)
2089 dev->stats.rx_fifo_errors++;
2090 if (status & PCIErr) {
2091 u16 pci_cmd_status;
2092 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2093 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2094
2095 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2096 dev->name, pci_cmd_status);
2097 }
2098 }
2099
2100 static int rtl8139_poll(struct napi_struct *napi, int budget)
2101 {
2102 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2103 struct net_device *dev = tp->dev;
2104 void __iomem *ioaddr = tp->mmio_addr;
2105 int work_done;
2106
2107 spin_lock(&tp->rx_lock);
2108 work_done = 0;
2109 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2110 work_done += rtl8139_rx(dev, tp, budget);
2111
2112 if (work_done < budget) {
2113 unsigned long flags;
2114 /*
2115 * Order is important since data can get interrupted
2116 * again when we think we are done.
2117 */
2118 spin_lock_irqsave(&tp->lock, flags);
2119 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2120 __netif_rx_complete(dev, napi);
2121 spin_unlock_irqrestore(&tp->lock, flags);
2122 }
2123 spin_unlock(&tp->rx_lock);
2124
2125 return work_done;
2126 }
2127
2128 /* The interrupt handler does all of the Rx thread work and cleans up
2129 after the Tx thread. */
2130 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2131 {
2132 struct net_device *dev = (struct net_device *) dev_instance;
2133 struct rtl8139_private *tp = netdev_priv(dev);
2134 void __iomem *ioaddr = tp->mmio_addr;
2135 u16 status, ackstat;
2136 int link_changed = 0; /* avoid bogus "uninit" warning */
2137 int handled = 0;
2138
2139 spin_lock (&tp->lock);
2140 status = RTL_R16 (IntrStatus);
2141
2142 /* shared irq? */
2143 if (unlikely((status & rtl8139_intr_mask) == 0))
2144 goto out;
2145
2146 handled = 1;
2147
2148 /* h/w no longer present (hotplug?) or major error, bail */
2149 if (unlikely(status == 0xFFFF))
2150 goto out;
2151
2152 /* close possible race's with dev_close */
2153 if (unlikely(!netif_running(dev))) {
2154 RTL_W16 (IntrMask, 0);
2155 goto out;
2156 }
2157
2158 /* Acknowledge all of the current interrupt sources ASAP, but
2159 an first get an additional status bit from CSCR. */
2160 if (unlikely(status & RxUnderrun))
2161 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2162
2163 ackstat = status & ~(RxAckBits | TxErr);
2164 if (ackstat)
2165 RTL_W16 (IntrStatus, ackstat);
2166
2167 /* Receive packets are processed by poll routine.
2168 If not running start it now. */
2169 if (status & RxAckBits){
2170 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2171 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2172 __netif_rx_schedule(dev, &tp->napi);
2173 }
2174 }
2175
2176 /* Check uncommon events with one test. */
2177 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2178 rtl8139_weird_interrupt (dev, tp, ioaddr,
2179 status, link_changed);
2180
2181 if (status & (TxOK | TxErr)) {
2182 rtl8139_tx_interrupt (dev, tp, ioaddr);
2183 if (status & TxErr)
2184 RTL_W16 (IntrStatus, TxErr);
2185 }
2186 out:
2187 spin_unlock (&tp->lock);
2188
2189 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2190 dev->name, RTL_R16 (IntrStatus));
2191 return IRQ_RETVAL(handled);
2192 }
2193
2194 #ifdef CONFIG_NET_POLL_CONTROLLER
2195 /*
2196 * Polling receive - used by netconsole and other diagnostic tools
2197 * to allow network i/o with interrupts disabled.
2198 */
2199 static void rtl8139_poll_controller(struct net_device *dev)
2200 {
2201 disable_irq(dev->irq);
2202 rtl8139_interrupt(dev->irq, dev);
2203 enable_irq(dev->irq);
2204 }
2205 #endif
2206
2207 static int rtl8139_close (struct net_device *dev)
2208 {
2209 struct rtl8139_private *tp = netdev_priv(dev);
2210 void __iomem *ioaddr = tp->mmio_addr;
2211 unsigned long flags;
2212
2213 netif_stop_queue(dev);
2214 napi_disable(&tp->napi);
2215
2216 if (netif_msg_ifdown(tp))
2217 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2218 dev->name, RTL_R16 (IntrStatus));
2219
2220 spin_lock_irqsave (&tp->lock, flags);
2221
2222 /* Stop the chip's Tx and Rx DMA processes. */
2223 RTL_W8 (ChipCmd, 0);
2224
2225 /* Disable interrupts by clearing the interrupt mask. */
2226 RTL_W16 (IntrMask, 0);
2227
2228 /* Update the error counts. */
2229 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2230 RTL_W32 (RxMissed, 0);
2231
2232 spin_unlock_irqrestore (&tp->lock, flags);
2233
2234 free_irq (dev->irq, dev);
2235
2236 rtl8139_tx_clear (tp);
2237
2238 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2239 tp->rx_ring, tp->rx_ring_dma);
2240 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2241 tp->tx_bufs, tp->tx_bufs_dma);
2242 tp->rx_ring = NULL;
2243 tp->tx_bufs = NULL;
2244
2245 /* Green! Put the chip in low-power mode. */
2246 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2247
2248 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2249 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2250
2251 return 0;
2252 }
2253
2254
2255 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2256 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2257 other threads or interrupts aren't messing with the 8139. */
2258 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2259 {
2260 struct rtl8139_private *np = netdev_priv(dev);
2261 void __iomem *ioaddr = np->mmio_addr;
2262
2263 spin_lock_irq(&np->lock);
2264 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2265 u8 cfg3 = RTL_R8 (Config3);
2266 u8 cfg5 = RTL_R8 (Config5);
2267
2268 wol->supported = WAKE_PHY | WAKE_MAGIC
2269 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2270
2271 wol->wolopts = 0;
2272 if (cfg3 & Cfg3_LinkUp)
2273 wol->wolopts |= WAKE_PHY;
2274 if (cfg3 & Cfg3_Magic)
2275 wol->wolopts |= WAKE_MAGIC;
2276 /* (KON)FIXME: See how netdev_set_wol() handles the
2277 following constants. */
2278 if (cfg5 & Cfg5_UWF)
2279 wol->wolopts |= WAKE_UCAST;
2280 if (cfg5 & Cfg5_MWF)
2281 wol->wolopts |= WAKE_MCAST;
2282 if (cfg5 & Cfg5_BWF)
2283 wol->wolopts |= WAKE_BCAST;
2284 }
2285 spin_unlock_irq(&np->lock);
2286 }
2287
2288
2289 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2290 that wol points to kernel memory and other threads or interrupts
2291 aren't messing with the 8139. */
2292 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2293 {
2294 struct rtl8139_private *np = netdev_priv(dev);
2295 void __iomem *ioaddr = np->mmio_addr;
2296 u32 support;
2297 u8 cfg3, cfg5;
2298
2299 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2300 ? (WAKE_PHY | WAKE_MAGIC
2301 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2302 : 0);
2303 if (wol->wolopts & ~support)
2304 return -EINVAL;
2305
2306 spin_lock_irq(&np->lock);
2307 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2308 if (wol->wolopts & WAKE_PHY)
2309 cfg3 |= Cfg3_LinkUp;
2310 if (wol->wolopts & WAKE_MAGIC)
2311 cfg3 |= Cfg3_Magic;
2312 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2313 RTL_W8 (Config3, cfg3);
2314 RTL_W8 (Cfg9346, Cfg9346_Lock);
2315
2316 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2317 /* (KON)FIXME: These are untested. We may have to set the
2318 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2319 documentation. */
2320 if (wol->wolopts & WAKE_UCAST)
2321 cfg5 |= Cfg5_UWF;
2322 if (wol->wolopts & WAKE_MCAST)
2323 cfg5 |= Cfg5_MWF;
2324 if (wol->wolopts & WAKE_BCAST)
2325 cfg5 |= Cfg5_BWF;
2326 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2327 spin_unlock_irq(&np->lock);
2328
2329 return 0;
2330 }
2331
2332 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2333 {
2334 struct rtl8139_private *np = netdev_priv(dev);
2335 strcpy(info->driver, DRV_NAME);
2336 strcpy(info->version, DRV_VERSION);
2337 strcpy(info->bus_info, pci_name(np->pci_dev));
2338 info->regdump_len = np->regs_len;
2339 }
2340
2341 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2342 {
2343 struct rtl8139_private *np = netdev_priv(dev);
2344 spin_lock_irq(&np->lock);
2345 mii_ethtool_gset(&np->mii, cmd);
2346 spin_unlock_irq(&np->lock);
2347 return 0;
2348 }
2349
2350 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2351 {
2352 struct rtl8139_private *np = netdev_priv(dev);
2353 int rc;
2354 spin_lock_irq(&np->lock);
2355 rc = mii_ethtool_sset(&np->mii, cmd);
2356 spin_unlock_irq(&np->lock);
2357 return rc;
2358 }
2359
2360 static int rtl8139_nway_reset(struct net_device *dev)
2361 {
2362 struct rtl8139_private *np = netdev_priv(dev);
2363 return mii_nway_restart(&np->mii);
2364 }
2365
2366 static u32 rtl8139_get_link(struct net_device *dev)
2367 {
2368 struct rtl8139_private *np = netdev_priv(dev);
2369 return mii_link_ok(&np->mii);
2370 }
2371
2372 static u32 rtl8139_get_msglevel(struct net_device *dev)
2373 {
2374 struct rtl8139_private *np = netdev_priv(dev);
2375 return np->msg_enable;
2376 }
2377
2378 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2379 {
2380 struct rtl8139_private *np = netdev_priv(dev);
2381 np->msg_enable = datum;
2382 }
2383
2384 /* TODO: we are too slack to do reg dumping for pio, for now */
2385 #ifdef CONFIG_8139TOO_PIO
2386 #define rtl8139_get_regs_len NULL
2387 #define rtl8139_get_regs NULL
2388 #else
2389 static int rtl8139_get_regs_len(struct net_device *dev)
2390 {
2391 struct rtl8139_private *np = netdev_priv(dev);
2392 return np->regs_len;
2393 }
2394
2395 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2396 {
2397 struct rtl8139_private *np = netdev_priv(dev);
2398
2399 regs->version = RTL_REGS_VER;
2400
2401 spin_lock_irq(&np->lock);
2402 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2403 spin_unlock_irq(&np->lock);
2404 }
2405 #endif /* CONFIG_8139TOO_MMIO */
2406
2407 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2408 {
2409 switch (sset) {
2410 case ETH_SS_STATS:
2411 return RTL_NUM_STATS;
2412 default:
2413 return -EOPNOTSUPP;
2414 }
2415 }
2416
2417 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2418 {
2419 struct rtl8139_private *np = netdev_priv(dev);
2420
2421 data[0] = np->xstats.early_rx;
2422 data[1] = np->xstats.tx_buf_mapped;
2423 data[2] = np->xstats.tx_timeouts;
2424 data[3] = np->xstats.rx_lost_in_ring;
2425 }
2426
2427 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2428 {
2429 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2430 }
2431
2432 static const struct ethtool_ops rtl8139_ethtool_ops = {
2433 .get_drvinfo = rtl8139_get_drvinfo,
2434 .get_settings = rtl8139_get_settings,
2435 .set_settings = rtl8139_set_settings,
2436 .get_regs_len = rtl8139_get_regs_len,
2437 .get_regs = rtl8139_get_regs,
2438 .nway_reset = rtl8139_nway_reset,
2439 .get_link = rtl8139_get_link,
2440 .get_msglevel = rtl8139_get_msglevel,
2441 .set_msglevel = rtl8139_set_msglevel,
2442 .get_wol = rtl8139_get_wol,
2443 .set_wol = rtl8139_set_wol,
2444 .get_strings = rtl8139_get_strings,
2445 .get_sset_count = rtl8139_get_sset_count,
2446 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2447 };
2448
2449 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2450 {
2451 struct rtl8139_private *np = netdev_priv(dev);
2452 int rc;
2453
2454 if (!netif_running(dev))
2455 return -EINVAL;
2456
2457 spin_lock_irq(&np->lock);
2458 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2459 spin_unlock_irq(&np->lock);
2460
2461 return rc;
2462 }
2463
2464
2465 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2466 {
2467 struct rtl8139_private *tp = netdev_priv(dev);
2468 void __iomem *ioaddr = tp->mmio_addr;
2469 unsigned long flags;
2470
2471 if (netif_running(dev)) {
2472 spin_lock_irqsave (&tp->lock, flags);
2473 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2474 RTL_W32 (RxMissed, 0);
2475 spin_unlock_irqrestore (&tp->lock, flags);
2476 }
2477
2478 return &dev->stats;
2479 }
2480
2481 /* Set or clear the multicast filter for this adaptor.
2482 This routine is not state sensitive and need not be SMP locked. */
2483
2484 static void __set_rx_mode (struct net_device *dev)
2485 {
2486 struct rtl8139_private *tp = netdev_priv(dev);
2487 void __iomem *ioaddr = tp->mmio_addr;
2488 u32 mc_filter[2]; /* Multicast hash filter */
2489 int i, rx_mode;
2490 u32 tmp;
2491
2492 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2493 dev->name, dev->flags, RTL_R32 (RxConfig));
2494
2495 /* Note: do not reorder, GCC is clever about common statements. */
2496 if (dev->flags & IFF_PROMISC) {
2497 rx_mode =
2498 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2499 AcceptAllPhys;
2500 mc_filter[1] = mc_filter[0] = 0xffffffff;
2501 } else if ((dev->mc_count > multicast_filter_limit)
2502 || (dev->flags & IFF_ALLMULTI)) {
2503 /* Too many to filter perfectly -- accept all multicasts. */
2504 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2505 mc_filter[1] = mc_filter[0] = 0xffffffff;
2506 } else {
2507 struct dev_mc_list *mclist;
2508 rx_mode = AcceptBroadcast | AcceptMyPhys;
2509 mc_filter[1] = mc_filter[0] = 0;
2510 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2511 i++, mclist = mclist->next) {
2512 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2513
2514 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2515 rx_mode |= AcceptMulticast;
2516 }
2517 }
2518
2519 /* We can safely update without stopping the chip. */
2520 tmp = rtl8139_rx_config | rx_mode;
2521 if (tp->rx_config != tmp) {
2522 RTL_W32_F (RxConfig, tmp);
2523 tp->rx_config = tmp;
2524 }
2525 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2526 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2527 }
2528
2529 static void rtl8139_set_rx_mode (struct net_device *dev)
2530 {
2531 unsigned long flags;
2532 struct rtl8139_private *tp = netdev_priv(dev);
2533
2534 spin_lock_irqsave (&tp->lock, flags);
2535 __set_rx_mode(dev);
2536 spin_unlock_irqrestore (&tp->lock, flags);
2537 }
2538
2539 #ifdef CONFIG_PM
2540
2541 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2542 {
2543 struct net_device *dev = pci_get_drvdata (pdev);
2544 struct rtl8139_private *tp = netdev_priv(dev);
2545 void __iomem *ioaddr = tp->mmio_addr;
2546 unsigned long flags;
2547
2548 pci_save_state (pdev);
2549
2550 if (!netif_running (dev))
2551 return 0;
2552
2553 netif_device_detach (dev);
2554
2555 spin_lock_irqsave (&tp->lock, flags);
2556
2557 /* Disable interrupts, stop Tx and Rx. */
2558 RTL_W16 (IntrMask, 0);
2559 RTL_W8 (ChipCmd, 0);
2560
2561 /* Update the error counts. */
2562 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2563 RTL_W32 (RxMissed, 0);
2564
2565 spin_unlock_irqrestore (&tp->lock, flags);
2566
2567 pci_set_power_state (pdev, PCI_D3hot);
2568
2569 return 0;
2570 }
2571
2572
2573 static int rtl8139_resume (struct pci_dev *pdev)
2574 {
2575 struct net_device *dev = pci_get_drvdata (pdev);
2576
2577 pci_restore_state (pdev);
2578 if (!netif_running (dev))
2579 return 0;
2580 pci_set_power_state (pdev, PCI_D0);
2581 rtl8139_init_ring (dev);
2582 rtl8139_hw_start (dev);
2583 netif_device_attach (dev);
2584 return 0;
2585 }
2586
2587 #endif /* CONFIG_PM */
2588
2589
2590 static struct pci_driver rtl8139_pci_driver = {
2591 .name = DRV_NAME,
2592 .id_table = rtl8139_pci_tbl,
2593 .probe = rtl8139_init_one,
2594 .remove = __devexit_p(rtl8139_remove_one),
2595 #ifdef CONFIG_PM
2596 .suspend = rtl8139_suspend,
2597 .resume = rtl8139_resume,
2598 #endif /* CONFIG_PM */
2599 };
2600
2601
2602 static int __init rtl8139_init_module (void)
2603 {
2604 /* when we're a module, we always print a version message,
2605 * even if no 8139 board is found.
2606 */
2607 #ifdef MODULE
2608 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2609 #endif
2610
2611 return pci_register_driver(&rtl8139_pci_driver);
2612 }
2613
2614
2615 static void __exit rtl8139_cleanup_module (void)
2616 {
2617 pci_unregister_driver (&rtl8139_pci_driver);
2618 }
2619
2620
2621 module_init(rtl8139_init_module);
2622 module_exit(rtl8139_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree