include/asm-ppc/mmu.h

   1 /*
   2  * PowerPC memory management structures
   3  */
   4
   5 #ifdef __KERNEL__
   6 #ifndef _PPC_MMU_H_
   7 #define _PPC_MMU_H_
   8
   9
  10 #ifndef __ASSEMBLY__
  11
  12 /*
  13  * Define physical address type.  Machines using split size
  14  * virtual/physical addressing like 32-bit virtual / 36-bit
  15  * physical need a larger than native word size type. -Matt
  16  */
  17 #ifndef CONFIG_PHYS_64BIT
  18 typedef unsigned long phys_addr_t;
  19 #define PHYS_FMT        "%.8lx"
  20 #else
  21 typedef unsigned long long phys_addr_t;
  22 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
  23 #define PHYS_FMT        "%16Lx"
  24 #endif
  25
  26 /* Default "unsigned long" context */
  27 typedef unsigned long mm_context_t;
  28
  29 /* Hardware Page Table Entry */
  30 typedef struct _PTE {
  31 #ifdef CONFIG_PPC64BRIDGE
  32         unsigned long long vsid:52;
  33         unsigned long api:5;
  34         unsigned long :5;
  35         unsigned long h:1;
  36         unsigned long v:1;
  37         unsigned long long rpn:52;
  38 #else /* CONFIG_PPC64BRIDGE */
  39         unsigned long v:1;      /* Entry is valid */
  40         unsigned long vsid:24;  /* Virtual segment identifier */
  41         unsigned long h:1;      /* Hash algorithm indicator */
  42         unsigned long api:6;    /* Abbreviated page index */
  43         unsigned long rpn:20;   /* Real (physical) page number */
  44 #endif /* CONFIG_PPC64BRIDGE */
  45         unsigned long    :3;    /* Unused */
  46         unsigned long r:1;      /* Referenced */
  47         unsigned long c:1;      /* Changed */
  48         unsigned long w:1;      /* Write-thru cache mode */
  49         unsigned long i:1;      /* Cache inhibited */
  50         unsigned long m:1;      /* Memory coherence */
  51         unsigned long g:1;      /* Guarded */
  52         unsigned long  :1;      /* Unused */
  53         unsigned long pp:2;     /* Page protection */
  54 } PTE;
  55
  56 /* Values for PP (assumes Ks=0, Kp=1) */
  57 #define PP_RWXX 0       /* Supervisor read/write, User none */
  58 #define PP_RWRX 1       /* Supervisor read/write, User read */
  59 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  60 #define PP_RXRX 3       /* Supervisor read,       User read */
  61
  62 /* Segment Register */
  63 typedef struct _SEGREG {
  64         unsigned long t:1;      /* Normal or I/O  type */
  65         unsigned long ks:1;     /* Supervisor 'key' (normally 0) */
  66         unsigned long kp:1;     /* User 'key' (normally 1) */
  67         unsigned long n:1;      /* No-execute */
  68         unsigned long :4;       /* Unused */
  69         unsigned long vsid:24;  /* Virtual Segment Identifier */
  70 } SEGREG;
  71
  72 /* Block Address Translation (BAT) Registers */
  73 typedef struct _P601_BATU {     /* Upper part of BAT for 601 processor */
  74         unsigned long bepi:15;  /* Effective page index (virtual address) */
  75         unsigned long :8;       /* unused */
  76         unsigned long w:1;
  77         unsigned long i:1;      /* Cache inhibit */
  78         unsigned long m:1;      /* Memory coherence */
  79         unsigned long ks:1;     /* Supervisor key (normally 0) */
  80         unsigned long kp:1;     /* User key (normally 1) */
  81         unsigned long pp:2;     /* Page access protections */
  82 } P601_BATU;
  83
  84 typedef struct _BATU {          /* Upper part of BAT (all except 601) */
  85 #ifdef CONFIG_PPC64BRIDGE
  86         unsigned long long bepi:47;
  87 #else /* CONFIG_PPC64BRIDGE */
  88         unsigned long bepi:15;  /* Effective page index (virtual address) */
  89 #endif /* CONFIG_PPC64BRIDGE */
  90         unsigned long :4;       /* Unused */
  91         unsigned long bl:11;    /* Block size mask */
  92         unsigned long vs:1;     /* Supervisor valid */
  93         unsigned long vp:1;     /* User valid */
  94 } BATU;
  95
  96 typedef struct _P601_BATL {     /* Lower part of BAT for 601 processor */
  97         unsigned long brpn:15;  /* Real page index (physical address) */
  98         unsigned long :10;      /* Unused */
  99         unsigned long v:1;      /* Valid bit */
 100         unsigned long bl:6;     /* Block size mask */
 101 } P601_BATL;
 102
 103 typedef struct _BATL {          /* Lower part of BAT (all except 601) */
 104 #ifdef CONFIG_PPC64BRIDGE
 105         unsigned long long brpn:47;
 106 #else /* CONFIG_PPC64BRIDGE */
 107         unsigned long brpn:15;  /* Real page index (physical address) */
 108 #endif /* CONFIG_PPC64BRIDGE */
 109         unsigned long :10;      /* Unused */
 110         unsigned long w:1;      /* Write-thru cache */
 111         unsigned long i:1;      /* Cache inhibit */
 112         unsigned long m:1;      /* Memory coherence */
 113         unsigned long g:1;      /* Guarded (MBZ in IBAT) */
 114         unsigned long :1;       /* Unused */
 115         unsigned long pp:2;     /* Page access protections */
 116 } BATL;
 117
 118 typedef struct _BAT {
 119         BATU batu;              /* Upper register */
 120         BATL batl;              /* Lower register */
 121 } BAT;
 122
 123 typedef struct _P601_BAT {
 124         P601_BATU batu;         /* Upper register */
 125         P601_BATL batl;         /* Lower register */
 126 } P601_BAT;
 127
 128 #endif /* __ASSEMBLY__ */
 129
 130 /* Block size masks */
 131 #define BL_128K 0x000
 132 #define BL_256K 0x001
 133 #define BL_512K 0x003
 134 #define BL_1M   0x007
 135 #define BL_2M   0x00F
 136 #define BL_4M   0x01F
 137 #define BL_8M   0x03F
 138 #define BL_16M  0x07F
 139 #define BL_32M  0x0FF
 140 #define BL_64M  0x1FF
 141 #define BL_128M 0x3FF
 142 #define BL_256M 0x7FF
 143
 144 /* BAT Access Protection */
 145 #define BPP_XX  0x00            /* No access */
 146 #define BPP_RX  0x01            /* Read only */
 147 #define BPP_RW  0x02            /* Read/write */
 148
 149 /* Control/status registers for the MPC8xx.
 150  * A write operation to these registers causes serialized access.
 151  * During software tablewalk, the registers used perform mask/shift-add
 152  * operations when written/read.  A TLB entry is created when the Mx_RPN
 153  * is written, and the contents of several registers are used to
 154  * create the entry.
 155  */
 156 #define SPRN_MI_CTR     784     /* Instruction TLB control register */
 157 #define MI_GPM          0x80000000      /* Set domain manager mode */
 158 #define MI_PPM          0x40000000      /* Set subpage protection */
 159 #define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 160 #define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 161 #define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 162 #define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
 163 #define MI_RESETVAL     0x00000000      /* Value of register at reset */
 164
 165 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 166  * Ks = 0, Kp = 1.
 167  */
 168 #define SPRN_MI_AP      786
 169 #define MI_Ks           0x80000000      /* Should not be set */
 170 #define MI_Kp           0x40000000      /* Should always be set */
 171
 172 /* The effective page number register.  When read, contains the information
 173  * about the last instruction TLB miss.  When MI_RPN is written, bits in
 174  * this register are used to create the TLB entry.
 175  */
 176 #define SPRN_MI_EPN     787
 177 #define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
 178 #define MI_EVALID       0x00000200      /* Entry is valid */
 179 #define MI_ASIDMASK     0x0000000f      /* ASID match value */
 180                                         /* Reset value is undefined */
 181
 182 /* A "level 1" or "segment" or whatever you want to call it register.
 183  * For the instruction TLB, it contains bits that get loaded into the
 184  * TLB entry when the MI_RPN is written.
 185  */
 186 #define SPRN_MI_TWC     789
 187 #define MI_APG          0x000001e0      /* Access protection group (0) */
 188 #define MI_GUARDED      0x00000010      /* Guarded storage */
 189 #define MI_PSMASK       0x0000000c      /* Mask of page size bits */
 190 #define MI_PS8MEG       0x0000000c      /* 8M page size */
 191 #define MI_PS512K       0x00000004      /* 512K page size */
 192 #define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
 193 #define MI_SVALID       0x00000001      /* Segment entry is valid */
 194                                         /* Reset value is undefined */
 195
 196 /* Real page number.  Defined by the pte.  Writing this register
 197  * causes a TLB entry to be created for the instruction TLB, using
 198  * additional information from the MI_EPN, and MI_TWC registers.
 199  */
 200 #define SPRN_MI_RPN     790
 201
 202 /* Define an RPN value for mapping kernel memory to large virtual
 203  * pages for boot initialization.  This has real page number of 0,
 204  * large page size, shared page, cache enabled, and valid.
 205  * Also mark all subpages valid and write access.
 206  */
 207 #define MI_BOOTINIT     0x000001fd
 208
 209 #define SPRN_MD_CTR     792     /* Data TLB control register */
 210 #define MD_GPM          0x80000000      /* Set domain manager mode */
 211 #define MD_PPM          0x40000000      /* Set subpage protection */
 212 #define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 213 #define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
 214 #define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 215 #define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
 216 #define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 217 #define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
 218 #define MD_RESETVAL     0x04000000      /* Value of register at reset */
 219
 220 #define SPRN_M_CASID    793     /* Address space ID (context) to match */
 221 #define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
 222
 223
 224 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 225  * Ks = 0, Kp = 1.
 226  */
 227 #define SPRN_MD_AP      794
 228 #define MD_Ks           0x80000000      /* Should not be set */
 229 #define MD_Kp           0x40000000      /* Should always be set */
 230
 231 /* The effective page number register.  When read, contains the information
 232  * about the last instruction TLB miss.  When MD_RPN is written, bits in
 233  * this register are used to create the TLB entry.
 234  */
 235 #define SPRN_MD_EPN     795
 236 #define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
 237 #define MD_EVALID       0x00000200      /* Entry is valid */
 238 #define MD_ASIDMASK     0x0000000f      /* ASID match value */
 239                                         /* Reset value is undefined */
 240
 241 /* The pointer to the base address of the first level page table.
 242  * During a software tablewalk, reading this register provides the address
 243  * of the entry associated with MD_EPN.
 244  */
 245 #define SPRN_M_TWB      796
 246 #define M_L1TB          0xfffff000      /* Level 1 table base address */
 247 #define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
 248                                         /* Reset value is undefined */
 249
 250 /* A "level 1" or "segment" or whatever you want to call it register.
 251  * For the data TLB, it contains bits that get loaded into the TLB entry
 252  * when the MD_RPN is written.  It is also provides the hardware assist
 253  * for finding the PTE address during software tablewalk.
 254  */
 255 #define SPRN_MD_TWC     797
 256 #define MD_L2TB         0xfffff000      /* Level 2 table base address */
 257 #define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
 258 #define MD_APG          0x000001e0      /* Access protection group (0) */
 259 #define MD_GUARDED      0x00000010      /* Guarded storage */
 260 #define MD_PSMASK       0x0000000c      /* Mask of page size bits */
 261 #define MD_PS8MEG       0x0000000c      /* 8M page size */
 262 #define MD_PS512K       0x00000004      /* 512K page size */
 263 #define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
 264 #define MD_WT           0x00000002      /* Use writethrough page attribute */
 265 #define MD_SVALID       0x00000001      /* Segment entry is valid */
 266                                         /* Reset value is undefined */
 267
 268
 269 /* Real page number.  Defined by the pte.  Writing this register
 270  * causes a TLB entry to be created for the data TLB, using
 271  * additional information from the MD_EPN, and MD_TWC registers.
 272  */
 273 #define SPRN_MD_RPN     798
 274
 275 /* This is a temporary storage register that could be used to save
 276  * a processor working register during a tablewalk.
 277  */
 278 #define SPRN_M_TW       799
 279
 280 /*
 281  * At present, all PowerPC 400-class processors share a similar TLB
 282  * architecture. The instruction and data sides share a unified,
 283  * 64-entry, fully-associative TLB which is maintained totally under
 284  * software control. In addition, the instruction side has a
 285  * hardware-managed, 4-entry, fully- associative TLB which serves as a
 286  * first level to the shared TLB. These two TLBs are known as the UTLB
 287  * and ITLB, respectively.
 288  */
 289
 290 #define        PPC4XX_TLB_SIZE 64
 291
 292 /*
 293  * TLB entries are defined by a "high" tag portion and a "low" data
 294  * portion.  On all architectures, the data portion is 32-bits.
 295  *
 296  * TLB entries are managed entirely under software control by reading,
 297  * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
 298  * instructions.
 299  */
 300
 301 #define TLB_LO          1
 302 #define TLB_HI          0
 303
 304 #define TLB_DATA        TLB_LO
 305 #define TLB_TAG         TLB_HI
 306
 307 /* Tag portion */
 308
 309 #define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
 310 #define TLB_PAGESZ_MASK 0x00000380
 311 #define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
 312 #define   PAGESZ_1K             0
 313 #define   PAGESZ_4K             1
 314 #define   PAGESZ_16K            2
 315 #define   PAGESZ_64K            3
 316 #define   PAGESZ_256K           4
 317 #define   PAGESZ_1M             5
 318 #define   PAGESZ_4M             6
 319 #define   PAGESZ_16M            7
 320 #define TLB_VALID       0x00000040      /* Entry is valid */
 321
 322 /* Data portion */
 323
 324 #define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
 325 #define TLB_PERM_MASK   0x00000300
 326 #define TLB_EX          0x00000200      /* Instruction execution allowed */
 327 #define TLB_WR          0x00000100      /* Writes permitted */
 328 #define TLB_ZSEL_MASK   0x000000F0
 329 #define TLB_ZSEL(x)     (((x) & 0xF) << 4)
 330 #define TLB_ATTR_MASK   0x0000000F
 331 #define TLB_W           0x00000008      /* Caching is write-through */
 332 #define TLB_I           0x00000004      /* Caching is inhibited */
 333 #define TLB_M           0x00000002      /* Memory is coherent */
 334 #define TLB_G           0x00000001      /* Memory is guarded from prefetch */
 335
 336 /*
 337  * PPC440 support
 338  */
 339 #define PPC44x_MMUCR_TID        0x000000ff
 340 #define PPC44x_MMUCR_STS        0x00010000
 341
 342 #define PPC44x_TLB_PAGEID       0
 343 #define PPC44x_TLB_XLAT         1
 344 #define PPC44x_TLB_ATTRIB       2
 345
 346 /* Page identification fields */
 347 #define PPC44x_TLB_EPN_MASK     0xfffffc00      /* Effective Page Number */
 348 #define PPC44x_TLB_VALID        0x00000200      /* Valid flag */
 349 #define PPC44x_TLB_TS           0x00000100      /* Translation address space */
 350 #define PPC44x_TLB_1K           0x00000000      /* Page sizes */
 351 #define PPC44x_TLB_4K           0x00000010
 352 #define PPC44x_TLB_16K          0x00000020
 353 #define PPC44x_TLB_64K          0x00000030
 354 #define PPC44x_TLB_256K         0x00000040
 355 #define PPC44x_TLB_1M           0x00000050
 356 #define PPC44x_TLB_16M          0x00000070
 357 #define PPC44x_TLB_256M         0x00000090
 358
 359 /* Translation fields */
 360 #define PPC44x_TLB_RPN_MASK     0xfffffc00      /* Real Page Number */
 361 #define PPC44x_TLB_ERPN_MASK    0x0000000f
 362
 363 /* Storage attribute and access control fields */
 364 #define PPC44x_TLB_ATTR_MASK    0x0000ff80
 365 #define PPC44x_TLB_U0           0x00008000      /* User 0 */
 366 #define PPC44x_TLB_U1           0x00004000      /* User 1 */
 367 #define PPC44x_TLB_U2           0x00002000      /* User 2 */
 368 #define PPC44x_TLB_U3           0x00001000      /* User 3 */
 369 #define PPC44x_TLB_W            0x00000800      /* Caching is write-through */
 370 #define PPC44x_TLB_I            0x00000400      /* Caching is inhibited */
 371 #define PPC44x_TLB_M            0x00000200      /* Memory is coherent */
 372 #define PPC44x_TLB_G            0x00000100      /* Memory is guarded */
 373 #define PPC44x_TLB_E            0x00000080      /* Memory is guarded */
 374
 375 #define PPC44x_TLB_PERM_MASK    0x0000003f
 376 #define PPC44x_TLB_UX           0x00000020      /* User execution */
 377 #define PPC44x_TLB_UW           0x00000010      /* User write */
 378 #define PPC44x_TLB_UR           0x00000008      /* User read */
 379 #define PPC44x_TLB_SX           0x00000004      /* Super execution */
 380 #define PPC44x_TLB_SW           0x00000002      /* Super write */
 381 #define PPC44x_TLB_SR           0x00000001      /* Super read */
 382
 383 /* Book-E defined page sizes */
 384 #define BOOKE_PAGESZ_1K         0
 385 #define BOOKE_PAGESZ_4K         1
 386 #define BOOKE_PAGESZ_16K        2
 387 #define BOOKE_PAGESZ_64K        3
 388 #define BOOKE_PAGESZ_256K       4
 389 #define BOOKE_PAGESZ_1M         5
 390 #define BOOKE_PAGESZ_4M         6
 391 #define BOOKE_PAGESZ_16M        7
 392 #define BOOKE_PAGESZ_64M        8
 393 #define BOOKE_PAGESZ_256M       9
 394 #define BOOKE_PAGESZ_1GB        10
 395 #define BOOKE_PAGESZ_4GB        11
 396 #define BOOKE_PAGESZ_16GB       12
 397 #define BOOKE_PAGESZ_64GB       13
 398 #define BOOKE_PAGESZ_256GB      14
 399 #define BOOKE_PAGESZ_1TB        15
 400
 401 /*
 402  * Freescale Book-E MMU support
 403  */
 404
 405 #define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
 406 #define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
 407 #define MAS0_NV(x)      ((x) & 0x00000FFF)
 408
 409 #define MAS1_VALID      0x80000000
 410 #define MAS1_IPROT      0x40000000
 411 #define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
 412 #define MAS1_TS         0x00001000
 413 #define MAS1_TSIZE(x)   ((x << 8) & 0x00000F00)
 414
 415 #define MAS2_EPN        0xFFFFF000
 416 #define MAS2_X0         0x00000040
 417 #define MAS2_X1         0x00000020
 418 #define MAS2_W          0x00000010
 419 #define MAS2_I          0x00000008
 420 #define MAS2_M          0x00000004
 421 #define MAS2_G          0x00000002
 422 #define MAS2_E          0x00000001
 423
 424 #define MAS3_RPN        0xFFFFF000
 425 #define MAS3_U0         0x00000200
 426 #define MAS3_U1         0x00000100
 427 #define MAS3_U2         0x00000080
 428 #define MAS3_U3         0x00000040
 429 #define MAS3_UX         0x00000020
 430 #define MAS3_SX         0x00000010
 431 #define MAS3_UW         0x00000008
 432 #define MAS3_SW         0x00000004
 433 #define MAS3_UR         0x00000002
 434 #define MAS3_SR         0x00000001
 435
 436 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
 437 #define MAS4_TIDDSEL    0x000F0000
 438 #define MAS4_TSIZED(x)  MAS1_TSIZE(x)
 439 #define MAS4_X0D        0x00000040
 440 #define MAS4_X1D        0x00000020
 441 #define MAS4_WD         0x00000010
 442 #define MAS4_ID         0x00000008
 443 #define MAS4_MD         0x00000004
 444 #define MAS4_GD         0x00000002
 445 #define MAS4_ED         0x00000001
 446
 447 #define MAS6_SPID0      0x3FFF0000
 448 #define MAS6_SPID1      0x00007FFE
 449 #define MAS6_SAS        0x00000001
 450 #define MAS6_SPID       MAS6_SPID0
 451
 452 #define MAS7_RPN        0xFFFFFFFF
 453
 454 #endif /* _PPC_MMU_H_ */
 455 #endif /* __KERNEL__ */