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s3c2410fb: remove fb_info pointer from s3c2410fb_info
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / s3c2410fb.c
blobf7a026fa50799bc8b64e3bb45268848d2fa96a89
1 /*
2 * linux/drivers/video/s3c2410fb.c
3 * Copyright (c) Arnaud Patard, Ben Dooks
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
7 * more details.
8 *
9 * S3C2410 LCD Controller Frame Buffer Driver
10 * based on skeletonfb.c, sa1100fb.c and others
11 *
12 * ChangeLog
13 * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
14 * - u32 state -> pm_message_t state
15 * - S3C2410_{VA,SZ}_LCD -> S3C24XX
16 *
17 * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
18 * - Removed the ioctl
19 * - use readl/writel instead of __raw_writel/__raw_readl
20 *
21 * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
22 * - Added the possibility to set on or off the
23 * debugging mesaages
24 * - Replaced 0 and 1 by on or off when reading the
25 * /sys files
26 *
27 * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
28 * - added non 16bpp modes
29 * - updated platform information for range of x/y/bpp
30 * - add code to ensure palette is written correctly
31 * - add pixel clock divisor control
32 *
33 * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
34 * - Removed the use of currcon as it no more exist
35 * - Added LCD power sysfs interface
36 *
37 * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
38 * - minor cleanups
39 * - add suspend/resume support
40 * - s3c2410fb_setcolreg() not valid in >8bpp modes
41 * - removed last CONFIG_FB_S3C2410_FIXED
42 * - ensure lcd controller stopped before cleanup
43 * - added sysfs interface for backlight power
44 * - added mask for gpio configuration
45 * - ensured IRQs disabled during GPIO configuration
46 * - disable TPAL before enabling video
47 *
48 * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
49 * - Suppress command line options
50 *
51 * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
52 * - code cleanup
53 *
54 * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
55 * - Renamed from h1940fb.c to s3c2410fb.c
56 * - Add support for different devices
57 * - Backlight support
58 *
59 * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
60 * - added clock (de-)allocation code
61 * - added fixem fbmem option
62 *
63 * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
64 * - code cleanup
65 * - added a forgotten return in h1940fb_init
66 *
67 * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
68 * - code cleanup and extended debugging
69 *
70 * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
71 * - First version
72 */
73
74 #include <linux/module.h>
75 #include <linux/kernel.h>
76 #include <linux/errno.h>
77 #include <linux/string.h>
78 #include <linux/mm.h>
79 #include <linux/slab.h>
80 #include <linux/delay.h>
81 #include <linux/fb.h>
82 #include <linux/init.h>
83 #include <linux/dma-mapping.h>
84 #include <linux/interrupt.h>
85 #include <linux/workqueue.h>
86 #include <linux/wait.h>
87 #include <linux/platform_device.h>
88 #include <linux/clk.h>
89
90 #include <asm/io.h>
91 #include <asm/uaccess.h>
92 #include <asm/div64.h>
93
94 #include <asm/mach/map.h>
95 #include <asm/arch/regs-lcd.h>
96 #include <asm/arch/regs-gpio.h>
97 #include <asm/arch/fb.h>
98
99 #ifdef CONFIG_PM
100 #include <linux/pm.h>
101 #endif
102
103 #include "s3c2410fb.h"
104
105 static struct s3c2410fb_mach_info *mach_info;
106
107 /* Debugging stuff */
108 #ifdef CONFIG_FB_S3C2410_DEBUG
109 static int debug = 1;
110 #else
111 static int debug = 0;
112 #endif
113
114 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
115
116 /* useful functions */
117
118 /* s3c2410fb_set_lcdaddr
119 *
120 * initialise lcd controller address pointers
121 */
122 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
123 {
124 unsigned long saddr1, saddr2, saddr3;
125 int line_length = info->var.xres * info->var.bits_per_pixel;
126
127 saddr1 = info->fix.smem_start >> 1;
128 saddr2 = info->fix.smem_start;
129 saddr2 += (line_length * info->var.yres) / 8;
130 saddr2 >>= 1;
131
132 saddr3 = S3C2410_OFFSIZE(0) |
133 S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff);
134
135 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
136 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
137 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
138
139 writel(saddr1, S3C2410_LCDSADDR1);
140 writel(saddr2, S3C2410_LCDSADDR2);
141 writel(saddr3, S3C2410_LCDSADDR3);
142 }
143
144 /* s3c2410fb_calc_pixclk()
145 *
146 * calculate divisor for clk->pixclk
147 */
148 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
149 unsigned long pixclk)
150 {
151 unsigned long clk = clk_get_rate(fbi->clk);
152 unsigned long long div;
153
154 /* pixclk is in picoseoncds, our clock is in Hz
155 *
156 * Hz -> picoseconds is / 10^-12
157 */
158
159 div = (unsigned long long)clk * pixclk;
160 do_div(div, 1000000UL);
161 do_div(div, 1000000UL);
162
163 dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
164 return div;
165 }
166
167 /*
168 * s3c2410fb_check_var():
169 * Get the video params out of 'var'. If a value doesn't fit, round it up,
170 * if it's too big, return -EINVAL.
171 *
172 */
173 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
174 struct fb_info *info)
175 {
176 struct s3c2410fb_info *fbi = info->par;
177
178 dprintk("check_var(var=%p, info=%p)\n", var, info);
179
180 /* validate x/y resolution */
181
182 if (var->yres > fbi->mach_info->yres.max)
183 var->yres = fbi->mach_info->yres.max;
184 else if (var->yres < fbi->mach_info->yres.min)
185 var->yres = fbi->mach_info->yres.min;
186
187 if (var->xres > fbi->mach_info->xres.max)
188 var->yres = fbi->mach_info->xres.max;
189 else if (var->xres < fbi->mach_info->xres.min)
190 var->xres = fbi->mach_info->xres.min;
191
192 /* validate bpp */
193
194 if (var->bits_per_pixel > fbi->mach_info->bpp.max)
195 var->bits_per_pixel = fbi->mach_info->bpp.max;
196 else if (var->bits_per_pixel < fbi->mach_info->bpp.min)
197 var->bits_per_pixel = fbi->mach_info->bpp.min;
198
199 var->transp.offset = 0;
200 var->transp.length = 0;
201 /* set r/g/b positions */
202 switch (var->bits_per_pixel) {
203 case 1:
204 case 2:
205 case 4:
206 var->red.offset = 0;
207 var->red.length = var->bits_per_pixel;
208 var->green = var->red;
209 var->blue = var->red;
210 break;
211 case 8:
212 if (fbi->mach_info->type != S3C2410_LCDCON1_TFT) {
213 /* 8 bpp 332 */
214 var->red.length = 3;
215 var->red.offset = 5;
216 var->green.length = 3;
217 var->green.offset = 2;
218 var->blue.length = 2;
219 var->blue.offset = 0;
220 } else {
221 var->red.offset = 0;
222 var->red.length = 8;
223 var->green = var->red;
224 var->blue = var->red;
225 }
226 break;
227 case 12:
228 /* 12 bpp 444 */
229 var->red.length = 4;
230 var->red.offset = 8;
231 var->green.length = 4;
232 var->green.offset = 4;
233 var->blue.length = 4;
234 var->blue.offset = 0;
235 break;
236
237 default:
238 case 16:
239 if (fbi->regs.lcdcon5 & S3C2410_LCDCON5_FRM565) {
240 /* 16 bpp, 565 format */
241 var->red.offset = 11;
242 var->green.offset = 5;
243 var->blue.offset = 0;
244 var->red.length = 5;
245 var->green.length = 6;
246 var->blue.length = 5;
247 } else {
248 /* 16 bpp, 5551 format */
249 var->red.offset = 11;
250 var->green.offset = 6;
251 var->blue.offset = 1;
252 var->red.length = 5;
253 var->green.length = 5;
254 var->blue.length = 5;
255 }
256 break;
257 case 24:
258 /* 24 bpp 888 */
259 var->red.length = 8;
260 var->red.offset = 16;
261 var->green.length = 8;
262 var->green.offset = 8;
263 var->blue.length = 8;
264 var->blue.offset = 0;
265 break;
266
267
268 }
269 return 0;
270 }
271
272 /* s3c2410fb_activate_var
273 *
274 * activate (set) the controller from the given framebuffer
275 * information
276 */
277 static void s3c2410fb_activate_var(struct fb_info *info,
278 struct fb_var_screeninfo *var)
279 {
280 struct s3c2410fb_info *fbi = info->par;
281 int hs;
282
283 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
284 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
285
286 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
287 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
288 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
289
290 fbi->regs.lcdcon1 |= fbi->mach_info->type;
291
292 if (fbi->mach_info->type == S3C2410_LCDCON1_TFT)
293 switch (var->bits_per_pixel) {
294 case 1:
295 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
296 break;
297 case 2:
298 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
299 break;
300 case 4:
301 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
302 break;
303 case 8:
304 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
305 break;
306 case 16:
307 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
308 break;
309
310 default:
311 /* invalid pixel depth */
312 dev_err(fbi->dev, "invalid bpp %d\n",
313 var->bits_per_pixel);
314 }
315 else
316 switch (var->bits_per_pixel) {
317 case 1:
318 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
319 break;
320 case 2:
321 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
322 break;
323 case 4:
324 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
325 break;
326 case 8:
327 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
328 break;
329 case 12:
330 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
331 break;
332
333 default:
334 /* invalid pixel depth */
335 dev_err(fbi->dev, "invalid bpp %d\n",
336 var->bits_per_pixel);
337 }
338
339 /* check to see if we need to update sync/borders */
340
341 if (!fbi->mach_info->fixed_syncs) {
342 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
343 var->upper_margin, var->lower_margin, var->vsync_len);
344
345 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
346 var->left_margin, var->right_margin, var->hsync_len);
347
348 fbi->regs.lcdcon2 =
349 S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
350 S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
351 S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
352
353 fbi->regs.lcdcon3 =
354 S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
355 S3C2410_LCDCON3_HFPD(var->left_margin - 1);
356
357 fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
358 fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
359 }
360
361 /* update X/Y info */
362
363 fbi->regs.lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
364 fbi->regs.lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
365
366 switch (fbi->mach_info->type) {
367 case S3C2410_LCDCON1_DSCAN4:
368 case S3C2410_LCDCON1_STN8:
369 hs = var->xres / 8;
370 break;
371 case S3C2410_LCDCON1_STN4:
372 hs = var->xres / 4;
373 break;
374 default:
375 case S3C2410_LCDCON1_TFT:
376 hs = var->xres;
377 break;
378 }
379
380 /* Special cases : STN color displays */
381 if (((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN8BPP) ||
382 ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN12BPP))
383 hs = hs * 3;
384
385 fbi->regs.lcdcon3 &= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
386 fbi->regs.lcdcon3 |= S3C2410_LCDCON3_HOZVAL(hs - 1);
387
388 if (var->pixclock > 0) {
389 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
390
391 if (fbi->mach_info->type == S3C2410_LCDCON1_TFT) {
392 clkdiv = (clkdiv / 2) - 1;
393 if (clkdiv < 0)
394 clkdiv = 0;
395 } else {
396 clkdiv = (clkdiv / 2);
397 if (clkdiv < 2)
398 clkdiv = 2;
399 }
400
401 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
402 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
403 }
404
405 /* write new registers */
406
407 dprintk("new register set:\n");
408 dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
409 dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
410 dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
411 dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
412 dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
413
414 writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
415 writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
416 writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
417 writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
418 writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
419
420 /* set lcd address pointers */
421 s3c2410fb_set_lcdaddr(info);
422
423 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
424 }
425
426 /*
427 * s3c2410fb_set_par - Alters the hardware state.
428 * @info: frame buffer structure that represents a single frame buffer
429 *
430 */
431 static int s3c2410fb_set_par(struct fb_info *info)
432 {
433 struct fb_var_screeninfo *var = &info->var;
434
435 switch (var->bits_per_pixel) {
436 case 16:
437 info->fix.visual = FB_VISUAL_TRUECOLOR;
438 break;
439 case 1:
440 info->fix.visual = FB_VISUAL_MONO01;
441 break;
442 default:
443 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
444 break;
445 }
446
447 info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
448
449 /* activate this new configuration */
450
451 s3c2410fb_activate_var(info, var);
452 return 0;
453 }
454
455 static void schedule_palette_update(struct s3c2410fb_info *fbi,
456 unsigned int regno, unsigned int val)
457 {
458 unsigned long flags;
459 unsigned long irqen;
460 void __iomem *regs = fbi->io;
461
462 local_irq_save(flags);
463
464 fbi->palette_buffer[regno] = val;
465
466 if (!fbi->palette_ready) {
467 fbi->palette_ready = 1;
468
469 /* enable IRQ */
470 irqen = readl(regs + S3C2410_LCDINTMSK);
471 irqen &= ~S3C2410_LCDINT_FRSYNC;
472 writel(irqen, regs + S3C2410_LCDINTMSK);
473 }
474
475 local_irq_restore(flags);
476 }
477
478 /* from pxafb.c */
479 static inline unsigned int chan_to_field(unsigned int chan,
480 struct fb_bitfield *bf)
481 {
482 chan &= 0xffff;
483 chan >>= 16 - bf->length;
484 return chan << bf->offset;
485 }
486
487 static int s3c2410fb_setcolreg(unsigned regno,
488 unsigned red, unsigned green, unsigned blue,
489 unsigned transp, struct fb_info *info)
490 {
491 struct s3c2410fb_info *fbi = info->par;
492 unsigned int val;
493
494 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
495 regno, red, green, blue); */
496
497 switch (info->fix.visual) {
498 case FB_VISUAL_TRUECOLOR:
499 /* true-colour, use pseudo-palette */
500
501 if (regno < 16) {
502 u32 *pal = info->pseudo_palette;
503
504 val = chan_to_field(red, &info->var.red);
505 val |= chan_to_field(green, &info->var.green);
506 val |= chan_to_field(blue, &info->var.blue);
507
508 pal[regno] = val;
509 }
510 break;
511
512 case FB_VISUAL_PSEUDOCOLOR:
513 if (regno < 256) {
514 /* currently assume RGB 5-6-5 mode */
515
516 val = ((red >> 0) & 0xf800);
517 val |= ((green >> 5) & 0x07e0);
518 val |= ((blue >> 11) & 0x001f);
519
520 writel(val, S3C2410_TFTPAL(regno));
521 schedule_palette_update(fbi, regno, val);
522 }
523
524 break;
525
526 default:
527 return 1; /* unknown type */
528 }
529
530 return 0;
531 }
532
533 /*
534 * s3c2410fb_blank
535 * @blank_mode: the blank mode we want.
536 * @info: frame buffer structure that represents a single frame buffer
537 *
538 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
539 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
540 * video mode which doesn't support it. Implements VESA suspend
541 * and powerdown modes on hardware that supports disabling hsync/vsync:
542 * blank_mode == 2: suspend vsync
543 * blank_mode == 3: suspend hsync
544 * blank_mode == 4: powerdown
545 *
546 * Returns negative errno on error, or zero on success.
547 *
548 */
549 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
550 {
551 dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
552
553 if (mach_info == NULL)
554 return -EINVAL;
555
556 if (blank_mode == FB_BLANK_UNBLANK)
557 writel(0x0, S3C2410_TPAL);
558 else {
559 dprintk("setting TPAL to output 0x000000\n");
560 writel(S3C2410_TPAL_EN, S3C2410_TPAL);
561 }
562
563 return 0;
564 }
565
566 static int s3c2410fb_debug_show(struct device *dev,
567 struct device_attribute *attr, char *buf)
568 {
569 return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
570 }
571 static int s3c2410fb_debug_store(struct device *dev,
572 struct device_attribute *attr,
573 const char *buf, size_t len)
574 {
575 if (mach_info == NULL)
576 return -EINVAL;
577
578 if (len < 1)
579 return -EINVAL;
580
581 if (strnicmp(buf, "on", 2) == 0 ||
582 strnicmp(buf, "1", 1) == 0) {
583 debug = 1;
584 printk(KERN_DEBUG "s3c2410fb: Debug On");
585 } else if (strnicmp(buf, "off", 3) == 0 ||
586 strnicmp(buf, "0", 1) == 0) {
587 debug = 0;
588 printk(KERN_DEBUG "s3c2410fb: Debug Off");
589 } else {
590 return -EINVAL;
591 }
592
593 return len;
594 }
595
596 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
597
598 static struct fb_ops s3c2410fb_ops = {
599 .owner = THIS_MODULE,
600 .fb_check_var = s3c2410fb_check_var,
601 .fb_set_par = s3c2410fb_set_par,
602 .fb_blank = s3c2410fb_blank,
603 .fb_setcolreg = s3c2410fb_setcolreg,
604 .fb_fillrect = cfb_fillrect,
605 .fb_copyarea = cfb_copyarea,
606 .fb_imageblit = cfb_imageblit,
607 };
608
609 /*
610 * s3c2410fb_map_video_memory():
611 * Allocates the DRAM memory for the frame buffer. This buffer is
612 * remapped into a non-cached, non-buffered, memory region to
613 * allow palette and pixel writes to occur without flushing the
614 * cache. Once this area is remapped, all virtual memory
615 * access to the video memory should occur at the new region.
616 */
617 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
618 {
619 struct s3c2410fb_info *fbi = info->par;
620
621 dprintk("map_video_memory(fbi=%p)\n", fbi);
622
623 fbi->map_size = PAGE_ALIGN(info->fix.smem_len + PAGE_SIZE);
624 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
625 &fbi->map_dma, GFP_KERNEL);
626
627 fbi->map_size = info->fix.smem_len;
628
629 if (fbi->map_cpu) {
630 /* prevent initial garbage on screen */
631 dprintk("map_video_memory: clear %p:%08x\n",
632 fbi->map_cpu, fbi->map_size);
633 memset(fbi->map_cpu, 0xf0, fbi->map_size);
634
635 fbi->screen_dma = fbi->map_dma;
636 info->screen_base = fbi->map_cpu;
637 info->fix.smem_start = fbi->screen_dma;
638
639 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
640 fbi->map_dma, fbi->map_cpu, info->fix.smem_len);
641 }
642
643 return fbi->map_cpu ? 0 : -ENOMEM;
644 }
645
646 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
647 {
648 dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu,
649 fbi->map_dma);
650 }
651
652 static inline void modify_gpio(void __iomem *reg,
653 unsigned long set, unsigned long mask)
654 {
655 unsigned long tmp;
656
657 tmp = readl(reg) & ~mask;
658 writel(tmp | set, reg);
659 }
660
661 /*
662 * s3c2410fb_init_registers - Initialise all LCD-related registers
663 */
664 static int s3c2410fb_init_registers(struct fb_info *info)
665 {
666 struct s3c2410fb_info *fbi = info->par;
667 unsigned long flags;
668 void __iomem *regs = fbi->io;
669
670 /* Initialise LCD with values from haret */
671
672 local_irq_save(flags);
673
674 /* modify the gpio(s) with interrupts set (bjd) */
675
676 modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask);
677 modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
678 modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask);
679 modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
680
681 local_irq_restore(flags);
682
683 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
684 writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
685 writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
686 writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
687 writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
688
689 s3c2410fb_set_lcdaddr(info);
690
691 dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
692 writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
693
694 dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
695
696 /* ensure temporary palette disabled */
697 writel(0x00, regs + S3C2410_TPAL);
698
699 /* Enable video by setting the ENVID bit to 1 */
700 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
701 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
702 return 0;
703 }
704
705 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
706 {
707 unsigned int i;
708 void __iomem *regs = fbi->io;
709
710 fbi->palette_ready = 0;
711
712 for (i = 0; i < 256; i++) {
713 unsigned long ent = fbi->palette_buffer[i];
714 if (ent == PALETTE_BUFF_CLEAR)
715 continue;
716
717 writel(ent, regs + S3C2410_TFTPAL(i));
718
719 /* it seems the only way to know exactly
720 * if the palette wrote ok, is to check
721 * to see if the value verifies ok
722 */
723
724 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
725 fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
726 else
727 fbi->palette_ready = 1; /* retry */
728 }
729 }
730
731 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
732 {
733 struct s3c2410fb_info *fbi = dev_id;
734 void __iomem *regs = fbi->io;
735 unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
736
737 if (lcdirq & S3C2410_LCDINT_FRSYNC) {
738 if (fbi->palette_ready)
739 s3c2410fb_write_palette(fbi);
740
741 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
742 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
743 }
744
745 return IRQ_HANDLED;
746 }
747
748 static char driver_name[] = "s3c2410fb";
749
750 static int __init s3c2410fb_probe(struct platform_device *pdev)
751 {
752 struct s3c2410fb_info *info;
753 struct fb_info *fbinfo;
754 struct s3c2410fb_hw *mregs;
755 struct resource *res;
756 int ret;
757 int irq;
758 int i;
759 int size;
760 u32 lcdcon1;
761
762 mach_info = pdev->dev.platform_data;
763 if (mach_info == NULL) {
764 dev_err(&pdev->dev,
765 "no platform data for lcd, cannot attach\n");
766 return -EINVAL;
767 }
768
769 mregs = &mach_info->regs;
770
771 irq = platform_get_irq(pdev, 0);
772 if (irq < 0) {
773 dev_err(&pdev->dev, "no irq for device\n");
774 return -ENOENT;
775 }
776
777 fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
778 if (!fbinfo)
779 return -ENOMEM;
780
781 info = fbinfo->par;
782 info->dev = &pdev->dev;
783
784 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
785 if (res == NULL) {
786 dev_err(&pdev->dev, "failed to get memory registers\n");
787 ret = -ENXIO;
788 goto dealloc_fb;
789 }
790
791 size = (res->end - res->start) + 1;
792 info->mem = request_mem_region(res->start, size, pdev->name);
793 if (info->mem == NULL) {
794 dev_err(&pdev->dev, "failed to get memory region\n");
795 ret = -ENOENT;
796 goto dealloc_fb;
797 }
798
799 info->io = ioremap(res->start, size);
800 if (info->io == NULL) {
801 dev_err(&pdev->dev, "ioremap() of registers failed\n");
802 ret = -ENXIO;
803 goto release_mem;
804 }
805
806 platform_set_drvdata(pdev, fbinfo);
807
808 dprintk("devinit\n");
809
810 strcpy(fbinfo->fix.id, driver_name);
811
812 memcpy(&info->regs, &mach_info->regs, sizeof(info->regs));
813
814 /* Stop the video and unset ENVID if set */
815 info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
816 lcdcon1 = readl(info->io + S3C2410_LCDCON1);
817 writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
818
819 info->mach_info = pdev->dev.platform_data;
820
821 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
822 fbinfo->fix.type_aux = 0;
823 fbinfo->fix.xpanstep = 0;
824 fbinfo->fix.ypanstep = 0;
825 fbinfo->fix.ywrapstep = 0;
826 fbinfo->fix.accel = FB_ACCEL_NONE;
827
828 fbinfo->var.nonstd = 0;
829 fbinfo->var.activate = FB_ACTIVATE_NOW;
830 fbinfo->var.height = mach_info->height;
831 fbinfo->var.width = mach_info->width;
832 fbinfo->var.accel_flags = 0;
833 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
834
835 fbinfo->fbops = &s3c2410fb_ops;
836 fbinfo->flags = FBINFO_FLAG_DEFAULT;
837 fbinfo->pseudo_palette = &info->pseudo_pal;
838
839 fbinfo->var.xres = mach_info->xres.defval;
840 fbinfo->var.xres_virtual = mach_info->xres.defval;
841 fbinfo->var.yres = mach_info->yres.defval;
842 fbinfo->var.yres_virtual = mach_info->yres.defval;
843 fbinfo->var.bits_per_pixel = mach_info->bpp.defval;
844
845 fbinfo->var.upper_margin =
846 S3C2410_LCDCON2_GET_VBPD(mregs->lcdcon2) + 1;
847 fbinfo->var.lower_margin =
848 S3C2410_LCDCON2_GET_VFPD(mregs->lcdcon2) + 1;
849 fbinfo->var.vsync_len =
850 S3C2410_LCDCON2_GET_VSPW(mregs->lcdcon2) + 1;
851
852 fbinfo->var.left_margin =
853 S3C2410_LCDCON3_GET_HFPD(mregs->lcdcon3) + 1;
854 fbinfo->var.right_margin =
855 S3C2410_LCDCON3_GET_HBPD(mregs->lcdcon3) + 1;
856 fbinfo->var.hsync_len =
857 S3C2410_LCDCON4_GET_HSPW(mregs->lcdcon4) + 1;
858
859 fbinfo->var.red.offset = 11;
860 fbinfo->var.green.offset = 5;
861 fbinfo->var.blue.offset = 0;
862 fbinfo->var.transp.offset = 0;
863 fbinfo->var.red.length = 5;
864 fbinfo->var.green.length = 6;
865 fbinfo->var.blue.length = 5;
866 fbinfo->var.transp.length = 0;
867 fbinfo->fix.smem_len = mach_info->xres.max *
868 mach_info->yres.max *
869 mach_info->bpp.max / 8;
870
871 for (i = 0; i < 256; i++)
872 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
873
874 ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
875 if (ret) {
876 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
877 ret = -EBUSY;
878 goto release_regs;
879 }
880
881 info->clk = clk_get(NULL, "lcd");
882 if (!info->clk || IS_ERR(info->clk)) {
883 printk(KERN_ERR "failed to get lcd clock source\n");
884 ret = -ENOENT;
885 goto release_irq;
886 }
887
888 clk_enable(info->clk);
889 dprintk("got and enabled clock\n");
890
891 msleep(1);
892
893 /* Initialize video memory */
894 ret = s3c2410fb_map_video_memory(fbinfo);
895 if (ret) {
896 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
897 ret = -ENOMEM;
898 goto release_clock;
899 }
900
901 dprintk("got video memory\n");
902
903 s3c2410fb_init_registers(fbinfo);
904
905 s3c2410fb_check_var(&fbinfo->var, fbinfo);
906
907 ret = register_framebuffer(fbinfo);
908 if (ret < 0) {
909 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
910 ret);
911 goto free_video_memory;
912 }
913
914 /* create device files */
915 device_create_file(&pdev->dev, &dev_attr_debug);
916
917 printk(KERN_INFO "fb%d: %s frame buffer device\n",
918 fbinfo->node, fbinfo->fix.id);
919
920 return 0;
921
922 free_video_memory:
923 s3c2410fb_unmap_video_memory(info);
924 release_clock:
925 clk_disable(info->clk);
926 clk_put(info->clk);
927 release_irq:
928 free_irq(irq, info);
929 release_regs:
930 iounmap(info->io);
931 release_mem:
932 release_resource(info->mem);
933 kfree(info->mem);
934 dealloc_fb:
935 framebuffer_release(fbinfo);
936 return ret;
937 }
938
939 /* s3c2410fb_stop_lcd
940 *
941 * shutdown the lcd controller
942 */
943 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
944 {
945 unsigned long flags;
946
947 local_irq_save(flags);
948
949 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
950 writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
951
952 local_irq_restore(flags);
953 }
954
955 /*
956 * Cleanup
957 */
958 static int s3c2410fb_remove(struct platform_device *pdev)
959 {
960 struct fb_info *fbinfo = platform_get_drvdata(pdev);
961 struct s3c2410fb_info *info = fbinfo->par;
962 int irq;
963
964 s3c2410fb_stop_lcd(info);
965 msleep(1);
966
967 s3c2410fb_unmap_video_memory(info);
968
969 if (info->clk) {
970 clk_disable(info->clk);
971 clk_put(info->clk);
972 info->clk = NULL;
973 }
974
975 irq = platform_get_irq(pdev, 0);
976 free_irq(irq, info);
977
978 release_resource(info->mem);
979 kfree(info->mem);
980 iounmap(info->io);
981 unregister_framebuffer(fbinfo);
982
983 return 0;
984 }
985
986 #ifdef CONFIG_PM
987
988 /* suspend and resume support for the lcd controller */
989 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
990 {
991 struct fb_info *fbinfo = platform_get_drvdata(dev);
992 struct s3c2410fb_info *info = fbinfo->par;
993
994 s3c2410fb_stop_lcd(info);
995
996 /* sleep before disabling the clock, we need to ensure
997 * the LCD DMA engine is not going to get back on the bus
998 * before the clock goes off again (bjd) */
999
1000 msleep(1);
1001 clk_disable(info->clk);
1002
1003 return 0;
1004 }
1005
1006 static int s3c2410fb_resume(struct platform_device *dev)
1007 {
1008 struct fb_info *fbinfo = platform_get_drvdata(dev);
1009 struct s3c2410fb_info *info = fbinfo->par;
1010
1011 clk_enable(info->clk);
1012 msleep(1);
1013
1014 s3c2410fb_init_registers(info);
1015
1016 return 0;
1017 }
1018
1019 #else
1020 #define s3c2410fb_suspend NULL
1021 #define s3c2410fb_resume NULL
1022 #endif
1023
1024 static struct platform_driver s3c2410fb_driver = {
1025 .probe = s3c2410fb_probe,
1026 .remove = s3c2410fb_remove,
1027 .suspend = s3c2410fb_suspend,
1028 .resume = s3c2410fb_resume,
1029 .driver = {
1030 .name = "s3c2410-lcd",
1031 .owner = THIS_MODULE,
1032 },
1033 };
1034
1035 int __devinit s3c2410fb_init(void)
1036 {
1037 return platform_driver_register(&s3c2410fb_driver);
1038 }
1039
1040 static void __exit s3c2410fb_cleanup(void)
1041 {
1042 platform_driver_unregister(&s3c2410fb_driver);
1043 }
1044
1045 module_init(s3c2410fb_init);
1046 module_exit(s3c2410fb_cleanup);
1047
1048 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1049 "Ben Dooks <ben-linux@fluff.org>");
1050 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1051 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree