drivers/hwmon/coretemp.c

   1 /*
   2  * coretemp.c - Linux kernel module for hardware monitoring
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * Inspired from many hwmon drivers
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301 USA.
  21  */
  22
  23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  24
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/slab.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/hwmon.h>
  30 #include <linux/sysfs.h>
  31 #include <linux/hwmon-sysfs.h>
  32 #include <linux/err.h>
  33 #include <linux/mutex.h>
  34 #include <linux/list.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/cpu.h>
  37 #include <linux/pci.h>
  38 #include <asm/msr.h>
  39 #include <asm/processor.h>
  40 #include <asm/smp.h>
  41
  42 #define DRVNAME "coretemp"
  43
  44 typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL,
  45                 SHOW_NAME } SHOW;
  46
  47 /*
  48  * Functions declaration
  49  */
  50
  51 static struct coretemp_data *coretemp_update_device(struct device *dev);
  52
  53 struct coretemp_data {
  54         struct device *hwmon_dev;
  55         struct mutex update_lock;
  56         const char *name;
  57         u32 id;
  58         u16 core_id;
  59         char valid;             /* zero until following fields are valid */
  60         unsigned long last_updated;     /* in jiffies */
  61         int temp;
  62         int tjmax;
  63         int ttarget;
  64         u8 alarm;
  65 };
  66
  67 /*
  68  * Sysfs stuff
  69  */
  70
  71 static ssize_t show_name(struct device *dev, struct device_attribute
  72                           *devattr, char *buf)
  73 {
  74         int ret;
  75         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  76         struct coretemp_data *data = dev_get_drvdata(dev);
  77
  78         if (attr->index == SHOW_NAME)
  79                 ret = sprintf(buf, "%s\n", data->name);
  80         else    /* show label */
  81                 ret = sprintf(buf, "Core %d\n", data->core_id);
  82         return ret;
  83 }
  84
  85 static ssize_t show_alarm(struct device *dev, struct device_attribute
  86                           *devattr, char *buf)
  87 {
  88         struct coretemp_data *data = coretemp_update_device(dev);
  89         /* read the Out-of-spec log, never clear */
  90         return sprintf(buf, "%d\n", data->alarm);
  91 }
  92
  93 static ssize_t show_temp(struct device *dev,
  94                          struct device_attribute *devattr, char *buf)
  95 {
  96         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  97         struct coretemp_data *data = coretemp_update_device(dev);
  98         int err;
  99
 100         if (attr->index == SHOW_TEMP)
 101                 err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN;
 102         else if (attr->index == SHOW_TJMAX)
 103                 err = sprintf(buf, "%d\n", data->tjmax);
 104         else
 105                 err = sprintf(buf, "%d\n", data->ttarget);
 106         return err;
 107 }
 108
 109 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL,
 110                           SHOW_TEMP);
 111 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL,
 112                           SHOW_TJMAX);
 113 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL,
 114                           SHOW_TTARGET);
 115 static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL);
 116 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL);
 117 static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME);
 118
 119 static struct attribute *coretemp_attributes[] = {
 120         &sensor_dev_attr_name.dev_attr.attr,
 121         &sensor_dev_attr_temp1_label.dev_attr.attr,
 122         &dev_attr_temp1_crit_alarm.attr,
 123         &sensor_dev_attr_temp1_input.dev_attr.attr,
 124         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 125         NULL
 126 };
 127
 128 static const struct attribute_group coretemp_group = {
 129         .attrs = coretemp_attributes,
 130 };
 131
 132 static struct coretemp_data *coretemp_update_device(struct device *dev)
 133 {
 134         struct coretemp_data *data = dev_get_drvdata(dev);
 135
 136         mutex_lock(&data->update_lock);
 137
 138         if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
 139                 u32 eax, edx;
 140
 141                 data->valid = 0;
 142                 rdmsr_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
 143                 data->alarm = (eax >> 5) & 1;
 144                 /* update only if data has been valid */
 145                 if (eax & 0x80000000) {
 146                         data->temp = data->tjmax - (((eax >> 16)
 147                                                         & 0x7f) * 1000);
 148                         data->valid = 1;
 149                 } else {
 150                         dev_dbg(dev, "Temperature data invalid (0x%x)\n", eax);
 151                 }
 152                 data->last_updated = jiffies;
 153         }
 154
 155         mutex_unlock(&data->update_lock);
 156         return data;
 157 }
 158
 159 static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
 160 {
 161         /* The 100C is default for both mobile and non mobile CPUs */
 162
 163         int tjmax = 100000;
 164         int tjmax_ee = 85000;
 165         int usemsr_ee = 1;
 166         int err;
 167         u32 eax, edx;
 168         struct pci_dev *host_bridge;
 169
 170         /* Early chips have no MSR for TjMax */
 171
 172         if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
 173                 usemsr_ee = 0;
 174         }
 175
 176         /* Atom CPUs */
 177
 178         if (c->x86_model == 0x1c) {
 179                 usemsr_ee = 0;
 180
 181                 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 182
 183                 if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
 184                     && (host_bridge->device == 0xa000   /* NM10 based nettop */
 185                     || host_bridge->device == 0xa010))  /* NM10 based netbook */
 186                         tjmax = 100000;
 187                 else
 188                         tjmax = 90000;
 189
 190                 pci_dev_put(host_bridge);
 191         }
 192
 193         if ((c->x86_model > 0xe) && (usemsr_ee)) {
 194                 u8 platform_id;
 195
 196                 /* Now we can detect the mobile CPU using Intel provided table
 197                    http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
 198                    For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
 199                 */
 200
 201                 err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
 202                 if (err) {
 203                         dev_warn(dev,
 204                                  "Unable to access MSR 0x17, assuming desktop"
 205                                  " CPU\n");
 206                         usemsr_ee = 0;
 207                 } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
 208                         /* Trust bit 28 up to Penryn, I could not find any
 209                            documentation on that; if you happen to know
 210                            someone at Intel please ask */
 211                         usemsr_ee = 0;
 212                 } else {
 213                         /* Platform ID bits 52:50 (EDX starts at bit 32) */
 214                         platform_id = (edx >> 18) & 0x7;
 215
 216                         /* Mobile Penryn CPU seems to be platform ID 7 or 5
 217                           (guesswork) */
 218                         if ((c->x86_model == 0x17) &&
 219                             ((platform_id == 5) || (platform_id == 7))) {
 220                                 /* If MSR EE bit is set, set it to 90 degrees C,
 221                                    otherwise 105 degrees C */
 222                                 tjmax_ee = 90000;
 223                                 tjmax = 105000;
 224                         }
 225                 }
 226         }
 227
 228         if (usemsr_ee) {
 229
 230                 err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
 231                 if (err) {
 232                         dev_warn(dev,
 233                                  "Unable to access MSR 0xEE, for Tjmax, left"
 234                                  " at default\n");
 235                 } else if (eax & 0x40000000) {
 236                         tjmax = tjmax_ee;
 237                 }
 238         /* if we dont use msr EE it means we are desktop CPU (with exeception
 239            of Atom) */
 240         } else if (tjmax == 100000) {
 241                 dev_warn(dev, "Using relative temperature scale!\n");
 242         }
 243
 244         return tjmax;
 245 }
 246
 247 static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
 248                                struct device *dev)
 249 {
 250         /* The 100C is default for both mobile and non mobile CPUs */
 251         int err;
 252         u32 eax, edx;
 253         u32 val;
 254
 255         /* A new feature of current Intel(R) processors, the
 256            IA32_TEMPERATURE_TARGET contains the TjMax value */
 257         err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
 258         if (err) {
 259                 dev_warn(dev, "Unable to read TjMax from CPU.\n");
 260         } else {
 261                 val = (eax >> 16) & 0xff;
 262                 /*
 263                  * If the TjMax is not plausible, an assumption
 264                  * will be used
 265                  */
 266                 if (val >= 70 && val <= 125) {
 267                         dev_info(dev, "TjMax is %d C.\n", val);
 268                         return val * 1000;
 269                 }
 270         }
 271
 272         /*
 273          * An assumption is made for early CPUs and unreadable MSR.
 274          * NOTE: the calculated value may not be correct.
 275          */
 276         return adjust_tjmax(c, id, dev);
 277 }
 278
 279 static void __devinit get_ucode_rev_on_cpu(void *edx)
 280 {
 281         u32 eax;
 282
 283         wrmsr(MSR_IA32_UCODE_REV, 0, 0);
 284         sync_core();
 285         rdmsr(MSR_IA32_UCODE_REV, eax, *(u32 *)edx);
 286 }
 287
 288 static int __devinit coretemp_probe(struct platform_device *pdev)
 289 {
 290         struct coretemp_data *data;
 291         struct cpuinfo_x86 *c = &cpu_data(pdev->id);
 292         int err;
 293         u32 eax, edx;
 294
 295         if (!(data = kzalloc(sizeof(struct coretemp_data), GFP_KERNEL))) {
 296                 err = -ENOMEM;
 297                 dev_err(&pdev->dev, "Out of memory\n");
 298                 goto exit;
 299         }
 300
 301         data->id = pdev->id;
 302 #ifdef CONFIG_SMP
 303         data->core_id = c->cpu_core_id;
 304 #endif
 305         data->name = "coretemp";
 306         mutex_init(&data->update_lock);
 307
 308         /* test if we can access the THERM_STATUS MSR */
 309         err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
 310         if (err) {
 311                 dev_err(&pdev->dev,
 312                         "Unable to access THERM_STATUS MSR, giving up\n");
 313                 goto exit_free;
 314         }
 315
 316         /* Check if we have problem with errata AE18 of Core processors:
 317            Readings might stop update when processor visited too deep sleep,
 318            fixed for stepping D0 (6EC).
 319         */
 320
 321         if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) {
 322                 /* check for microcode update */
 323                 err = smp_call_function_single(data->id, get_ucode_rev_on_cpu,
 324                                                &edx, 1);
 325                 if (err) {
 326                         dev_err(&pdev->dev,
 327                                 "Cannot determine microcode revision of "
 328                                 "CPU#%u (%d)!\n", data->id, err);
 329                         err = -ENODEV;
 330                         goto exit_free;
 331                 } else if (edx < 0x39) {
 332                         err = -ENODEV;
 333                         dev_err(&pdev->dev,
 334                                 "Errata AE18 not fixed, update BIOS or "
 335                                 "microcode of the CPU!\n");
 336                         goto exit_free;
 337                 }
 338         }
 339
 340         data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 341         platform_set_drvdata(pdev, data);
 342
 343         /*
 344          * read the still undocumented IA32_TEMPERATURE_TARGET. It exists
 345          * on older CPUs but not in this register,
 346          * Atoms don't have it either.
 347          */
 348
 349         if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
 350                 err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
 351                     &eax, &edx);
 352                 if (err) {
 353                         dev_warn(&pdev->dev, "Unable to read"
 354                                         " IA32_TEMPERATURE_TARGET MSR\n");
 355                 } else {
 356                         data->ttarget = data->tjmax -
 357                                         (((eax >> 8) & 0xff) * 1000);
 358                         err = device_create_file(&pdev->dev,
 359                                         &sensor_dev_attr_temp1_max.dev_attr);
 360                         if (err)
 361                                 goto exit_free;
 362                 }
 363         }
 364
 365         if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group)))
 366                 goto exit_dev;
 367
 368         data->hwmon_dev = hwmon_device_register(&pdev->dev);
 369         if (IS_ERR(data->hwmon_dev)) {
 370                 err = PTR_ERR(data->hwmon_dev);
 371                 dev_err(&pdev->dev, "Class registration failed (%d)\n",
 372                         err);
 373                 goto exit_class;
 374         }
 375
 376         return 0;
 377
 378 exit_class:
 379         sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
 380 exit_dev:
 381         device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
 382 exit_free:
 383         kfree(data);
 384 exit:
 385         return err;
 386 }
 387
 388 static int __devexit coretemp_remove(struct platform_device *pdev)
 389 {
 390         struct coretemp_data *data = platform_get_drvdata(pdev);
 391
 392         hwmon_device_unregister(data->hwmon_dev);
 393         sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
 394         device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
 395         platform_set_drvdata(pdev, NULL);
 396         kfree(data);
 397         return 0;
 398 }
 399
 400 static struct platform_driver coretemp_driver = {
 401         .driver = {
 402                 .owner = THIS_MODULE,
 403                 .name = DRVNAME,
 404         },
 405         .probe = coretemp_probe,
 406         .remove = __devexit_p(coretemp_remove),
 407 };
 408
 409 struct pdev_entry {
 410         struct list_head list;
 411         struct platform_device *pdev;
 412         unsigned int cpu;
 413 #ifdef CONFIG_SMP
 414         u16 phys_proc_id;
 415         u16 cpu_core_id;
 416 #endif
 417 };
 418
 419 static LIST_HEAD(pdev_list);
 420 static DEFINE_MUTEX(pdev_list_mutex);
 421
 422 static int __cpuinit coretemp_device_add(unsigned int cpu)
 423 {
 424         int err;
 425         struct platform_device *pdev;
 426         struct pdev_entry *pdev_entry;
 427         struct cpuinfo_x86 *c = &cpu_data(cpu);
 428
 429         /*
 430          * CPUID.06H.EAX[0] indicates whether the CPU has thermal
 431          * sensors. We check this bit only, all the early CPUs
 432          * without thermal sensors will be filtered out.
 433          */
 434         if (!cpu_has(c, X86_FEATURE_DTS)) {
 435                 pr_info("CPU (model=0x%x) has no thermal sensor\n",
 436                         c->x86_model);
 437                 return 0;
 438         }
 439
 440         mutex_lock(&pdev_list_mutex);
 441
 442 #ifdef CONFIG_SMP
 443         /* Skip second HT entry of each core */
 444         list_for_each_entry(pdev_entry, &pdev_list, list) {
 445                 if (c->phys_proc_id == pdev_entry->phys_proc_id &&
 446                     c->cpu_core_id == pdev_entry->cpu_core_id) {
 447                         err = 0;        /* Not an error */
 448                         goto exit;
 449                 }
 450         }
 451 #endif
 452
 453         pdev = platform_device_alloc(DRVNAME, cpu);
 454         if (!pdev) {
 455                 err = -ENOMEM;
 456                 pr_err("Device allocation failed\n");
 457                 goto exit;
 458         }
 459
 460         pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
 461         if (!pdev_entry) {
 462                 err = -ENOMEM;
 463                 goto exit_device_put;
 464         }
 465
 466         err = platform_device_add(pdev);
 467         if (err) {
 468                 pr_err("Device addition failed (%d)\n", err);
 469                 goto exit_device_free;
 470         }
 471
 472         pdev_entry->pdev = pdev;
 473         pdev_entry->cpu = cpu;
 474 #ifdef CONFIG_SMP
 475         pdev_entry->phys_proc_id = c->phys_proc_id;
 476         pdev_entry->cpu_core_id = c->cpu_core_id;
 477 #endif
 478         list_add_tail(&pdev_entry->list, &pdev_list);
 479         mutex_unlock(&pdev_list_mutex);
 480
 481         return 0;
 482
 483 exit_device_free:
 484         kfree(pdev_entry);
 485 exit_device_put:
 486         platform_device_put(pdev);
 487 exit:
 488         mutex_unlock(&pdev_list_mutex);
 489         return err;
 490 }
 491
 492 static void __cpuinit coretemp_device_remove(unsigned int cpu)
 493 {
 494         struct pdev_entry *p;
 495         unsigned int i;
 496
 497         mutex_lock(&pdev_list_mutex);
 498         list_for_each_entry(p, &pdev_list, list) {
 499                 if (p->cpu != cpu)
 500                         continue;
 501
 502                 platform_device_unregister(p->pdev);
 503                 list_del(&p->list);
 504                 mutex_unlock(&pdev_list_mutex);
 505                 kfree(p);
 506                 for_each_cpu(i, cpu_sibling_mask(cpu))
 507                         if (i != cpu && !coretemp_device_add(i))
 508                                 break;
 509                 return;
 510         }
 511         mutex_unlock(&pdev_list_mutex);
 512 }
 513
 514 static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb,
 515                                  unsigned long action, void *hcpu)
 516 {
 517         unsigned int cpu = (unsigned long) hcpu;
 518
 519         switch (action) {
 520         case CPU_ONLINE:
 521         case CPU_DOWN_FAILED:
 522                 coretemp_device_add(cpu);
 523                 break;
 524         case CPU_DOWN_PREPARE:
 525                 coretemp_device_remove(cpu);
 526                 break;
 527         }
 528         return NOTIFY_OK;
 529 }
 530
 531 static struct notifier_block coretemp_cpu_notifier __refdata = {
 532         .notifier_call = coretemp_cpu_callback,
 533 };
 534
 535 static int __init coretemp_init(void)
 536 {
 537         int i, err = -ENODEV;
 538
 539         /* quick check if we run Intel */
 540         if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
 541                 goto exit;
 542
 543         err = platform_driver_register(&coretemp_driver);
 544         if (err)
 545                 goto exit;
 546
 547         for_each_online_cpu(i)
 548                 coretemp_device_add(i);
 549
 550 #ifndef CONFIG_HOTPLUG_CPU
 551         if (list_empty(&pdev_list)) {
 552                 err = -ENODEV;
 553                 goto exit_driver_unreg;
 554         }
 555 #endif
 556
 557         register_hotcpu_notifier(&coretemp_cpu_notifier);
 558         return 0;
 559
 560 #ifndef CONFIG_HOTPLUG_CPU
 561 exit_driver_unreg:
 562         platform_driver_unregister(&coretemp_driver);
 563 #endif
 564 exit:
 565         return err;
 566 }
 567
 568 static void __exit coretemp_exit(void)
 569 {
 570         struct pdev_entry *p, *n;
 571
 572         unregister_hotcpu_notifier(&coretemp_cpu_notifier);
 573         mutex_lock(&pdev_list_mutex);
 574         list_for_each_entry_safe(p, n, &pdev_list, list) {
 575                 platform_device_unregister(p->pdev);
 576                 list_del(&p->list);
 577                 kfree(p);
 578         }
 579         mutex_unlock(&pdev_list_mutex);
 580         platform_driver_unregister(&coretemp_driver);
 581 }
 582
 583 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
 584 MODULE_DESCRIPTION("Intel Core temperature monitor");
 585 MODULE_LICENSE("GPL");
 586
 587 module_init(coretemp_init)
 588 module_exit(coretemp_exit)