arch/arm/mach-at91rm9200/irq.c

   1 /*
   2  * linux/arch/arm/mach-at91rm9200/irq.c
   3  *
   4  *  Copyright (C) 2004 SAN People
   5  *  Copyright (C) 2004 ATMEL
   6  *  Copyright (C) Rick Bronson
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/mm.h>
  26 #include <linux/types.h>
  27
  28 #include <asm/hardware.h>
  29 #include <asm/irq.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/setup.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/irq.h>
  35 #include <asm/mach/map.h>
  36
  37
  38 static void at91_aic_mask_irq(unsigned int irq)
  39 {
  40         /* Disable interrupt on AIC */
  41         at91_sys_write(AT91_AIC_IDCR, 1 << irq);
  42 }
  43
  44 static void at91_aic_unmask_irq(unsigned int irq)
  45 {
  46         /* Enable interrupt on AIC */
  47         at91_sys_write(AT91_AIC_IECR, 1 << irq);
  48 }
  49
  50 static int at91_aic_set_type(unsigned irq, unsigned type)
  51 {
  52         unsigned int smr, srctype;
  53
  54         switch (type) {
  55         case IRQT_HIGH:
  56                 srctype = AT91_AIC_SRCTYPE_HIGH;
  57                 break;
  58         case IRQT_RISING:
  59                 srctype = AT91_AIC_SRCTYPE_RISING;
  60                 break;
  61         case IRQT_LOW:
  62                 if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0))  /* only supported on external interrupts */
  63                         return -EINVAL;
  64                 srctype = AT91_AIC_SRCTYPE_LOW;
  65                 break;
  66         case IRQT_FALLING:
  67                 if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0))  /* only supported on external interrupts */
  68                         return -EINVAL;
  69                 srctype = AT91_AIC_SRCTYPE_FALLING;
  70                 break;
  71         default:
  72                 return -EINVAL;
  73         }
  74
  75         smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
  76         at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
  77         return 0;
  78 }
  79
  80 #ifdef CONFIG_PM
  81
  82 static u32 wakeups;
  83 static u32 backups;
  84
  85 static int at91_aic_set_wake(unsigned irq, unsigned value)
  86 {
  87         if (unlikely(irq >= 32))
  88                 return -EINVAL;
  89
  90         if (value)
  91                 wakeups |= (1 << irq);
  92         else
  93                 wakeups &= ~(1 << irq);
  94
  95         return 0;
  96 }
  97
  98 void at91_irq_suspend(void)
  99 {
 100         backups = at91_sys_read(AT91_AIC_IMR);
 101         at91_sys_write(AT91_AIC_IDCR, backups);
 102         at91_sys_write(AT91_AIC_IECR, wakeups);
 103 }
 104
 105 void at91_irq_resume(void)
 106 {
 107         at91_sys_write(AT91_AIC_IDCR, wakeups);
 108         at91_sys_write(AT91_AIC_IECR, backups);
 109 }
 110
 111 #else
 112 #define at91_aic_set_wake       NULL
 113 #endif
 114
 115 static struct irq_chip at91_aic_chip = {
 116         .name           = "AIC",
 117         .ack            = at91_aic_mask_irq,
 118         .mask           = at91_aic_mask_irq,
 119         .unmask         = at91_aic_unmask_irq,
 120         .set_type       = at91_aic_set_type,
 121         .set_wake       = at91_aic_set_wake,
 122 };
 123
 124 /*
 125  * Initialize the AIC interrupt controller.
 126  */
 127 void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
 128 {
 129         unsigned int i;
 130
 131         /*
 132          * The IVR is used by macro get_irqnr_and_base to read and verify.
 133          * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
 134          */
 135         for (i = 0; i < NR_AIC_IRQS; i++) {
 136                 /* Put irq number in Source Vector Register: */
 137                 at91_sys_write(AT91_AIC_SVR(i), i);
 138                 /* Active Low interrupt, with the specified priority */
 139                 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
 140
 141                 set_irq_chip(i, &at91_aic_chip);
 142                 set_irq_handler(i, handle_level_irq);
 143                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 144
 145                 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
 146                 if (i < 8)
 147                         at91_sys_write(AT91_AIC_EOICR, 0);
 148         }
 149
 150         /*
 151          * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
 152          * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
 153          */
 154         at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);
 155
 156         /* No debugging in AIC: Debug (Protect) Control Register */
 157         at91_sys_write(AT91_AIC_DCR, 0);
 158
 159         /* Disable and clear all interrupts initially */
 160         at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
 161         at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 162 }