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b43: add my copyrights and myself as the module author
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / b43 / main.c
blob24077023d4846d0af06c68d18d37d0beedb1eef1
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
11
12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33 */
34
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/moduleparam.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
47
48 #include "b43.h"
49 #include "main.h"
50 #include "debugfs.h"
51 #include "phy_common.h"
52 #include "phy_g.h"
53 #include "phy_n.h"
54 #include "dma.h"
55 #include "pio.h"
56 #include "sysfs.h"
57 #include "xmit.h"
58 #include "lo.h"
59 #include "pcmcia.h"
60 #include "sdio.h"
61 #include <linux/mmc/sdio_func.h>
62
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
70
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
78
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
107
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
115
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
122 BCMA_CORETABLE_END
123 };
124 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
125 #endif
126
127 #ifdef CONFIG_B43_SSB
128 static const struct ssb_device_id b43_ssb_tbl[] = {
129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
139 SSB_DEVTABLE_END
140 };
141 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
142 #endif
143
144 /* Channel and ratetables are shared for all devices.
145 * They can't be const, because ieee80211 puts some precalculated
146 * data in there. This data is the same for all devices, so we don't
147 * get concurrency issues */
148 #define RATETAB_ENT(_rateid, _flags) \
149 { \
150 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
151 .hw_value = (_rateid), \
152 .flags = (_flags), \
153 }
154
155 /*
156 * NOTE: When changing this, sync with xmit.c's
157 * b43_plcp_get_bitrate_idx_* functions!
158 */
159 static struct ieee80211_rate __b43_ratetable[] = {
160 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
161 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
162 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
163 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
165 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
166 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
172 };
173
174 #define b43_a_ratetable (__b43_ratetable + 4)
175 #define b43_a_ratetable_size 8
176 #define b43_b_ratetable (__b43_ratetable + 0)
177 #define b43_b_ratetable_size 4
178 #define b43_g_ratetable (__b43_ratetable + 0)
179 #define b43_g_ratetable_size 12
180
181 #define CHAN4G(_channel, _freq, _flags) { \
182 .band = IEEE80211_BAND_2GHZ, \
183 .center_freq = (_freq), \
184 .hw_value = (_channel), \
185 .flags = (_flags), \
186 .max_antenna_gain = 0, \
187 .max_power = 30, \
188 }
189 static struct ieee80211_channel b43_2ghz_chantable[] = {
190 CHAN4G(1, 2412, 0),
191 CHAN4G(2, 2417, 0),
192 CHAN4G(3, 2422, 0),
193 CHAN4G(4, 2427, 0),
194 CHAN4G(5, 2432, 0),
195 CHAN4G(6, 2437, 0),
196 CHAN4G(7, 2442, 0),
197 CHAN4G(8, 2447, 0),
198 CHAN4G(9, 2452, 0),
199 CHAN4G(10, 2457, 0),
200 CHAN4G(11, 2462, 0),
201 CHAN4G(12, 2467, 0),
202 CHAN4G(13, 2472, 0),
203 CHAN4G(14, 2484, 0),
204 };
205 #undef CHAN4G
206
207 #define CHAN5G(_channel, _flags) { \
208 .band = IEEE80211_BAND_5GHZ, \
209 .center_freq = 5000 + (5 * (_channel)), \
210 .hw_value = (_channel), \
211 .flags = (_flags), \
212 .max_antenna_gain = 0, \
213 .max_power = 30, \
214 }
215 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
216 CHAN5G(32, 0), CHAN5G(34, 0),
217 CHAN5G(36, 0), CHAN5G(38, 0),
218 CHAN5G(40, 0), CHAN5G(42, 0),
219 CHAN5G(44, 0), CHAN5G(46, 0),
220 CHAN5G(48, 0), CHAN5G(50, 0),
221 CHAN5G(52, 0), CHAN5G(54, 0),
222 CHAN5G(56, 0), CHAN5G(58, 0),
223 CHAN5G(60, 0), CHAN5G(62, 0),
224 CHAN5G(64, 0), CHAN5G(66, 0),
225 CHAN5G(68, 0), CHAN5G(70, 0),
226 CHAN5G(72, 0), CHAN5G(74, 0),
227 CHAN5G(76, 0), CHAN5G(78, 0),
228 CHAN5G(80, 0), CHAN5G(82, 0),
229 CHAN5G(84, 0), CHAN5G(86, 0),
230 CHAN5G(88, 0), CHAN5G(90, 0),
231 CHAN5G(92, 0), CHAN5G(94, 0),
232 CHAN5G(96, 0), CHAN5G(98, 0),
233 CHAN5G(100, 0), CHAN5G(102, 0),
234 CHAN5G(104, 0), CHAN5G(106, 0),
235 CHAN5G(108, 0), CHAN5G(110, 0),
236 CHAN5G(112, 0), CHAN5G(114, 0),
237 CHAN5G(116, 0), CHAN5G(118, 0),
238 CHAN5G(120, 0), CHAN5G(122, 0),
239 CHAN5G(124, 0), CHAN5G(126, 0),
240 CHAN5G(128, 0), CHAN5G(130, 0),
241 CHAN5G(132, 0), CHAN5G(134, 0),
242 CHAN5G(136, 0), CHAN5G(138, 0),
243 CHAN5G(140, 0), CHAN5G(142, 0),
244 CHAN5G(144, 0), CHAN5G(145, 0),
245 CHAN5G(146, 0), CHAN5G(147, 0),
246 CHAN5G(148, 0), CHAN5G(149, 0),
247 CHAN5G(150, 0), CHAN5G(151, 0),
248 CHAN5G(152, 0), CHAN5G(153, 0),
249 CHAN5G(154, 0), CHAN5G(155, 0),
250 CHAN5G(156, 0), CHAN5G(157, 0),
251 CHAN5G(158, 0), CHAN5G(159, 0),
252 CHAN5G(160, 0), CHAN5G(161, 0),
253 CHAN5G(162, 0), CHAN5G(163, 0),
254 CHAN5G(164, 0), CHAN5G(165, 0),
255 CHAN5G(166, 0), CHAN5G(168, 0),
256 CHAN5G(170, 0), CHAN5G(172, 0),
257 CHAN5G(174, 0), CHAN5G(176, 0),
258 CHAN5G(178, 0), CHAN5G(180, 0),
259 CHAN5G(182, 0), CHAN5G(184, 0),
260 CHAN5G(186, 0), CHAN5G(188, 0),
261 CHAN5G(190, 0), CHAN5G(192, 0),
262 CHAN5G(194, 0), CHAN5G(196, 0),
263 CHAN5G(198, 0), CHAN5G(200, 0),
264 CHAN5G(202, 0), CHAN5G(204, 0),
265 CHAN5G(206, 0), CHAN5G(208, 0),
266 CHAN5G(210, 0), CHAN5G(212, 0),
267 CHAN5G(214, 0), CHAN5G(216, 0),
268 CHAN5G(218, 0), CHAN5G(220, 0),
269 CHAN5G(222, 0), CHAN5G(224, 0),
270 CHAN5G(226, 0), CHAN5G(228, 0),
271 };
272
273 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
274 CHAN5G(34, 0), CHAN5G(36, 0),
275 CHAN5G(38, 0), CHAN5G(40, 0),
276 CHAN5G(42, 0), CHAN5G(44, 0),
277 CHAN5G(46, 0), CHAN5G(48, 0),
278 CHAN5G(52, 0), CHAN5G(56, 0),
279 CHAN5G(60, 0), CHAN5G(64, 0),
280 CHAN5G(100, 0), CHAN5G(104, 0),
281 CHAN5G(108, 0), CHAN5G(112, 0),
282 CHAN5G(116, 0), CHAN5G(120, 0),
283 CHAN5G(124, 0), CHAN5G(128, 0),
284 CHAN5G(132, 0), CHAN5G(136, 0),
285 CHAN5G(140, 0), CHAN5G(149, 0),
286 CHAN5G(153, 0), CHAN5G(157, 0),
287 CHAN5G(161, 0), CHAN5G(165, 0),
288 CHAN5G(184, 0), CHAN5G(188, 0),
289 CHAN5G(192, 0), CHAN5G(196, 0),
290 CHAN5G(200, 0), CHAN5G(204, 0),
291 CHAN5G(208, 0), CHAN5G(212, 0),
292 CHAN5G(216, 0),
293 };
294 #undef CHAN5G
295
296 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
297 .band = IEEE80211_BAND_5GHZ,
298 .channels = b43_5ghz_nphy_chantable,
299 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
300 .bitrates = b43_a_ratetable,
301 .n_bitrates = b43_a_ratetable_size,
302 };
303
304 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
305 .band = IEEE80211_BAND_5GHZ,
306 .channels = b43_5ghz_aphy_chantable,
307 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
308 .bitrates = b43_a_ratetable,
309 .n_bitrates = b43_a_ratetable_size,
310 };
311
312 static struct ieee80211_supported_band b43_band_2GHz = {
313 .band = IEEE80211_BAND_2GHZ,
314 .channels = b43_2ghz_chantable,
315 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
316 .bitrates = b43_g_ratetable,
317 .n_bitrates = b43_g_ratetable_size,
318 };
319
320 static void b43_wireless_core_exit(struct b43_wldev *dev);
321 static int b43_wireless_core_init(struct b43_wldev *dev);
322 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
323 static int b43_wireless_core_start(struct b43_wldev *dev);
324 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
325 struct ieee80211_vif *vif,
326 struct ieee80211_bss_conf *conf,
327 u32 changed);
328
329 static int b43_ratelimit(struct b43_wl *wl)
330 {
331 if (!wl || !wl->current_dev)
332 return 1;
333 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
334 return 1;
335 /* We are up and running.
336 * Ratelimit the messages to avoid DoS over the net. */
337 return net_ratelimit();
338 }
339
340 void b43info(struct b43_wl *wl, const char *fmt, ...)
341 {
342 struct va_format vaf;
343 va_list args;
344
345 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
346 return;
347 if (!b43_ratelimit(wl))
348 return;
349
350 va_start(args, fmt);
351
352 vaf.fmt = fmt;
353 vaf.va = &args;
354
355 printk(KERN_INFO "b43-%s: %pV",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
357
358 va_end(args);
359 }
360
361 void b43err(struct b43_wl *wl, const char *fmt, ...)
362 {
363 struct va_format vaf;
364 va_list args;
365
366 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
367 return;
368 if (!b43_ratelimit(wl))
369 return;
370
371 va_start(args, fmt);
372
373 vaf.fmt = fmt;
374 vaf.va = &args;
375
376 printk(KERN_ERR "b43-%s ERROR: %pV",
377 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
378
379 va_end(args);
380 }
381
382 void b43warn(struct b43_wl *wl, const char *fmt, ...)
383 {
384 struct va_format vaf;
385 va_list args;
386
387 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
388 return;
389 if (!b43_ratelimit(wl))
390 return;
391
392 va_start(args, fmt);
393
394 vaf.fmt = fmt;
395 vaf.va = &args;
396
397 printk(KERN_WARNING "b43-%s warning: %pV",
398 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
399
400 va_end(args);
401 }
402
403 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
404 {
405 struct va_format vaf;
406 va_list args;
407
408 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
409 return;
410
411 va_start(args, fmt);
412
413 vaf.fmt = fmt;
414 vaf.va = &args;
415
416 printk(KERN_DEBUG "b43-%s debug: %pV",
417 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
418
419 va_end(args);
420 }
421
422 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
423 {
424 u32 macctl;
425
426 B43_WARN_ON(offset % 4 != 0);
427
428 macctl = b43_read32(dev, B43_MMIO_MACCTL);
429 if (macctl & B43_MACCTL_BE)
430 val = swab32(val);
431
432 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
433 mmiowb();
434 b43_write32(dev, B43_MMIO_RAM_DATA, val);
435 }
436
437 static inline void b43_shm_control_word(struct b43_wldev *dev,
438 u16 routing, u16 offset)
439 {
440 u32 control;
441
442 /* "offset" is the WORD offset. */
443 control = routing;
444 control <<= 16;
445 control |= offset;
446 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
447 }
448
449 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
450 {
451 u32 ret;
452
453 if (routing == B43_SHM_SHARED) {
454 B43_WARN_ON(offset & 0x0001);
455 if (offset & 0x0003) {
456 /* Unaligned access */
457 b43_shm_control_word(dev, routing, offset >> 2);
458 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
459 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
460 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
461
462 goto out;
463 }
464 offset >>= 2;
465 }
466 b43_shm_control_word(dev, routing, offset);
467 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
468 out:
469 return ret;
470 }
471
472 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
473 {
474 u16 ret;
475
476 if (routing == B43_SHM_SHARED) {
477 B43_WARN_ON(offset & 0x0001);
478 if (offset & 0x0003) {
479 /* Unaligned access */
480 b43_shm_control_word(dev, routing, offset >> 2);
481 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
482
483 goto out;
484 }
485 offset >>= 2;
486 }
487 b43_shm_control_word(dev, routing, offset);
488 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
489 out:
490 return ret;
491 }
492
493 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
494 {
495 if (routing == B43_SHM_SHARED) {
496 B43_WARN_ON(offset & 0x0001);
497 if (offset & 0x0003) {
498 /* Unaligned access */
499 b43_shm_control_word(dev, routing, offset >> 2);
500 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
501 value & 0xFFFF);
502 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
503 b43_write16(dev, B43_MMIO_SHM_DATA,
504 (value >> 16) & 0xFFFF);
505 return;
506 }
507 offset >>= 2;
508 }
509 b43_shm_control_word(dev, routing, offset);
510 b43_write32(dev, B43_MMIO_SHM_DATA, value);
511 }
512
513 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
514 {
515 if (routing == B43_SHM_SHARED) {
516 B43_WARN_ON(offset & 0x0001);
517 if (offset & 0x0003) {
518 /* Unaligned access */
519 b43_shm_control_word(dev, routing, offset >> 2);
520 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
521 return;
522 }
523 offset >>= 2;
524 }
525 b43_shm_control_word(dev, routing, offset);
526 b43_write16(dev, B43_MMIO_SHM_DATA, value);
527 }
528
529 /* Read HostFlags */
530 u64 b43_hf_read(struct b43_wldev *dev)
531 {
532 u64 ret;
533
534 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
535 ret <<= 16;
536 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
537 ret <<= 16;
538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
539
540 return ret;
541 }
542
543 /* Write HostFlags */
544 void b43_hf_write(struct b43_wldev *dev, u64 value)
545 {
546 u16 lo, mi, hi;
547
548 lo = (value & 0x00000000FFFFULL);
549 mi = (value & 0x0000FFFF0000ULL) >> 16;
550 hi = (value & 0xFFFF00000000ULL) >> 32;
551 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
552 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
554 }
555
556 /* Read the firmware capabilities bitmask (Opensource firmware only) */
557 static u16 b43_fwcapa_read(struct b43_wldev *dev)
558 {
559 B43_WARN_ON(!dev->fw.opensource);
560 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
561 }
562
563 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
564 {
565 u32 low, high;
566
567 B43_WARN_ON(dev->dev->core_rev < 3);
568
569 /* The hardware guarantees us an atomic read, if we
570 * read the low register first. */
571 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
572 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
573
574 *tsf = high;
575 *tsf <<= 32;
576 *tsf |= low;
577 }
578
579 static void b43_time_lock(struct b43_wldev *dev)
580 {
581 u32 macctl;
582
583 macctl = b43_read32(dev, B43_MMIO_MACCTL);
584 macctl |= B43_MACCTL_TBTTHOLD;
585 b43_write32(dev, B43_MMIO_MACCTL, macctl);
586 /* Commit the write */
587 b43_read32(dev, B43_MMIO_MACCTL);
588 }
589
590 static void b43_time_unlock(struct b43_wldev *dev)
591 {
592 u32 macctl;
593
594 macctl = b43_read32(dev, B43_MMIO_MACCTL);
595 macctl &= ~B43_MACCTL_TBTTHOLD;
596 b43_write32(dev, B43_MMIO_MACCTL, macctl);
597 /* Commit the write */
598 b43_read32(dev, B43_MMIO_MACCTL);
599 }
600
601 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
602 {
603 u32 low, high;
604
605 B43_WARN_ON(dev->dev->core_rev < 3);
606
607 low = tsf;
608 high = (tsf >> 32);
609 /* The hardware guarantees us an atomic write, if we
610 * write the low register first. */
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
612 mmiowb();
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
614 mmiowb();
615 }
616
617 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
618 {
619 b43_time_lock(dev);
620 b43_tsf_write_locked(dev, tsf);
621 b43_time_unlock(dev);
622 }
623
624 static
625 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
626 {
627 static const u8 zero_addr[ETH_ALEN] = { 0 };
628 u16 data;
629
630 if (!mac)
631 mac = zero_addr;
632
633 offset |= 0x0020;
634 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
635
636 data = mac[0];
637 data |= mac[1] << 8;
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
639 data = mac[2];
640 data |= mac[3] << 8;
641 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
642 data = mac[4];
643 data |= mac[5] << 8;
644 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
645 }
646
647 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
648 {
649 const u8 *mac;
650 const u8 *bssid;
651 u8 mac_bssid[ETH_ALEN * 2];
652 int i;
653 u32 tmp;
654
655 bssid = dev->wl->bssid;
656 mac = dev->wl->mac_addr;
657
658 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
659
660 memcpy(mac_bssid, mac, ETH_ALEN);
661 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
662
663 /* Write our MAC address and BSSID to template ram */
664 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
665 tmp = (u32) (mac_bssid[i + 0]);
666 tmp |= (u32) (mac_bssid[i + 1]) << 8;
667 tmp |= (u32) (mac_bssid[i + 2]) << 16;
668 tmp |= (u32) (mac_bssid[i + 3]) << 24;
669 b43_ram_write(dev, 0x20 + i, tmp);
670 }
671 }
672
673 static void b43_upload_card_macaddress(struct b43_wldev *dev)
674 {
675 b43_write_mac_bssid_templates(dev);
676 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
677 }
678
679 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
680 {
681 /* slot_time is in usec. */
682 /* This test used to exit for all but a G PHY. */
683 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
684 return;
685 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
686 /* Shared memory location 0x0010 is the slot time and should be
687 * set to slot_time; however, this register is initially 0 and changing
688 * the value adversely affects the transmit rate for BCM4311
689 * devices. Until this behavior is unterstood, delete this step
690 *
691 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
692 */
693 }
694
695 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
696 {
697 b43_set_slot_time(dev, 9);
698 }
699
700 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
701 {
702 b43_set_slot_time(dev, 20);
703 }
704
705 /* DummyTransmission function, as documented on
706 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
707 */
708 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
709 {
710 struct b43_phy *phy = &dev->phy;
711 unsigned int i, max_loop;
712 u16 value;
713 u32 buffer[5] = {
714 0x00000000,
715 0x00D40000,
716 0x00000000,
717 0x01000000,
718 0x00000000,
719 };
720
721 if (ofdm) {
722 max_loop = 0x1E;
723 buffer[0] = 0x000201CC;
724 } else {
725 max_loop = 0xFA;
726 buffer[0] = 0x000B846E;
727 }
728
729 for (i = 0; i < 5; i++)
730 b43_ram_write(dev, i * 4, buffer[i]);
731
732 b43_write16(dev, 0x0568, 0x0000);
733 if (dev->dev->core_rev < 11)
734 b43_write16(dev, 0x07C0, 0x0000);
735 else
736 b43_write16(dev, 0x07C0, 0x0100);
737 value = (ofdm ? 0x41 : 0x40);
738 b43_write16(dev, 0x050C, value);
739 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
740 b43_write16(dev, 0x0514, 0x1A02);
741 b43_write16(dev, 0x0508, 0x0000);
742 b43_write16(dev, 0x050A, 0x0000);
743 b43_write16(dev, 0x054C, 0x0000);
744 b43_write16(dev, 0x056A, 0x0014);
745 b43_write16(dev, 0x0568, 0x0826);
746 b43_write16(dev, 0x0500, 0x0000);
747 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
748 //SPEC TODO
749 }
750
751 switch (phy->type) {
752 case B43_PHYTYPE_N:
753 b43_write16(dev, 0x0502, 0x00D0);
754 break;
755 case B43_PHYTYPE_LP:
756 b43_write16(dev, 0x0502, 0x0050);
757 break;
758 default:
759 b43_write16(dev, 0x0502, 0x0030);
760 }
761
762 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
763 b43_radio_write16(dev, 0x0051, 0x0017);
764 for (i = 0x00; i < max_loop; i++) {
765 value = b43_read16(dev, 0x050E);
766 if (value & 0x0080)
767 break;
768 udelay(10);
769 }
770 for (i = 0x00; i < 0x0A; i++) {
771 value = b43_read16(dev, 0x050E);
772 if (value & 0x0400)
773 break;
774 udelay(10);
775 }
776 for (i = 0x00; i < 0x19; i++) {
777 value = b43_read16(dev, 0x0690);
778 if (!(value & 0x0100))
779 break;
780 udelay(10);
781 }
782 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
783 b43_radio_write16(dev, 0x0051, 0x0037);
784 }
785
786 static void key_write(struct b43_wldev *dev,
787 u8 index, u8 algorithm, const u8 *key)
788 {
789 unsigned int i;
790 u32 offset;
791 u16 value;
792 u16 kidx;
793
794 /* Key index/algo block */
795 kidx = b43_kidx_to_fw(dev, index);
796 value = ((kidx << 4) | algorithm);
797 b43_shm_write16(dev, B43_SHM_SHARED,
798 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
799
800 /* Write the key to the Key Table Pointer offset */
801 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
802 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
803 value = key[i];
804 value |= (u16) (key[i + 1]) << 8;
805 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
806 }
807 }
808
809 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
810 {
811 u32 addrtmp[2] = { 0, 0, };
812 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
813
814 if (b43_new_kidx_api(dev))
815 pairwise_keys_start = B43_NR_GROUP_KEYS;
816
817 B43_WARN_ON(index < pairwise_keys_start);
818 /* We have four default TX keys and possibly four default RX keys.
819 * Physical mac 0 is mapped to physical key 4 or 8, depending
820 * on the firmware version.
821 * So we must adjust the index here.
822 */
823 index -= pairwise_keys_start;
824 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
825
826 if (addr) {
827 addrtmp[0] = addr[0];
828 addrtmp[0] |= ((u32) (addr[1]) << 8);
829 addrtmp[0] |= ((u32) (addr[2]) << 16);
830 addrtmp[0] |= ((u32) (addr[3]) << 24);
831 addrtmp[1] = addr[4];
832 addrtmp[1] |= ((u32) (addr[5]) << 8);
833 }
834
835 /* Receive match transmitter address (RCMTA) mechanism */
836 b43_shm_write32(dev, B43_SHM_RCMTA,
837 (index * 2) + 0, addrtmp[0]);
838 b43_shm_write16(dev, B43_SHM_RCMTA,
839 (index * 2) + 1, addrtmp[1]);
840 }
841
842 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
843 * When a packet is received, the iv32 is checked.
844 * - if it doesn't the packet is returned without modification (and software
845 * decryption can be done). That's what happen when iv16 wrap.
846 * - if it does, the rc4 key is computed, and decryption is tried.
847 * Either it will success and B43_RX_MAC_DEC is returned,
848 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
849 * and the packet is not usable (it got modified by the ucode).
850 * So in order to never have B43_RX_MAC_DECERR, we should provide
851 * a iv32 and phase1key that match. Because we drop packets in case of
852 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
853 * packets will be lost without higher layer knowing (ie no resync possible
854 * until next wrap).
855 *
856 * NOTE : this should support 50 key like RCMTA because
857 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
858 */
859 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
860 u16 *phase1key)
861 {
862 unsigned int i;
863 u32 offset;
864 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
865
866 if (!modparam_hwtkip)
867 return;
868
869 if (b43_new_kidx_api(dev))
870 pairwise_keys_start = B43_NR_GROUP_KEYS;
871
872 B43_WARN_ON(index < pairwise_keys_start);
873 /* We have four default TX keys and possibly four default RX keys.
874 * Physical mac 0 is mapped to physical key 4 or 8, depending
875 * on the firmware version.
876 * So we must adjust the index here.
877 */
878 index -= pairwise_keys_start;
879 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
880
881 if (b43_debug(dev, B43_DBG_KEYS)) {
882 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
883 index, iv32);
884 }
885 /* Write the key to the RX tkip shared mem */
886 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
887 for (i = 0; i < 10; i += 2) {
888 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
889 phase1key ? phase1key[i / 2] : 0);
890 }
891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
893 }
894
895 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
896 struct ieee80211_vif *vif,
897 struct ieee80211_key_conf *keyconf,
898 struct ieee80211_sta *sta,
899 u32 iv32, u16 *phase1key)
900 {
901 struct b43_wl *wl = hw_to_b43_wl(hw);
902 struct b43_wldev *dev;
903 int index = keyconf->hw_key_idx;
904
905 if (B43_WARN_ON(!modparam_hwtkip))
906 return;
907
908 /* This is only called from the RX path through mac80211, where
909 * our mutex is already locked. */
910 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
911 dev = wl->current_dev;
912 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
913
914 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
915
916 rx_tkip_phase1_write(dev, index, iv32, phase1key);
917 /* only pairwise TKIP keys are supported right now */
918 if (WARN_ON(!sta))
919 return;
920 keymac_write(dev, index, sta->addr);
921 }
922
923 static void do_key_write(struct b43_wldev *dev,
924 u8 index, u8 algorithm,
925 const u8 *key, size_t key_len, const u8 *mac_addr)
926 {
927 u8 buf[B43_SEC_KEYSIZE] = { 0, };
928 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
929
930 if (b43_new_kidx_api(dev))
931 pairwise_keys_start = B43_NR_GROUP_KEYS;
932
933 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
934 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
935
936 if (index >= pairwise_keys_start)
937 keymac_write(dev, index, NULL); /* First zero out mac. */
938 if (algorithm == B43_SEC_ALGO_TKIP) {
939 /*
940 * We should provide an initial iv32, phase1key pair.
941 * We could start with iv32=0 and compute the corresponding
942 * phase1key, but this means calling ieee80211_get_tkip_key
943 * with a fake skb (or export other tkip function).
944 * Because we are lazy we hope iv32 won't start with
945 * 0xffffffff and let's b43_op_update_tkip_key provide a
946 * correct pair.
947 */
948 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
949 } else if (index >= pairwise_keys_start) /* clear it */
950 rx_tkip_phase1_write(dev, index, 0, NULL);
951 if (key)
952 memcpy(buf, key, key_len);
953 key_write(dev, index, algorithm, buf);
954 if (index >= pairwise_keys_start)
955 keymac_write(dev, index, mac_addr);
956
957 dev->key[index].algorithm = algorithm;
958 }
959
960 static int b43_key_write(struct b43_wldev *dev,
961 int index, u8 algorithm,
962 const u8 *key, size_t key_len,
963 const u8 *mac_addr,
964 struct ieee80211_key_conf *keyconf)
965 {
966 int i;
967 int pairwise_keys_start;
968
969 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
970 * - Temporal Encryption Key (128 bits)
971 * - Temporal Authenticator Tx MIC Key (64 bits)
972 * - Temporal Authenticator Rx MIC Key (64 bits)
973 *
974 * Hardware only store TEK
975 */
976 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
977 key_len = 16;
978 if (key_len > B43_SEC_KEYSIZE)
979 return -EINVAL;
980 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
981 /* Check that we don't already have this key. */
982 B43_WARN_ON(dev->key[i].keyconf == keyconf);
983 }
984 if (index < 0) {
985 /* Pairwise key. Get an empty slot for the key. */
986 if (b43_new_kidx_api(dev))
987 pairwise_keys_start = B43_NR_GROUP_KEYS;
988 else
989 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
990 for (i = pairwise_keys_start;
991 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
992 i++) {
993 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
994 if (!dev->key[i].keyconf) {
995 /* found empty */
996 index = i;
997 break;
998 }
999 }
1000 if (index < 0) {
1001 b43warn(dev->wl, "Out of hardware key memory\n");
1002 return -ENOSPC;
1003 }
1004 } else
1005 B43_WARN_ON(index > 3);
1006
1007 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1008 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1009 /* Default RX key */
1010 B43_WARN_ON(mac_addr);
1011 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1012 }
1013 keyconf->hw_key_idx = index;
1014 dev->key[index].keyconf = keyconf;
1015
1016 return 0;
1017 }
1018
1019 static int b43_key_clear(struct b43_wldev *dev, int index)
1020 {
1021 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1022 return -EINVAL;
1023 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1024 NULL, B43_SEC_KEYSIZE, NULL);
1025 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1026 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1027 NULL, B43_SEC_KEYSIZE, NULL);
1028 }
1029 dev->key[index].keyconf = NULL;
1030
1031 return 0;
1032 }
1033
1034 static void b43_clear_keys(struct b43_wldev *dev)
1035 {
1036 int i, count;
1037
1038 if (b43_new_kidx_api(dev))
1039 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1040 else
1041 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1042 for (i = 0; i < count; i++)
1043 b43_key_clear(dev, i);
1044 }
1045
1046 static void b43_dump_keymemory(struct b43_wldev *dev)
1047 {
1048 unsigned int i, index, count, offset, pairwise_keys_start;
1049 u8 mac[ETH_ALEN];
1050 u16 algo;
1051 u32 rcmta0;
1052 u16 rcmta1;
1053 u64 hf;
1054 struct b43_key *key;
1055
1056 if (!b43_debug(dev, B43_DBG_KEYS))
1057 return;
1058
1059 hf = b43_hf_read(dev);
1060 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1061 !!(hf & B43_HF_USEDEFKEYS));
1062 if (b43_new_kidx_api(dev)) {
1063 pairwise_keys_start = B43_NR_GROUP_KEYS;
1064 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1065 } else {
1066 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1067 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1068 }
1069 for (index = 0; index < count; index++) {
1070 key = &(dev->key[index]);
1071 printk(KERN_DEBUG "Key slot %02u: %s",
1072 index, (key->keyconf == NULL) ? " " : "*");
1073 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1074 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1075 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1076 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1077 }
1078
1079 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1080 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1081 printk(" Algo: %04X/%02X", algo, key->algorithm);
1082
1083 if (index >= pairwise_keys_start) {
1084 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1085 printk(" TKIP: ");
1086 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1087 for (i = 0; i < 14; i += 2) {
1088 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1089 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1090 }
1091 }
1092 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1093 ((index - pairwise_keys_start) * 2) + 0);
1094 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1095 ((index - pairwise_keys_start) * 2) + 1);
1096 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1097 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1098 printk(" MAC: %pM", mac);
1099 } else
1100 printk(" DEFAULT KEY");
1101 printk("\n");
1102 }
1103 }
1104
1105 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1106 {
1107 u32 macctl;
1108 u16 ucstat;
1109 bool hwps;
1110 bool awake;
1111 int i;
1112
1113 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1114 (ps_flags & B43_PS_DISABLED));
1115 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1116
1117 if (ps_flags & B43_PS_ENABLED) {
1118 hwps = 1;
1119 } else if (ps_flags & B43_PS_DISABLED) {
1120 hwps = 0;
1121 } else {
1122 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1123 // and thus is not an AP and we are associated, set bit 25
1124 }
1125 if (ps_flags & B43_PS_AWAKE) {
1126 awake = 1;
1127 } else if (ps_flags & B43_PS_ASLEEP) {
1128 awake = 0;
1129 } else {
1130 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1131 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1132 // successful, set bit26
1133 }
1134
1135 /* FIXME: For now we force awake-on and hwps-off */
1136 hwps = 0;
1137 awake = 1;
1138
1139 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1140 if (hwps)
1141 macctl |= B43_MACCTL_HWPS;
1142 else
1143 macctl &= ~B43_MACCTL_HWPS;
1144 if (awake)
1145 macctl |= B43_MACCTL_AWAKE;
1146 else
1147 macctl &= ~B43_MACCTL_AWAKE;
1148 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1149 /* Commit write */
1150 b43_read32(dev, B43_MMIO_MACCTL);
1151 if (awake && dev->dev->core_rev >= 5) {
1152 /* Wait for the microcode to wake up. */
1153 for (i = 0; i < 100; i++) {
1154 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1155 B43_SHM_SH_UCODESTAT);
1156 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1157 break;
1158 udelay(10);
1159 }
1160 }
1161 }
1162
1163 #ifdef CONFIG_B43_BCMA
1164 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1165 {
1166 u32 flags;
1167
1168 /* Put PHY into reset */
1169 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1170 flags |= B43_BCMA_IOCTL_PHY_RESET;
1171 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1172 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1173 udelay(2);
1174
1175 /* Take PHY out of reset */
1176 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1177 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1178 flags |= BCMA_IOCTL_FGC;
1179 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1180 udelay(1);
1181
1182 /* Do not force clock anymore */
1183 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1184 flags &= ~BCMA_IOCTL_FGC;
1185 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1186 udelay(1);
1187 }
1188
1189 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1190 {
1191 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1192 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1193 b43_bcma_phy_reset(dev);
1194 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1195 }
1196 #endif
1197
1198 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1199 {
1200 struct ssb_device *sdev = dev->dev->sdev;
1201 u32 tmslow;
1202 u32 flags = 0;
1203
1204 if (gmode)
1205 flags |= B43_TMSLOW_GMODE;
1206 flags |= B43_TMSLOW_PHYCLKEN;
1207 flags |= B43_TMSLOW_PHYRESET;
1208 if (dev->phy.type == B43_PHYTYPE_N)
1209 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1210 b43_device_enable(dev, flags);
1211 msleep(2); /* Wait for the PLL to turn on. */
1212
1213 /* Now take the PHY out of Reset again */
1214 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1215 tmslow |= SSB_TMSLOW_FGC;
1216 tmslow &= ~B43_TMSLOW_PHYRESET;
1217 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1218 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1219 msleep(1);
1220 tmslow &= ~SSB_TMSLOW_FGC;
1221 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1222 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1223 msleep(1);
1224 }
1225
1226 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1227 {
1228 u32 macctl;
1229
1230 switch (dev->dev->bus_type) {
1231 #ifdef CONFIG_B43_BCMA
1232 case B43_BUS_BCMA:
1233 b43_bcma_wireless_core_reset(dev, gmode);
1234 break;
1235 #endif
1236 #ifdef CONFIG_B43_SSB
1237 case B43_BUS_SSB:
1238 b43_ssb_wireless_core_reset(dev, gmode);
1239 break;
1240 #endif
1241 }
1242
1243 /* Turn Analog ON, but only if we already know the PHY-type.
1244 * This protects against very early setup where we don't know the
1245 * PHY-type, yet. wireless_core_reset will be called once again later,
1246 * when we know the PHY-type. */
1247 if (dev->phy.ops)
1248 dev->phy.ops->switch_analog(dev, 1);
1249
1250 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1251 macctl &= ~B43_MACCTL_GMODE;
1252 if (gmode)
1253 macctl |= B43_MACCTL_GMODE;
1254 macctl |= B43_MACCTL_IHR_ENABLED;
1255 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1256 }
1257
1258 static void handle_irq_transmit_status(struct b43_wldev *dev)
1259 {
1260 u32 v0, v1;
1261 u16 tmp;
1262 struct b43_txstatus stat;
1263
1264 while (1) {
1265 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1266 if (!(v0 & 0x00000001))
1267 break;
1268 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1269
1270 stat.cookie = (v0 >> 16);
1271 stat.seq = (v1 & 0x0000FFFF);
1272 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1273 tmp = (v0 & 0x0000FFFF);
1274 stat.frame_count = ((tmp & 0xF000) >> 12);
1275 stat.rts_count = ((tmp & 0x0F00) >> 8);
1276 stat.supp_reason = ((tmp & 0x001C) >> 2);
1277 stat.pm_indicated = !!(tmp & 0x0080);
1278 stat.intermediate = !!(tmp & 0x0040);
1279 stat.for_ampdu = !!(tmp & 0x0020);
1280 stat.acked = !!(tmp & 0x0002);
1281
1282 b43_handle_txstatus(dev, &stat);
1283 }
1284 }
1285
1286 static void drain_txstatus_queue(struct b43_wldev *dev)
1287 {
1288 u32 dummy;
1289
1290 if (dev->dev->core_rev < 5)
1291 return;
1292 /* Read all entries from the microcode TXstatus FIFO
1293 * and throw them away.
1294 */
1295 while (1) {
1296 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1297 if (!(dummy & 0x00000001))
1298 break;
1299 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1300 }
1301 }
1302
1303 static u32 b43_jssi_read(struct b43_wldev *dev)
1304 {
1305 u32 val = 0;
1306
1307 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1308 val <<= 16;
1309 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1310
1311 return val;
1312 }
1313
1314 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1315 {
1316 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1318 }
1319
1320 static void b43_generate_noise_sample(struct b43_wldev *dev)
1321 {
1322 b43_jssi_write(dev, 0x7F7F7F7F);
1323 b43_write32(dev, B43_MMIO_MACCMD,
1324 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1325 }
1326
1327 static void b43_calculate_link_quality(struct b43_wldev *dev)
1328 {
1329 /* Top half of Link Quality calculation. */
1330
1331 if (dev->phy.type != B43_PHYTYPE_G)
1332 return;
1333 if (dev->noisecalc.calculation_running)
1334 return;
1335 dev->noisecalc.calculation_running = 1;
1336 dev->noisecalc.nr_samples = 0;
1337
1338 b43_generate_noise_sample(dev);
1339 }
1340
1341 static void handle_irq_noise(struct b43_wldev *dev)
1342 {
1343 struct b43_phy_g *phy = dev->phy.g;
1344 u16 tmp;
1345 u8 noise[4];
1346 u8 i, j;
1347 s32 average;
1348
1349 /* Bottom half of Link Quality calculation. */
1350
1351 if (dev->phy.type != B43_PHYTYPE_G)
1352 return;
1353
1354 /* Possible race condition: It might be possible that the user
1355 * changed to a different channel in the meantime since we
1356 * started the calculation. We ignore that fact, since it's
1357 * not really that much of a problem. The background noise is
1358 * an estimation only anyway. Slightly wrong results will get damped
1359 * by the averaging of the 8 sample rounds. Additionally the
1360 * value is shortlived. So it will be replaced by the next noise
1361 * calculation round soon. */
1362
1363 B43_WARN_ON(!dev->noisecalc.calculation_running);
1364 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1365 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1366 noise[2] == 0x7F || noise[3] == 0x7F)
1367 goto generate_new;
1368
1369 /* Get the noise samples. */
1370 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1371 i = dev->noisecalc.nr_samples;
1372 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1373 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1376 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1377 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1378 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1379 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1380 dev->noisecalc.nr_samples++;
1381 if (dev->noisecalc.nr_samples == 8) {
1382 /* Calculate the Link Quality by the noise samples. */
1383 average = 0;
1384 for (i = 0; i < 8; i++) {
1385 for (j = 0; j < 4; j++)
1386 average += dev->noisecalc.samples[i][j];
1387 }
1388 average /= (8 * 4);
1389 average *= 125;
1390 average += 64;
1391 average /= 128;
1392 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1393 tmp = (tmp / 128) & 0x1F;
1394 if (tmp >= 8)
1395 average += 2;
1396 else
1397 average -= 25;
1398 if (tmp == 8)
1399 average -= 72;
1400 else
1401 average -= 48;
1402
1403 dev->stats.link_noise = average;
1404 dev->noisecalc.calculation_running = 0;
1405 return;
1406 }
1407 generate_new:
1408 b43_generate_noise_sample(dev);
1409 }
1410
1411 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1412 {
1413 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1414 ///TODO: PS TBTT
1415 } else {
1416 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1417 b43_power_saving_ctl_bits(dev, 0);
1418 }
1419 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1420 dev->dfq_valid = 1;
1421 }
1422
1423 static void handle_irq_atim_end(struct b43_wldev *dev)
1424 {
1425 if (dev->dfq_valid) {
1426 b43_write32(dev, B43_MMIO_MACCMD,
1427 b43_read32(dev, B43_MMIO_MACCMD)
1428 | B43_MACCMD_DFQ_VALID);
1429 dev->dfq_valid = 0;
1430 }
1431 }
1432
1433 static void handle_irq_pmq(struct b43_wldev *dev)
1434 {
1435 u32 tmp;
1436
1437 //TODO: AP mode.
1438
1439 while (1) {
1440 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1441 if (!(tmp & 0x00000008))
1442 break;
1443 }
1444 /* 16bit write is odd, but correct. */
1445 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1446 }
1447
1448 static void b43_write_template_common(struct b43_wldev *dev,
1449 const u8 *data, u16 size,
1450 u16 ram_offset,
1451 u16 shm_size_offset, u8 rate)
1452 {
1453 u32 i, tmp;
1454 struct b43_plcp_hdr4 plcp;
1455
1456 plcp.data = 0;
1457 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1458 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1459 ram_offset += sizeof(u32);
1460 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1461 * So leave the first two bytes of the next write blank.
1462 */
1463 tmp = (u32) (data[0]) << 16;
1464 tmp |= (u32) (data[1]) << 24;
1465 b43_ram_write(dev, ram_offset, tmp);
1466 ram_offset += sizeof(u32);
1467 for (i = 2; i < size; i += sizeof(u32)) {
1468 tmp = (u32) (data[i + 0]);
1469 if (i + 1 < size)
1470 tmp |= (u32) (data[i + 1]) << 8;
1471 if (i + 2 < size)
1472 tmp |= (u32) (data[i + 2]) << 16;
1473 if (i + 3 < size)
1474 tmp |= (u32) (data[i + 3]) << 24;
1475 b43_ram_write(dev, ram_offset + i - 2, tmp);
1476 }
1477 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1478 size + sizeof(struct b43_plcp_hdr6));
1479 }
1480
1481 /* Check if the use of the antenna that ieee80211 told us to
1482 * use is possible. This will fall back to DEFAULT.
1483 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1484 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1485 u8 antenna_nr)
1486 {
1487 u8 antenna_mask;
1488
1489 if (antenna_nr == 0) {
1490 /* Zero means "use default antenna". That's always OK. */
1491 return 0;
1492 }
1493
1494 /* Get the mask of available antennas. */
1495 if (dev->phy.gmode)
1496 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1497 else
1498 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1499
1500 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1501 /* This antenna is not available. Fall back to default. */
1502 return 0;
1503 }
1504
1505 return antenna_nr;
1506 }
1507
1508 /* Convert a b43 antenna number value to the PHY TX control value. */
1509 static u16 b43_antenna_to_phyctl(int antenna)
1510 {
1511 switch (antenna) {
1512 case B43_ANTENNA0:
1513 return B43_TXH_PHY_ANT0;
1514 case B43_ANTENNA1:
1515 return B43_TXH_PHY_ANT1;
1516 case B43_ANTENNA2:
1517 return B43_TXH_PHY_ANT2;
1518 case B43_ANTENNA3:
1519 return B43_TXH_PHY_ANT3;
1520 case B43_ANTENNA_AUTO0:
1521 case B43_ANTENNA_AUTO1:
1522 return B43_TXH_PHY_ANT01AUTO;
1523 }
1524 B43_WARN_ON(1);
1525 return 0;
1526 }
1527
1528 static void b43_write_beacon_template(struct b43_wldev *dev,
1529 u16 ram_offset,
1530 u16 shm_size_offset)
1531 {
1532 unsigned int i, len, variable_len;
1533 const struct ieee80211_mgmt *bcn;
1534 const u8 *ie;
1535 bool tim_found = 0;
1536 unsigned int rate;
1537 u16 ctl;
1538 int antenna;
1539 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1540
1541 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1542 len = min((size_t) dev->wl->current_beacon->len,
1543 0x200 - sizeof(struct b43_plcp_hdr6));
1544 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1545
1546 b43_write_template_common(dev, (const u8 *)bcn,
1547 len, ram_offset, shm_size_offset, rate);
1548
1549 /* Write the PHY TX control parameters. */
1550 antenna = B43_ANTENNA_DEFAULT;
1551 antenna = b43_antenna_to_phyctl(antenna);
1552 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1553 /* We can't send beacons with short preamble. Would get PHY errors. */
1554 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1555 ctl &= ~B43_TXH_PHY_ANT;
1556 ctl &= ~B43_TXH_PHY_ENC;
1557 ctl |= antenna;
1558 if (b43_is_cck_rate(rate))
1559 ctl |= B43_TXH_PHY_ENC_CCK;
1560 else
1561 ctl |= B43_TXH_PHY_ENC_OFDM;
1562 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1563
1564 /* Find the position of the TIM and the DTIM_period value
1565 * and write them to SHM. */
1566 ie = bcn->u.beacon.variable;
1567 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1568 for (i = 0; i < variable_len - 2; ) {
1569 uint8_t ie_id, ie_len;
1570
1571 ie_id = ie[i];
1572 ie_len = ie[i + 1];
1573 if (ie_id == 5) {
1574 u16 tim_position;
1575 u16 dtim_period;
1576 /* This is the TIM Information Element */
1577
1578 /* Check whether the ie_len is in the beacon data range. */
1579 if (variable_len < ie_len + 2 + i)
1580 break;
1581 /* A valid TIM is at least 4 bytes long. */
1582 if (ie_len < 4)
1583 break;
1584 tim_found = 1;
1585
1586 tim_position = sizeof(struct b43_plcp_hdr6);
1587 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1588 tim_position += i;
1589
1590 dtim_period = ie[i + 3];
1591
1592 b43_shm_write16(dev, B43_SHM_SHARED,
1593 B43_SHM_SH_TIMBPOS, tim_position);
1594 b43_shm_write16(dev, B43_SHM_SHARED,
1595 B43_SHM_SH_DTIMPER, dtim_period);
1596 break;
1597 }
1598 i += ie_len + 2;
1599 }
1600 if (!tim_found) {
1601 /*
1602 * If ucode wants to modify TIM do it behind the beacon, this
1603 * will happen, for example, when doing mesh networking.
1604 */
1605 b43_shm_write16(dev, B43_SHM_SHARED,
1606 B43_SHM_SH_TIMBPOS,
1607 len + sizeof(struct b43_plcp_hdr6));
1608 b43_shm_write16(dev, B43_SHM_SHARED,
1609 B43_SHM_SH_DTIMPER, 0);
1610 }
1611 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1612 }
1613
1614 static void b43_upload_beacon0(struct b43_wldev *dev)
1615 {
1616 struct b43_wl *wl = dev->wl;
1617
1618 if (wl->beacon0_uploaded)
1619 return;
1620 b43_write_beacon_template(dev, 0x68, 0x18);
1621 wl->beacon0_uploaded = 1;
1622 }
1623
1624 static void b43_upload_beacon1(struct b43_wldev *dev)
1625 {
1626 struct b43_wl *wl = dev->wl;
1627
1628 if (wl->beacon1_uploaded)
1629 return;
1630 b43_write_beacon_template(dev, 0x468, 0x1A);
1631 wl->beacon1_uploaded = 1;
1632 }
1633
1634 static void handle_irq_beacon(struct b43_wldev *dev)
1635 {
1636 struct b43_wl *wl = dev->wl;
1637 u32 cmd, beacon0_valid, beacon1_valid;
1638
1639 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1640 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1641 return;
1642
1643 /* This is the bottom half of the asynchronous beacon update. */
1644
1645 /* Ignore interrupt in the future. */
1646 dev->irq_mask &= ~B43_IRQ_BEACON;
1647
1648 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1649 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1650 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1651
1652 /* Schedule interrupt manually, if busy. */
1653 if (beacon0_valid && beacon1_valid) {
1654 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1655 dev->irq_mask |= B43_IRQ_BEACON;
1656 return;
1657 }
1658
1659 if (unlikely(wl->beacon_templates_virgin)) {
1660 /* We never uploaded a beacon before.
1661 * Upload both templates now, but only mark one valid. */
1662 wl->beacon_templates_virgin = 0;
1663 b43_upload_beacon0(dev);
1664 b43_upload_beacon1(dev);
1665 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1666 cmd |= B43_MACCMD_BEACON0_VALID;
1667 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1668 } else {
1669 if (!beacon0_valid) {
1670 b43_upload_beacon0(dev);
1671 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1672 cmd |= B43_MACCMD_BEACON0_VALID;
1673 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1674 } else if (!beacon1_valid) {
1675 b43_upload_beacon1(dev);
1676 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1677 cmd |= B43_MACCMD_BEACON1_VALID;
1678 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1679 }
1680 }
1681 }
1682
1683 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1684 {
1685 u32 old_irq_mask = dev->irq_mask;
1686
1687 /* update beacon right away or defer to irq */
1688 handle_irq_beacon(dev);
1689 if (old_irq_mask != dev->irq_mask) {
1690 /* The handler updated the IRQ mask. */
1691 B43_WARN_ON(!dev->irq_mask);
1692 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1693 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1694 } else {
1695 /* Device interrupts are currently disabled. That means
1696 * we just ran the hardirq handler and scheduled the
1697 * IRQ thread. The thread will write the IRQ mask when
1698 * it finished, so there's nothing to do here. Writing
1699 * the mask _here_ would incorrectly re-enable IRQs. */
1700 }
1701 }
1702 }
1703
1704 static void b43_beacon_update_trigger_work(struct work_struct *work)
1705 {
1706 struct b43_wl *wl = container_of(work, struct b43_wl,
1707 beacon_update_trigger);
1708 struct b43_wldev *dev;
1709
1710 mutex_lock(&wl->mutex);
1711 dev = wl->current_dev;
1712 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1713 if (b43_bus_host_is_sdio(dev->dev)) {
1714 /* wl->mutex is enough. */
1715 b43_do_beacon_update_trigger_work(dev);
1716 mmiowb();
1717 } else {
1718 spin_lock_irq(&wl->hardirq_lock);
1719 b43_do_beacon_update_trigger_work(dev);
1720 mmiowb();
1721 spin_unlock_irq(&wl->hardirq_lock);
1722 }
1723 }
1724 mutex_unlock(&wl->mutex);
1725 }
1726
1727 /* Asynchronously update the packet templates in template RAM.
1728 * Locking: Requires wl->mutex to be locked. */
1729 static void b43_update_templates(struct b43_wl *wl)
1730 {
1731 struct sk_buff *beacon;
1732
1733 /* This is the top half of the ansynchronous beacon update.
1734 * The bottom half is the beacon IRQ.
1735 * Beacon update must be asynchronous to avoid sending an
1736 * invalid beacon. This can happen for example, if the firmware
1737 * transmits a beacon while we are updating it. */
1738
1739 /* We could modify the existing beacon and set the aid bit in
1740 * the TIM field, but that would probably require resizing and
1741 * moving of data within the beacon template.
1742 * Simply request a new beacon and let mac80211 do the hard work. */
1743 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1744 if (unlikely(!beacon))
1745 return;
1746
1747 if (wl->current_beacon)
1748 dev_kfree_skb_any(wl->current_beacon);
1749 wl->current_beacon = beacon;
1750 wl->beacon0_uploaded = 0;
1751 wl->beacon1_uploaded = 0;
1752 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1753 }
1754
1755 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1756 {
1757 b43_time_lock(dev);
1758 if (dev->dev->core_rev >= 3) {
1759 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1760 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1761 } else {
1762 b43_write16(dev, 0x606, (beacon_int >> 6));
1763 b43_write16(dev, 0x610, beacon_int);
1764 }
1765 b43_time_unlock(dev);
1766 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1767 }
1768
1769 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1770 {
1771 u16 reason;
1772
1773 /* Read the register that contains the reason code for the panic. */
1774 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1775 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1776
1777 switch (reason) {
1778 default:
1779 b43dbg(dev->wl, "The panic reason is unknown.\n");
1780 /* fallthrough */
1781 case B43_FWPANIC_DIE:
1782 /* Do not restart the controller or firmware.
1783 * The device is nonfunctional from now on.
1784 * Restarting would result in this panic to trigger again,
1785 * so we avoid that recursion. */
1786 break;
1787 case B43_FWPANIC_RESTART:
1788 b43_controller_restart(dev, "Microcode panic");
1789 break;
1790 }
1791 }
1792
1793 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1794 {
1795 unsigned int i, cnt;
1796 u16 reason, marker_id, marker_line;
1797 __le16 *buf;
1798
1799 /* The proprietary firmware doesn't have this IRQ. */
1800 if (!dev->fw.opensource)
1801 return;
1802
1803 /* Read the register that contains the reason code for this IRQ. */
1804 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1805
1806 switch (reason) {
1807 case B43_DEBUGIRQ_PANIC:
1808 b43_handle_firmware_panic(dev);
1809 break;
1810 case B43_DEBUGIRQ_DUMP_SHM:
1811 if (!B43_DEBUG)
1812 break; /* Only with driver debugging enabled. */
1813 buf = kmalloc(4096, GFP_ATOMIC);
1814 if (!buf) {
1815 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1816 goto out;
1817 }
1818 for (i = 0; i < 4096; i += 2) {
1819 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1820 buf[i / 2] = cpu_to_le16(tmp);
1821 }
1822 b43info(dev->wl, "Shared memory dump:\n");
1823 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1824 16, 2, buf, 4096, 1);
1825 kfree(buf);
1826 break;
1827 case B43_DEBUGIRQ_DUMP_REGS:
1828 if (!B43_DEBUG)
1829 break; /* Only with driver debugging enabled. */
1830 b43info(dev->wl, "Microcode register dump:\n");
1831 for (i = 0, cnt = 0; i < 64; i++) {
1832 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1833 if (cnt == 0)
1834 printk(KERN_INFO);
1835 printk("r%02u: 0x%04X ", i, tmp);
1836 cnt++;
1837 if (cnt == 6) {
1838 printk("\n");
1839 cnt = 0;
1840 }
1841 }
1842 printk("\n");
1843 break;
1844 case B43_DEBUGIRQ_MARKER:
1845 if (!B43_DEBUG)
1846 break; /* Only with driver debugging enabled. */
1847 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1848 B43_MARKER_ID_REG);
1849 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1850 B43_MARKER_LINE_REG);
1851 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1852 "at line number %u\n",
1853 marker_id, marker_line);
1854 break;
1855 default:
1856 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1857 reason);
1858 }
1859 out:
1860 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1861 b43_shm_write16(dev, B43_SHM_SCRATCH,
1862 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1863 }
1864
1865 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1866 {
1867 u32 reason;
1868 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1869 u32 merged_dma_reason = 0;
1870 int i;
1871
1872 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1873 return;
1874
1875 reason = dev->irq_reason;
1876 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1877 dma_reason[i] = dev->dma_reason[i];
1878 merged_dma_reason |= dma_reason[i];
1879 }
1880
1881 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1882 b43err(dev->wl, "MAC transmission error\n");
1883
1884 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1885 b43err(dev->wl, "PHY transmission error\n");
1886 rmb();
1887 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1888 atomic_set(&dev->phy.txerr_cnt,
1889 B43_PHY_TX_BADNESS_LIMIT);
1890 b43err(dev->wl, "Too many PHY TX errors, "
1891 "restarting the controller\n");
1892 b43_controller_restart(dev, "PHY TX errors");
1893 }
1894 }
1895
1896 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1897 B43_DMAIRQ_NONFATALMASK))) {
1898 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1899 b43err(dev->wl, "Fatal DMA error: "
1900 "0x%08X, 0x%08X, 0x%08X, "
1901 "0x%08X, 0x%08X, 0x%08X\n",
1902 dma_reason[0], dma_reason[1],
1903 dma_reason[2], dma_reason[3],
1904 dma_reason[4], dma_reason[5]);
1905 b43err(dev->wl, "This device does not support DMA "
1906 "on your system. It will now be switched to PIO.\n");
1907 /* Fall back to PIO transfers if we get fatal DMA errors! */
1908 dev->use_pio = 1;
1909 b43_controller_restart(dev, "DMA error");
1910 return;
1911 }
1912 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1913 b43err(dev->wl, "DMA error: "
1914 "0x%08X, 0x%08X, 0x%08X, "
1915 "0x%08X, 0x%08X, 0x%08X\n",
1916 dma_reason[0], dma_reason[1],
1917 dma_reason[2], dma_reason[3],
1918 dma_reason[4], dma_reason[5]);
1919 }
1920 }
1921
1922 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1923 handle_irq_ucode_debug(dev);
1924 if (reason & B43_IRQ_TBTT_INDI)
1925 handle_irq_tbtt_indication(dev);
1926 if (reason & B43_IRQ_ATIM_END)
1927 handle_irq_atim_end(dev);
1928 if (reason & B43_IRQ_BEACON)
1929 handle_irq_beacon(dev);
1930 if (reason & B43_IRQ_PMQ)
1931 handle_irq_pmq(dev);
1932 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1933 ;/* TODO */
1934 if (reason & B43_IRQ_NOISESAMPLE_OK)
1935 handle_irq_noise(dev);
1936
1937 /* Check the DMA reason registers for received data. */
1938 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1939 if (b43_using_pio_transfers(dev))
1940 b43_pio_rx(dev->pio.rx_queue);
1941 else
1942 b43_dma_rx(dev->dma.rx_ring);
1943 }
1944 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1945 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1946 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1947 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1948 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1949
1950 if (reason & B43_IRQ_TX_OK)
1951 handle_irq_transmit_status(dev);
1952
1953 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1954 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1955
1956 #if B43_DEBUG
1957 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1958 dev->irq_count++;
1959 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1960 if (reason & (1 << i))
1961 dev->irq_bit_count[i]++;
1962 }
1963 }
1964 #endif
1965 }
1966
1967 /* Interrupt thread handler. Handles device interrupts in thread context. */
1968 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1969 {
1970 struct b43_wldev *dev = dev_id;
1971
1972 mutex_lock(&dev->wl->mutex);
1973 b43_do_interrupt_thread(dev);
1974 mmiowb();
1975 mutex_unlock(&dev->wl->mutex);
1976
1977 return IRQ_HANDLED;
1978 }
1979
1980 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1981 {
1982 u32 reason;
1983
1984 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1985 * On SDIO, this runs under wl->mutex. */
1986
1987 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1988 if (reason == 0xffffffff) /* shared IRQ */
1989 return IRQ_NONE;
1990 reason &= dev->irq_mask;
1991 if (!reason)
1992 return IRQ_NONE;
1993
1994 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1995 & 0x0001DC00;
1996 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1997 & 0x0000DC00;
1998 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1999 & 0x0000DC00;
2000 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2001 & 0x0001DC00;
2002 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2003 & 0x0000DC00;
2004 /* Unused ring
2005 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2006 & 0x0000DC00;
2007 */
2008
2009 /* ACK the interrupt. */
2010 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2011 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2012 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2013 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2014 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2015 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2016 /* Unused ring
2017 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2018 */
2019
2020 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2021 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2022 /* Save the reason bitmasks for the IRQ thread handler. */
2023 dev->irq_reason = reason;
2024
2025 return IRQ_WAKE_THREAD;
2026 }
2027
2028 /* Interrupt handler top-half. This runs with interrupts disabled. */
2029 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2030 {
2031 struct b43_wldev *dev = dev_id;
2032 irqreturn_t ret;
2033
2034 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2035 return IRQ_NONE;
2036
2037 spin_lock(&dev->wl->hardirq_lock);
2038 ret = b43_do_interrupt(dev);
2039 mmiowb();
2040 spin_unlock(&dev->wl->hardirq_lock);
2041
2042 return ret;
2043 }
2044
2045 /* SDIO interrupt handler. This runs in process context. */
2046 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2047 {
2048 struct b43_wl *wl = dev->wl;
2049 irqreturn_t ret;
2050
2051 mutex_lock(&wl->mutex);
2052
2053 ret = b43_do_interrupt(dev);
2054 if (ret == IRQ_WAKE_THREAD)
2055 b43_do_interrupt_thread(dev);
2056
2057 mutex_unlock(&wl->mutex);
2058 }
2059
2060 void b43_do_release_fw(struct b43_firmware_file *fw)
2061 {
2062 release_firmware(fw->data);
2063 fw->data = NULL;
2064 fw->filename = NULL;
2065 }
2066
2067 static void b43_release_firmware(struct b43_wldev *dev)
2068 {
2069 b43_do_release_fw(&dev->fw.ucode);
2070 b43_do_release_fw(&dev->fw.pcm);
2071 b43_do_release_fw(&dev->fw.initvals);
2072 b43_do_release_fw(&dev->fw.initvals_band);
2073 }
2074
2075 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2076 {
2077 const char text[] =
2078 "You must go to " \
2079 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2080 "and download the correct firmware for this driver version. " \
2081 "Please carefully read all instructions on this website.\n";
2082
2083 if (error)
2084 b43err(wl, text);
2085 else
2086 b43warn(wl, text);
2087 }
2088
2089 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2090 const char *name,
2091 struct b43_firmware_file *fw)
2092 {
2093 const struct firmware *blob;
2094 struct b43_fw_header *hdr;
2095 u32 size;
2096 int err;
2097
2098 if (!name) {
2099 /* Don't fetch anything. Free possibly cached firmware. */
2100 /* FIXME: We should probably keep it anyway, to save some headache
2101 * on suspend/resume with multiband devices. */
2102 b43_do_release_fw(fw);
2103 return 0;
2104 }
2105 if (fw->filename) {
2106 if ((fw->type == ctx->req_type) &&
2107 (strcmp(fw->filename, name) == 0))
2108 return 0; /* Already have this fw. */
2109 /* Free the cached firmware first. */
2110 /* FIXME: We should probably do this later after we successfully
2111 * got the new fw. This could reduce headache with multiband devices.
2112 * We could also redesign this to cache the firmware for all possible
2113 * bands all the time. */
2114 b43_do_release_fw(fw);
2115 }
2116
2117 switch (ctx->req_type) {
2118 case B43_FWTYPE_PROPRIETARY:
2119 snprintf(ctx->fwname, sizeof(ctx->fwname),
2120 "b43%s/%s.fw",
2121 modparam_fwpostfix, name);
2122 break;
2123 case B43_FWTYPE_OPENSOURCE:
2124 snprintf(ctx->fwname, sizeof(ctx->fwname),
2125 "b43-open%s/%s.fw",
2126 modparam_fwpostfix, name);
2127 break;
2128 default:
2129 B43_WARN_ON(1);
2130 return -ENOSYS;
2131 }
2132 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2133 if (err == -ENOENT) {
2134 snprintf(ctx->errors[ctx->req_type],
2135 sizeof(ctx->errors[ctx->req_type]),
2136 "Firmware file \"%s\" not found\n", ctx->fwname);
2137 return err;
2138 } else if (err) {
2139 snprintf(ctx->errors[ctx->req_type],
2140 sizeof(ctx->errors[ctx->req_type]),
2141 "Firmware file \"%s\" request failed (err=%d)\n",
2142 ctx->fwname, err);
2143 return err;
2144 }
2145 if (blob->size < sizeof(struct b43_fw_header))
2146 goto err_format;
2147 hdr = (struct b43_fw_header *)(blob->data);
2148 switch (hdr->type) {
2149 case B43_FW_TYPE_UCODE:
2150 case B43_FW_TYPE_PCM:
2151 size = be32_to_cpu(hdr->size);
2152 if (size != blob->size - sizeof(struct b43_fw_header))
2153 goto err_format;
2154 /* fallthrough */
2155 case B43_FW_TYPE_IV:
2156 if (hdr->ver != 1)
2157 goto err_format;
2158 break;
2159 default:
2160 goto err_format;
2161 }
2162
2163 fw->data = blob;
2164 fw->filename = name;
2165 fw->type = ctx->req_type;
2166
2167 return 0;
2168
2169 err_format:
2170 snprintf(ctx->errors[ctx->req_type],
2171 sizeof(ctx->errors[ctx->req_type]),
2172 "Firmware file \"%s\" format error.\n", ctx->fwname);
2173 release_firmware(blob);
2174
2175 return -EPROTO;
2176 }
2177
2178 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2179 {
2180 struct b43_wldev *dev = ctx->dev;
2181 struct b43_firmware *fw = &ctx->dev->fw;
2182 const u8 rev = ctx->dev->dev->core_rev;
2183 const char *filename;
2184 u32 tmshigh;
2185 int err;
2186
2187 /* Files for HT and LCN were found by trying one by one */
2188
2189 /* Get microcode */
2190 if ((rev >= 5) && (rev <= 10)) {
2191 filename = "ucode5";
2192 } else if ((rev >= 11) && (rev <= 12)) {
2193 filename = "ucode11";
2194 } else if (rev == 13) {
2195 filename = "ucode13";
2196 } else if (rev == 14) {
2197 filename = "ucode14";
2198 } else if (rev == 15) {
2199 filename = "ucode15";
2200 } else {
2201 switch (dev->phy.type) {
2202 case B43_PHYTYPE_N:
2203 if (rev >= 16)
2204 filename = "ucode16_mimo";
2205 else
2206 goto err_no_ucode;
2207 break;
2208 case B43_PHYTYPE_HT:
2209 if (rev == 29)
2210 filename = "ucode29_mimo";
2211 else
2212 goto err_no_ucode;
2213 break;
2214 case B43_PHYTYPE_LCN:
2215 if (rev == 24)
2216 filename = "ucode24_mimo";
2217 else
2218 goto err_no_ucode;
2219 break;
2220 default:
2221 goto err_no_ucode;
2222 }
2223 }
2224 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2225 if (err)
2226 goto err_load;
2227
2228 /* Get PCM code */
2229 if ((rev >= 5) && (rev <= 10))
2230 filename = "pcm5";
2231 else if (rev >= 11)
2232 filename = NULL;
2233 else
2234 goto err_no_pcm;
2235 fw->pcm_request_failed = 0;
2236 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2237 if (err == -ENOENT) {
2238 /* We did not find a PCM file? Not fatal, but
2239 * core rev <= 10 must do without hwcrypto then. */
2240 fw->pcm_request_failed = 1;
2241 } else if (err)
2242 goto err_load;
2243
2244 /* Get initvals */
2245 switch (dev->phy.type) {
2246 case B43_PHYTYPE_A:
2247 if ((rev >= 5) && (rev <= 10)) {
2248 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2249 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2250 filename = "a0g1initvals5";
2251 else
2252 filename = "a0g0initvals5";
2253 } else
2254 goto err_no_initvals;
2255 break;
2256 case B43_PHYTYPE_G:
2257 if ((rev >= 5) && (rev <= 10))
2258 filename = "b0g0initvals5";
2259 else if (rev >= 13)
2260 filename = "b0g0initvals13";
2261 else
2262 goto err_no_initvals;
2263 break;
2264 case B43_PHYTYPE_N:
2265 if (rev >= 16)
2266 filename = "n0initvals16";
2267 else if ((rev >= 11) && (rev <= 12))
2268 filename = "n0initvals11";
2269 else
2270 goto err_no_initvals;
2271 break;
2272 case B43_PHYTYPE_LP:
2273 if (rev == 13)
2274 filename = "lp0initvals13";
2275 else if (rev == 14)
2276 filename = "lp0initvals14";
2277 else if (rev >= 15)
2278 filename = "lp0initvals15";
2279 else
2280 goto err_no_initvals;
2281 break;
2282 case B43_PHYTYPE_HT:
2283 if (rev == 29)
2284 filename = "ht0initvals29";
2285 else
2286 goto err_no_initvals;
2287 break;
2288 case B43_PHYTYPE_LCN:
2289 if (rev == 24)
2290 filename = "lcn0initvals24";
2291 else
2292 goto err_no_initvals;
2293 break;
2294 default:
2295 goto err_no_initvals;
2296 }
2297 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2298 if (err)
2299 goto err_load;
2300
2301 /* Get bandswitch initvals */
2302 switch (dev->phy.type) {
2303 case B43_PHYTYPE_A:
2304 if ((rev >= 5) && (rev <= 10)) {
2305 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2306 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2307 filename = "a0g1bsinitvals5";
2308 else
2309 filename = "a0g0bsinitvals5";
2310 } else if (rev >= 11)
2311 filename = NULL;
2312 else
2313 goto err_no_initvals;
2314 break;
2315 case B43_PHYTYPE_G:
2316 if ((rev >= 5) && (rev <= 10))
2317 filename = "b0g0bsinitvals5";
2318 else if (rev >= 11)
2319 filename = NULL;
2320 else
2321 goto err_no_initvals;
2322 break;
2323 case B43_PHYTYPE_N:
2324 if (rev >= 16)
2325 filename = "n0bsinitvals16";
2326 else if ((rev >= 11) && (rev <= 12))
2327 filename = "n0bsinitvals11";
2328 else
2329 goto err_no_initvals;
2330 break;
2331 case B43_PHYTYPE_LP:
2332 if (rev == 13)
2333 filename = "lp0bsinitvals13";
2334 else if (rev == 14)
2335 filename = "lp0bsinitvals14";
2336 else if (rev >= 15)
2337 filename = "lp0bsinitvals15";
2338 else
2339 goto err_no_initvals;
2340 break;
2341 case B43_PHYTYPE_HT:
2342 if (rev == 29)
2343 filename = "ht0bsinitvals29";
2344 else
2345 goto err_no_initvals;
2346 break;
2347 case B43_PHYTYPE_LCN:
2348 if (rev == 24)
2349 filename = "lcn0bsinitvals24";
2350 else
2351 goto err_no_initvals;
2352 break;
2353 default:
2354 goto err_no_initvals;
2355 }
2356 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2357 if (err)
2358 goto err_load;
2359
2360 return 0;
2361
2362 err_no_ucode:
2363 err = ctx->fatal_failure = -EOPNOTSUPP;
2364 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2365 "is required for your device (wl-core rev %u)\n", rev);
2366 goto error;
2367
2368 err_no_pcm:
2369 err = ctx->fatal_failure = -EOPNOTSUPP;
2370 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2371 "is required for your device (wl-core rev %u)\n", rev);
2372 goto error;
2373
2374 err_no_initvals:
2375 err = ctx->fatal_failure = -EOPNOTSUPP;
2376 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2377 "is required for your device (wl-core rev %u)\n", rev);
2378 goto error;
2379
2380 err_load:
2381 /* We failed to load this firmware image. The error message
2382 * already is in ctx->errors. Return and let our caller decide
2383 * what to do. */
2384 goto error;
2385
2386 error:
2387 b43_release_firmware(dev);
2388 return err;
2389 }
2390
2391 static int b43_request_firmware(struct b43_wldev *dev)
2392 {
2393 struct b43_request_fw_context *ctx;
2394 unsigned int i;
2395 int err;
2396 const char *errmsg;
2397
2398 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2399 if (!ctx)
2400 return -ENOMEM;
2401 ctx->dev = dev;
2402
2403 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2404 err = b43_try_request_fw(ctx);
2405 if (!err)
2406 goto out; /* Successfully loaded it. */
2407 err = ctx->fatal_failure;
2408 if (err)
2409 goto out;
2410
2411 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2412 err = b43_try_request_fw(ctx);
2413 if (!err)
2414 goto out; /* Successfully loaded it. */
2415 err = ctx->fatal_failure;
2416 if (err)
2417 goto out;
2418
2419 /* Could not find a usable firmware. Print the errors. */
2420 for (i = 0; i < B43_NR_FWTYPES; i++) {
2421 errmsg = ctx->errors[i];
2422 if (strlen(errmsg))
2423 b43err(dev->wl, errmsg);
2424 }
2425 b43_print_fw_helptext(dev->wl, 1);
2426 err = -ENOENT;
2427
2428 out:
2429 kfree(ctx);
2430 return err;
2431 }
2432
2433 static int b43_upload_microcode(struct b43_wldev *dev)
2434 {
2435 struct wiphy *wiphy = dev->wl->hw->wiphy;
2436 const size_t hdr_len = sizeof(struct b43_fw_header);
2437 const __be32 *data;
2438 unsigned int i, len;
2439 u16 fwrev, fwpatch, fwdate, fwtime;
2440 u32 tmp, macctl;
2441 int err = 0;
2442
2443 /* Jump the microcode PSM to offset 0 */
2444 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2445 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2446 macctl |= B43_MACCTL_PSM_JMP0;
2447 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2448 /* Zero out all microcode PSM registers and shared memory. */
2449 for (i = 0; i < 64; i++)
2450 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2451 for (i = 0; i < 4096; i += 2)
2452 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2453
2454 /* Upload Microcode. */
2455 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2456 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2457 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2458 for (i = 0; i < len; i++) {
2459 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2460 udelay(10);
2461 }
2462
2463 if (dev->fw.pcm.data) {
2464 /* Upload PCM data. */
2465 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2466 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2467 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2468 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2469 /* No need for autoinc bit in SHM_HW */
2470 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2471 for (i = 0; i < len; i++) {
2472 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2473 udelay(10);
2474 }
2475 }
2476
2477 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2478
2479 /* Start the microcode PSM */
2480 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2481 macctl &= ~B43_MACCTL_PSM_JMP0;
2482 macctl |= B43_MACCTL_PSM_RUN;
2483 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2484
2485 /* Wait for the microcode to load and respond */
2486 i = 0;
2487 while (1) {
2488 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2489 if (tmp == B43_IRQ_MAC_SUSPENDED)
2490 break;
2491 i++;
2492 if (i >= 20) {
2493 b43err(dev->wl, "Microcode not responding\n");
2494 b43_print_fw_helptext(dev->wl, 1);
2495 err = -ENODEV;
2496 goto error;
2497 }
2498 msleep(50);
2499 }
2500 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2501
2502 /* Get and check the revisions. */
2503 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2504 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2505 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2506 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2507
2508 if (fwrev <= 0x128) {
2509 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2510 "binary drivers older than version 4.x is unsupported. "
2511 "You must upgrade your firmware files.\n");
2512 b43_print_fw_helptext(dev->wl, 1);
2513 err = -EOPNOTSUPP;
2514 goto error;
2515 }
2516 dev->fw.rev = fwrev;
2517 dev->fw.patch = fwpatch;
2518 if (dev->fw.rev >= 598)
2519 dev->fw.hdr_format = B43_FW_HDR_598;
2520 else if (dev->fw.rev >= 410)
2521 dev->fw.hdr_format = B43_FW_HDR_410;
2522 else
2523 dev->fw.hdr_format = B43_FW_HDR_351;
2524 dev->fw.opensource = (fwdate == 0xFFFF);
2525
2526 /* Default to use-all-queues. */
2527 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2528 dev->qos_enabled = !!modparam_qos;
2529 /* Default to firmware/hardware crypto acceleration. */
2530 dev->hwcrypto_enabled = 1;
2531
2532 if (dev->fw.opensource) {
2533 u16 fwcapa;
2534
2535 /* Patchlevel info is encoded in the "time" field. */
2536 dev->fw.patch = fwtime;
2537 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2538 dev->fw.rev, dev->fw.patch);
2539
2540 fwcapa = b43_fwcapa_read(dev);
2541 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2542 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2543 /* Disable hardware crypto and fall back to software crypto. */
2544 dev->hwcrypto_enabled = 0;
2545 }
2546 if (!(fwcapa & B43_FWCAPA_QOS)) {
2547 b43info(dev->wl, "QoS not supported by firmware\n");
2548 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2549 * ieee80211_unregister to make sure the networking core can
2550 * properly free possible resources. */
2551 dev->wl->hw->queues = 1;
2552 dev->qos_enabled = 0;
2553 }
2554 } else {
2555 b43info(dev->wl, "Loading firmware version %u.%u "
2556 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2557 fwrev, fwpatch,
2558 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2559 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2560 if (dev->fw.pcm_request_failed) {
2561 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2562 "Hardware accelerated cryptography is disabled.\n");
2563 b43_print_fw_helptext(dev->wl, 0);
2564 }
2565 }
2566
2567 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2568 dev->fw.rev, dev->fw.patch);
2569 wiphy->hw_version = dev->dev->core_id;
2570
2571 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2572 /* We're over the deadline, but we keep support for old fw
2573 * until it turns out to be in major conflict with something new. */
2574 b43warn(dev->wl, "You are using an old firmware image. "
2575 "Support for old firmware will be removed soon "
2576 "(official deadline was July 2008).\n");
2577 b43_print_fw_helptext(dev->wl, 0);
2578 }
2579
2580 return 0;
2581
2582 error:
2583 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2584 macctl &= ~B43_MACCTL_PSM_RUN;
2585 macctl |= B43_MACCTL_PSM_JMP0;
2586 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2587
2588 return err;
2589 }
2590
2591 static int b43_write_initvals(struct b43_wldev *dev,
2592 const struct b43_iv *ivals,
2593 size_t count,
2594 size_t array_size)
2595 {
2596 const struct b43_iv *iv;
2597 u16 offset;
2598 size_t i;
2599 bool bit32;
2600
2601 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2602 iv = ivals;
2603 for (i = 0; i < count; i++) {
2604 if (array_size < sizeof(iv->offset_size))
2605 goto err_format;
2606 array_size -= sizeof(iv->offset_size);
2607 offset = be16_to_cpu(iv->offset_size);
2608 bit32 = !!(offset & B43_IV_32BIT);
2609 offset &= B43_IV_OFFSET_MASK;
2610 if (offset >= 0x1000)
2611 goto err_format;
2612 if (bit32) {
2613 u32 value;
2614
2615 if (array_size < sizeof(iv->data.d32))
2616 goto err_format;
2617 array_size -= sizeof(iv->data.d32);
2618
2619 value = get_unaligned_be32(&iv->data.d32);
2620 b43_write32(dev, offset, value);
2621
2622 iv = (const struct b43_iv *)((const uint8_t *)iv +
2623 sizeof(__be16) +
2624 sizeof(__be32));
2625 } else {
2626 u16 value;
2627
2628 if (array_size < sizeof(iv->data.d16))
2629 goto err_format;
2630 array_size -= sizeof(iv->data.d16);
2631
2632 value = be16_to_cpu(iv->data.d16);
2633 b43_write16(dev, offset, value);
2634
2635 iv = (const struct b43_iv *)((const uint8_t *)iv +
2636 sizeof(__be16) +
2637 sizeof(__be16));
2638 }
2639 }
2640 if (array_size)
2641 goto err_format;
2642
2643 return 0;
2644
2645 err_format:
2646 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2647 b43_print_fw_helptext(dev->wl, 1);
2648
2649 return -EPROTO;
2650 }
2651
2652 static int b43_upload_initvals(struct b43_wldev *dev)
2653 {
2654 const size_t hdr_len = sizeof(struct b43_fw_header);
2655 const struct b43_fw_header *hdr;
2656 struct b43_firmware *fw = &dev->fw;
2657 const struct b43_iv *ivals;
2658 size_t count;
2659 int err;
2660
2661 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2662 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2663 count = be32_to_cpu(hdr->size);
2664 err = b43_write_initvals(dev, ivals, count,
2665 fw->initvals.data->size - hdr_len);
2666 if (err)
2667 goto out;
2668 if (fw->initvals_band.data) {
2669 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2670 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2671 count = be32_to_cpu(hdr->size);
2672 err = b43_write_initvals(dev, ivals, count,
2673 fw->initvals_band.data->size - hdr_len);
2674 if (err)
2675 goto out;
2676 }
2677 out:
2678
2679 return err;
2680 }
2681
2682 /* Initialize the GPIOs
2683 * http://bcm-specs.sipsolutions.net/GPIO
2684 */
2685 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2686 {
2687 struct ssb_bus *bus = dev->dev->sdev->bus;
2688
2689 #ifdef CONFIG_SSB_DRIVER_PCICORE
2690 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2691 #else
2692 return bus->chipco.dev;
2693 #endif
2694 }
2695
2696 static int b43_gpio_init(struct b43_wldev *dev)
2697 {
2698 struct ssb_device *gpiodev;
2699 u32 mask, set;
2700
2701 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2702 & ~B43_MACCTL_GPOUTSMSK);
2703
2704 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2705 | 0x000F);
2706
2707 mask = 0x0000001F;
2708 set = 0x0000000F;
2709 if (dev->dev->chip_id == 0x4301) {
2710 mask |= 0x0060;
2711 set |= 0x0060;
2712 }
2713 if (0 /* FIXME: conditional unknown */ ) {
2714 b43_write16(dev, B43_MMIO_GPIO_MASK,
2715 b43_read16(dev, B43_MMIO_GPIO_MASK)
2716 | 0x0100);
2717 mask |= 0x0180;
2718 set |= 0x0180;
2719 }
2720 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2721 b43_write16(dev, B43_MMIO_GPIO_MASK,
2722 b43_read16(dev, B43_MMIO_GPIO_MASK)
2723 | 0x0200);
2724 mask |= 0x0200;
2725 set |= 0x0200;
2726 }
2727 if (dev->dev->core_rev >= 2)
2728 mask |= 0x0010; /* FIXME: This is redundant. */
2729
2730 switch (dev->dev->bus_type) {
2731 #ifdef CONFIG_B43_BCMA
2732 case B43_BUS_BCMA:
2733 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2734 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2735 BCMA_CC_GPIOCTL) & mask) | set);
2736 break;
2737 #endif
2738 #ifdef CONFIG_B43_SSB
2739 case B43_BUS_SSB:
2740 gpiodev = b43_ssb_gpio_dev(dev);
2741 if (gpiodev)
2742 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2743 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2744 & mask) | set);
2745 break;
2746 #endif
2747 }
2748
2749 return 0;
2750 }
2751
2752 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2753 static void b43_gpio_cleanup(struct b43_wldev *dev)
2754 {
2755 struct ssb_device *gpiodev;
2756
2757 switch (dev->dev->bus_type) {
2758 #ifdef CONFIG_B43_BCMA
2759 case B43_BUS_BCMA:
2760 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2761 0);
2762 break;
2763 #endif
2764 #ifdef CONFIG_B43_SSB
2765 case B43_BUS_SSB:
2766 gpiodev = b43_ssb_gpio_dev(dev);
2767 if (gpiodev)
2768 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2769 break;
2770 #endif
2771 }
2772 }
2773
2774 /* http://bcm-specs.sipsolutions.net/EnableMac */
2775 void b43_mac_enable(struct b43_wldev *dev)
2776 {
2777 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2778 u16 fwstate;
2779
2780 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2781 B43_SHM_SH_UCODESTAT);
2782 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2783 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2784 b43err(dev->wl, "b43_mac_enable(): The firmware "
2785 "should be suspended, but current state is %u\n",
2786 fwstate);
2787 }
2788 }
2789
2790 dev->mac_suspended--;
2791 B43_WARN_ON(dev->mac_suspended < 0);
2792 if (dev->mac_suspended == 0) {
2793 b43_write32(dev, B43_MMIO_MACCTL,
2794 b43_read32(dev, B43_MMIO_MACCTL)
2795 | B43_MACCTL_ENABLED);
2796 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2797 B43_IRQ_MAC_SUSPENDED);
2798 /* Commit writes */
2799 b43_read32(dev, B43_MMIO_MACCTL);
2800 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2801 b43_power_saving_ctl_bits(dev, 0);
2802 }
2803 }
2804
2805 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2806 void b43_mac_suspend(struct b43_wldev *dev)
2807 {
2808 int i;
2809 u32 tmp;
2810
2811 might_sleep();
2812 B43_WARN_ON(dev->mac_suspended < 0);
2813
2814 if (dev->mac_suspended == 0) {
2815 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2816 b43_write32(dev, B43_MMIO_MACCTL,
2817 b43_read32(dev, B43_MMIO_MACCTL)
2818 & ~B43_MACCTL_ENABLED);
2819 /* force pci to flush the write */
2820 b43_read32(dev, B43_MMIO_MACCTL);
2821 for (i = 35; i; i--) {
2822 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2823 if (tmp & B43_IRQ_MAC_SUSPENDED)
2824 goto out;
2825 udelay(10);
2826 }
2827 /* Hm, it seems this will take some time. Use msleep(). */
2828 for (i = 40; i; i--) {
2829 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2830 if (tmp & B43_IRQ_MAC_SUSPENDED)
2831 goto out;
2832 msleep(1);
2833 }
2834 b43err(dev->wl, "MAC suspend failed\n");
2835 }
2836 out:
2837 dev->mac_suspended++;
2838 }
2839
2840 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2841 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2842 {
2843 u32 tmp;
2844
2845 switch (dev->dev->bus_type) {
2846 #ifdef CONFIG_B43_BCMA
2847 case B43_BUS_BCMA:
2848 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2849 if (on)
2850 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2851 else
2852 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2853 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2854 break;
2855 #endif
2856 #ifdef CONFIG_B43_SSB
2857 case B43_BUS_SSB:
2858 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2859 if (on)
2860 tmp |= B43_TMSLOW_MACPHYCLKEN;
2861 else
2862 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2863 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2864 break;
2865 #endif
2866 }
2867 }
2868
2869 static void b43_adjust_opmode(struct b43_wldev *dev)
2870 {
2871 struct b43_wl *wl = dev->wl;
2872 u32 ctl;
2873 u16 cfp_pretbtt;
2874
2875 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2876 /* Reset status to STA infrastructure mode. */
2877 ctl &= ~B43_MACCTL_AP;
2878 ctl &= ~B43_MACCTL_KEEP_CTL;
2879 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2880 ctl &= ~B43_MACCTL_KEEP_BAD;
2881 ctl &= ~B43_MACCTL_PROMISC;
2882 ctl &= ~B43_MACCTL_BEACPROMISC;
2883 ctl |= B43_MACCTL_INFRA;
2884
2885 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2886 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2887 ctl |= B43_MACCTL_AP;
2888 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2889 ctl &= ~B43_MACCTL_INFRA;
2890
2891 if (wl->filter_flags & FIF_CONTROL)
2892 ctl |= B43_MACCTL_KEEP_CTL;
2893 if (wl->filter_flags & FIF_FCSFAIL)
2894 ctl |= B43_MACCTL_KEEP_BAD;
2895 if (wl->filter_flags & FIF_PLCPFAIL)
2896 ctl |= B43_MACCTL_KEEP_BADPLCP;
2897 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2898 ctl |= B43_MACCTL_PROMISC;
2899 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2900 ctl |= B43_MACCTL_BEACPROMISC;
2901
2902 /* Workaround: On old hardware the HW-MAC-address-filter
2903 * doesn't work properly, so always run promisc in filter
2904 * it in software. */
2905 if (dev->dev->core_rev <= 4)
2906 ctl |= B43_MACCTL_PROMISC;
2907
2908 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2909
2910 cfp_pretbtt = 2;
2911 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2912 if (dev->dev->chip_id == 0x4306 &&
2913 dev->dev->chip_rev == 3)
2914 cfp_pretbtt = 100;
2915 else
2916 cfp_pretbtt = 50;
2917 }
2918 b43_write16(dev, 0x612, cfp_pretbtt);
2919
2920 /* FIXME: We don't currently implement the PMQ mechanism,
2921 * so always disable it. If we want to implement PMQ,
2922 * we need to enable it here (clear DISCPMQ) in AP mode.
2923 */
2924 if (0 /* ctl & B43_MACCTL_AP */) {
2925 b43_write32(dev, B43_MMIO_MACCTL,
2926 b43_read32(dev, B43_MMIO_MACCTL)
2927 & ~B43_MACCTL_DISCPMQ);
2928 } else {
2929 b43_write32(dev, B43_MMIO_MACCTL,
2930 b43_read32(dev, B43_MMIO_MACCTL)
2931 | B43_MACCTL_DISCPMQ);
2932 }
2933 }
2934
2935 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2936 {
2937 u16 offset;
2938
2939 if (is_ofdm) {
2940 offset = 0x480;
2941 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2942 } else {
2943 offset = 0x4C0;
2944 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2945 }
2946 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2947 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2948 }
2949
2950 static void b43_rate_memory_init(struct b43_wldev *dev)
2951 {
2952 switch (dev->phy.type) {
2953 case B43_PHYTYPE_A:
2954 case B43_PHYTYPE_G:
2955 case B43_PHYTYPE_N:
2956 case B43_PHYTYPE_LP:
2957 case B43_PHYTYPE_HT:
2958 case B43_PHYTYPE_LCN:
2959 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2960 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2961 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2962 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2963 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2964 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2965 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2966 if (dev->phy.type == B43_PHYTYPE_A)
2967 break;
2968 /* fallthrough */
2969 case B43_PHYTYPE_B:
2970 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2971 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2972 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2973 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2974 break;
2975 default:
2976 B43_WARN_ON(1);
2977 }
2978 }
2979
2980 /* Set the default values for the PHY TX Control Words. */
2981 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2982 {
2983 u16 ctl = 0;
2984
2985 ctl |= B43_TXH_PHY_ENC_CCK;
2986 ctl |= B43_TXH_PHY_ANT01AUTO;
2987 ctl |= B43_TXH_PHY_TXPWR;
2988
2989 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2990 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2991 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2992 }
2993
2994 /* Set the TX-Antenna for management frames sent by firmware. */
2995 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2996 {
2997 u16 ant;
2998 u16 tmp;
2999
3000 ant = b43_antenna_to_phyctl(antenna);
3001
3002 /* For ACK/CTS */
3003 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3004 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3005 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3006 /* For Probe Resposes */
3007 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3008 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3009 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3010 }
3011
3012 /* This is the opposite of b43_chip_init() */
3013 static void b43_chip_exit(struct b43_wldev *dev)
3014 {
3015 b43_phy_exit(dev);
3016 b43_gpio_cleanup(dev);
3017 /* firmware is released later */
3018 }
3019
3020 /* Initialize the chip
3021 * http://bcm-specs.sipsolutions.net/ChipInit
3022 */
3023 static int b43_chip_init(struct b43_wldev *dev)
3024 {
3025 struct b43_phy *phy = &dev->phy;
3026 int err;
3027 u32 macctl;
3028 u16 value16;
3029
3030 /* Initialize the MAC control */
3031 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3032 if (dev->phy.gmode)
3033 macctl |= B43_MACCTL_GMODE;
3034 macctl |= B43_MACCTL_INFRA;
3035 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3036
3037 err = b43_request_firmware(dev);
3038 if (err)
3039 goto out;
3040 err = b43_upload_microcode(dev);
3041 if (err)
3042 goto out; /* firmware is released later */
3043
3044 err = b43_gpio_init(dev);
3045 if (err)
3046 goto out; /* firmware is released later */
3047
3048 err = b43_upload_initvals(dev);
3049 if (err)
3050 goto err_gpio_clean;
3051
3052 /* Turn the Analog on and initialize the PHY. */
3053 phy->ops->switch_analog(dev, 1);
3054 err = b43_phy_init(dev);
3055 if (err)
3056 goto err_gpio_clean;
3057
3058 /* Disable Interference Mitigation. */
3059 if (phy->ops->interf_mitigation)
3060 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3061
3062 /* Select the antennae */
3063 if (phy->ops->set_rx_antenna)
3064 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3065 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3066
3067 if (phy->type == B43_PHYTYPE_B) {
3068 value16 = b43_read16(dev, 0x005E);
3069 value16 |= 0x0004;
3070 b43_write16(dev, 0x005E, value16);
3071 }
3072 b43_write32(dev, 0x0100, 0x01000000);
3073 if (dev->dev->core_rev < 5)
3074 b43_write32(dev, 0x010C, 0x01000000);
3075
3076 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3077 & ~B43_MACCTL_INFRA);
3078 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3079 | B43_MACCTL_INFRA);
3080
3081 /* Probe Response Timeout value */
3082 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3083 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3084
3085 /* Initially set the wireless operation mode. */
3086 b43_adjust_opmode(dev);
3087
3088 if (dev->dev->core_rev < 3) {
3089 b43_write16(dev, 0x060E, 0x0000);
3090 b43_write16(dev, 0x0610, 0x8000);
3091 b43_write16(dev, 0x0604, 0x0000);
3092 b43_write16(dev, 0x0606, 0x0200);
3093 } else {
3094 b43_write32(dev, 0x0188, 0x80000000);
3095 b43_write32(dev, 0x018C, 0x02000000);
3096 }
3097 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3098 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3099 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3100 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3101 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3102 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3103 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3104
3105 b43_mac_phy_clock_set(dev, true);
3106
3107 switch (dev->dev->bus_type) {
3108 #ifdef CONFIG_B43_BCMA
3109 case B43_BUS_BCMA:
3110 /* FIXME: 0xE74 is quite common, but should be read from CC */
3111 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3112 break;
3113 #endif
3114 #ifdef CONFIG_B43_SSB
3115 case B43_BUS_SSB:
3116 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3117 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3118 break;
3119 #endif
3120 }
3121
3122 err = 0;
3123 b43dbg(dev->wl, "Chip initialized\n");
3124 out:
3125 return err;
3126
3127 err_gpio_clean:
3128 b43_gpio_cleanup(dev);
3129 return err;
3130 }
3131
3132 static void b43_periodic_every60sec(struct b43_wldev *dev)
3133 {
3134 const struct b43_phy_operations *ops = dev->phy.ops;
3135
3136 if (ops->pwork_60sec)
3137 ops->pwork_60sec(dev);
3138
3139 /* Force check the TX power emission now. */
3140 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3141 }
3142
3143 static void b43_periodic_every30sec(struct b43_wldev *dev)
3144 {
3145 /* Update device statistics. */
3146 b43_calculate_link_quality(dev);
3147 }
3148
3149 static void b43_periodic_every15sec(struct b43_wldev *dev)
3150 {
3151 struct b43_phy *phy = &dev->phy;
3152 u16 wdr;
3153
3154 if (dev->fw.opensource) {
3155 /* Check if the firmware is still alive.
3156 * It will reset the watchdog counter to 0 in its idle loop. */
3157 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3158 if (unlikely(wdr)) {
3159 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3160 b43_controller_restart(dev, "Firmware watchdog");
3161 return;
3162 } else {
3163 b43_shm_write16(dev, B43_SHM_SCRATCH,
3164 B43_WATCHDOG_REG, 1);
3165 }
3166 }
3167
3168 if (phy->ops->pwork_15sec)
3169 phy->ops->pwork_15sec(dev);
3170
3171 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3172 wmb();
3173
3174 #if B43_DEBUG
3175 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3176 unsigned int i;
3177
3178 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3179 dev->irq_count / 15,
3180 dev->tx_count / 15,
3181 dev->rx_count / 15);
3182 dev->irq_count = 0;
3183 dev->tx_count = 0;
3184 dev->rx_count = 0;
3185 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3186 if (dev->irq_bit_count[i]) {
3187 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3188 dev->irq_bit_count[i] / 15, i, (1 << i));
3189 dev->irq_bit_count[i] = 0;
3190 }
3191 }
3192 }
3193 #endif
3194 }
3195
3196 static void do_periodic_work(struct b43_wldev *dev)
3197 {
3198 unsigned int state;
3199
3200 state = dev->periodic_state;
3201 if (state % 4 == 0)
3202 b43_periodic_every60sec(dev);
3203 if (state % 2 == 0)
3204 b43_periodic_every30sec(dev);
3205 b43_periodic_every15sec(dev);
3206 }
3207
3208 /* Periodic work locking policy:
3209 * The whole periodic work handler is protected by
3210 * wl->mutex. If another lock is needed somewhere in the
3211 * pwork callchain, it's acquired in-place, where it's needed.
3212 */
3213 static void b43_periodic_work_handler(struct work_struct *work)
3214 {
3215 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3216 periodic_work.work);
3217 struct b43_wl *wl = dev->wl;
3218 unsigned long delay;
3219
3220 mutex_lock(&wl->mutex);
3221
3222 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3223 goto out;
3224 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3225 goto out_requeue;
3226
3227 do_periodic_work(dev);
3228
3229 dev->periodic_state++;
3230 out_requeue:
3231 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3232 delay = msecs_to_jiffies(50);
3233 else
3234 delay = round_jiffies_relative(HZ * 15);
3235 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3236 out:
3237 mutex_unlock(&wl->mutex);
3238 }
3239
3240 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3241 {
3242 struct delayed_work *work = &dev->periodic_work;
3243
3244 dev->periodic_state = 0;
3245 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3246 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3247 }
3248
3249 /* Check if communication with the device works correctly. */
3250 static int b43_validate_chipaccess(struct b43_wldev *dev)
3251 {
3252 u32 v, backup0, backup4;
3253
3254 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3255 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3256
3257 /* Check for read/write and endianness problems. */
3258 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3259 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3260 goto error;
3261 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3262 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3263 goto error;
3264
3265 /* Check if unaligned 32bit SHM_SHARED access works properly.
3266 * However, don't bail out on failure, because it's noncritical. */
3267 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3268 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3269 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3270 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3271 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3272 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3273 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3274 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3275 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3276 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3277 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3278 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3279
3280 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3281 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3282
3283 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3284 /* The 32bit register shadows the two 16bit registers
3285 * with update sideeffects. Validate this. */
3286 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3287 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3288 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3289 goto error;
3290 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3291 goto error;
3292 }
3293 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3294
3295 v = b43_read32(dev, B43_MMIO_MACCTL);
3296 v |= B43_MACCTL_GMODE;
3297 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3298 goto error;
3299
3300 return 0;
3301 error:
3302 b43err(dev->wl, "Failed to validate the chipaccess\n");
3303 return -ENODEV;
3304 }
3305
3306 static void b43_security_init(struct b43_wldev *dev)
3307 {
3308 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3309 /* KTP is a word address, but we address SHM bytewise.
3310 * So multiply by two.
3311 */
3312 dev->ktp *= 2;
3313 /* Number of RCMTA address slots */
3314 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3315 /* Clear the key memory. */
3316 b43_clear_keys(dev);
3317 }
3318
3319 #ifdef CONFIG_B43_HWRNG
3320 static int b43_rng_read(struct hwrng *rng, u32 *data)
3321 {
3322 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3323 struct b43_wldev *dev;
3324 int count = -ENODEV;
3325
3326 mutex_lock(&wl->mutex);
3327 dev = wl->current_dev;
3328 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3329 *data = b43_read16(dev, B43_MMIO_RNG);
3330 count = sizeof(u16);
3331 }
3332 mutex_unlock(&wl->mutex);
3333
3334 return count;
3335 }
3336 #endif /* CONFIG_B43_HWRNG */
3337
3338 static void b43_rng_exit(struct b43_wl *wl)
3339 {
3340 #ifdef CONFIG_B43_HWRNG
3341 if (wl->rng_initialized)
3342 hwrng_unregister(&wl->rng);
3343 #endif /* CONFIG_B43_HWRNG */
3344 }
3345
3346 static int b43_rng_init(struct b43_wl *wl)
3347 {
3348 int err = 0;
3349
3350 #ifdef CONFIG_B43_HWRNG
3351 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3352 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3353 wl->rng.name = wl->rng_name;
3354 wl->rng.data_read = b43_rng_read;
3355 wl->rng.priv = (unsigned long)wl;
3356 wl->rng_initialized = 1;
3357 err = hwrng_register(&wl->rng);
3358 if (err) {
3359 wl->rng_initialized = 0;
3360 b43err(wl, "Failed to register the random "
3361 "number generator (%d)\n", err);
3362 }
3363 #endif /* CONFIG_B43_HWRNG */
3364
3365 return err;
3366 }
3367
3368 static void b43_tx_work(struct work_struct *work)
3369 {
3370 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3371 struct b43_wldev *dev;
3372 struct sk_buff *skb;
3373 int err = 0;
3374
3375 mutex_lock(&wl->mutex);
3376 dev = wl->current_dev;
3377 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3378 mutex_unlock(&wl->mutex);
3379 return;
3380 }
3381
3382 while (skb_queue_len(&wl->tx_queue)) {
3383 skb = skb_dequeue(&wl->tx_queue);
3384
3385 if (b43_using_pio_transfers(dev))
3386 err = b43_pio_tx(dev, skb);
3387 else
3388 err = b43_dma_tx(dev, skb);
3389 if (unlikely(err))
3390 dev_kfree_skb(skb); /* Drop it */
3391 }
3392
3393 #if B43_DEBUG
3394 dev->tx_count++;
3395 #endif
3396 mutex_unlock(&wl->mutex);
3397 }
3398
3399 static void b43_op_tx(struct ieee80211_hw *hw,
3400 struct sk_buff *skb)
3401 {
3402 struct b43_wl *wl = hw_to_b43_wl(hw);
3403
3404 if (unlikely(skb->len < 2 + 2 + 6)) {
3405 /* Too short, this can't be a valid frame. */
3406 dev_kfree_skb_any(skb);
3407 return;
3408 }
3409 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3410
3411 skb_queue_tail(&wl->tx_queue, skb);
3412 ieee80211_queue_work(wl->hw, &wl->tx_work);
3413 }
3414
3415 static void b43_qos_params_upload(struct b43_wldev *dev,
3416 const struct ieee80211_tx_queue_params *p,
3417 u16 shm_offset)
3418 {
3419 u16 params[B43_NR_QOSPARAMS];
3420 int bslots, tmp;
3421 unsigned int i;
3422
3423 if (!dev->qos_enabled)
3424 return;
3425
3426 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3427
3428 memset(&params, 0, sizeof(params));
3429
3430 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3431 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3432 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3433 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3434 params[B43_QOSPARAM_AIFS] = p->aifs;
3435 params[B43_QOSPARAM_BSLOTS] = bslots;
3436 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3437
3438 for (i = 0; i < ARRAY_SIZE(params); i++) {
3439 if (i == B43_QOSPARAM_STATUS) {
3440 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3441 shm_offset + (i * 2));
3442 /* Mark the parameters as updated. */
3443 tmp |= 0x100;
3444 b43_shm_write16(dev, B43_SHM_SHARED,
3445 shm_offset + (i * 2),
3446 tmp);
3447 } else {
3448 b43_shm_write16(dev, B43_SHM_SHARED,
3449 shm_offset + (i * 2),
3450 params[i]);
3451 }
3452 }
3453 }
3454
3455 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3456 static const u16 b43_qos_shm_offsets[] = {
3457 /* [mac80211-queue-nr] = SHM_OFFSET, */
3458 [0] = B43_QOS_VOICE,
3459 [1] = B43_QOS_VIDEO,
3460 [2] = B43_QOS_BESTEFFORT,
3461 [3] = B43_QOS_BACKGROUND,
3462 };
3463
3464 /* Update all QOS parameters in hardware. */
3465 static void b43_qos_upload_all(struct b43_wldev *dev)
3466 {
3467 struct b43_wl *wl = dev->wl;
3468 struct b43_qos_params *params;
3469 unsigned int i;
3470
3471 if (!dev->qos_enabled)
3472 return;
3473
3474 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3475 ARRAY_SIZE(wl->qos_params));
3476
3477 b43_mac_suspend(dev);
3478 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3479 params = &(wl->qos_params[i]);
3480 b43_qos_params_upload(dev, &(params->p),
3481 b43_qos_shm_offsets[i]);
3482 }
3483 b43_mac_enable(dev);
3484 }
3485
3486 static void b43_qos_clear(struct b43_wl *wl)
3487 {
3488 struct b43_qos_params *params;
3489 unsigned int i;
3490
3491 /* Initialize QoS parameters to sane defaults. */
3492
3493 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3494 ARRAY_SIZE(wl->qos_params));
3495
3496 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3497 params = &(wl->qos_params[i]);
3498
3499 switch (b43_qos_shm_offsets[i]) {
3500 case B43_QOS_VOICE:
3501 params->p.txop = 0;
3502 params->p.aifs = 2;
3503 params->p.cw_min = 0x0001;
3504 params->p.cw_max = 0x0001;
3505 break;
3506 case B43_QOS_VIDEO:
3507 params->p.txop = 0;
3508 params->p.aifs = 2;
3509 params->p.cw_min = 0x0001;
3510 params->p.cw_max = 0x0001;
3511 break;
3512 case B43_QOS_BESTEFFORT:
3513 params->p.txop = 0;
3514 params->p.aifs = 3;
3515 params->p.cw_min = 0x0001;
3516 params->p.cw_max = 0x03FF;
3517 break;
3518 case B43_QOS_BACKGROUND:
3519 params->p.txop = 0;
3520 params->p.aifs = 7;
3521 params->p.cw_min = 0x0001;
3522 params->p.cw_max = 0x03FF;
3523 break;
3524 default:
3525 B43_WARN_ON(1);
3526 }
3527 }
3528 }
3529
3530 /* Initialize the core's QOS capabilities */
3531 static void b43_qos_init(struct b43_wldev *dev)
3532 {
3533 if (!dev->qos_enabled) {
3534 /* Disable QOS support. */
3535 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3536 b43_write16(dev, B43_MMIO_IFSCTL,
3537 b43_read16(dev, B43_MMIO_IFSCTL)
3538 & ~B43_MMIO_IFSCTL_USE_EDCF);
3539 b43dbg(dev->wl, "QoS disabled\n");
3540 return;
3541 }
3542
3543 /* Upload the current QOS parameters. */
3544 b43_qos_upload_all(dev);
3545
3546 /* Enable QOS support. */
3547 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3548 b43_write16(dev, B43_MMIO_IFSCTL,
3549 b43_read16(dev, B43_MMIO_IFSCTL)
3550 | B43_MMIO_IFSCTL_USE_EDCF);
3551 b43dbg(dev->wl, "QoS enabled\n");
3552 }
3553
3554 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3555 const struct ieee80211_tx_queue_params *params)
3556 {
3557 struct b43_wl *wl = hw_to_b43_wl(hw);
3558 struct b43_wldev *dev;
3559 unsigned int queue = (unsigned int)_queue;
3560 int err = -ENODEV;
3561
3562 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3563 /* Queue not available or don't support setting
3564 * params on this queue. Return success to not
3565 * confuse mac80211. */
3566 return 0;
3567 }
3568 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3569 ARRAY_SIZE(wl->qos_params));
3570
3571 mutex_lock(&wl->mutex);
3572 dev = wl->current_dev;
3573 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3574 goto out_unlock;
3575
3576 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3577 b43_mac_suspend(dev);
3578 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3579 b43_qos_shm_offsets[queue]);
3580 b43_mac_enable(dev);
3581 err = 0;
3582
3583 out_unlock:
3584 mutex_unlock(&wl->mutex);
3585
3586 return err;
3587 }
3588
3589 static int b43_op_get_stats(struct ieee80211_hw *hw,
3590 struct ieee80211_low_level_stats *stats)
3591 {
3592 struct b43_wl *wl = hw_to_b43_wl(hw);
3593
3594 mutex_lock(&wl->mutex);
3595 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3596 mutex_unlock(&wl->mutex);
3597
3598 return 0;
3599 }
3600
3601 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3602 {
3603 struct b43_wl *wl = hw_to_b43_wl(hw);
3604 struct b43_wldev *dev;
3605 u64 tsf;
3606
3607 mutex_lock(&wl->mutex);
3608 dev = wl->current_dev;
3609
3610 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3611 b43_tsf_read(dev, &tsf);
3612 else
3613 tsf = 0;
3614
3615 mutex_unlock(&wl->mutex);
3616
3617 return tsf;
3618 }
3619
3620 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3621 {
3622 struct b43_wl *wl = hw_to_b43_wl(hw);
3623 struct b43_wldev *dev;
3624
3625 mutex_lock(&wl->mutex);
3626 dev = wl->current_dev;
3627
3628 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3629 b43_tsf_write(dev, tsf);
3630
3631 mutex_unlock(&wl->mutex);
3632 }
3633
3634 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3635 {
3636 u32 tmp;
3637
3638 switch (dev->dev->bus_type) {
3639 #ifdef CONFIG_B43_BCMA
3640 case B43_BUS_BCMA:
3641 b43err(dev->wl,
3642 "Putting PHY into reset not supported on BCMA\n");
3643 break;
3644 #endif
3645 #ifdef CONFIG_B43_SSB
3646 case B43_BUS_SSB:
3647 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3648 tmp &= ~B43_TMSLOW_GMODE;
3649 tmp |= B43_TMSLOW_PHYRESET;
3650 tmp |= SSB_TMSLOW_FGC;
3651 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3652 msleep(1);
3653
3654 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3655 tmp &= ~SSB_TMSLOW_FGC;
3656 tmp |= B43_TMSLOW_PHYRESET;
3657 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3658 msleep(1);
3659
3660 break;
3661 #endif
3662 }
3663 }
3664
3665 static const char *band_to_string(enum ieee80211_band band)
3666 {
3667 switch (band) {
3668 case IEEE80211_BAND_5GHZ:
3669 return "5";
3670 case IEEE80211_BAND_2GHZ:
3671 return "2.4";
3672 default:
3673 break;
3674 }
3675 B43_WARN_ON(1);
3676 return "";
3677 }
3678
3679 /* Expects wl->mutex locked */
3680 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3681 {
3682 struct b43_wldev *up_dev = NULL;
3683 struct b43_wldev *down_dev;
3684 struct b43_wldev *d;
3685 int err;
3686 bool uninitialized_var(gmode);
3687 int prev_status;
3688
3689 /* Find a device and PHY which supports the band. */
3690 list_for_each_entry(d, &wl->devlist, list) {
3691 switch (chan->band) {
3692 case IEEE80211_BAND_5GHZ:
3693 if (d->phy.supports_5ghz) {
3694 up_dev = d;
3695 gmode = 0;
3696 }
3697 break;
3698 case IEEE80211_BAND_2GHZ:
3699 if (d->phy.supports_2ghz) {
3700 up_dev = d;
3701 gmode = 1;
3702 }
3703 break;
3704 default:
3705 B43_WARN_ON(1);
3706 return -EINVAL;
3707 }
3708 if (up_dev)
3709 break;
3710 }
3711 if (!up_dev) {
3712 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3713 band_to_string(chan->band));
3714 return -ENODEV;
3715 }
3716 if ((up_dev == wl->current_dev) &&
3717 (!!wl->current_dev->phy.gmode == !!gmode)) {
3718 /* This device is already running. */
3719 return 0;
3720 }
3721 b43dbg(wl, "Switching to %s-GHz band\n",
3722 band_to_string(chan->band));
3723 down_dev = wl->current_dev;
3724
3725 prev_status = b43_status(down_dev);
3726 /* Shutdown the currently running core. */
3727 if (prev_status >= B43_STAT_STARTED)
3728 down_dev = b43_wireless_core_stop(down_dev);
3729 if (prev_status >= B43_STAT_INITIALIZED)
3730 b43_wireless_core_exit(down_dev);
3731
3732 if (down_dev != up_dev) {
3733 /* We switch to a different core, so we put PHY into
3734 * RESET on the old core. */
3735 b43_put_phy_into_reset(down_dev);
3736 }
3737
3738 /* Now start the new core. */
3739 up_dev->phy.gmode = gmode;
3740 if (prev_status >= B43_STAT_INITIALIZED) {
3741 err = b43_wireless_core_init(up_dev);
3742 if (err) {
3743 b43err(wl, "Fatal: Could not initialize device for "
3744 "selected %s-GHz band\n",
3745 band_to_string(chan->band));
3746 goto init_failure;
3747 }
3748 }
3749 if (prev_status >= B43_STAT_STARTED) {
3750 err = b43_wireless_core_start(up_dev);
3751 if (err) {
3752 b43err(wl, "Fatal: Coult not start device for "
3753 "selected %s-GHz band\n",
3754 band_to_string(chan->band));
3755 b43_wireless_core_exit(up_dev);
3756 goto init_failure;
3757 }
3758 }
3759 B43_WARN_ON(b43_status(up_dev) != prev_status);
3760
3761 wl->current_dev = up_dev;
3762
3763 return 0;
3764 init_failure:
3765 /* Whoops, failed to init the new core. No core is operating now. */
3766 wl->current_dev = NULL;
3767 return err;
3768 }
3769
3770 /* Write the short and long frame retry limit values. */
3771 static void b43_set_retry_limits(struct b43_wldev *dev,
3772 unsigned int short_retry,
3773 unsigned int long_retry)
3774 {
3775 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3776 * the chip-internal counter. */
3777 short_retry = min(short_retry, (unsigned int)0xF);
3778 long_retry = min(long_retry, (unsigned int)0xF);
3779
3780 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3781 short_retry);
3782 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3783 long_retry);
3784 }
3785
3786 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3787 {
3788 struct b43_wl *wl = hw_to_b43_wl(hw);
3789 struct b43_wldev *dev;
3790 struct b43_phy *phy;
3791 struct ieee80211_conf *conf = &hw->conf;
3792 int antenna;
3793 int err = 0;
3794 bool reload_bss = false;
3795
3796 mutex_lock(&wl->mutex);
3797
3798 dev = wl->current_dev;
3799
3800 /* Switch the band (if necessary). This might change the active core. */
3801 err = b43_switch_band(wl, conf->channel);
3802 if (err)
3803 goto out_unlock_mutex;
3804
3805 /* Need to reload all settings if the core changed */
3806 if (dev != wl->current_dev) {
3807 dev = wl->current_dev;
3808 changed = ~0;
3809 reload_bss = true;
3810 }
3811
3812 phy = &dev->phy;
3813
3814 if (conf_is_ht(conf))
3815 phy->is_40mhz =
3816 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3817 else
3818 phy->is_40mhz = false;
3819
3820 b43_mac_suspend(dev);
3821
3822 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3823 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3824 conf->long_frame_max_tx_count);
3825 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3826 if (!changed)
3827 goto out_mac_enable;
3828
3829 /* Switch to the requested channel.
3830 * The firmware takes care of races with the TX handler. */
3831 if (conf->channel->hw_value != phy->channel)
3832 b43_switch_channel(dev, conf->channel->hw_value);
3833
3834 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3835
3836 /* Adjust the desired TX power level. */
3837 if (conf->power_level != 0) {
3838 if (conf->power_level != phy->desired_txpower) {
3839 phy->desired_txpower = conf->power_level;
3840 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3841 B43_TXPWR_IGNORE_TSSI);
3842 }
3843 }
3844
3845 /* Antennas for RX and management frame TX. */
3846 antenna = B43_ANTENNA_DEFAULT;
3847 b43_mgmtframe_txantenna(dev, antenna);
3848 antenna = B43_ANTENNA_DEFAULT;
3849 if (phy->ops->set_rx_antenna)
3850 phy->ops->set_rx_antenna(dev, antenna);
3851
3852 if (wl->radio_enabled != phy->radio_on) {
3853 if (wl->radio_enabled) {
3854 b43_software_rfkill(dev, false);
3855 b43info(dev->wl, "Radio turned on by software\n");
3856 if (!dev->radio_hw_enable) {
3857 b43info(dev->wl, "The hardware RF-kill button "
3858 "still turns the radio physically off. "
3859 "Press the button to turn it on.\n");
3860 }
3861 } else {
3862 b43_software_rfkill(dev, true);
3863 b43info(dev->wl, "Radio turned off by software\n");
3864 }
3865 }
3866
3867 out_mac_enable:
3868 b43_mac_enable(dev);
3869 out_unlock_mutex:
3870 mutex_unlock(&wl->mutex);
3871
3872 if (wl->vif && reload_bss)
3873 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3874
3875 return err;
3876 }
3877
3878 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3879 {
3880 struct ieee80211_supported_band *sband =
3881 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3882 struct ieee80211_rate *rate;
3883 int i;
3884 u16 basic, direct, offset, basic_offset, rateptr;
3885
3886 for (i = 0; i < sband->n_bitrates; i++) {
3887 rate = &sband->bitrates[i];
3888
3889 if (b43_is_cck_rate(rate->hw_value)) {
3890 direct = B43_SHM_SH_CCKDIRECT;
3891 basic = B43_SHM_SH_CCKBASIC;
3892 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3893 offset &= 0xF;
3894 } else {
3895 direct = B43_SHM_SH_OFDMDIRECT;
3896 basic = B43_SHM_SH_OFDMBASIC;
3897 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3898 offset &= 0xF;
3899 }
3900
3901 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3902
3903 if (b43_is_cck_rate(rate->hw_value)) {
3904 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3905 basic_offset &= 0xF;
3906 } else {
3907 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3908 basic_offset &= 0xF;
3909 }
3910
3911 /*
3912 * Get the pointer that we need to point to
3913 * from the direct map
3914 */
3915 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3916 direct + 2 * basic_offset);
3917 /* and write it to the basic map */
3918 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3919 rateptr);
3920 }
3921 }
3922
3923 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3924 struct ieee80211_vif *vif,
3925 struct ieee80211_bss_conf *conf,
3926 u32 changed)
3927 {
3928 struct b43_wl *wl = hw_to_b43_wl(hw);
3929 struct b43_wldev *dev;
3930
3931 mutex_lock(&wl->mutex);
3932
3933 dev = wl->current_dev;
3934 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3935 goto out_unlock_mutex;
3936
3937 B43_WARN_ON(wl->vif != vif);
3938
3939 if (changed & BSS_CHANGED_BSSID) {
3940 if (conf->bssid)
3941 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3942 else
3943 memset(wl->bssid, 0, ETH_ALEN);
3944 }
3945
3946 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3947 if (changed & BSS_CHANGED_BEACON &&
3948 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3949 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3950 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3951 b43_update_templates(wl);
3952
3953 if (changed & BSS_CHANGED_BSSID)
3954 b43_write_mac_bssid_templates(dev);
3955 }
3956
3957 b43_mac_suspend(dev);
3958
3959 /* Update templates for AP/mesh mode. */
3960 if (changed & BSS_CHANGED_BEACON_INT &&
3961 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3962 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3963 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3964 conf->beacon_int)
3965 b43_set_beacon_int(dev, conf->beacon_int);
3966
3967 if (changed & BSS_CHANGED_BASIC_RATES)
3968 b43_update_basic_rates(dev, conf->basic_rates);
3969
3970 if (changed & BSS_CHANGED_ERP_SLOT) {
3971 if (conf->use_short_slot)
3972 b43_short_slot_timing_enable(dev);
3973 else
3974 b43_short_slot_timing_disable(dev);
3975 }
3976
3977 b43_mac_enable(dev);
3978 out_unlock_mutex:
3979 mutex_unlock(&wl->mutex);
3980 }
3981
3982 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3983 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3984 struct ieee80211_key_conf *key)
3985 {
3986 struct b43_wl *wl = hw_to_b43_wl(hw);
3987 struct b43_wldev *dev;
3988 u8 algorithm;
3989 u8 index;
3990 int err;
3991 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3992
3993 if (modparam_nohwcrypt)
3994 return -ENOSPC; /* User disabled HW-crypto */
3995
3996 mutex_lock(&wl->mutex);
3997
3998 dev = wl->current_dev;
3999 err = -ENODEV;
4000 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4001 goto out_unlock;
4002
4003 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4004 /* We don't have firmware for the crypto engine.
4005 * Must use software-crypto. */
4006 err = -EOPNOTSUPP;
4007 goto out_unlock;
4008 }
4009
4010 err = -EINVAL;
4011 switch (key->cipher) {
4012 case WLAN_CIPHER_SUITE_WEP40:
4013 algorithm = B43_SEC_ALGO_WEP40;
4014 break;
4015 case WLAN_CIPHER_SUITE_WEP104:
4016 algorithm = B43_SEC_ALGO_WEP104;
4017 break;
4018 case WLAN_CIPHER_SUITE_TKIP:
4019 algorithm = B43_SEC_ALGO_TKIP;
4020 break;
4021 case WLAN_CIPHER_SUITE_CCMP:
4022 algorithm = B43_SEC_ALGO_AES;
4023 break;
4024 default:
4025 B43_WARN_ON(1);
4026 goto out_unlock;
4027 }
4028 index = (u8) (key->keyidx);
4029 if (index > 3)
4030 goto out_unlock;
4031
4032 switch (cmd) {
4033 case SET_KEY:
4034 if (algorithm == B43_SEC_ALGO_TKIP &&
4035 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4036 !modparam_hwtkip)) {
4037 /* We support only pairwise key */
4038 err = -EOPNOTSUPP;
4039 goto out_unlock;
4040 }
4041
4042 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4043 if (WARN_ON(!sta)) {
4044 err = -EOPNOTSUPP;
4045 goto out_unlock;
4046 }
4047 /* Pairwise key with an assigned MAC address. */
4048 err = b43_key_write(dev, -1, algorithm,
4049 key->key, key->keylen,
4050 sta->addr, key);
4051 } else {
4052 /* Group key */
4053 err = b43_key_write(dev, index, algorithm,
4054 key->key, key->keylen, NULL, key);
4055 }
4056 if (err)
4057 goto out_unlock;
4058
4059 if (algorithm == B43_SEC_ALGO_WEP40 ||
4060 algorithm == B43_SEC_ALGO_WEP104) {
4061 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4062 } else {
4063 b43_hf_write(dev,
4064 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4065 }
4066 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4067 if (algorithm == B43_SEC_ALGO_TKIP)
4068 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4069 break;
4070 case DISABLE_KEY: {
4071 err = b43_key_clear(dev, key->hw_key_idx);
4072 if (err)
4073 goto out_unlock;
4074 break;
4075 }
4076 default:
4077 B43_WARN_ON(1);
4078 }
4079
4080 out_unlock:
4081 if (!err) {
4082 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4083 "mac: %pM\n",
4084 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4085 sta ? sta->addr : bcast_addr);
4086 b43_dump_keymemory(dev);
4087 }
4088 mutex_unlock(&wl->mutex);
4089
4090 return err;
4091 }
4092
4093 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4094 unsigned int changed, unsigned int *fflags,
4095 u64 multicast)
4096 {
4097 struct b43_wl *wl = hw_to_b43_wl(hw);
4098 struct b43_wldev *dev;
4099
4100 mutex_lock(&wl->mutex);
4101 dev = wl->current_dev;
4102 if (!dev) {
4103 *fflags = 0;
4104 goto out_unlock;
4105 }
4106
4107 *fflags &= FIF_PROMISC_IN_BSS |
4108 FIF_ALLMULTI |
4109 FIF_FCSFAIL |
4110 FIF_PLCPFAIL |
4111 FIF_CONTROL |
4112 FIF_OTHER_BSS |
4113 FIF_BCN_PRBRESP_PROMISC;
4114
4115 changed &= FIF_PROMISC_IN_BSS |
4116 FIF_ALLMULTI |
4117 FIF_FCSFAIL |
4118 FIF_PLCPFAIL |
4119 FIF_CONTROL |
4120 FIF_OTHER_BSS |
4121 FIF_BCN_PRBRESP_PROMISC;
4122
4123 wl->filter_flags = *fflags;
4124
4125 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4126 b43_adjust_opmode(dev);
4127
4128 out_unlock:
4129 mutex_unlock(&wl->mutex);
4130 }
4131
4132 /* Locking: wl->mutex
4133 * Returns the current dev. This might be different from the passed in dev,
4134 * because the core might be gone away while we unlocked the mutex. */
4135 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4136 {
4137 struct b43_wl *wl;
4138 struct b43_wldev *orig_dev;
4139 u32 mask;
4140
4141 if (!dev)
4142 return NULL;
4143 wl = dev->wl;
4144 redo:
4145 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4146 return dev;
4147
4148 /* Cancel work. Unlock to avoid deadlocks. */
4149 mutex_unlock(&wl->mutex);
4150 cancel_delayed_work_sync(&dev->periodic_work);
4151 cancel_work_sync(&wl->tx_work);
4152 mutex_lock(&wl->mutex);
4153 dev = wl->current_dev;
4154 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4155 /* Whoops, aliens ate up the device while we were unlocked. */
4156 return dev;
4157 }
4158
4159 /* Disable interrupts on the device. */
4160 b43_set_status(dev, B43_STAT_INITIALIZED);
4161 if (b43_bus_host_is_sdio(dev->dev)) {
4162 /* wl->mutex is locked. That is enough. */
4163 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4164 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4165 } else {
4166 spin_lock_irq(&wl->hardirq_lock);
4167 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4168 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4169 spin_unlock_irq(&wl->hardirq_lock);
4170 }
4171 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4172 orig_dev = dev;
4173 mutex_unlock(&wl->mutex);
4174 if (b43_bus_host_is_sdio(dev->dev)) {
4175 b43_sdio_free_irq(dev);
4176 } else {
4177 synchronize_irq(dev->dev->irq);
4178 free_irq(dev->dev->irq, dev);
4179 }
4180 mutex_lock(&wl->mutex);
4181 dev = wl->current_dev;
4182 if (!dev)
4183 return dev;
4184 if (dev != orig_dev) {
4185 if (b43_status(dev) >= B43_STAT_STARTED)
4186 goto redo;
4187 return dev;
4188 }
4189 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4190 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4191
4192 /* Drain the TX queue */
4193 while (skb_queue_len(&wl->tx_queue))
4194 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
4195
4196 b43_mac_suspend(dev);
4197 b43_leds_exit(dev);
4198 b43dbg(wl, "Wireless interface stopped\n");
4199
4200 return dev;
4201 }
4202
4203 /* Locking: wl->mutex */
4204 static int b43_wireless_core_start(struct b43_wldev *dev)
4205 {
4206 int err;
4207
4208 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4209
4210 drain_txstatus_queue(dev);
4211 if (b43_bus_host_is_sdio(dev->dev)) {
4212 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4213 if (err) {
4214 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4215 goto out;
4216 }
4217 } else {
4218 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4219 b43_interrupt_thread_handler,
4220 IRQF_SHARED, KBUILD_MODNAME, dev);
4221 if (err) {
4222 b43err(dev->wl, "Cannot request IRQ-%d\n",
4223 dev->dev->irq);
4224 goto out;
4225 }
4226 }
4227
4228 /* We are ready to run. */
4229 ieee80211_wake_queues(dev->wl->hw);
4230 b43_set_status(dev, B43_STAT_STARTED);
4231
4232 /* Start data flow (TX/RX). */
4233 b43_mac_enable(dev);
4234 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4235
4236 /* Start maintenance work */
4237 b43_periodic_tasks_setup(dev);
4238
4239 b43_leds_init(dev);
4240
4241 b43dbg(dev->wl, "Wireless interface started\n");
4242 out:
4243 return err;
4244 }
4245
4246 /* Get PHY and RADIO versioning numbers */
4247 static int b43_phy_versioning(struct b43_wldev *dev)
4248 {
4249 struct b43_phy *phy = &dev->phy;
4250 u32 tmp;
4251 u8 analog_type;
4252 u8 phy_type;
4253 u8 phy_rev;
4254 u16 radio_manuf;
4255 u16 radio_ver;
4256 u16 radio_rev;
4257 int unsupported = 0;
4258
4259 /* Get PHY versioning */
4260 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4261 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4262 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4263 phy_rev = (tmp & B43_PHYVER_VERSION);
4264 switch (phy_type) {
4265 case B43_PHYTYPE_A:
4266 if (phy_rev >= 4)
4267 unsupported = 1;
4268 break;
4269 case B43_PHYTYPE_B:
4270 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4271 && phy_rev != 7)
4272 unsupported = 1;
4273 break;
4274 case B43_PHYTYPE_G:
4275 if (phy_rev > 9)
4276 unsupported = 1;
4277 break;
4278 #ifdef CONFIG_B43_PHY_N
4279 case B43_PHYTYPE_N:
4280 if (phy_rev > 9)
4281 unsupported = 1;
4282 break;
4283 #endif
4284 #ifdef CONFIG_B43_PHY_LP
4285 case B43_PHYTYPE_LP:
4286 if (phy_rev > 2)
4287 unsupported = 1;
4288 break;
4289 #endif
4290 #ifdef CONFIG_B43_PHY_HT
4291 case B43_PHYTYPE_HT:
4292 if (phy_rev > 1)
4293 unsupported = 1;
4294 break;
4295 #endif
4296 #ifdef CONFIG_B43_PHY_LCN
4297 case B43_PHYTYPE_LCN:
4298 if (phy_rev > 1)
4299 unsupported = 1;
4300 break;
4301 #endif
4302 default:
4303 unsupported = 1;
4304 }
4305 if (unsupported) {
4306 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4307 "(Analog %u, Type %u, Revision %u)\n",
4308 analog_type, phy_type, phy_rev);
4309 return -EOPNOTSUPP;
4310 }
4311 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4312 analog_type, phy_type, phy_rev);
4313
4314 /* Get RADIO versioning */
4315 if (dev->dev->core_rev >= 24) {
4316 u16 radio24[3];
4317
4318 for (tmp = 0; tmp < 3; tmp++) {
4319 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4320 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4321 }
4322
4323 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4324 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4325
4326 radio_manuf = 0x17F;
4327 radio_ver = (radio24[2] << 8) | radio24[1];
4328 radio_rev = (radio24[0] & 0xF);
4329 } else {
4330 if (dev->dev->chip_id == 0x4317) {
4331 if (dev->dev->chip_rev == 0)
4332 tmp = 0x3205017F;
4333 else if (dev->dev->chip_rev == 1)
4334 tmp = 0x4205017F;
4335 else
4336 tmp = 0x5205017F;
4337 } else {
4338 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4339 B43_RADIOCTL_ID);
4340 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4341 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4342 B43_RADIOCTL_ID);
4343 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4344 << 16;
4345 }
4346 radio_manuf = (tmp & 0x00000FFF);
4347 radio_ver = (tmp & 0x0FFFF000) >> 12;
4348 radio_rev = (tmp & 0xF0000000) >> 28;
4349 }
4350
4351 if (radio_manuf != 0x17F /* Broadcom */)
4352 unsupported = 1;
4353 switch (phy_type) {
4354 case B43_PHYTYPE_A:
4355 if (radio_ver != 0x2060)
4356 unsupported = 1;
4357 if (radio_rev != 1)
4358 unsupported = 1;
4359 if (radio_manuf != 0x17F)
4360 unsupported = 1;
4361 break;
4362 case B43_PHYTYPE_B:
4363 if ((radio_ver & 0xFFF0) != 0x2050)
4364 unsupported = 1;
4365 break;
4366 case B43_PHYTYPE_G:
4367 if (radio_ver != 0x2050)
4368 unsupported = 1;
4369 break;
4370 case B43_PHYTYPE_N:
4371 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4372 unsupported = 1;
4373 break;
4374 case B43_PHYTYPE_LP:
4375 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4376 unsupported = 1;
4377 break;
4378 case B43_PHYTYPE_HT:
4379 if (radio_ver != 0x2059)
4380 unsupported = 1;
4381 break;
4382 case B43_PHYTYPE_LCN:
4383 if (radio_ver != 0x2064)
4384 unsupported = 1;
4385 break;
4386 default:
4387 B43_WARN_ON(1);
4388 }
4389 if (unsupported) {
4390 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4391 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4392 radio_manuf, radio_ver, radio_rev);
4393 return -EOPNOTSUPP;
4394 }
4395 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4396 radio_manuf, radio_ver, radio_rev);
4397
4398 phy->radio_manuf = radio_manuf;
4399 phy->radio_ver = radio_ver;
4400 phy->radio_rev = radio_rev;
4401
4402 phy->analog = analog_type;
4403 phy->type = phy_type;
4404 phy->rev = phy_rev;
4405
4406 return 0;
4407 }
4408
4409 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4410 struct b43_phy *phy)
4411 {
4412 phy->hardware_power_control = !!modparam_hwpctl;
4413 phy->next_txpwr_check_time = jiffies;
4414 /* PHY TX errors counter. */
4415 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4416
4417 #if B43_DEBUG
4418 phy->phy_locked = 0;
4419 phy->radio_locked = 0;
4420 #endif
4421 }
4422
4423 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4424 {
4425 dev->dfq_valid = 0;
4426
4427 /* Assume the radio is enabled. If it's not enabled, the state will
4428 * immediately get fixed on the first periodic work run. */
4429 dev->radio_hw_enable = 1;
4430
4431 /* Stats */
4432 memset(&dev->stats, 0, sizeof(dev->stats));
4433
4434 setup_struct_phy_for_init(dev, &dev->phy);
4435
4436 /* IRQ related flags */
4437 dev->irq_reason = 0;
4438 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4439 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4440 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4441 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4442
4443 dev->mac_suspended = 1;
4444
4445 /* Noise calculation context */
4446 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4447 }
4448
4449 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4450 {
4451 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4452 u64 hf;
4453
4454 if (!modparam_btcoex)
4455 return;
4456 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4457 return;
4458 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4459 return;
4460
4461 hf = b43_hf_read(dev);
4462 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4463 hf |= B43_HF_BTCOEXALT;
4464 else
4465 hf |= B43_HF_BTCOEX;
4466 b43_hf_write(dev, hf);
4467 }
4468
4469 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4470 {
4471 if (!modparam_btcoex)
4472 return;
4473 //TODO
4474 }
4475
4476 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4477 {
4478 struct ssb_bus *bus;
4479 u32 tmp;
4480
4481 if (dev->dev->bus_type != B43_BUS_SSB)
4482 return;
4483
4484 bus = dev->dev->sdev->bus;
4485
4486 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4487 (bus->chip_id == 0x4312)) {
4488 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4489 tmp &= ~SSB_IMCFGLO_REQTO;
4490 tmp &= ~SSB_IMCFGLO_SERTO;
4491 tmp |= 0x3;
4492 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4493 ssb_commit_settings(bus);
4494 }
4495 }
4496
4497 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4498 {
4499 u16 pu_delay;
4500
4501 /* The time value is in microseconds. */
4502 if (dev->phy.type == B43_PHYTYPE_A)
4503 pu_delay = 3700;
4504 else
4505 pu_delay = 1050;
4506 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4507 pu_delay = 500;
4508 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4509 pu_delay = max(pu_delay, (u16)2400);
4510
4511 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4512 }
4513
4514 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4515 static void b43_set_pretbtt(struct b43_wldev *dev)
4516 {
4517 u16 pretbtt;
4518
4519 /* The time value is in microseconds. */
4520 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4521 pretbtt = 2;
4522 } else {
4523 if (dev->phy.type == B43_PHYTYPE_A)
4524 pretbtt = 120;
4525 else
4526 pretbtt = 250;
4527 }
4528 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4529 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4530 }
4531
4532 /* Shutdown a wireless core */
4533 /* Locking: wl->mutex */
4534 static void b43_wireless_core_exit(struct b43_wldev *dev)
4535 {
4536 u32 macctl;
4537
4538 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4539 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4540 return;
4541
4542 /* Unregister HW RNG driver */
4543 b43_rng_exit(dev->wl);
4544
4545 b43_set_status(dev, B43_STAT_UNINIT);
4546
4547 /* Stop the microcode PSM. */
4548 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4549 macctl &= ~B43_MACCTL_PSM_RUN;
4550 macctl |= B43_MACCTL_PSM_JMP0;
4551 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4552
4553 b43_dma_free(dev);
4554 b43_pio_free(dev);
4555 b43_chip_exit(dev);
4556 dev->phy.ops->switch_analog(dev, 0);
4557 if (dev->wl->current_beacon) {
4558 dev_kfree_skb_any(dev->wl->current_beacon);
4559 dev->wl->current_beacon = NULL;
4560 }
4561
4562 b43_device_disable(dev, 0);
4563 b43_bus_may_powerdown(dev);
4564 }
4565
4566 /* Initialize a wireless core */
4567 static int b43_wireless_core_init(struct b43_wldev *dev)
4568 {
4569 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4570 struct b43_phy *phy = &dev->phy;
4571 int err;
4572 u64 hf;
4573
4574 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4575
4576 err = b43_bus_powerup(dev, 0);
4577 if (err)
4578 goto out;
4579 if (!b43_device_is_enabled(dev))
4580 b43_wireless_core_reset(dev, phy->gmode);
4581
4582 /* Reset all data structures. */
4583 setup_struct_wldev_for_init(dev);
4584 phy->ops->prepare_structs(dev);
4585
4586 /* Enable IRQ routing to this device. */
4587 switch (dev->dev->bus_type) {
4588 #ifdef CONFIG_B43_BCMA
4589 case B43_BUS_BCMA:
4590 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4591 dev->dev->bdev, true);
4592 break;
4593 #endif
4594 #ifdef CONFIG_B43_SSB
4595 case B43_BUS_SSB:
4596 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4597 dev->dev->sdev);
4598 break;
4599 #endif
4600 }
4601
4602 b43_imcfglo_timeouts_workaround(dev);
4603 b43_bluetooth_coext_disable(dev);
4604 if (phy->ops->prepare_hardware) {
4605 err = phy->ops->prepare_hardware(dev);
4606 if (err)
4607 goto err_busdown;
4608 }
4609 err = b43_chip_init(dev);
4610 if (err)
4611 goto err_busdown;
4612 b43_shm_write16(dev, B43_SHM_SHARED,
4613 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4614 hf = b43_hf_read(dev);
4615 if (phy->type == B43_PHYTYPE_G) {
4616 hf |= B43_HF_SYMW;
4617 if (phy->rev == 1)
4618 hf |= B43_HF_GDCW;
4619 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4620 hf |= B43_HF_OFDMPABOOST;
4621 }
4622 if (phy->radio_ver == 0x2050) {
4623 if (phy->radio_rev == 6)
4624 hf |= B43_HF_4318TSSI;
4625 if (phy->radio_rev < 6)
4626 hf |= B43_HF_VCORECALC;
4627 }
4628 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4629 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4630 #ifdef CONFIG_SSB_DRIVER_PCICORE
4631 if (dev->dev->bus_type == B43_BUS_SSB &&
4632 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4633 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4634 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4635 #endif
4636 hf &= ~B43_HF_SKCFPUP;
4637 b43_hf_write(dev, hf);
4638
4639 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4640 B43_DEFAULT_LONG_RETRY_LIMIT);
4641 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4642 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4643
4644 /* Disable sending probe responses from firmware.
4645 * Setting the MaxTime to one usec will always trigger
4646 * a timeout, so we never send any probe resp.
4647 * A timeout of zero is infinite. */
4648 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4649
4650 b43_rate_memory_init(dev);
4651 b43_set_phytxctl_defaults(dev);
4652
4653 /* Minimum Contention Window */
4654 if (phy->type == B43_PHYTYPE_B)
4655 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4656 else
4657 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4658 /* Maximum Contention Window */
4659 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4660
4661 if (b43_bus_host_is_pcmcia(dev->dev) ||
4662 b43_bus_host_is_sdio(dev->dev)) {
4663 dev->__using_pio_transfers = 1;
4664 err = b43_pio_init(dev);
4665 } else if (dev->use_pio) {
4666 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4667 "This should not be needed and will result in lower "
4668 "performance.\n");
4669 dev->__using_pio_transfers = 1;
4670 err = b43_pio_init(dev);
4671 } else {
4672 dev->__using_pio_transfers = 0;
4673 err = b43_dma_init(dev);
4674 }
4675 if (err)
4676 goto err_chip_exit;
4677 b43_qos_init(dev);
4678 b43_set_synth_pu_delay(dev, 1);
4679 b43_bluetooth_coext_enable(dev);
4680
4681 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4682 b43_upload_card_macaddress(dev);
4683 b43_security_init(dev);
4684
4685 ieee80211_wake_queues(dev->wl->hw);
4686
4687 b43_set_status(dev, B43_STAT_INITIALIZED);
4688
4689 /* Register HW RNG driver */
4690 b43_rng_init(dev->wl);
4691
4692 out:
4693 return err;
4694
4695 err_chip_exit:
4696 b43_chip_exit(dev);
4697 err_busdown:
4698 b43_bus_may_powerdown(dev);
4699 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4700 return err;
4701 }
4702
4703 static int b43_op_add_interface(struct ieee80211_hw *hw,
4704 struct ieee80211_vif *vif)
4705 {
4706 struct b43_wl *wl = hw_to_b43_wl(hw);
4707 struct b43_wldev *dev;
4708 int err = -EOPNOTSUPP;
4709
4710 /* TODO: allow WDS/AP devices to coexist */
4711
4712 if (vif->type != NL80211_IFTYPE_AP &&
4713 vif->type != NL80211_IFTYPE_MESH_POINT &&
4714 vif->type != NL80211_IFTYPE_STATION &&
4715 vif->type != NL80211_IFTYPE_WDS &&
4716 vif->type != NL80211_IFTYPE_ADHOC)
4717 return -EOPNOTSUPP;
4718
4719 mutex_lock(&wl->mutex);
4720 if (wl->operating)
4721 goto out_mutex_unlock;
4722
4723 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4724
4725 dev = wl->current_dev;
4726 wl->operating = 1;
4727 wl->vif = vif;
4728 wl->if_type = vif->type;
4729 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4730
4731 b43_adjust_opmode(dev);
4732 b43_set_pretbtt(dev);
4733 b43_set_synth_pu_delay(dev, 0);
4734 b43_upload_card_macaddress(dev);
4735
4736 err = 0;
4737 out_mutex_unlock:
4738 mutex_unlock(&wl->mutex);
4739
4740 if (err == 0)
4741 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4742
4743 return err;
4744 }
4745
4746 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4747 struct ieee80211_vif *vif)
4748 {
4749 struct b43_wl *wl = hw_to_b43_wl(hw);
4750 struct b43_wldev *dev = wl->current_dev;
4751
4752 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4753
4754 mutex_lock(&wl->mutex);
4755
4756 B43_WARN_ON(!wl->operating);
4757 B43_WARN_ON(wl->vif != vif);
4758 wl->vif = NULL;
4759
4760 wl->operating = 0;
4761
4762 b43_adjust_opmode(dev);
4763 memset(wl->mac_addr, 0, ETH_ALEN);
4764 b43_upload_card_macaddress(dev);
4765
4766 mutex_unlock(&wl->mutex);
4767 }
4768
4769 static int b43_op_start(struct ieee80211_hw *hw)
4770 {
4771 struct b43_wl *wl = hw_to_b43_wl(hw);
4772 struct b43_wldev *dev = wl->current_dev;
4773 int did_init = 0;
4774 int err = 0;
4775
4776 /* Kill all old instance specific information to make sure
4777 * the card won't use it in the short timeframe between start
4778 * and mac80211 reconfiguring it. */
4779 memset(wl->bssid, 0, ETH_ALEN);
4780 memset(wl->mac_addr, 0, ETH_ALEN);
4781 wl->filter_flags = 0;
4782 wl->radiotap_enabled = 0;
4783 b43_qos_clear(wl);
4784 wl->beacon0_uploaded = 0;
4785 wl->beacon1_uploaded = 0;
4786 wl->beacon_templates_virgin = 1;
4787 wl->radio_enabled = 1;
4788
4789 mutex_lock(&wl->mutex);
4790
4791 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4792 err = b43_wireless_core_init(dev);
4793 if (err)
4794 goto out_mutex_unlock;
4795 did_init = 1;
4796 }
4797
4798 if (b43_status(dev) < B43_STAT_STARTED) {
4799 err = b43_wireless_core_start(dev);
4800 if (err) {
4801 if (did_init)
4802 b43_wireless_core_exit(dev);
4803 goto out_mutex_unlock;
4804 }
4805 }
4806
4807 /* XXX: only do if device doesn't support rfkill irq */
4808 wiphy_rfkill_start_polling(hw->wiphy);
4809
4810 out_mutex_unlock:
4811 mutex_unlock(&wl->mutex);
4812
4813 /* reload configuration */
4814 b43_op_config(hw, ~0);
4815
4816 return err;
4817 }
4818
4819 static void b43_op_stop(struct ieee80211_hw *hw)
4820 {
4821 struct b43_wl *wl = hw_to_b43_wl(hw);
4822 struct b43_wldev *dev = wl->current_dev;
4823
4824 cancel_work_sync(&(wl->beacon_update_trigger));
4825
4826 mutex_lock(&wl->mutex);
4827 if (b43_status(dev) >= B43_STAT_STARTED) {
4828 dev = b43_wireless_core_stop(dev);
4829 if (!dev)
4830 goto out_unlock;
4831 }
4832 b43_wireless_core_exit(dev);
4833 wl->radio_enabled = 0;
4834
4835 out_unlock:
4836 mutex_unlock(&wl->mutex);
4837
4838 cancel_work_sync(&(wl->txpower_adjust_work));
4839 }
4840
4841 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4842 struct ieee80211_sta *sta, bool set)
4843 {
4844 struct b43_wl *wl = hw_to_b43_wl(hw);
4845
4846 /* FIXME: add locking */
4847 b43_update_templates(wl);
4848
4849 return 0;
4850 }
4851
4852 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4853 struct ieee80211_vif *vif,
4854 enum sta_notify_cmd notify_cmd,
4855 struct ieee80211_sta *sta)
4856 {
4857 struct b43_wl *wl = hw_to_b43_wl(hw);
4858
4859 B43_WARN_ON(!vif || wl->vif != vif);
4860 }
4861
4862 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4863 {
4864 struct b43_wl *wl = hw_to_b43_wl(hw);
4865 struct b43_wldev *dev;
4866
4867 mutex_lock(&wl->mutex);
4868 dev = wl->current_dev;
4869 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4870 /* Disable CFP update during scan on other channels. */
4871 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4872 }
4873 mutex_unlock(&wl->mutex);
4874 }
4875
4876 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4877 {
4878 struct b43_wl *wl = hw_to_b43_wl(hw);
4879 struct b43_wldev *dev;
4880
4881 mutex_lock(&wl->mutex);
4882 dev = wl->current_dev;
4883 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4884 /* Re-enable CFP update. */
4885 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4886 }
4887 mutex_unlock(&wl->mutex);
4888 }
4889
4890 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4891 struct survey_info *survey)
4892 {
4893 struct b43_wl *wl = hw_to_b43_wl(hw);
4894 struct b43_wldev *dev = wl->current_dev;
4895 struct ieee80211_conf *conf = &hw->conf;
4896
4897 if (idx != 0)
4898 return -ENOENT;
4899
4900 survey->channel = conf->channel;
4901 survey->filled = SURVEY_INFO_NOISE_DBM;
4902 survey->noise = dev->stats.link_noise;
4903
4904 return 0;
4905 }
4906
4907 static const struct ieee80211_ops b43_hw_ops = {
4908 .tx = b43_op_tx,
4909 .conf_tx = b43_op_conf_tx,
4910 .add_interface = b43_op_add_interface,
4911 .remove_interface = b43_op_remove_interface,
4912 .config = b43_op_config,
4913 .bss_info_changed = b43_op_bss_info_changed,
4914 .configure_filter = b43_op_configure_filter,
4915 .set_key = b43_op_set_key,
4916 .update_tkip_key = b43_op_update_tkip_key,
4917 .get_stats = b43_op_get_stats,
4918 .get_tsf = b43_op_get_tsf,
4919 .set_tsf = b43_op_set_tsf,
4920 .start = b43_op_start,
4921 .stop = b43_op_stop,
4922 .set_tim = b43_op_beacon_set_tim,
4923 .sta_notify = b43_op_sta_notify,
4924 .sw_scan_start = b43_op_sw_scan_start_notifier,
4925 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4926 .get_survey = b43_op_get_survey,
4927 .rfkill_poll = b43_rfkill_poll,
4928 };
4929
4930 /* Hard-reset the chip. Do not call this directly.
4931 * Use b43_controller_restart()
4932 */
4933 static void b43_chip_reset(struct work_struct *work)
4934 {
4935 struct b43_wldev *dev =
4936 container_of(work, struct b43_wldev, restart_work);
4937 struct b43_wl *wl = dev->wl;
4938 int err = 0;
4939 int prev_status;
4940
4941 mutex_lock(&wl->mutex);
4942
4943 prev_status = b43_status(dev);
4944 /* Bring the device down... */
4945 if (prev_status >= B43_STAT_STARTED) {
4946 dev = b43_wireless_core_stop(dev);
4947 if (!dev) {
4948 err = -ENODEV;
4949 goto out;
4950 }
4951 }
4952 if (prev_status >= B43_STAT_INITIALIZED)
4953 b43_wireless_core_exit(dev);
4954
4955 /* ...and up again. */
4956 if (prev_status >= B43_STAT_INITIALIZED) {
4957 err = b43_wireless_core_init(dev);
4958 if (err)
4959 goto out;
4960 }
4961 if (prev_status >= B43_STAT_STARTED) {
4962 err = b43_wireless_core_start(dev);
4963 if (err) {
4964 b43_wireless_core_exit(dev);
4965 goto out;
4966 }
4967 }
4968 out:
4969 if (err)
4970 wl->current_dev = NULL; /* Failed to init the dev. */
4971 mutex_unlock(&wl->mutex);
4972
4973 if (err) {
4974 b43err(wl, "Controller restart FAILED\n");
4975 return;
4976 }
4977
4978 /* reload configuration */
4979 b43_op_config(wl->hw, ~0);
4980 if (wl->vif)
4981 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
4982
4983 b43info(wl, "Controller restarted\n");
4984 }
4985
4986 static int b43_setup_bands(struct b43_wldev *dev,
4987 bool have_2ghz_phy, bool have_5ghz_phy)
4988 {
4989 struct ieee80211_hw *hw = dev->wl->hw;
4990
4991 if (have_2ghz_phy)
4992 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4993 if (dev->phy.type == B43_PHYTYPE_N) {
4994 if (have_5ghz_phy)
4995 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4996 } else {
4997 if (have_5ghz_phy)
4998 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4999 }
5000
5001 dev->phy.supports_2ghz = have_2ghz_phy;
5002 dev->phy.supports_5ghz = have_5ghz_phy;
5003
5004 return 0;
5005 }
5006
5007 static void b43_wireless_core_detach(struct b43_wldev *dev)
5008 {
5009 /* We release firmware that late to not be required to re-request
5010 * is all the time when we reinit the core. */
5011 b43_release_firmware(dev);
5012 b43_phy_free(dev);
5013 }
5014
5015 static int b43_wireless_core_attach(struct b43_wldev *dev)
5016 {
5017 struct b43_wl *wl = dev->wl;
5018 struct pci_dev *pdev = NULL;
5019 int err;
5020 u32 tmp;
5021 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
5022
5023 /* Do NOT do any device initialization here.
5024 * Do it in wireless_core_init() instead.
5025 * This function is for gathering basic information about the HW, only.
5026 * Also some structs may be set up here. But most likely you want to have
5027 * that in core_init(), too.
5028 */
5029
5030 #ifdef CONFIG_B43_SSB
5031 if (dev->dev->bus_type == B43_BUS_SSB &&
5032 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5033 pdev = dev->dev->sdev->bus->host_pci;
5034 #endif
5035
5036 err = b43_bus_powerup(dev, 0);
5037 if (err) {
5038 b43err(wl, "Bus powerup failed\n");
5039 goto out;
5040 }
5041
5042 /* Get the PHY type. */
5043 switch (dev->dev->bus_type) {
5044 #ifdef CONFIG_B43_BCMA
5045 case B43_BUS_BCMA:
5046 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5047 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5048 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5049 break;
5050 #endif
5051 #ifdef CONFIG_B43_SSB
5052 case B43_BUS_SSB:
5053 if (dev->dev->core_rev >= 5) {
5054 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5055 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5056 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5057 } else
5058 B43_WARN_ON(1);
5059 break;
5060 #endif
5061 }
5062
5063 dev->phy.gmode = have_2ghz_phy;
5064 dev->phy.radio_on = 1;
5065 b43_wireless_core_reset(dev, dev->phy.gmode);
5066
5067 err = b43_phy_versioning(dev);
5068 if (err)
5069 goto err_powerdown;
5070 /* Check if this device supports multiband. */
5071 if (!pdev ||
5072 (pdev->device != 0x4312 &&
5073 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5074 /* No multiband support. */
5075 have_2ghz_phy = 0;
5076 have_5ghz_phy = 0;
5077 switch (dev->phy.type) {
5078 case B43_PHYTYPE_A:
5079 have_5ghz_phy = 1;
5080 break;
5081 case B43_PHYTYPE_LP: //FIXME not always!
5082 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5083 have_5ghz_phy = 1;
5084 #endif
5085 case B43_PHYTYPE_G:
5086 case B43_PHYTYPE_N:
5087 case B43_PHYTYPE_HT:
5088 case B43_PHYTYPE_LCN:
5089 have_2ghz_phy = 1;
5090 break;
5091 default:
5092 B43_WARN_ON(1);
5093 }
5094 }
5095 if (dev->phy.type == B43_PHYTYPE_A) {
5096 /* FIXME */
5097 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5098 err = -EOPNOTSUPP;
5099 goto err_powerdown;
5100 }
5101 if (1 /* disable A-PHY */) {
5102 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5103 if (dev->phy.type != B43_PHYTYPE_N &&
5104 dev->phy.type != B43_PHYTYPE_LP) {
5105 have_2ghz_phy = 1;
5106 have_5ghz_phy = 0;
5107 }
5108 }
5109
5110 err = b43_phy_allocate(dev);
5111 if (err)
5112 goto err_powerdown;
5113
5114 dev->phy.gmode = have_2ghz_phy;
5115 b43_wireless_core_reset(dev, dev->phy.gmode);
5116
5117 err = b43_validate_chipaccess(dev);
5118 if (err)
5119 goto err_phy_free;
5120 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5121 if (err)
5122 goto err_phy_free;
5123
5124 /* Now set some default "current_dev" */
5125 if (!wl->current_dev)
5126 wl->current_dev = dev;
5127 INIT_WORK(&dev->restart_work, b43_chip_reset);
5128
5129 dev->phy.ops->switch_analog(dev, 0);
5130 b43_device_disable(dev, 0);
5131 b43_bus_may_powerdown(dev);
5132
5133 out:
5134 return err;
5135
5136 err_phy_free:
5137 b43_phy_free(dev);
5138 err_powerdown:
5139 b43_bus_may_powerdown(dev);
5140 return err;
5141 }
5142
5143 static void b43_one_core_detach(struct b43_bus_dev *dev)
5144 {
5145 struct b43_wldev *wldev;
5146 struct b43_wl *wl;
5147
5148 /* Do not cancel ieee80211-workqueue based work here.
5149 * See comment in b43_remove(). */
5150
5151 wldev = b43_bus_get_wldev(dev);
5152 wl = wldev->wl;
5153 b43_debugfs_remove_device(wldev);
5154 b43_wireless_core_detach(wldev);
5155 list_del(&wldev->list);
5156 wl->nr_devs--;
5157 b43_bus_set_wldev(dev, NULL);
5158 kfree(wldev);
5159 }
5160
5161 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5162 {
5163 struct b43_wldev *wldev;
5164 int err = -ENOMEM;
5165
5166 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5167 if (!wldev)
5168 goto out;
5169
5170 wldev->use_pio = b43_modparam_pio;
5171 wldev->dev = dev;
5172 wldev->wl = wl;
5173 b43_set_status(wldev, B43_STAT_UNINIT);
5174 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5175 INIT_LIST_HEAD(&wldev->list);
5176
5177 err = b43_wireless_core_attach(wldev);
5178 if (err)
5179 goto err_kfree_wldev;
5180
5181 list_add(&wldev->list, &wl->devlist);
5182 wl->nr_devs++;
5183 b43_bus_set_wldev(dev, wldev);
5184 b43_debugfs_add_device(wldev);
5185
5186 out:
5187 return err;
5188
5189 err_kfree_wldev:
5190 kfree(wldev);
5191 return err;
5192 }
5193
5194 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5195 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5196 (pdev->device == _device) && \
5197 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5198 (pdev->subsystem_device == _subdevice) )
5199
5200 static void b43_sprom_fixup(struct ssb_bus *bus)
5201 {
5202 struct pci_dev *pdev;
5203
5204 /* boardflags workarounds */
5205 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5206 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
5207 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5208 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5209 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
5210 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5211 if (bus->bustype == SSB_BUSTYPE_PCI) {
5212 pdev = bus->host_pci;
5213 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5214 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5215 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5216 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5217 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5218 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5219 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5220 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5221 }
5222 }
5223
5224 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5225 {
5226 struct ieee80211_hw *hw = wl->hw;
5227
5228 ssb_set_devtypedata(dev->sdev, NULL);
5229 ieee80211_free_hw(hw);
5230 }
5231
5232 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5233 {
5234 struct ssb_sprom *sprom = dev->bus_sprom;
5235 struct ieee80211_hw *hw;
5236 struct b43_wl *wl;
5237 char chip_name[6];
5238
5239 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5240 if (!hw) {
5241 b43err(NULL, "Could not allocate ieee80211 device\n");
5242 return ERR_PTR(-ENOMEM);
5243 }
5244 wl = hw_to_b43_wl(hw);
5245
5246 /* fill hw info */
5247 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5248 IEEE80211_HW_SIGNAL_DBM;
5249
5250 hw->wiphy->interface_modes =
5251 BIT(NL80211_IFTYPE_AP) |
5252 BIT(NL80211_IFTYPE_MESH_POINT) |
5253 BIT(NL80211_IFTYPE_STATION) |
5254 BIT(NL80211_IFTYPE_WDS) |
5255 BIT(NL80211_IFTYPE_ADHOC);
5256
5257 hw->queues = modparam_qos ? 4 : 1;
5258 wl->mac80211_initially_registered_queues = hw->queues;
5259 hw->max_rates = 2;
5260 SET_IEEE80211_DEV(hw, dev->dev);
5261 if (is_valid_ether_addr(sprom->et1mac))
5262 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5263 else
5264 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5265
5266 /* Initialize struct b43_wl */
5267 wl->hw = hw;
5268 mutex_init(&wl->mutex);
5269 spin_lock_init(&wl->hardirq_lock);
5270 INIT_LIST_HEAD(&wl->devlist);
5271 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5272 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5273 INIT_WORK(&wl->tx_work, b43_tx_work);
5274 skb_queue_head_init(&wl->tx_queue);
5275
5276 snprintf(chip_name, ARRAY_SIZE(chip_name),
5277 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5278 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5279 dev->core_rev);
5280 return wl;
5281 }
5282
5283 #ifdef CONFIG_B43_BCMA
5284 static int b43_bcma_probe(struct bcma_device *core)
5285 {
5286 struct b43_bus_dev *dev;
5287 struct b43_wl *wl;
5288 int err;
5289
5290 dev = b43_bus_dev_bcma_init(core);
5291 if (!dev)
5292 return -ENODEV;
5293
5294 wl = b43_wireless_init(dev);
5295 if (IS_ERR(wl)) {
5296 err = PTR_ERR(wl);
5297 goto bcma_out;
5298 }
5299
5300 err = b43_one_core_attach(dev, wl);
5301 if (err)
5302 goto bcma_err_wireless_exit;
5303
5304 err = ieee80211_register_hw(wl->hw);
5305 if (err)
5306 goto bcma_err_one_core_detach;
5307 b43_leds_register(wl->current_dev);
5308
5309 bcma_out:
5310 return err;
5311
5312 bcma_err_one_core_detach:
5313 b43_one_core_detach(dev);
5314 bcma_err_wireless_exit:
5315 ieee80211_free_hw(wl->hw);
5316 return err;
5317 }
5318
5319 static void b43_bcma_remove(struct bcma_device *core)
5320 {
5321 struct b43_wldev *wldev = bcma_get_drvdata(core);
5322 struct b43_wl *wl = wldev->wl;
5323
5324 /* We must cancel any work here before unregistering from ieee80211,
5325 * as the ieee80211 unreg will destroy the workqueue. */
5326 cancel_work_sync(&wldev->restart_work);
5327
5328 /* Restore the queues count before unregistering, because firmware detect
5329 * might have modified it. Restoring is important, so the networking
5330 * stack can properly free resources. */
5331 wl->hw->queues = wl->mac80211_initially_registered_queues;
5332 b43_leds_stop(wldev);
5333 ieee80211_unregister_hw(wl->hw);
5334
5335 b43_one_core_detach(wldev->dev);
5336
5337 b43_leds_unregister(wl);
5338
5339 ieee80211_free_hw(wl->hw);
5340 }
5341
5342 static struct bcma_driver b43_bcma_driver = {
5343 .name = KBUILD_MODNAME,
5344 .id_table = b43_bcma_tbl,
5345 .probe = b43_bcma_probe,
5346 .remove = b43_bcma_remove,
5347 };
5348 #endif
5349
5350 #ifdef CONFIG_B43_SSB
5351 static
5352 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5353 {
5354 struct b43_bus_dev *dev;
5355 struct b43_wl *wl;
5356 int err;
5357 int first = 0;
5358
5359 dev = b43_bus_dev_ssb_init(sdev);
5360 if (!dev)
5361 return -ENOMEM;
5362
5363 wl = ssb_get_devtypedata(sdev);
5364 if (!wl) {
5365 /* Probing the first core. Must setup common struct b43_wl */
5366 first = 1;
5367 b43_sprom_fixup(sdev->bus);
5368 wl = b43_wireless_init(dev);
5369 if (IS_ERR(wl)) {
5370 err = PTR_ERR(wl);
5371 goto out;
5372 }
5373 ssb_set_devtypedata(sdev, wl);
5374 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5375 }
5376 err = b43_one_core_attach(dev, wl);
5377 if (err)
5378 goto err_wireless_exit;
5379
5380 if (first) {
5381 err = ieee80211_register_hw(wl->hw);
5382 if (err)
5383 goto err_one_core_detach;
5384 b43_leds_register(wl->current_dev);
5385 }
5386
5387 out:
5388 return err;
5389
5390 err_one_core_detach:
5391 b43_one_core_detach(dev);
5392 err_wireless_exit:
5393 if (first)
5394 b43_wireless_exit(dev, wl);
5395 return err;
5396 }
5397
5398 static void b43_ssb_remove(struct ssb_device *sdev)
5399 {
5400 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5401 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5402 struct b43_bus_dev *dev = wldev->dev;
5403
5404 /* We must cancel any work here before unregistering from ieee80211,
5405 * as the ieee80211 unreg will destroy the workqueue. */
5406 cancel_work_sync(&wldev->restart_work);
5407
5408 B43_WARN_ON(!wl);
5409 if (wl->current_dev == wldev) {
5410 /* Restore the queues count before unregistering, because firmware detect
5411 * might have modified it. Restoring is important, so the networking
5412 * stack can properly free resources. */
5413 wl->hw->queues = wl->mac80211_initially_registered_queues;
5414 b43_leds_stop(wldev);
5415 ieee80211_unregister_hw(wl->hw);
5416 }
5417
5418 b43_one_core_detach(dev);
5419
5420 if (list_empty(&wl->devlist)) {
5421 b43_leds_unregister(wl);
5422 /* Last core on the chip unregistered.
5423 * We can destroy common struct b43_wl.
5424 */
5425 b43_wireless_exit(dev, wl);
5426 }
5427 }
5428
5429 static struct ssb_driver b43_ssb_driver = {
5430 .name = KBUILD_MODNAME,
5431 .id_table = b43_ssb_tbl,
5432 .probe = b43_ssb_probe,
5433 .remove = b43_ssb_remove,
5434 };
5435 #endif /* CONFIG_B43_SSB */
5436
5437 /* Perform a hardware reset. This can be called from any context. */
5438 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5439 {
5440 /* Must avoid requeueing, if we are in shutdown. */
5441 if (b43_status(dev) < B43_STAT_INITIALIZED)
5442 return;
5443 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5444 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5445 }
5446
5447 static void b43_print_driverinfo(void)
5448 {
5449 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5450 *feat_leds = "", *feat_sdio = "";
5451
5452 #ifdef CONFIG_B43_PCI_AUTOSELECT
5453 feat_pci = "P";
5454 #endif
5455 #ifdef CONFIG_B43_PCMCIA
5456 feat_pcmcia = "M";
5457 #endif
5458 #ifdef CONFIG_B43_PHY_N
5459 feat_nphy = "N";
5460 #endif
5461 #ifdef CONFIG_B43_LEDS
5462 feat_leds = "L";
5463 #endif
5464 #ifdef CONFIG_B43_SDIO
5465 feat_sdio = "S";
5466 #endif
5467 printk(KERN_INFO "Broadcom 43xx driver loaded "
5468 "[ Features: %s%s%s%s%s ]\n",
5469 feat_pci, feat_pcmcia, feat_nphy,
5470 feat_leds, feat_sdio);
5471 }
5472
5473 static int __init b43_init(void)
5474 {
5475 int err;
5476
5477 b43_debugfs_init();
5478 err = b43_pcmcia_init();
5479 if (err)
5480 goto err_dfs_exit;
5481 err = b43_sdio_init();
5482 if (err)
5483 goto err_pcmcia_exit;
5484 #ifdef CONFIG_B43_BCMA
5485 err = bcma_driver_register(&b43_bcma_driver);
5486 if (err)
5487 goto err_sdio_exit;
5488 #endif
5489 #ifdef CONFIG_B43_SSB
5490 err = ssb_driver_register(&b43_ssb_driver);
5491 if (err)
5492 goto err_bcma_driver_exit;
5493 #endif
5494 b43_print_driverinfo();
5495
5496 return err;
5497
5498 #ifdef CONFIG_B43_SSB
5499 err_bcma_driver_exit:
5500 #endif
5501 #ifdef CONFIG_B43_BCMA
5502 bcma_driver_unregister(&b43_bcma_driver);
5503 err_sdio_exit:
5504 #endif
5505 b43_sdio_exit();
5506 err_pcmcia_exit:
5507 b43_pcmcia_exit();
5508 err_dfs_exit:
5509 b43_debugfs_exit();
5510 return err;
5511 }
5512
5513 static void __exit b43_exit(void)
5514 {
5515 #ifdef CONFIG_B43_SSB
5516 ssb_driver_unregister(&b43_ssb_driver);
5517 #endif
5518 #ifdef CONFIG_B43_BCMA
5519 bcma_driver_unregister(&b43_bcma_driver);
5520 #endif
5521 b43_sdio_exit();
5522 b43_pcmcia_exit();
5523 b43_debugfs_exit();
5524 }
5525
5526 module_init(b43_init)
5527 module_exit(b43_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree