1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
33 #include <linux/sched.h>
34 #include <linux/firmware.h>
35 #include <linux/version.h>
36 #include <linux/etherdevice.h>
37 #include <linux/vmalloc.h>
38 #include <linux/usb.h>
39 #include <net/mac80211.h>
42 #define RF_CHANGE_BY_INIT 0
43 #define RF_CHANGE_BY_IPS BIT(28)
44 #define RF_CHANGE_BY_PS BIT(29)
45 #define RF_CHANGE_BY_HW BIT(30)
46 #define RF_CHANGE_BY_SW BIT(31)
48 #define IQK_ADDA_REG_NUM 16
49 #define IQK_MAC_REG_NUM 4
51 #define MAX_KEY_LEN 61
52 #define KEY_BUF_SIZE 5
55 /*aci: 0x00 Best Effort*/
56 /*aci: 0x01 Background*/
59 /*Max: define total number.*/
65 #define QOS_QUEUE_NUM 4
66 #define RTL_MAC80211_NUM_QUEUE 5
68 #define QBSS_LOAD_SIZE 5
69 #define MAX_WMMELE_LENGTH 64
71 /*slot time for 11g. */
72 #define RTL_SLOT_TIME_9 9
73 #define RTL_SLOT_TIME_20 20
75 /*related with tcp/ip. */
77 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
78 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
79 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
81 #define PROTOC_TYPE_SIZE 2
83 /*related with 802.11 frame*/
84 #define MAC80211_3ADDR_LEN 24
85 #define MAC80211_4ADDR_LEN 30
87 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
88 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
89 #define MAX_PG_GROUP 13
90 #define CHANNEL_GROUP_MAX_2G 3
91 #define CHANNEL_GROUP_IDX_5GL 3
92 #define CHANNEL_GROUP_IDX_5GM 6
93 #define CHANNEL_GROUP_IDX_5GH 9
94 #define CHANNEL_GROUP_MAX_5G 9
95 #define CHANNEL_MAX_NUMBER_2G 14
96 #define AVG_THERMAL_NUM 8
112 enum rt_eeprom_type
{
119 RTL_STATUS_INTERFACE_START
= 0,
123 HARDWARE_TYPE_RTL8192E
,
124 HARDWARE_TYPE_RTL8192U
,
125 HARDWARE_TYPE_RTL8192SE
,
126 HARDWARE_TYPE_RTL8192SU
,
127 HARDWARE_TYPE_RTL8192CE
,
128 HARDWARE_TYPE_RTL8192CU
,
129 HARDWARE_TYPE_RTL8192DE
,
130 HARDWARE_TYPE_RTL8192DU
,
131 HARDWARE_TYPE_RTL8723E
,
132 HARDWARE_TYPE_RTL8723U
,
138 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
139 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
140 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
141 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
142 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
143 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
144 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
145 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
146 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
147 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
148 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
149 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
150 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
151 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
152 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
153 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
154 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
155 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
156 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
157 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
158 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
159 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
160 #define IS_HARDWARE_TYPE_8723(rtlhal) \
161 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
163 enum scan_operation_backup_opt
{
186 u32 rfswitch_control
;
189 u32 rfrxiq_imbalance
;
191 u32 rftxiq_imbalance
;
194 u32 rflssi_readbackpi
;
198 IO_CMD_PAUSE_DM_BY_SCAN
= 0,
199 IO_CMD_RESUME_DM_BY_SCAN
= 1,
204 HW_VAR_MULTICAST_REG
,
208 HW_VAR_SECURITY_CONF
,
209 HW_VAR_BEACON_INTERVAL
,
211 HW_VAR_LISTEN_INTERVAL
,
224 HW_VAR_RATE_FALLBACK_CONTROL
,
225 HW_VAR_CONTENTION_WINDOW
,
230 HW_VAR_AMPDU_MIN_SPACE
,
231 HW_VAR_SHORTGI_DENSITY
,
233 HW_VAR_MCS_RATE_AVAILABLE
,
236 HW_VAR_DIS_Req_Qsize
,
237 HW_VAR_CCX_CHNL_LOAD
,
238 HW_VAR_CCX_NOISE_HISTOGRAM
,
245 HW_VAR_SET_DEV_POWER
,
255 HW_VAR_USER_CONTROL_TURBO_MODE
,
261 HW_VAR_AUTOLOAD_STATUS
,
262 HW_VAR_RF_2R_DISABLE
,
264 HW_VAR_H2C_FW_PWRMODE
,
265 HW_VAR_H2C_FW_JOINBSSRPT
,
266 HW_VAR_FW_PSMODE_STATUS
,
267 HW_VAR_1X1_RECV_COMBINE
,
268 HW_VAR_STOP_SEND_BEACON
,
273 HW_VAR_H2C_FW_UPDATE_GTK
,
276 HW_VAR_WF_IS_MAC_ADDR
,
277 HW_VAR_H2C_FW_OFFLOAD
,
280 HW_VAR_HANDLE_FW_C2H
,
281 HW_VAR_DL_FW_RSVD_PAGE
,
283 HW_VAR_HW_SEQ_ENABLE
,
288 HW_VAR_SWITCH_EPHY_WoWLAN
,
289 HW_VAR_INT_MIGRATION
,
300 enum _RT_MEDIA_STATUS
{
301 RT_MEDIA_DISCONNECT
= 0,
307 RT_CID_8187_ALPHA0
= 1,
308 RT_CID_8187_SERCOMM_PS
= 2,
309 RT_CID_8187_HW_LED
= 3,
310 RT_CID_8187_NETGEAR
= 4,
312 RT_CID_819x_CAMEO
= 6,
313 RT_CID_819x_RUNTOP
= 7,
314 RT_CID_819x_Senao
= 8,
316 RT_CID_819x_Netcore
= 10,
317 RT_CID_Nettronix
= 11,
321 RT_CID_819x_ALPHA
= 15,
322 RT_CID_819x_Sitecom
= 16,
324 RT_CID_819x_Lenovo
= 18,
325 RT_CID_819x_QMI
= 19,
326 RT_CID_819x_Edimax_Belkin
= 20,
327 RT_CID_819x_Sercomm_Belkin
= 21,
328 RT_CID_819x_CAMEO1
= 22,
329 RT_CID_819x_MSI
= 23,
330 RT_CID_819x_Acer
= 24,
332 RT_CID_819x_CLEVO
= 28,
333 RT_CID_819x_Arcadyan_Belkin
= 29,
334 RT_CID_819x_SAMSUNG
= 30,
335 RT_CID_819x_WNC_COREGA
= 31,
336 RT_CID_819x_Foxcoon
= 32,
337 RT_CID_819x_DELL
= 33,
343 HW_DESC_TX_NEXTDESC_ADDR
,
351 PRIME_CHNL_OFFSET_DONT_CARE
= 0,
352 PRIME_CHNL_OFFSET_LOWER
= 1,
353 PRIME_CHNL_OFFSET_UPPER
= 2,
363 enum ht_channel_width
{
364 HT_CHANNEL_WIDTH_20
= 0,
365 HT_CHANNEL_WIDTH_20_40
= 1,
368 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
369 Cipher Suites Encryption Algorithms */
372 WEP40_ENCRYPTION
= 1,
374 RSERVED_ENCRYPTION
= 3,
375 AESCCMP_ENCRYPTION
= 4,
376 WEP104_ENCRYPTION
= 5,
381 _HAL_STATE_START
= 1,
404 EFUSE_HWSET_MAX_SIZE
,
405 EFUSE_MAX_SECTION_MAP
,
406 EFUSE_REAL_CONTENT_SIZE
,
421 RTL_IMR_BCNDMAINT6
, /*Beacon DMA Interrupt 6 */
422 RTL_IMR_BCNDMAINT5
, /*Beacon DMA Interrupt 5 */
423 RTL_IMR_BCNDMAINT4
, /*Beacon DMA Interrupt 4 */
424 RTL_IMR_BCNDMAINT3
, /*Beacon DMA Interrupt 3 */
425 RTL_IMR_BCNDMAINT2
, /*Beacon DMA Interrupt 2 */
426 RTL_IMR_BCNDMAINT1
, /*Beacon DMA Interrupt 1 */
427 RTL_IMR_BCNDOK8
, /*Beacon Queue DMA OK Interrup 8 */
428 RTL_IMR_BCNDOK7
, /*Beacon Queue DMA OK Interrup 7 */
429 RTL_IMR_BCNDOK6
, /*Beacon Queue DMA OK Interrup 6 */
430 RTL_IMR_BCNDOK5
, /*Beacon Queue DMA OK Interrup 5 */
431 RTL_IMR_BCNDOK4
, /*Beacon Queue DMA OK Interrup 4 */
432 RTL_IMR_BCNDOK3
, /*Beacon Queue DMA OK Interrup 3 */
433 RTL_IMR_BCNDOK2
, /*Beacon Queue DMA OK Interrup 2 */
434 RTL_IMR_BCNDOK1
, /*Beacon Queue DMA OK Interrup 1 */
435 RTL_IMR_TIMEOUT2
, /*Timeout interrupt 2 */
436 RTL_IMR_TIMEOUT1
, /*Timeout interrupt 1 */
437 RTL_IMR_TXFOVW
, /*Transmit FIFO Overflow */
438 RTL_IMR_PSTIMEOUT
, /*Power save time out interrupt */
439 RTL_IMR_BcnInt
, /*Beacon DMA Interrupt 0 */
440 RTL_IMR_RXFOVW
, /*Receive FIFO Overflow */
441 RTL_IMR_RDU
, /*Receive Descriptor Unavailable */
442 RTL_IMR_ATIMEND
, /*For 92C,ATIM Window End Interrupt */
443 RTL_IMR_BDOK
, /*Beacon Queue DMA OK Interrup */
444 RTL_IMR_HIGHDOK
, /*High Queue DMA OK Interrupt */
445 RTL_IMR_COMDOK
, /*Command Queue DMA OK Interrupt*/
446 RTL_IMR_TBDOK
, /*Transmit Beacon OK interrup */
447 RTL_IMR_MGNTDOK
, /*Management Queue DMA OK Interrupt */
448 RTL_IMR_TBDER
, /*For 92C,Transmit Beacon Error Interrupt */
449 RTL_IMR_BKDOK
, /*AC_BK DMA OK Interrupt */
450 RTL_IMR_BEDOK
, /*AC_BE DMA OK Interrupt */
451 RTL_IMR_VIDOK
, /*AC_VI DMA OK Interrupt */
452 RTL_IMR_VODOK
, /*AC_VO DMA Interrupt */
453 RTL_IMR_ROK
, /*Receive DMA OK Interrupt */
454 RTL_IBSS_INT_MASKS
, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
457 /*CCK Rates, TxHT = 0 */
463 /*OFDM Rates, TxHT = 0 */
480 /*Firmware PS mode for control LPS.*/
482 FW_PS_ACTIVE_MODE
= 0,
487 FW_PS_UAPSD_WMM_MODE
= 5,
488 FW_PS_UAPSD_MODE
= 6,
490 FW_PS_WWLAN_MODE
= 8,
491 FW_PS_PM_Radio_Off
= 9,
492 FW_PS_PM_Card_Disable
= 10,
496 EACTIVE
, /*Active/Continuous access. */
497 EMAXPS
, /*Max power save mode. */
498 EFASTPS
, /*Fast power save mode. */
499 EAUTOPS
, /*Auto power save mode. */
504 LED_CTL_POWER_ON
= 1,
509 LED_CTL_SITE_SURVEY
= 6,
510 LED_CTL_POWER_OFF
= 7,
511 LED_CTL_START_TO_LINK
= 8,
512 LED_CTL_START_WPS
= 9,
513 LED_CTL_STOP_WPS
= 10,
524 /*acm implementation method.*/
526 eAcmWay0_SwAndHw
= 0,
532 SINGLEMAC_SINGLEPHY
= 0,
545 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
559 WIRELESS_MODE_UNKNOWN
= 0x00,
560 WIRELESS_MODE_A
= 0x01,
561 WIRELESS_MODE_B
= 0x02,
562 WIRELESS_MODE_G
= 0x04,
563 WIRELESS_MODE_AUTO
= 0x08,
564 WIRELESS_MODE_N_24G
= 0x10,
565 WIRELESS_MODE_N_5G
= 0x20
568 #define IS_WIRELESS_MODE_A(wirelessmode) \
569 (wirelessmode == WIRELESS_MODE_A)
570 #define IS_WIRELESS_MODE_B(wirelessmode) \
571 (wirelessmode == WIRELESS_MODE_B)
572 #define IS_WIRELESS_MODE_G(wirelessmode) \
573 (wirelessmode == WIRELESS_MODE_G)
574 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
575 (wirelessmode == WIRELESS_MODE_N_24G)
576 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
577 (wirelessmode == WIRELESS_MODE_N_5G)
579 enum ratr_table_mode
{
580 RATR_INX_WIRELESS_NGB
= 0,
581 RATR_INX_WIRELESS_NG
= 1,
582 RATR_INX_WIRELESS_NB
= 2,
583 RATR_INX_WIRELESS_N
= 3,
584 RATR_INX_WIRELESS_GB
= 4,
585 RATR_INX_WIRELESS_G
= 5,
586 RATR_INX_WIRELESS_B
= 6,
587 RATR_INX_WIRELESS_MC
= 7,
588 RATR_INX_WIRELESS_A
= 8,
591 enum rtl_link_state
{
593 MAC80211_LINKING
= 1,
595 MAC80211_LINKED_SCANNING
= 3,
612 struct octet_string
{
617 struct rtl_hdr_3addr
{
627 struct rtl_info_element
{
633 struct rtl_probe_rsp
{
634 struct rtl_hdr_3addr header
;
636 __le16 beacon_interval
;
638 /*SSID, supported rates, FH params, DS params,
639 CF params, IBSS params, TIM (if beacon), RSN */
640 struct rtl_info_element info_element
[0];
644 /*ledpin Identify how to implement this SW led.*/
647 enum rtl_led_pin ledpin
;
653 struct rtl_led sw_led0
;
654 struct rtl_led sw_led1
;
657 struct rtl_qos_parameters
{
665 struct rt_smooth_data
{
666 u32 elements
[100]; /*array to store values */
667 u32 index
; /*index to current array to store */
668 u32 total_num
; /*num of valid elements */
669 u32 total_val
; /*sum of valid elements */
672 struct false_alarm_statistics
{
674 u32 cnt_rate_illegal
;
677 u32 cnt_fast_fsync_fail
;
678 u32 cnt_sb_search_fail
;
693 struct wireless_stats
{
694 unsigned long txbytesunicast
;
695 unsigned long txbytesmulticast
;
696 unsigned long txbytesbroadcast
;
697 unsigned long rxbytesunicast
;
700 /*Correct smoothed ss in Dbm, only used
701 in driver to report real power now. */
702 long recv_signal_power
;
704 long last_sigstrength_inpercent
;
706 u32 rssi_calculate_cnt
;
708 /*Transformed, in dbm. Beautified signal
709 strength for UI, not correct. */
710 long signal_strength
;
712 u8 rx_rssi_percentage
[4];
713 u8 rx_evm_percentage
[2];
715 struct rt_smooth_data ui_rssi
;
716 struct rt_smooth_data ui_link_quality
;
719 struct rate_adaptive
{
720 u8 rate_adaptive_disabled
;
724 u32 high_rssi_thresh_for_ra
;
725 u32 high2low_rssi_thresh_for_ra
;
726 u8 low2high_rssi_thresh_for_ra40m
;
727 u32 low_rssi_thresh_for_ra40M
;
728 u8 low2high_rssi_thresh_for_ra20m
;
729 u32 low_rssi_thresh_for_ra20M
;
730 u32 upper_rssi_threshold_ratr
;
731 u32 middleupper_rssi_threshold_ratr
;
732 u32 middle_rssi_threshold_ratr
;
733 u32 middlelow_rssi_threshold_ratr
;
734 u32 low_rssi_threshold_ratr
;
735 u32 ultralow_rssi_threshold_ratr
;
736 u32 low_rssi_threshold_ratr_40m
;
737 u32 low_rssi_threshold_ratr_20m
;
740 u32 ping_rssi_thresh_for_ra
;
745 struct regd_pair_mapping
{
751 struct rtl_regulatory
{
759 struct regd_pair_mapping
*regpair
;
763 bool rfkill_state
; /*0 is off, 1 is on */
766 #define IQK_MATRIX_REG_NUM 8
767 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
768 struct iqk_matrix_regs
{
770 long value
[1][IQK_MATRIX_REG_NUM
];
773 struct phy_parameters
{
778 enum hw_param_tab_index
{
793 struct bb_reg_def phyreg_def
[4]; /*Radio A/B/C/D */
794 struct init_gain initgain_backup
;
795 enum io_type current_io_type
;
800 u8 set_bwmode_inprogress
;
801 u8 sw_chnl_inprogress
;
806 u8 set_io_inprogress
;
809 /* record for power tracking */
821 u32 reg_c04
, reg_c08
, reg_874
;
823 u32 iqk_mac_backup
[IQK_MAC_REG_NUM
];
824 u32 iqk_bb_backup
[10];
828 struct iqk_matrix_regs iqk_matrix_regsetting
[IQK_MATRIX_SETTINGS_NUM
];
834 /* MAX_PG_GROUP groups of pwr diff by rates */
835 u32 mcs_txpwrlevel_origoffset
[MAX_PG_GROUP
][16];
836 u8 default_initialgain
[4];
838 /* the current Tx power level */
840 u8 cur_ofdm24g_txpwridx
;
842 u32 rfreg_chnlval
[2];
844 u32 reg_rf3c
[2]; /* pathA / pathB */
850 struct phy_parameters hwparam_tables
[MAX_TAB
];
854 #define MAX_TID_COUNT 9
855 #define RTL_AGG_OFF 0
857 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
858 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
869 struct rtl_tid_data
{
871 struct rtl_ht_agg agg
;
877 struct mutex bb_mutex
;
880 unsigned long pci_mem_end
; /*shared mem end */
881 unsigned long pci_mem_start
; /*shared mem start */
884 unsigned long pci_base_addr
; /*device I/O address */
886 void (*write8_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u8 val
);
887 void (*write16_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u16 val
);
888 void (*write32_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u32 val
);
889 int (*writeN_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u16 len
,
892 u8(*read8_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
893 u16(*read16_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
894 u32(*read32_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
895 int (*readN_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
, u16 len
,
900 u8 mac_addr
[ETH_ALEN
];
901 u8 mac80211_registered
;
907 struct ieee80211_supported_band bands
[IEEE80211_NUM_BANDS
];
908 struct ieee80211_hw
*hw
;
909 struct ieee80211_vif
*vif
;
910 enum nl80211_iftype opmode
;
912 /*Probe Beacon management */
913 struct rtl_tid_data tids
[MAX_TID_COUNT
];
914 enum rtl_link_state link_state
;
930 struct sk_buff_head skb_waitq
[MAX_TID_COUNT
];
931 u8 earlymode_threshold
;
939 u8 mcs
[16]; /* 16 bytes mcs for HT rates. */
940 u32 basic_rates
; /* b/g rates */
945 u8 mode
; /* wireless mode */
950 u8 cur_40_prime_sc_bk
;
960 u8 min_space_cfg
; /*For Min spacing configurations */
962 u8 current_ampdu_factor
;
963 u8 current_ampdu_density
;
966 struct ieee80211_tx_queue_params edca_param
[RTL_MAC80211_NUM_QUEUE
];
967 struct rtl_qos_parameters ac
[AC_MAX
];
971 struct ieee80211_hw
*hw
;
973 enum intf_type interface
;
974 u16 hw_type
; /*92c or 92d or 92s and so on */
977 u32 version
; /*version of chip */
978 u8 state
; /*stop 0, start 1 */
985 bool h2c_setinprogress
;
988 /*Reserve page start offset except beacon in TxQ. */
989 u8 fw_rsvdpage_startoffset
;
992 /* FW Cmd IO related */
995 bool set_fwcmd_inprogress
;
999 bool driver_going2unload
;
1001 /*AMPDU init min space*/
1002 u8 minspace_cfg
; /*For Min spacing configurations */
1005 enum macphy_mode macphymode
;
1006 enum band_type current_bandtype
; /* 0:2.4G, 1:5G */
1007 enum band_type current_bandtypebackup
;
1008 enum band_type bandset
;
1009 /* dual MAC 0--Mac0 1--Mac1 */
1011 /* just for DualMac S3S4 */
1013 bool earlymode_enable
;
1015 bool during_mac0init_radiob
;
1016 bool during_mac1init_radioa
;
1017 bool reloadtxpowerindex
;
1018 /* True if IMR or IQK have done
1019 for 2.4G in scan progress */
1020 bool load_imrandiqk_setting_for2g
;
1022 bool disable_amsdu_8k
;
1025 struct rtl_security
{
1030 bool use_defaultkey
;
1031 /*Encryption Algorithm for Unicast Packet */
1032 enum rt_enc_alg pairwise_enc_algorithm
;
1033 /*Encryption Algorithm for Brocast/Multicast */
1034 enum rt_enc_alg group_enc_algorithm
;
1036 /*local Key buffer, indx 0 is for
1037 pairwise key 1-4 is for agoup key. */
1038 u8 key_buf
[KEY_BUF_SIZE
][MAX_KEY_LEN
];
1039 u8 key_len
[KEY_BUF_SIZE
];
1041 /*The pointer of Pairwise Key,
1042 it always points to KeyBuf[4] */
1047 /*PHY status for Dynamic Management */
1048 long entry_min_undecoratedsmoothed_pwdb
;
1049 long undecorated_smoothed_pwdb
; /*out dm */
1050 long entry_max_undecoratedsmoothed_pwdb
;
1051 bool dm_initialgain_enable
;
1052 bool dynamic_txpower_enable
;
1053 bool current_turbo_edca
;
1054 bool is_any_nonbepkts
; /*out dm */
1055 bool is_cur_rdlstate
;
1056 bool txpower_trackingInit
;
1057 bool disable_framebursting
;
1059 bool txpower_tracking
;
1061 bool rfpath_rxenable
[4];
1062 bool inform_fw_driverctrldm
;
1063 bool current_mrc_switch
;
1066 u8 thermalvalue_rxgain
;
1067 u8 thermalvalue_iqk
;
1068 u8 thermalvalue_lck
;
1071 u8 thermalvalue_avg
[AVG_THERMAL_NUM
];
1072 u8 thermalvalue_avg_index
;
1074 u8 dynamic_txhighpower_lvl
; /*Tx high power level */
1075 u8 dm_flag
; /*Indicate each dynamic mechanism's status. */
1077 u8 txpower_track_control
;
1078 bool interrupt_migration
;
1079 bool disable_tx_int
;
1082 u8 power_index_backup
[6];
1085 #define EFUSE_MAX_LOGICAL_SIZE 256
1090 u16 max_physical_size
;
1092 u8 efuse_map
[2][EFUSE_MAX_LOGICAL_SIZE
];
1093 u16 efuse_usedbytes
;
1094 u8 efuse_usedpercentage
;
1095 #ifdef EFUSE_REPG_WORKAROUND
1096 bool efuse_re_pg_sec1flag
;
1097 u8 efuse_re_pg_data
[8];
1100 u8 autoload_failflag
;
1109 u16 eeprom_channelplan
;
1116 bool txpwr_fromeprom
;
1117 u8 eeprom_crystalcap
;
1119 u8 eeprom_tssi_5g
[3][2]; /* for 5GL/5GM/5GH band. */
1120 u8 eeprom_pwrlimit_ht20
[CHANNEL_GROUP_MAX
];
1121 u8 eeprom_pwrlimit_ht40
[CHANNEL_GROUP_MAX
];
1122 u8 eeprom_chnlarea_txpwr_cck
[2][CHANNEL_GROUP_MAX_2G
];
1123 u8 eeprom_chnlarea_txpwr_ht40_1s
[2][CHANNEL_GROUP_MAX
];
1124 u8 eeprom_chnlarea_txpwr_ht40_2sdiif
[2][CHANNEL_GROUP_MAX
];
1125 u8 txpwrlevel_cck
[2][CHANNEL_MAX_NUMBER_2G
];
1126 u8 txpwrlevel_ht40_1s
[2][CHANNEL_MAX_NUMBER
]; /*For HT 40MHZ pwr */
1127 u8 txpwrlevel_ht40_2s
[2][CHANNEL_MAX_NUMBER
]; /*For HT 40MHZ pwr */
1129 u8 internal_pa_5g
[2]; /* pathA / pathB */
1133 /*For power group */
1134 u8 eeprom_pwrgroup
[2][3];
1135 u8 pwrgroup_ht20
[2][CHANNEL_MAX_NUMBER
];
1136 u8 pwrgroup_ht40
[2][CHANNEL_MAX_NUMBER
];
1138 char txpwr_ht20diff
[2][CHANNEL_MAX_NUMBER
]; /*HT 20<->40 Pwr diff */
1139 /*For HT<->legacy pwr diff*/
1140 u8 txpwr_legacyhtdiff
[2][CHANNEL_MAX_NUMBER
];
1141 u8 txpwr_safetyflag
; /* Band edge enable flag */
1142 u16 eeprom_txpowerdiff
;
1143 u8 legacy_httxpowerdiff
; /* Legacy to HT rate power diff */
1144 u8 antenna_txpwdiff
[3];
1146 u8 eeprom_regulatory
;
1147 u8 eeprom_thermalmeter
;
1148 u8 thermalmeter
[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1150 u8 crystalcap
; /* CrystalCap. */
1154 u8 legacy_ht_txpowerdiff
; /*Legacy to HT rate power diff */
1155 bool apk_thermalmeterignore
;
1157 bool b1x1_recvcombine
;
1165 bool pwrdomain_protect
;
1166 bool set_rfpowerstate_inprogress
;
1167 bool in_powersavemode
;
1168 bool rfchange_inprogress
;
1169 bool swrf_processing
;
1173 * just for PCIE ASPM
1174 * If it supports ASPM, Offset[560h] = 0x40,
1175 * otherwise Offset[560h] = 0x00.
1178 bool support_backdoor
;
1181 enum rt_psmode dot11_psmode
; /*Power save mode configured. */
1186 /*For Fw control LPS mode */
1188 /*Record Fw PS mode status. */
1189 bool fw_current_inpsmode
;
1190 u8 reg_max_lps_awakeintvl
;
1202 /*just for PCIE ASPM */
1203 u8 const_amdpci_aspm
;
1207 enum rf_pwrstate inactive_pwrstate
;
1208 enum rf_pwrstate rfpwr_state
; /*cur power state */
1214 bool multi_buffered
;
1216 unsigned int dtim_counter
;
1217 unsigned int sleep_ms
;
1218 unsigned long last_sleep_jiffies
;
1219 unsigned long last_awake_jiffies
;
1220 unsigned long last_delaylps_stamp_jiffies
;
1221 unsigned long last_dtim
;
1222 unsigned long last_beacon
;
1223 unsigned long last_action
;
1224 unsigned long last_slept
;
1232 u16 rate
; /*in 100 kbps */
1233 u8 received_channel
;
1242 u8 signalquality
; /*in 0-100 index. */
1244 * Real power in dBm for this packet,
1245 * no beautification and aggregation.
1247 s32 recvsignalpower
;
1248 s8 rxpower
; /*in dBm Translate from PWdB */
1249 u8 signalstrength
; /*in 0-100 index. */
1253 u16 shortpreamble
:1;
1264 bool rx_is40Mhzpacket
;
1266 u8 rx_mimo_signalstrength
[4]; /*in 0~100 index */
1267 s8 rx_mimo_signalquality
[2];
1268 bool packet_matchbssid
;
1271 bool packet_beacon
; /*for rssi */
1272 char cck_adc_pwdb
[4]; /*for rx path selection */
1275 struct rt_link_detect
{
1276 u32 num_tx_in4period
[4];
1277 u32 num_rx_in4period
[4];
1279 u32 num_tx_inperiod
;
1280 u32 num_rx_inperiod
;
1283 bool higher_busytraffic
;
1284 bool higher_busyrxtraffic
;
1287 struct rtl_tcb_desc
{
1295 u8 rts_use_shortpreamble
:1;
1296 u8 rts_use_shortgi
:1;
1302 u8 use_shortpreamble
:1;
1303 u8 use_driver_rate
:1;
1304 u8 disable_ratefallback
:1;
1316 /* The max value by HW */
1320 struct rtl_hal_ops
{
1321 int (*init_sw_vars
) (struct ieee80211_hw
*hw
);
1322 void (*deinit_sw_vars
) (struct ieee80211_hw
*hw
);
1323 void (*read_chip_version
)(struct ieee80211_hw
*hw
);
1324 void (*read_eeprom_info
) (struct ieee80211_hw
*hw
);
1325 void (*interrupt_recognized
) (struct ieee80211_hw
*hw
,
1326 u32
*p_inta
, u32
*p_intb
);
1327 int (*hw_init
) (struct ieee80211_hw
*hw
);
1328 void (*hw_disable
) (struct ieee80211_hw
*hw
);
1329 void (*hw_suspend
) (struct ieee80211_hw
*hw
);
1330 void (*hw_resume
) (struct ieee80211_hw
*hw
);
1331 void (*enable_interrupt
) (struct ieee80211_hw
*hw
);
1332 void (*disable_interrupt
) (struct ieee80211_hw
*hw
);
1333 int (*set_network_type
) (struct ieee80211_hw
*hw
,
1334 enum nl80211_iftype type
);
1335 void (*set_chk_bssid
)(struct ieee80211_hw
*hw
,
1337 void (*set_bw_mode
) (struct ieee80211_hw
*hw
,
1338 enum nl80211_channel_type ch_type
);
1339 u8(*switch_channel
) (struct ieee80211_hw
*hw
);
1340 void (*set_qos
) (struct ieee80211_hw
*hw
, int aci
);
1341 void (*set_bcn_reg
) (struct ieee80211_hw
*hw
);
1342 void (*set_bcn_intv
) (struct ieee80211_hw
*hw
);
1343 void (*update_interrupt_mask
) (struct ieee80211_hw
*hw
,
1344 u32 add_msr
, u32 rm_msr
);
1345 void (*get_hw_reg
) (struct ieee80211_hw
*hw
, u8 variable
, u8
*val
);
1346 void (*set_hw_reg
) (struct ieee80211_hw
*hw
, u8 variable
, u8
*val
);
1347 void (*update_rate_table
) (struct ieee80211_hw
*hw
);
1348 void (*update_rate_mask
) (struct ieee80211_hw
*hw
, u8 rssi_level
);
1349 void (*fill_tx_desc
) (struct ieee80211_hw
*hw
,
1350 struct ieee80211_hdr
*hdr
, u8
*pdesc_tx
,
1351 struct ieee80211_tx_info
*info
,
1352 struct sk_buff
*skb
, unsigned int queue_index
);
1353 void (*fill_fake_txdesc
) (struct ieee80211_hw
*hw
, u8
* pDesc
,
1354 u32 buffer_len
, bool bIsPsPoll
);
1355 void (*fill_tx_cmddesc
) (struct ieee80211_hw
*hw
, u8
*pdesc
,
1356 bool firstseg
, bool lastseg
,
1357 struct sk_buff
*skb
);
1358 bool (*cmd_send_packet
)(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
1359 bool (*query_rx_desc
) (struct ieee80211_hw
*hw
,
1360 struct rtl_stats
*stats
,
1361 struct ieee80211_rx_status
*rx_status
,
1362 u8
*pdesc
, struct sk_buff
*skb
);
1363 void (*set_channel_access
) (struct ieee80211_hw
*hw
);
1364 bool (*radio_onoff_checking
) (struct ieee80211_hw
*hw
, u8
*valid
);
1365 void (*dm_watchdog
) (struct ieee80211_hw
*hw
);
1366 void (*scan_operation_backup
) (struct ieee80211_hw
*hw
, u8 operation
);
1367 bool (*set_rf_power_state
) (struct ieee80211_hw
*hw
,
1368 enum rf_pwrstate rfpwr_state
);
1369 void (*led_control
) (struct ieee80211_hw
*hw
,
1370 enum led_ctl_mode ledaction
);
1371 void (*set_desc
) (u8
*pdesc
, bool istx
, u8 desc_name
, u8
*val
);
1372 u32 (*get_desc
) (u8
*pdesc
, bool istx
, u8 desc_name
);
1373 void (*tx_polling
) (struct ieee80211_hw
*hw
, unsigned int hw_queue
);
1374 void (*enable_hw_sec
) (struct ieee80211_hw
*hw
);
1375 void (*set_key
) (struct ieee80211_hw
*hw
, u32 key_index
,
1376 u8
*p_macaddr
, bool is_group
, u8 enc_algo
,
1377 bool is_wepkey
, bool clear_all
);
1378 void (*init_sw_leds
) (struct ieee80211_hw
*hw
);
1379 void (*deinit_sw_leds
) (struct ieee80211_hw
*hw
);
1380 u32 (*get_bbreg
) (struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
);
1381 void (*set_bbreg
) (struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
,
1383 u32 (*get_rfreg
) (struct ieee80211_hw
*hw
, enum radio_path rfpath
,
1384 u32 regaddr
, u32 bitmask
);
1385 void (*set_rfreg
) (struct ieee80211_hw
*hw
, enum radio_path rfpath
,
1386 u32 regaddr
, u32 bitmask
, u32 data
);
1387 bool (*phy_rf6052_config
) (struct ieee80211_hw
*hw
);
1388 void (*phy_rf6052_set_cck_txpower
) (struct ieee80211_hw
*hw
,
1390 void (*phy_rf6052_set_ofdm_txpower
) (struct ieee80211_hw
*hw
,
1391 u8
*ppowerlevel
, u8 channel
);
1392 bool (*config_bb_with_headerfile
) (struct ieee80211_hw
*hw
,
1394 bool (*config_bb_with_pgheaderfile
) (struct ieee80211_hw
*hw
,
1396 void (*phy_lc_calibrate
) (struct ieee80211_hw
*hw
, bool is2t
);
1397 void (*phy_set_bw_mode_callback
) (struct ieee80211_hw
*hw
);
1398 void (*dm_dynamic_txpower
) (struct ieee80211_hw
*hw
);
1401 struct rtl_intf_ops
{
1403 void (*read_efuse_byte
)(struct ieee80211_hw
*hw
, u16 _offset
, u8
*pbuf
);
1404 int (*adapter_start
) (struct ieee80211_hw
*hw
);
1405 void (*adapter_stop
) (struct ieee80211_hw
*hw
);
1407 int (*adapter_tx
) (struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
1408 int (*reset_trx_ring
) (struct ieee80211_hw
*hw
);
1409 bool (*waitq_insert
) (struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
1412 void (*disable_aspm
) (struct ieee80211_hw
*hw
);
1413 void (*enable_aspm
) (struct ieee80211_hw
*hw
);
1418 struct rtl_mod_params
{
1419 /* default: 0 = using hardware encryption */
1423 struct rtl_hal_usbint_cfg
{
1430 void (*usb_rx_hdl
)(struct ieee80211_hw
*, struct sk_buff
*);
1431 void (*usb_rx_segregate_hdl
)(struct ieee80211_hw
*, struct sk_buff
*,
1432 struct sk_buff_head
*);
1435 void (*usb_tx_cleanup
)(struct ieee80211_hw
*, struct sk_buff
*);
1436 int (*usb_tx_post_hdl
)(struct ieee80211_hw
*, struct urb
*,
1438 struct sk_buff
*(*usb_tx_aggregate_hdl
)(struct ieee80211_hw
*,
1439 struct sk_buff_head
*);
1441 /* endpoint mapping */
1442 int (*usb_endpoint_mapping
)(struct ieee80211_hw
*hw
);
1443 u16 (*usb_mq_to_hwq
)(__le16 fc
, u16 mac80211_queue_index
);
1446 struct rtl_hal_cfg
{
1450 struct rtl_hal_ops
*ops
;
1451 struct rtl_mod_params
*mod_params
;
1452 struct rtl_hal_usbint_cfg
*usb_interface_cfg
;
1454 /*this map used for some registers or vars
1455 defined int HAL but used in MAIN */
1456 u32 maps
[RTL_VAR_MAP_MAX
];
1462 struct mutex conf_mutex
;
1465 spinlock_t ips_lock
;
1466 spinlock_t irq_th_lock
;
1467 spinlock_t h2c_lock
;
1468 spinlock_t rf_ps_lock
;
1470 spinlock_t lps_lock
;
1471 spinlock_t waitq_lock
;
1472 spinlock_t tx_urb_lock
;
1475 spinlock_t cck_and_rw_pagea_lock
;
1479 struct ieee80211_hw
*hw
;
1482 struct timer_list watchdog_timer
;
1485 struct tasklet_struct irq_tasklet
;
1486 struct tasklet_struct irq_prepare_bcn_tasklet
;
1489 struct workqueue_struct
*rtl_wq
;
1490 struct delayed_work watchdog_wq
;
1491 struct delayed_work ips_nic_off_wq
;
1494 struct delayed_work ps_work
;
1495 struct delayed_work ps_rfon_wq
;
1499 u32 dbgp_type
[DBGP_TYPE_MAX
];
1500 u32 global_debuglevel
;
1501 u64 global_debugcomponents
;
1503 /* add for proc debug */
1504 struct proc_dir_entry
*proc_dir
;
1509 struct rtl_locks locks
;
1510 struct rtl_works works
;
1511 struct rtl_mac mac80211
;
1512 struct rtl_hal rtlhal
;
1513 struct rtl_regulatory regd
;
1514 struct rtl_rfkill rfkill
;
1518 struct rtl_security sec
;
1519 struct rtl_efuse efuse
;
1521 struct rtl_ps_ctl psc
;
1522 struct rate_adaptive ra
;
1523 struct wireless_stats stats
;
1524 struct rt_link_detect link_info
;
1525 struct false_alarm_statistics falsealm_cnt
;
1527 struct rtl_rate_priv
*rate_priv
;
1529 struct rtl_debug dbg
;
1532 *hal_cfg : for diff cards
1533 *intf_ops : for diff interrface usb/pcie
1535 struct rtl_hal_cfg
*cfg
;
1536 struct rtl_intf_ops
*intf_ops
;
1538 /*this var will be set by set_bit,
1539 and was used to indicate status of
1540 interface or hardware */
1541 unsigned long status
;
1543 /*This must be the last item so
1544 that it points to the data allocated
1545 beyond this structure like:
1546 rtl_pci_priv or rtl_usb_priv */
1550 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1551 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1552 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1553 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1554 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1557 /***************************************
1558 Bluetooth Co-existance Related
1559 ****************************************/
1580 enum bt_service_type
{
1587 BT_OTHER_ACTION
= 6,
1593 enum bt_radio_shared
{
1594 BT_RADIO_SHARED
= 0,
1595 BT_RADIO_INDIVIDUAL
= 1,
1598 struct bt_coexist_info
{
1600 /* EEPROM BT info. */
1601 u8 eeprom_bt_coexist
;
1603 u8 eeprom_bt_ant_num
;
1604 u8 eeprom_bt_ant_isolation
;
1605 u8 eeprom_bt_radio_shared
;
1611 u8 bt_cur_state
; /* 0:on, 1:off */
1612 u8 bt_ant_isolation
; /* 0:good, 1:bad */
1613 u8 bt_pape_ctrl
; /* 0:SW, 1:SW/HW dynamic */
1615 u8 bt_radio_shared_type
;
1616 u8 bt_rfreg_origin_1e
;
1617 u8 bt_rfreg_origin_1f
;
1625 bool b_bt_busy_traffic
;
1626 bool b_bt_traffic_mode_set
;
1627 bool b_bt_non_traffic_mode_set
;
1629 bool b_fw_coexist_all_off
;
1630 bool b_sw_coexist_all_off
;
1633 u8 bt_pre_rssi_state
;
1641 /****************************************
1642 mem access macro define start
1643 Call endian free function when
1644 1. Read/write packet content.
1645 2. Before write integer to IO.
1646 3. After read integer from IO.
1647 ****************************************/
1648 /* Convert little data endian to host ordering */
1649 #define EF1BYTE(_val) \
1651 #define EF2BYTE(_val) \
1653 #define EF4BYTE(_val) \
1656 /* Read le16 data from memory and convert to host ordering */
1657 #define READEF2BYTE(_ptr) \
1658 EF2BYTE(*((u16 *)(_ptr)))
1660 /* Write le16 data to memory in host ordering */
1661 #define WRITEEF2BYTE(_ptr, _val) \
1662 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1664 /* Create a bit mask
1666 * BIT_LEN_MASK_32(0) => 0x00000000
1667 * BIT_LEN_MASK_32(1) => 0x00000001
1668 * BIT_LEN_MASK_32(2) => 0x00000003
1669 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1671 #define BIT_LEN_MASK_32(__bitlen) \
1672 (0xFFFFFFFF >> (32 - (__bitlen)))
1673 #define BIT_LEN_MASK_16(__bitlen) \
1674 (0xFFFF >> (16 - (__bitlen)))
1675 #define BIT_LEN_MASK_8(__bitlen) \
1676 (0xFF >> (8 - (__bitlen)))
1678 /* Create an offset bit mask
1680 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1681 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1683 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1684 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1685 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1686 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1687 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1688 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1691 * Return 4-byte value in host byte ordering from
1692 * 4-byte pointer in little-endian system.
1694 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1695 (EF4BYTE(*((u32 *)(__pstart))))
1696 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1697 (EF2BYTE(*((u16 *)(__pstart))))
1698 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1699 (EF1BYTE(*((u8 *)(__pstart))))
1702 * Mask subfield (continuous bits in little-endian) of 4-byte value
1703 * and return the result in 4-byte value in host byte ordering.
1705 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1707 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1708 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1710 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1712 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1713 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1715 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1717 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1718 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1722 * Set subfield of little-endian 4-byte value to specified value.
1724 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1725 *((u8 *)(__pstart)) = EF1BYTE \
1727 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1728 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1731 /****************************************
1732 mem access macro define end
1733 ****************************************/
1735 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1737 #define RTL_WATCH_DOG_TIME 2000
1738 #define MSECS(t) msecs_to_jiffies(t)
1739 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1740 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1741 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1742 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1743 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1744 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1745 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1747 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1748 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1749 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1750 /*NIC halt, re-initialize hw parameters*/
1751 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1752 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1753 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1754 /*Always enable ASPM and Clock Req in initialization.*/
1755 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1756 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1757 #define RT_PS_LEVEL_ASPM BIT(7)
1758 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1759 #define RT_RF_LPS_DISALBE_2R BIT(30)
1760 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1761 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1762 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1763 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1764 (ppsc->cur_ps_level &= (~(_ps_flg)))
1765 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1766 (ppsc->cur_ps_level |= _ps_flg)
1768 #define container_of_dwork_rtl(x, y, z) \
1769 container_of(container_of(x, struct delayed_work, work), y, z)
1771 static inline u8
rtl_read_byte(struct rtl_priv
*rtlpriv
, u32 addr
)
1773 return rtlpriv
->io
.read8_sync(rtlpriv
, addr
);
1776 static inline u16
rtl_read_word(struct rtl_priv
*rtlpriv
, u32 addr
)
1778 return rtlpriv
->io
.read16_sync(rtlpriv
, addr
);
1781 static inline u32
rtl_read_dword(struct rtl_priv
*rtlpriv
, u32 addr
)
1783 return rtlpriv
->io
.read32_sync(rtlpriv
, addr
);
1786 static inline void rtl_write_byte(struct rtl_priv
*rtlpriv
, u32 addr
, u8 val8
)
1788 rtlpriv
->io
.write8_async(rtlpriv
, addr
, val8
);
1791 static inline void rtl_write_word(struct rtl_priv
*rtlpriv
, u32 addr
, u16 val16
)
1793 rtlpriv
->io
.write16_async(rtlpriv
, addr
, val16
);
1796 static inline void rtl_write_dword(struct rtl_priv
*rtlpriv
,
1797 u32 addr
, u32 val32
)
1799 rtlpriv
->io
.write32_async(rtlpriv
, addr
, val32
);
1802 static inline u32
rtl_get_bbreg(struct ieee80211_hw
*hw
,
1803 u32 regaddr
, u32 bitmask
)
1805 return ((struct rtl_priv
*)(hw
)->priv
)->cfg
->ops
->get_bbreg(hw
,
1810 static inline void rtl_set_bbreg(struct ieee80211_hw
*hw
, u32 regaddr
,
1811 u32 bitmask
, u32 data
)
1813 ((struct rtl_priv
*)(hw
)->priv
)->cfg
->ops
->set_bbreg(hw
,
1819 static inline u32
rtl_get_rfreg(struct ieee80211_hw
*hw
,
1820 enum radio_path rfpath
, u32 regaddr
,
1823 return ((struct rtl_priv
*)(hw
)->priv
)->cfg
->ops
->get_rfreg(hw
,
1829 static inline void rtl_set_rfreg(struct ieee80211_hw
*hw
,
1830 enum radio_path rfpath
, u32 regaddr
,
1831 u32 bitmask
, u32 data
)
1833 ((struct rtl_priv
*)(hw
)->priv
)->cfg
->ops
->set_rfreg(hw
,
1838 static inline bool is_hal_stop(struct rtl_hal
*rtlhal
)
1840 return (_HAL_STATE_STOP
== rtlhal
->state
);
1843 static inline void set_hal_start(struct rtl_hal
*rtlhal
)
1845 rtlhal
->state
= _HAL_STATE_START
;
1848 static inline void set_hal_stop(struct rtl_hal
*rtlhal
)
1850 rtlhal
->state
= _HAL_STATE_STOP
;
1853 static inline u8
get_rf_type(struct rtl_phy
*rtlphy
)
1855 return rtlphy
->rf_type
;