2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod_common_data.h"
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
35 #include <mach/am35xx.h>
38 * OMAP3xxx hardware module integration data
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod omap3xxx_mpu_hwmod
;
47 static struct omap_hwmod omap3xxx_iva_hwmod
;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod
;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod
;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod
;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod
;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod
;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod
;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod
;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod
;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod
;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod
;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod
;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod
;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod
;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod
;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod
;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod
;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod
;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod
;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod
;
67 static struct omap_hwmod omap34xx_sr1_hwmod
;
68 static struct omap_hwmod omap34xx_sr2_hwmod
;
69 static struct omap_hwmod omap34xx_mcspi1
;
70 static struct omap_hwmod omap34xx_mcspi2
;
71 static struct omap_hwmod omap34xx_mcspi3
;
72 static struct omap_hwmod omap34xx_mcspi4
;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod
;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod
;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod
;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod
;
78 static struct omap_hwmod omap3xxx_dma_system_hwmod
;
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod
;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod
;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod
;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod
;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod
;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod
;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod
;
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core
= {
90 .master
= &omap3xxx_l3_main_hwmod
,
91 .slave
= &omap3xxx_l4_core_hwmod
,
92 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per
= {
97 .master
= &omap3xxx_l3_main_hwmod
,
98 .slave
= &omap3xxx_l4_per_hwmod
,
99 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs
[] = {
104 { .irq
= INT_34XX_L3_DBG_IRQ
},
105 { .irq
= INT_34XX_L3_APP_IRQ
},
108 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs
[] = {
110 .pa_start
= 0x68000000,
111 .pa_end
= 0x6800ffff,
112 .flags
= ADDR_TYPE_RT
,
116 /* MPU -> L3 interface */
117 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main
= {
118 .master
= &omap3xxx_mpu_hwmod
,
119 .slave
= &omap3xxx_l3_main_hwmod
,
120 .addr
= omap3xxx_l3_main_addrs
,
121 .addr_cnt
= ARRAY_SIZE(omap3xxx_l3_main_addrs
),
122 .user
= OCP_USER_MPU
,
125 /* Slave interfaces on the L3 interconnect */
126 static struct omap_hwmod_ocp_if
*omap3xxx_l3_main_slaves
[] = {
127 &omap3xxx_mpu__l3_main
,
131 static struct omap_hwmod_ocp_if omap3xxx_dss__l3
= {
132 .master
= &omap3xxx_dss_core_hwmod
,
133 .slave
= &omap3xxx_l3_main_hwmod
,
136 .l3_perm_bit
= OMAP3_L3_CORE_FW_INIT_ID_DSS
,
137 .flags
= OMAP_FIREWALL_L3
,
140 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
143 /* Master interfaces on the L3 interconnect */
144 static struct omap_hwmod_ocp_if
*omap3xxx_l3_main_masters
[] = {
145 &omap3xxx_l3_main__l4_core
,
146 &omap3xxx_l3_main__l4_per
,
150 static struct omap_hwmod omap3xxx_l3_main_hwmod
= {
152 .class = &l3_hwmod_class
,
153 .mpu_irqs
= omap3xxx_l3_main_irqs
,
154 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_l3_main_irqs
),
155 .masters
= omap3xxx_l3_main_masters
,
156 .masters_cnt
= ARRAY_SIZE(omap3xxx_l3_main_masters
),
157 .slaves
= omap3xxx_l3_main_slaves
,
158 .slaves_cnt
= ARRAY_SIZE(omap3xxx_l3_main_slaves
),
159 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
160 .flags
= HWMOD_NO_IDLEST
,
163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod
;
164 static struct omap_hwmod omap3xxx_uart1_hwmod
;
165 static struct omap_hwmod omap3xxx_uart2_hwmod
;
166 static struct omap_hwmod omap3xxx_uart3_hwmod
;
167 static struct omap_hwmod omap3xxx_uart4_hwmod
;
168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod
;
170 /* l3_core -> usbhsotg interface */
171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3
= {
172 .master
= &omap3xxx_usbhsotg_hwmod
,
173 .slave
= &omap3xxx_l3_main_hwmod
,
174 .clk
= "core_l3_ick",
175 .user
= OCP_USER_MPU
,
178 /* l3_core -> am35xx_usbhsotg interface */
179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3
= {
180 .master
= &am35xx_usbhsotg_hwmod
,
181 .slave
= &omap3xxx_l3_main_hwmod
,
182 .clk
= "core_l3_ick",
183 .user
= OCP_USER_MPU
,
185 /* L4_CORE -> L4_WKUP interface */
186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup
= {
187 .master
= &omap3xxx_l4_core_hwmod
,
188 .slave
= &omap3xxx_l4_wkup_hwmod
,
189 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
192 /* L4 CORE -> MMC1 interface */
193 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space
[] = {
195 .pa_start
= 0x4809c000,
196 .pa_end
= 0x4809c1ff,
197 .flags
= ADDR_TYPE_RT
,
201 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1
= {
202 .master
= &omap3xxx_l4_core_hwmod
,
203 .slave
= &omap3xxx_mmc1_hwmod
,
205 .addr
= omap3xxx_mmc1_addr_space
,
206 .addr_cnt
= ARRAY_SIZE(omap3xxx_mmc1_addr_space
),
207 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
208 .flags
= OMAP_FIREWALL_L4
211 /* L4 CORE -> MMC2 interface */
212 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space
[] = {
214 .pa_start
= 0x480b4000,
215 .pa_end
= 0x480b41ff,
216 .flags
= ADDR_TYPE_RT
,
220 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2
= {
221 .master
= &omap3xxx_l4_core_hwmod
,
222 .slave
= &omap3xxx_mmc2_hwmod
,
224 .addr
= omap3xxx_mmc2_addr_space
,
225 .addr_cnt
= ARRAY_SIZE(omap3xxx_mmc2_addr_space
),
226 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
227 .flags
= OMAP_FIREWALL_L4
230 /* L4 CORE -> MMC3 interface */
231 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space
[] = {
233 .pa_start
= 0x480ad000,
234 .pa_end
= 0x480ad1ff,
235 .flags
= ADDR_TYPE_RT
,
239 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3
= {
240 .master
= &omap3xxx_l4_core_hwmod
,
241 .slave
= &omap3xxx_mmc3_hwmod
,
243 .addr
= omap3xxx_mmc3_addr_space
,
244 .addr_cnt
= ARRAY_SIZE(omap3xxx_mmc3_addr_space
),
245 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
246 .flags
= OMAP_FIREWALL_L4
249 /* L4 CORE -> UART1 interface */
250 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space
[] = {
252 .pa_start
= OMAP3_UART1_BASE
,
253 .pa_end
= OMAP3_UART1_BASE
+ SZ_8K
- 1,
254 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
258 static struct omap_hwmod_ocp_if omap3_l4_core__uart1
= {
259 .master
= &omap3xxx_l4_core_hwmod
,
260 .slave
= &omap3xxx_uart1_hwmod
,
262 .addr
= omap3xxx_uart1_addr_space
,
263 .addr_cnt
= ARRAY_SIZE(omap3xxx_uart1_addr_space
),
264 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
267 /* L4 CORE -> UART2 interface */
268 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space
[] = {
270 .pa_start
= OMAP3_UART2_BASE
,
271 .pa_end
= OMAP3_UART2_BASE
+ SZ_1K
- 1,
272 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
276 static struct omap_hwmod_ocp_if omap3_l4_core__uart2
= {
277 .master
= &omap3xxx_l4_core_hwmod
,
278 .slave
= &omap3xxx_uart2_hwmod
,
280 .addr
= omap3xxx_uart2_addr_space
,
281 .addr_cnt
= ARRAY_SIZE(omap3xxx_uart2_addr_space
),
282 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
285 /* L4 PER -> UART3 interface */
286 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space
[] = {
288 .pa_start
= OMAP3_UART3_BASE
,
289 .pa_end
= OMAP3_UART3_BASE
+ SZ_1K
- 1,
290 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
294 static struct omap_hwmod_ocp_if omap3_l4_per__uart3
= {
295 .master
= &omap3xxx_l4_per_hwmod
,
296 .slave
= &omap3xxx_uart3_hwmod
,
298 .addr
= omap3xxx_uart3_addr_space
,
299 .addr_cnt
= ARRAY_SIZE(omap3xxx_uart3_addr_space
),
300 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
303 /* L4 PER -> UART4 interface */
304 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space
[] = {
306 .pa_start
= OMAP3_UART4_BASE
,
307 .pa_end
= OMAP3_UART4_BASE
+ SZ_1K
- 1,
308 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
312 static struct omap_hwmod_ocp_if omap3_l4_per__uart4
= {
313 .master
= &omap3xxx_l4_per_hwmod
,
314 .slave
= &omap3xxx_uart4_hwmod
,
316 .addr
= omap3xxx_uart4_addr_space
,
317 .addr_cnt
= ARRAY_SIZE(omap3xxx_uart4_addr_space
),
318 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
321 /* I2C IP block address space length (in bytes) */
322 #define OMAP2_I2C_AS_LEN 128
324 /* L4 CORE -> I2C1 interface */
325 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space
[] = {
327 .pa_start
= 0x48070000,
328 .pa_end
= 0x48070000 + OMAP2_I2C_AS_LEN
- 1,
329 .flags
= ADDR_TYPE_RT
,
333 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1
= {
334 .master
= &omap3xxx_l4_core_hwmod
,
335 .slave
= &omap3xxx_i2c1_hwmod
,
337 .addr
= omap3xxx_i2c1_addr_space
,
338 .addr_cnt
= ARRAY_SIZE(omap3xxx_i2c1_addr_space
),
341 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C1_REGION
,
343 .flags
= OMAP_FIREWALL_L4
,
346 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
349 /* L4 CORE -> I2C2 interface */
350 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space
[] = {
352 .pa_start
= 0x48072000,
353 .pa_end
= 0x48072000 + OMAP2_I2C_AS_LEN
- 1,
354 .flags
= ADDR_TYPE_RT
,
358 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2
= {
359 .master
= &omap3xxx_l4_core_hwmod
,
360 .slave
= &omap3xxx_i2c2_hwmod
,
362 .addr
= omap3xxx_i2c2_addr_space
,
363 .addr_cnt
= ARRAY_SIZE(omap3xxx_i2c2_addr_space
),
366 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C2_REGION
,
368 .flags
= OMAP_FIREWALL_L4
,
371 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
374 /* L4 CORE -> I2C3 interface */
375 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space
[] = {
377 .pa_start
= 0x48060000,
378 .pa_end
= 0x48060000 + OMAP2_I2C_AS_LEN
- 1,
379 .flags
= ADDR_TYPE_RT
,
383 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3
= {
384 .master
= &omap3xxx_l4_core_hwmod
,
385 .slave
= &omap3xxx_i2c3_hwmod
,
387 .addr
= omap3xxx_i2c3_addr_space
,
388 .addr_cnt
= ARRAY_SIZE(omap3xxx_i2c3_addr_space
),
391 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C3_REGION
,
393 .flags
= OMAP_FIREWALL_L4
,
396 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
399 /* L4 CORE -> SR1 interface */
400 static struct omap_hwmod_addr_space omap3_sr1_addr_space
[] = {
402 .pa_start
= OMAP34XX_SR1_BASE
,
403 .pa_end
= OMAP34XX_SR1_BASE
+ SZ_1K
- 1,
404 .flags
= ADDR_TYPE_RT
,
408 static struct omap_hwmod_ocp_if omap3_l4_core__sr1
= {
409 .master
= &omap3xxx_l4_core_hwmod
,
410 .slave
= &omap34xx_sr1_hwmod
,
412 .addr
= omap3_sr1_addr_space
,
413 .addr_cnt
= ARRAY_SIZE(omap3_sr1_addr_space
),
414 .user
= OCP_USER_MPU
,
417 /* L4 CORE -> SR1 interface */
418 static struct omap_hwmod_addr_space omap3_sr2_addr_space
[] = {
420 .pa_start
= OMAP34XX_SR2_BASE
,
421 .pa_end
= OMAP34XX_SR2_BASE
+ SZ_1K
- 1,
422 .flags
= ADDR_TYPE_RT
,
426 static struct omap_hwmod_ocp_if omap3_l4_core__sr2
= {
427 .master
= &omap3xxx_l4_core_hwmod
,
428 .slave
= &omap34xx_sr2_hwmod
,
430 .addr
= omap3_sr2_addr_space
,
431 .addr_cnt
= ARRAY_SIZE(omap3_sr2_addr_space
),
432 .user
= OCP_USER_MPU
,
436 * usbhsotg interface data
439 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs
[] = {
441 .pa_start
= OMAP34XX_HSUSB_OTG_BASE
,
442 .pa_end
= OMAP34XX_HSUSB_OTG_BASE
+ SZ_4K
- 1,
443 .flags
= ADDR_TYPE_RT
447 /* l4_core -> usbhsotg */
448 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg
= {
449 .master
= &omap3xxx_l4_core_hwmod
,
450 .slave
= &omap3xxx_usbhsotg_hwmod
,
452 .addr
= omap3xxx_usbhsotg_addrs
,
453 .addr_cnt
= ARRAY_SIZE(omap3xxx_usbhsotg_addrs
),
454 .user
= OCP_USER_MPU
,
457 static struct omap_hwmod_ocp_if
*omap3xxx_usbhsotg_masters
[] = {
458 &omap3xxx_usbhsotg__l3
,
461 static struct omap_hwmod_ocp_if
*omap3xxx_usbhsotg_slaves
[] = {
462 &omap3xxx_l4_core__usbhsotg
,
465 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs
[] = {
467 .pa_start
= AM35XX_IPSS_USBOTGSS_BASE
,
468 .pa_end
= AM35XX_IPSS_USBOTGSS_BASE
+ SZ_4K
- 1,
469 .flags
= ADDR_TYPE_RT
473 /* l4_core -> usbhsotg */
474 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg
= {
475 .master
= &omap3xxx_l4_core_hwmod
,
476 .slave
= &am35xx_usbhsotg_hwmod
,
478 .addr
= am35xx_usbhsotg_addrs
,
479 .addr_cnt
= ARRAY_SIZE(am35xx_usbhsotg_addrs
),
480 .user
= OCP_USER_MPU
,
483 static struct omap_hwmod_ocp_if
*am35xx_usbhsotg_masters
[] = {
484 &am35xx_usbhsotg__l3
,
487 static struct omap_hwmod_ocp_if
*am35xx_usbhsotg_slaves
[] = {
488 &am35xx_l4_core__usbhsotg
,
490 /* Slave interfaces on the L4_CORE interconnect */
491 static struct omap_hwmod_ocp_if
*omap3xxx_l4_core_slaves
[] = {
492 &omap3xxx_l3_main__l4_core
,
496 static struct omap_hwmod omap3xxx_l4_core_hwmod
= {
498 .class = &l4_hwmod_class
,
499 .slaves
= omap3xxx_l4_core_slaves
,
500 .slaves_cnt
= ARRAY_SIZE(omap3xxx_l4_core_slaves
),
501 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
502 .flags
= HWMOD_NO_IDLEST
,
505 /* Slave interfaces on the L4_PER interconnect */
506 static struct omap_hwmod_ocp_if
*omap3xxx_l4_per_slaves
[] = {
507 &omap3xxx_l3_main__l4_per
,
511 static struct omap_hwmod omap3xxx_l4_per_hwmod
= {
513 .class = &l4_hwmod_class
,
514 .slaves
= omap3xxx_l4_per_slaves
,
515 .slaves_cnt
= ARRAY_SIZE(omap3xxx_l4_per_slaves
),
516 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
517 .flags
= HWMOD_NO_IDLEST
,
520 /* Slave interfaces on the L4_WKUP interconnect */
521 static struct omap_hwmod_ocp_if
*omap3xxx_l4_wkup_slaves
[] = {
522 &omap3xxx_l4_core__l4_wkup
,
526 static struct omap_hwmod omap3xxx_l4_wkup_hwmod
= {
528 .class = &l4_hwmod_class
,
529 .slaves
= omap3xxx_l4_wkup_slaves
,
530 .slaves_cnt
= ARRAY_SIZE(omap3xxx_l4_wkup_slaves
),
531 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
532 .flags
= HWMOD_NO_IDLEST
,
535 /* Master interfaces on the MPU device */
536 static struct omap_hwmod_ocp_if
*omap3xxx_mpu_masters
[] = {
537 &omap3xxx_mpu__l3_main
,
541 static struct omap_hwmod omap3xxx_mpu_hwmod
= {
543 .class = &mpu_hwmod_class
,
544 .main_clk
= "arm_fck",
545 .masters
= omap3xxx_mpu_masters
,
546 .masters_cnt
= ARRAY_SIZE(omap3xxx_mpu_masters
),
547 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
551 * IVA2_2 interface data
554 /* IVA2 <- L3 interface */
555 static struct omap_hwmod_ocp_if omap3xxx_l3__iva
= {
556 .master
= &omap3xxx_l3_main_hwmod
,
557 .slave
= &omap3xxx_iva_hwmod
,
559 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
562 static struct omap_hwmod_ocp_if
*omap3xxx_iva_masters
[] = {
570 static struct omap_hwmod omap3xxx_iva_hwmod
= {
572 .class = &iva_hwmod_class
,
573 .masters
= omap3xxx_iva_masters
,
574 .masters_cnt
= ARRAY_SIZE(omap3xxx_iva_masters
),
575 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
579 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc
= {
583 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
584 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
585 SYSC_HAS_EMUFREE
| SYSC_HAS_AUTOIDLE
),
586 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
587 .sysc_fields
= &omap_hwmod_sysc_type1
,
590 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class
= {
592 .sysc
= &omap3xxx_timer_1ms_sysc
,
593 .rev
= OMAP_TIMER_IP_VERSION_1
,
596 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc
= {
600 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
601 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
602 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
603 .sysc_fields
= &omap_hwmod_sysc_type1
,
606 static struct omap_hwmod_class omap3xxx_timer_hwmod_class
= {
608 .sysc
= &omap3xxx_timer_sysc
,
609 .rev
= OMAP_TIMER_IP_VERSION_1
,
613 static struct omap_hwmod omap3xxx_timer1_hwmod
;
614 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs
[] = {
618 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs
[] = {
620 .pa_start
= 0x48318000,
621 .pa_end
= 0x48318000 + SZ_1K
- 1,
622 .flags
= ADDR_TYPE_RT
626 /* l4_wkup -> timer1 */
627 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1
= {
628 .master
= &omap3xxx_l4_wkup_hwmod
,
629 .slave
= &omap3xxx_timer1_hwmod
,
631 .addr
= omap3xxx_timer1_addrs
,
632 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer1_addrs
),
633 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
636 /* timer1 slave port */
637 static struct omap_hwmod_ocp_if
*omap3xxx_timer1_slaves
[] = {
638 &omap3xxx_l4_wkup__timer1
,
642 static struct omap_hwmod omap3xxx_timer1_hwmod
= {
644 .mpu_irqs
= omap3xxx_timer1_mpu_irqs
,
645 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer1_mpu_irqs
),
646 .main_clk
= "gpt1_fck",
650 .module_bit
= OMAP3430_EN_GPT1_SHIFT
,
651 .module_offs
= WKUP_MOD
,
653 .idlest_idle_bit
= OMAP3430_ST_GPT1_SHIFT
,
656 .slaves
= omap3xxx_timer1_slaves
,
657 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer1_slaves
),
658 .class = &omap3xxx_timer_1ms_hwmod_class
,
659 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
663 static struct omap_hwmod omap3xxx_timer2_hwmod
;
664 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs
[] = {
668 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs
[] = {
670 .pa_start
= 0x49032000,
671 .pa_end
= 0x49032000 + SZ_1K
- 1,
672 .flags
= ADDR_TYPE_RT
676 /* l4_per -> timer2 */
677 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2
= {
678 .master
= &omap3xxx_l4_per_hwmod
,
679 .slave
= &omap3xxx_timer2_hwmod
,
681 .addr
= omap3xxx_timer2_addrs
,
682 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer2_addrs
),
683 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
686 /* timer2 slave port */
687 static struct omap_hwmod_ocp_if
*omap3xxx_timer2_slaves
[] = {
688 &omap3xxx_l4_per__timer2
,
692 static struct omap_hwmod omap3xxx_timer2_hwmod
= {
694 .mpu_irqs
= omap3xxx_timer2_mpu_irqs
,
695 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer2_mpu_irqs
),
696 .main_clk
= "gpt2_fck",
700 .module_bit
= OMAP3430_EN_GPT2_SHIFT
,
701 .module_offs
= OMAP3430_PER_MOD
,
703 .idlest_idle_bit
= OMAP3430_ST_GPT2_SHIFT
,
706 .slaves
= omap3xxx_timer2_slaves
,
707 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer2_slaves
),
708 .class = &omap3xxx_timer_1ms_hwmod_class
,
709 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
713 static struct omap_hwmod omap3xxx_timer3_hwmod
;
714 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs
[] = {
718 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs
[] = {
720 .pa_start
= 0x49034000,
721 .pa_end
= 0x49034000 + SZ_1K
- 1,
722 .flags
= ADDR_TYPE_RT
726 /* l4_per -> timer3 */
727 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3
= {
728 .master
= &omap3xxx_l4_per_hwmod
,
729 .slave
= &omap3xxx_timer3_hwmod
,
731 .addr
= omap3xxx_timer3_addrs
,
732 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer3_addrs
),
733 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
736 /* timer3 slave port */
737 static struct omap_hwmod_ocp_if
*omap3xxx_timer3_slaves
[] = {
738 &omap3xxx_l4_per__timer3
,
742 static struct omap_hwmod omap3xxx_timer3_hwmod
= {
744 .mpu_irqs
= omap3xxx_timer3_mpu_irqs
,
745 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer3_mpu_irqs
),
746 .main_clk
= "gpt3_fck",
750 .module_bit
= OMAP3430_EN_GPT3_SHIFT
,
751 .module_offs
= OMAP3430_PER_MOD
,
753 .idlest_idle_bit
= OMAP3430_ST_GPT3_SHIFT
,
756 .slaves
= omap3xxx_timer3_slaves
,
757 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer3_slaves
),
758 .class = &omap3xxx_timer_hwmod_class
,
759 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
763 static struct omap_hwmod omap3xxx_timer4_hwmod
;
764 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs
[] = {
768 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs
[] = {
770 .pa_start
= 0x49036000,
771 .pa_end
= 0x49036000 + SZ_1K
- 1,
772 .flags
= ADDR_TYPE_RT
776 /* l4_per -> timer4 */
777 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4
= {
778 .master
= &omap3xxx_l4_per_hwmod
,
779 .slave
= &omap3xxx_timer4_hwmod
,
781 .addr
= omap3xxx_timer4_addrs
,
782 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer4_addrs
),
783 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
786 /* timer4 slave port */
787 static struct omap_hwmod_ocp_if
*omap3xxx_timer4_slaves
[] = {
788 &omap3xxx_l4_per__timer4
,
792 static struct omap_hwmod omap3xxx_timer4_hwmod
= {
794 .mpu_irqs
= omap3xxx_timer4_mpu_irqs
,
795 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer4_mpu_irqs
),
796 .main_clk
= "gpt4_fck",
800 .module_bit
= OMAP3430_EN_GPT4_SHIFT
,
801 .module_offs
= OMAP3430_PER_MOD
,
803 .idlest_idle_bit
= OMAP3430_ST_GPT4_SHIFT
,
806 .slaves
= omap3xxx_timer4_slaves
,
807 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer4_slaves
),
808 .class = &omap3xxx_timer_hwmod_class
,
809 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
813 static struct omap_hwmod omap3xxx_timer5_hwmod
;
814 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs
[] = {
818 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs
[] = {
820 .pa_start
= 0x49038000,
821 .pa_end
= 0x49038000 + SZ_1K
- 1,
822 .flags
= ADDR_TYPE_RT
826 /* l4_per -> timer5 */
827 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5
= {
828 .master
= &omap3xxx_l4_per_hwmod
,
829 .slave
= &omap3xxx_timer5_hwmod
,
831 .addr
= omap3xxx_timer5_addrs
,
832 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer5_addrs
),
833 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
836 /* timer5 slave port */
837 static struct omap_hwmod_ocp_if
*omap3xxx_timer5_slaves
[] = {
838 &omap3xxx_l4_per__timer5
,
842 static struct omap_hwmod omap3xxx_timer5_hwmod
= {
844 .mpu_irqs
= omap3xxx_timer5_mpu_irqs
,
845 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer5_mpu_irqs
),
846 .main_clk
= "gpt5_fck",
850 .module_bit
= OMAP3430_EN_GPT5_SHIFT
,
851 .module_offs
= OMAP3430_PER_MOD
,
853 .idlest_idle_bit
= OMAP3430_ST_GPT5_SHIFT
,
856 .slaves
= omap3xxx_timer5_slaves
,
857 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer5_slaves
),
858 .class = &omap3xxx_timer_hwmod_class
,
859 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
863 static struct omap_hwmod omap3xxx_timer6_hwmod
;
864 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs
[] = {
868 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs
[] = {
870 .pa_start
= 0x4903A000,
871 .pa_end
= 0x4903A000 + SZ_1K
- 1,
872 .flags
= ADDR_TYPE_RT
876 /* l4_per -> timer6 */
877 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6
= {
878 .master
= &omap3xxx_l4_per_hwmod
,
879 .slave
= &omap3xxx_timer6_hwmod
,
881 .addr
= omap3xxx_timer6_addrs
,
882 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer6_addrs
),
883 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
886 /* timer6 slave port */
887 static struct omap_hwmod_ocp_if
*omap3xxx_timer6_slaves
[] = {
888 &omap3xxx_l4_per__timer6
,
892 static struct omap_hwmod omap3xxx_timer6_hwmod
= {
894 .mpu_irqs
= omap3xxx_timer6_mpu_irqs
,
895 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer6_mpu_irqs
),
896 .main_clk
= "gpt6_fck",
900 .module_bit
= OMAP3430_EN_GPT6_SHIFT
,
901 .module_offs
= OMAP3430_PER_MOD
,
903 .idlest_idle_bit
= OMAP3430_ST_GPT6_SHIFT
,
906 .slaves
= omap3xxx_timer6_slaves
,
907 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer6_slaves
),
908 .class = &omap3xxx_timer_hwmod_class
,
909 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
913 static struct omap_hwmod omap3xxx_timer7_hwmod
;
914 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs
[] = {
918 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs
[] = {
920 .pa_start
= 0x4903C000,
921 .pa_end
= 0x4903C000 + SZ_1K
- 1,
922 .flags
= ADDR_TYPE_RT
926 /* l4_per -> timer7 */
927 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7
= {
928 .master
= &omap3xxx_l4_per_hwmod
,
929 .slave
= &omap3xxx_timer7_hwmod
,
931 .addr
= omap3xxx_timer7_addrs
,
932 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer7_addrs
),
933 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
936 /* timer7 slave port */
937 static struct omap_hwmod_ocp_if
*omap3xxx_timer7_slaves
[] = {
938 &omap3xxx_l4_per__timer7
,
942 static struct omap_hwmod omap3xxx_timer7_hwmod
= {
944 .mpu_irqs
= omap3xxx_timer7_mpu_irqs
,
945 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer7_mpu_irqs
),
946 .main_clk
= "gpt7_fck",
950 .module_bit
= OMAP3430_EN_GPT7_SHIFT
,
951 .module_offs
= OMAP3430_PER_MOD
,
953 .idlest_idle_bit
= OMAP3430_ST_GPT7_SHIFT
,
956 .slaves
= omap3xxx_timer7_slaves
,
957 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer7_slaves
),
958 .class = &omap3xxx_timer_hwmod_class
,
959 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
963 static struct omap_hwmod omap3xxx_timer8_hwmod
;
964 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs
[] = {
968 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs
[] = {
970 .pa_start
= 0x4903E000,
971 .pa_end
= 0x4903E000 + SZ_1K
- 1,
972 .flags
= ADDR_TYPE_RT
976 /* l4_per -> timer8 */
977 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8
= {
978 .master
= &omap3xxx_l4_per_hwmod
,
979 .slave
= &omap3xxx_timer8_hwmod
,
981 .addr
= omap3xxx_timer8_addrs
,
982 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer8_addrs
),
983 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
986 /* timer8 slave port */
987 static struct omap_hwmod_ocp_if
*omap3xxx_timer8_slaves
[] = {
988 &omap3xxx_l4_per__timer8
,
992 static struct omap_hwmod omap3xxx_timer8_hwmod
= {
994 .mpu_irqs
= omap3xxx_timer8_mpu_irqs
,
995 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer8_mpu_irqs
),
996 .main_clk
= "gpt8_fck",
1000 .module_bit
= OMAP3430_EN_GPT8_SHIFT
,
1001 .module_offs
= OMAP3430_PER_MOD
,
1003 .idlest_idle_bit
= OMAP3430_ST_GPT8_SHIFT
,
1006 .slaves
= omap3xxx_timer8_slaves
,
1007 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer8_slaves
),
1008 .class = &omap3xxx_timer_hwmod_class
,
1009 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1013 static struct omap_hwmod omap3xxx_timer9_hwmod
;
1014 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs
[] = {
1018 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs
[] = {
1020 .pa_start
= 0x49040000,
1021 .pa_end
= 0x49040000 + SZ_1K
- 1,
1022 .flags
= ADDR_TYPE_RT
1026 /* l4_per -> timer9 */
1027 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9
= {
1028 .master
= &omap3xxx_l4_per_hwmod
,
1029 .slave
= &omap3xxx_timer9_hwmod
,
1031 .addr
= omap3xxx_timer9_addrs
,
1032 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer9_addrs
),
1033 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1036 /* timer9 slave port */
1037 static struct omap_hwmod_ocp_if
*omap3xxx_timer9_slaves
[] = {
1038 &omap3xxx_l4_per__timer9
,
1042 static struct omap_hwmod omap3xxx_timer9_hwmod
= {
1044 .mpu_irqs
= omap3xxx_timer9_mpu_irqs
,
1045 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer9_mpu_irqs
),
1046 .main_clk
= "gpt9_fck",
1050 .module_bit
= OMAP3430_EN_GPT9_SHIFT
,
1051 .module_offs
= OMAP3430_PER_MOD
,
1053 .idlest_idle_bit
= OMAP3430_ST_GPT9_SHIFT
,
1056 .slaves
= omap3xxx_timer9_slaves
,
1057 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer9_slaves
),
1058 .class = &omap3xxx_timer_hwmod_class
,
1059 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1063 static struct omap_hwmod omap3xxx_timer10_hwmod
;
1064 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs
[] = {
1068 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs
[] = {
1070 .pa_start
= 0x48086000,
1071 .pa_end
= 0x48086000 + SZ_1K
- 1,
1072 .flags
= ADDR_TYPE_RT
1076 /* l4_core -> timer10 */
1077 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10
= {
1078 .master
= &omap3xxx_l4_core_hwmod
,
1079 .slave
= &omap3xxx_timer10_hwmod
,
1081 .addr
= omap3xxx_timer10_addrs
,
1082 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer10_addrs
),
1083 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1086 /* timer10 slave port */
1087 static struct omap_hwmod_ocp_if
*omap3xxx_timer10_slaves
[] = {
1088 &omap3xxx_l4_core__timer10
,
1092 static struct omap_hwmod omap3xxx_timer10_hwmod
= {
1094 .mpu_irqs
= omap3xxx_timer10_mpu_irqs
,
1095 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer10_mpu_irqs
),
1096 .main_clk
= "gpt10_fck",
1100 .module_bit
= OMAP3430_EN_GPT10_SHIFT
,
1101 .module_offs
= CORE_MOD
,
1103 .idlest_idle_bit
= OMAP3430_ST_GPT10_SHIFT
,
1106 .slaves
= omap3xxx_timer10_slaves
,
1107 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer10_slaves
),
1108 .class = &omap3xxx_timer_1ms_hwmod_class
,
1109 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1113 static struct omap_hwmod omap3xxx_timer11_hwmod
;
1114 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs
[] = {
1118 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs
[] = {
1120 .pa_start
= 0x48088000,
1121 .pa_end
= 0x48088000 + SZ_1K
- 1,
1122 .flags
= ADDR_TYPE_RT
1126 /* l4_core -> timer11 */
1127 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11
= {
1128 .master
= &omap3xxx_l4_core_hwmod
,
1129 .slave
= &omap3xxx_timer11_hwmod
,
1131 .addr
= omap3xxx_timer11_addrs
,
1132 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer11_addrs
),
1133 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1136 /* timer11 slave port */
1137 static struct omap_hwmod_ocp_if
*omap3xxx_timer11_slaves
[] = {
1138 &omap3xxx_l4_core__timer11
,
1142 static struct omap_hwmod omap3xxx_timer11_hwmod
= {
1144 .mpu_irqs
= omap3xxx_timer11_mpu_irqs
,
1145 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer11_mpu_irqs
),
1146 .main_clk
= "gpt11_fck",
1150 .module_bit
= OMAP3430_EN_GPT11_SHIFT
,
1151 .module_offs
= CORE_MOD
,
1153 .idlest_idle_bit
= OMAP3430_ST_GPT11_SHIFT
,
1156 .slaves
= omap3xxx_timer11_slaves
,
1157 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer11_slaves
),
1158 .class = &omap3xxx_timer_hwmod_class
,
1159 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1163 static struct omap_hwmod omap3xxx_timer12_hwmod
;
1164 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs
[] = {
1168 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs
[] = {
1170 .pa_start
= 0x48304000,
1171 .pa_end
= 0x48304000 + SZ_1K
- 1,
1172 .flags
= ADDR_TYPE_RT
1176 /* l4_core -> timer12 */
1177 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12
= {
1178 .master
= &omap3xxx_l4_core_hwmod
,
1179 .slave
= &omap3xxx_timer12_hwmod
,
1181 .addr
= omap3xxx_timer12_addrs
,
1182 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer12_addrs
),
1183 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1186 /* timer12 slave port */
1187 static struct omap_hwmod_ocp_if
*omap3xxx_timer12_slaves
[] = {
1188 &omap3xxx_l4_core__timer12
,
1192 static struct omap_hwmod omap3xxx_timer12_hwmod
= {
1194 .mpu_irqs
= omap3xxx_timer12_mpu_irqs
,
1195 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer12_mpu_irqs
),
1196 .main_clk
= "gpt12_fck",
1200 .module_bit
= OMAP3430_EN_GPT12_SHIFT
,
1201 .module_offs
= WKUP_MOD
,
1203 .idlest_idle_bit
= OMAP3430_ST_GPT12_SHIFT
,
1206 .slaves
= omap3xxx_timer12_slaves
,
1207 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer12_slaves
),
1208 .class = &omap3xxx_timer_hwmod_class
,
1209 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1212 /* l4_wkup -> wd_timer2 */
1213 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs
[] = {
1215 .pa_start
= 0x48314000,
1216 .pa_end
= 0x4831407f,
1217 .flags
= ADDR_TYPE_RT
1221 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2
= {
1222 .master
= &omap3xxx_l4_wkup_hwmod
,
1223 .slave
= &omap3xxx_wd_timer2_hwmod
,
1225 .addr
= omap3xxx_wd_timer2_addrs
,
1226 .addr_cnt
= ARRAY_SIZE(omap3xxx_wd_timer2_addrs
),
1227 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1232 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1233 * overflow condition
1236 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc
= {
1238 .sysc_offs
= 0x0010,
1239 .syss_offs
= 0x0014,
1240 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_EMUFREE
|
1241 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1242 SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1243 SYSS_HAS_RESET_STATUS
),
1244 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1245 .sysc_fields
= &omap_hwmod_sysc_type1
,
1249 static struct omap_hwmod_class_sysconfig i2c_sysc
= {
1253 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1254 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1255 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1256 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1257 .sysc_fields
= &omap_hwmod_sysc_type1
,
1260 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class
= {
1262 .sysc
= &omap3xxx_wd_timer_sysc
,
1263 .pre_shutdown
= &omap2_wd_timer_disable
1267 static struct omap_hwmod_ocp_if
*omap3xxx_wd_timer2_slaves
[] = {
1268 &omap3xxx_l4_wkup__wd_timer2
,
1271 static struct omap_hwmod omap3xxx_wd_timer2_hwmod
= {
1272 .name
= "wd_timer2",
1273 .class = &omap3xxx_wd_timer_hwmod_class
,
1274 .main_clk
= "wdt2_fck",
1278 .module_bit
= OMAP3430_EN_WDT2_SHIFT
,
1279 .module_offs
= WKUP_MOD
,
1281 .idlest_idle_bit
= OMAP3430_ST_WDT2_SHIFT
,
1284 .slaves
= omap3xxx_wd_timer2_slaves
,
1285 .slaves_cnt
= ARRAY_SIZE(omap3xxx_wd_timer2_slaves
),
1286 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1288 * XXX: Use software supervised mode, HW supervised smartidle seems to
1289 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1291 .flags
= HWMOD_SWSUP_SIDLE
,
1296 static struct omap_hwmod_class_sysconfig uart_sysc
= {
1300 .sysc_flags
= (SYSC_HAS_SIDLEMODE
|
1301 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1302 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1303 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1304 .sysc_fields
= &omap_hwmod_sysc_type1
,
1307 static struct omap_hwmod_class uart_class
= {
1314 static struct omap_hwmod_irq_info uart1_mpu_irqs
[] = {
1315 { .irq
= INT_24XX_UART1_IRQ
, },
1318 static struct omap_hwmod_dma_info uart1_sdma_reqs
[] = {
1319 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART1_TX
, },
1320 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART1_RX
, },
1323 static struct omap_hwmod_ocp_if
*omap3xxx_uart1_slaves
[] = {
1324 &omap3_l4_core__uart1
,
1327 static struct omap_hwmod omap3xxx_uart1_hwmod
= {
1329 .mpu_irqs
= uart1_mpu_irqs
,
1330 .mpu_irqs_cnt
= ARRAY_SIZE(uart1_mpu_irqs
),
1331 .sdma_reqs
= uart1_sdma_reqs
,
1332 .sdma_reqs_cnt
= ARRAY_SIZE(uart1_sdma_reqs
),
1333 .main_clk
= "uart1_fck",
1336 .module_offs
= CORE_MOD
,
1338 .module_bit
= OMAP3430_EN_UART1_SHIFT
,
1340 .idlest_idle_bit
= OMAP3430_EN_UART1_SHIFT
,
1343 .slaves
= omap3xxx_uart1_slaves
,
1344 .slaves_cnt
= ARRAY_SIZE(omap3xxx_uart1_slaves
),
1345 .class = &uart_class
,
1346 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1351 static struct omap_hwmod_irq_info uart2_mpu_irqs
[] = {
1352 { .irq
= INT_24XX_UART2_IRQ
, },
1355 static struct omap_hwmod_dma_info uart2_sdma_reqs
[] = {
1356 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART2_TX
, },
1357 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART2_RX
, },
1360 static struct omap_hwmod_ocp_if
*omap3xxx_uart2_slaves
[] = {
1361 &omap3_l4_core__uart2
,
1364 static struct omap_hwmod omap3xxx_uart2_hwmod
= {
1366 .mpu_irqs
= uart2_mpu_irqs
,
1367 .mpu_irqs_cnt
= ARRAY_SIZE(uart2_mpu_irqs
),
1368 .sdma_reqs
= uart2_sdma_reqs
,
1369 .sdma_reqs_cnt
= ARRAY_SIZE(uart2_sdma_reqs
),
1370 .main_clk
= "uart2_fck",
1373 .module_offs
= CORE_MOD
,
1375 .module_bit
= OMAP3430_EN_UART2_SHIFT
,
1377 .idlest_idle_bit
= OMAP3430_EN_UART2_SHIFT
,
1380 .slaves
= omap3xxx_uart2_slaves
,
1381 .slaves_cnt
= ARRAY_SIZE(omap3xxx_uart2_slaves
),
1382 .class = &uart_class
,
1383 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1388 static struct omap_hwmod_irq_info uart3_mpu_irqs
[] = {
1389 { .irq
= INT_24XX_UART3_IRQ
, },
1392 static struct omap_hwmod_dma_info uart3_sdma_reqs
[] = {
1393 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART3_TX
, },
1394 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART3_RX
, },
1397 static struct omap_hwmod_ocp_if
*omap3xxx_uart3_slaves
[] = {
1398 &omap3_l4_per__uart3
,
1401 static struct omap_hwmod omap3xxx_uart3_hwmod
= {
1403 .mpu_irqs
= uart3_mpu_irqs
,
1404 .mpu_irqs_cnt
= ARRAY_SIZE(uart3_mpu_irqs
),
1405 .sdma_reqs
= uart3_sdma_reqs
,
1406 .sdma_reqs_cnt
= ARRAY_SIZE(uart3_sdma_reqs
),
1407 .main_clk
= "uart3_fck",
1410 .module_offs
= OMAP3430_PER_MOD
,
1412 .module_bit
= OMAP3430_EN_UART3_SHIFT
,
1414 .idlest_idle_bit
= OMAP3430_EN_UART3_SHIFT
,
1417 .slaves
= omap3xxx_uart3_slaves
,
1418 .slaves_cnt
= ARRAY_SIZE(omap3xxx_uart3_slaves
),
1419 .class = &uart_class
,
1420 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1425 static struct omap_hwmod_irq_info uart4_mpu_irqs
[] = {
1426 { .irq
= INT_36XX_UART4_IRQ
, },
1429 static struct omap_hwmod_dma_info uart4_sdma_reqs
[] = {
1430 { .name
= "rx", .dma_req
= OMAP36XX_DMA_UART4_RX
, },
1431 { .name
= "tx", .dma_req
= OMAP36XX_DMA_UART4_TX
, },
1434 static struct omap_hwmod_ocp_if
*omap3xxx_uart4_slaves
[] = {
1435 &omap3_l4_per__uart4
,
1438 static struct omap_hwmod omap3xxx_uart4_hwmod
= {
1440 .mpu_irqs
= uart4_mpu_irqs
,
1441 .mpu_irqs_cnt
= ARRAY_SIZE(uart4_mpu_irqs
),
1442 .sdma_reqs
= uart4_sdma_reqs
,
1443 .sdma_reqs_cnt
= ARRAY_SIZE(uart4_sdma_reqs
),
1444 .main_clk
= "uart4_fck",
1447 .module_offs
= OMAP3430_PER_MOD
,
1449 .module_bit
= OMAP3630_EN_UART4_SHIFT
,
1451 .idlest_idle_bit
= OMAP3630_EN_UART4_SHIFT
,
1454 .slaves
= omap3xxx_uart4_slaves
,
1455 .slaves_cnt
= ARRAY_SIZE(omap3xxx_uart4_slaves
),
1456 .class = &uart_class
,
1457 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1
),
1460 static struct omap_hwmod_class i2c_class
= {
1467 * display sub-system
1470 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc
= {
1472 .sysc_offs
= 0x0010,
1473 .syss_offs
= 0x0014,
1474 .sysc_flags
= (SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1475 .sysc_fields
= &omap_hwmod_sysc_type1
,
1478 static struct omap_hwmod_class omap3xxx_dss_hwmod_class
= {
1480 .sysc
= &omap3xxx_dss_sysc
,
1483 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs
[] = {
1484 { .name
= "dispc", .dma_req
= 5 },
1485 { .name
= "dsi1", .dma_req
= 74 },
1489 /* dss master ports */
1490 static struct omap_hwmod_ocp_if
*omap3xxx_dss_masters
[] = {
1494 static struct omap_hwmod_addr_space omap3xxx_dss_addrs
[] = {
1496 .pa_start
= 0x48050000,
1497 .pa_end
= 0x480503FF,
1498 .flags
= ADDR_TYPE_RT
1502 /* l4_core -> dss */
1503 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss
= {
1504 .master
= &omap3xxx_l4_core_hwmod
,
1505 .slave
= &omap3430es1_dss_core_hwmod
,
1507 .addr
= omap3xxx_dss_addrs
,
1508 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_addrs
),
1511 .l4_fw_region
= OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION
,
1512 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1513 .flags
= OMAP_FIREWALL_L4
,
1516 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1519 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss
= {
1520 .master
= &omap3xxx_l4_core_hwmod
,
1521 .slave
= &omap3xxx_dss_core_hwmod
,
1523 .addr
= omap3xxx_dss_addrs
,
1524 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_addrs
),
1527 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_CORE_REGION
,
1528 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1529 .flags
= OMAP_FIREWALL_L4
,
1532 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1535 /* dss slave ports */
1536 static struct omap_hwmod_ocp_if
*omap3430es1_dss_slaves
[] = {
1537 &omap3430es1_l4_core__dss
,
1540 static struct omap_hwmod_ocp_if
*omap3xxx_dss_slaves
[] = {
1541 &omap3xxx_l4_core__dss
,
1544 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
1545 { .role
= "tv_clk", .clk
= "dss_tv_fck" },
1546 { .role
= "video_clk", .clk
= "dss_96m_fck" },
1547 { .role
= "sys_clk", .clk
= "dss2_alwon_fck" },
1550 static struct omap_hwmod omap3430es1_dss_core_hwmod
= {
1552 .class = &omap3xxx_dss_hwmod_class
,
1553 .main_clk
= "dss1_alwon_fck", /* instead of dss_fck */
1554 .sdma_reqs
= omap3xxx_dss_sdma_chs
,
1555 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_dss_sdma_chs
),
1560 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1561 .module_offs
= OMAP3430_DSS_MOD
,
1563 .idlest_stdby_bit
= OMAP3430ES1_ST_DSS_SHIFT
,
1566 .opt_clks
= dss_opt_clks
,
1567 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
1568 .slaves
= omap3430es1_dss_slaves
,
1569 .slaves_cnt
= ARRAY_SIZE(omap3430es1_dss_slaves
),
1570 .masters
= omap3xxx_dss_masters
,
1571 .masters_cnt
= ARRAY_SIZE(omap3xxx_dss_masters
),
1572 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
),
1573 .flags
= HWMOD_NO_IDLEST
,
1576 static struct omap_hwmod omap3xxx_dss_core_hwmod
= {
1578 .class = &omap3xxx_dss_hwmod_class
,
1579 .main_clk
= "dss1_alwon_fck", /* instead of dss_fck */
1580 .sdma_reqs
= omap3xxx_dss_sdma_chs
,
1581 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_dss_sdma_chs
),
1586 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1587 .module_offs
= OMAP3430_DSS_MOD
,
1589 .idlest_idle_bit
= OMAP3430ES2_ST_DSS_IDLE_SHIFT
,
1590 .idlest_stdby_bit
= OMAP3430ES2_ST_DSS_STDBY_SHIFT
,
1593 .opt_clks
= dss_opt_clks
,
1594 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
1595 .slaves
= omap3xxx_dss_slaves
,
1596 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_slaves
),
1597 .masters
= omap3xxx_dss_masters
,
1598 .masters_cnt
= ARRAY_SIZE(omap3xxx_dss_masters
),
1599 .omap_chip
= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2
|
1600 CHIP_IS_OMAP3630ES1
| CHIP_GE_OMAP3630ES1_1
),
1605 * display controller
1608 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc
= {
1610 .sysc_offs
= 0x0010,
1611 .syss_offs
= 0x0014,
1612 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
1613 SYSC_HAS_MIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1614 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1615 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1616 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1617 .sysc_fields
= &omap_hwmod_sysc_type1
,
1620 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class
= {
1622 .sysc
= &omap3xxx_dispc_sysc
,
1625 static struct omap_hwmod_irq_info omap3xxx_dispc_irqs
[] = {
1629 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs
[] = {
1631 .pa_start
= 0x48050400,
1632 .pa_end
= 0x480507FF,
1633 .flags
= ADDR_TYPE_RT
1637 /* l4_core -> dss_dispc */
1638 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc
= {
1639 .master
= &omap3xxx_l4_core_hwmod
,
1640 .slave
= &omap3xxx_dss_dispc_hwmod
,
1642 .addr
= omap3xxx_dss_dispc_addrs
,
1643 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_dispc_addrs
),
1646 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_DISPC_REGION
,
1647 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1648 .flags
= OMAP_FIREWALL_L4
,
1651 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1654 /* dss_dispc slave ports */
1655 static struct omap_hwmod_ocp_if
*omap3xxx_dss_dispc_slaves
[] = {
1656 &omap3xxx_l4_core__dss_dispc
,
1659 static struct omap_hwmod omap3xxx_dss_dispc_hwmod
= {
1660 .name
= "dss_dispc",
1661 .class = &omap3xxx_dispc_hwmod_class
,
1662 .mpu_irqs
= omap3xxx_dispc_irqs
,
1663 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_dispc_irqs
),
1664 .main_clk
= "dss1_alwon_fck",
1668 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1669 .module_offs
= OMAP3430_DSS_MOD
,
1672 .slaves
= omap3xxx_dss_dispc_slaves
,
1673 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_dispc_slaves
),
1674 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
1675 CHIP_GE_OMAP3430ES2
| CHIP_IS_OMAP3630ES1
|
1676 CHIP_GE_OMAP3630ES1_1
),
1677 .flags
= HWMOD_NO_IDLEST
,
1682 * display serial interface controller
1685 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class
= {
1689 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs
[] = {
1694 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs
[] = {
1696 .pa_start
= 0x4804FC00,
1697 .pa_end
= 0x4804FFFF,
1698 .flags
= ADDR_TYPE_RT
1702 /* l4_core -> dss_dsi1 */
1703 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1
= {
1704 .master
= &omap3xxx_l4_core_hwmod
,
1705 .slave
= &omap3xxx_dss_dsi1_hwmod
,
1706 .addr
= omap3xxx_dss_dsi1_addrs
,
1707 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_dsi1_addrs
),
1710 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_DSI_REGION
,
1711 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1712 .flags
= OMAP_FIREWALL_L4
,
1715 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1718 /* dss_dsi1 slave ports */
1719 static struct omap_hwmod_ocp_if
*omap3xxx_dss_dsi1_slaves
[] = {
1720 &omap3xxx_l4_core__dss_dsi1
,
1723 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod
= {
1725 .class = &omap3xxx_dsi_hwmod_class
,
1726 .mpu_irqs
= omap3xxx_dsi1_irqs
,
1727 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_dsi1_irqs
),
1728 .main_clk
= "dss1_alwon_fck",
1732 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1733 .module_offs
= OMAP3430_DSS_MOD
,
1736 .slaves
= omap3xxx_dss_dsi1_slaves
,
1737 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_dsi1_slaves
),
1738 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
1739 CHIP_GE_OMAP3430ES2
| CHIP_IS_OMAP3630ES1
|
1740 CHIP_GE_OMAP3630ES1_1
),
1741 .flags
= HWMOD_NO_IDLEST
,
1746 * remote frame buffer interface
1749 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc
= {
1751 .sysc_offs
= 0x0010,
1752 .syss_offs
= 0x0014,
1753 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1755 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1756 .sysc_fields
= &omap_hwmod_sysc_type1
,
1759 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class
= {
1761 .sysc
= &omap3xxx_rfbi_sysc
,
1764 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs
[] = {
1766 .pa_start
= 0x48050800,
1767 .pa_end
= 0x48050BFF,
1768 .flags
= ADDR_TYPE_RT
1772 /* l4_core -> dss_rfbi */
1773 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi
= {
1774 .master
= &omap3xxx_l4_core_hwmod
,
1775 .slave
= &omap3xxx_dss_rfbi_hwmod
,
1777 .addr
= omap3xxx_dss_rfbi_addrs
,
1778 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_rfbi_addrs
),
1781 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_RFBI_REGION
,
1782 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1783 .flags
= OMAP_FIREWALL_L4
,
1786 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1789 /* dss_rfbi slave ports */
1790 static struct omap_hwmod_ocp_if
*omap3xxx_dss_rfbi_slaves
[] = {
1791 &omap3xxx_l4_core__dss_rfbi
,
1794 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod
= {
1796 .class = &omap3xxx_rfbi_hwmod_class
,
1797 .main_clk
= "dss1_alwon_fck",
1801 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1802 .module_offs
= OMAP3430_DSS_MOD
,
1805 .slaves
= omap3xxx_dss_rfbi_slaves
,
1806 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_rfbi_slaves
),
1807 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
1808 CHIP_GE_OMAP3430ES2
| CHIP_IS_OMAP3630ES1
|
1809 CHIP_GE_OMAP3630ES1_1
),
1810 .flags
= HWMOD_NO_IDLEST
,
1818 static struct omap_hwmod_class omap3xxx_venc_hwmod_class
= {
1823 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs
[] = {
1825 .pa_start
= 0x48050C00,
1826 .pa_end
= 0x48050FFF,
1827 .flags
= ADDR_TYPE_RT
1831 /* l4_core -> dss_venc */
1832 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc
= {
1833 .master
= &omap3xxx_l4_core_hwmod
,
1834 .slave
= &omap3xxx_dss_venc_hwmod
,
1835 .clk
= "dss_tv_fck",
1836 .addr
= omap3xxx_dss_venc_addrs
,
1837 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_venc_addrs
),
1840 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_VENC_REGION
,
1841 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1842 .flags
= OMAP_FIREWALL_L4
,
1845 .flags
= OCPIF_SWSUP_IDLE
,
1846 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1849 /* dss_venc slave ports */
1850 static struct omap_hwmod_ocp_if
*omap3xxx_dss_venc_slaves
[] = {
1851 &omap3xxx_l4_core__dss_venc
,
1854 static struct omap_hwmod omap3xxx_dss_venc_hwmod
= {
1856 .class = &omap3xxx_venc_hwmod_class
,
1857 .main_clk
= "dss1_alwon_fck",
1861 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1862 .module_offs
= OMAP3430_DSS_MOD
,
1865 .slaves
= omap3xxx_dss_venc_slaves
,
1866 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_venc_slaves
),
1867 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
1868 CHIP_GE_OMAP3430ES2
| CHIP_IS_OMAP3630ES1
|
1869 CHIP_GE_OMAP3630ES1_1
),
1870 .flags
= HWMOD_NO_IDLEST
,
1875 static struct omap_i2c_dev_attr i2c1_dev_attr
= {
1876 .fifo_depth
= 8, /* bytes */
1879 static struct omap_hwmod_irq_info i2c1_mpu_irqs
[] = {
1880 { .irq
= INT_24XX_I2C1_IRQ
, },
1883 static struct omap_hwmod_dma_info i2c1_sdma_reqs
[] = {
1884 { .name
= "tx", .dma_req
= OMAP24XX_DMA_I2C1_TX
},
1885 { .name
= "rx", .dma_req
= OMAP24XX_DMA_I2C1_RX
},
1888 static struct omap_hwmod_ocp_if
*omap3xxx_i2c1_slaves
[] = {
1889 &omap3_l4_core__i2c1
,
1892 static struct omap_hwmod omap3xxx_i2c1_hwmod
= {
1894 .mpu_irqs
= i2c1_mpu_irqs
,
1895 .mpu_irqs_cnt
= ARRAY_SIZE(i2c1_mpu_irqs
),
1896 .sdma_reqs
= i2c1_sdma_reqs
,
1897 .sdma_reqs_cnt
= ARRAY_SIZE(i2c1_sdma_reqs
),
1898 .main_clk
= "i2c1_fck",
1901 .module_offs
= CORE_MOD
,
1903 .module_bit
= OMAP3430_EN_I2C1_SHIFT
,
1905 .idlest_idle_bit
= OMAP3430_ST_I2C1_SHIFT
,
1908 .slaves
= omap3xxx_i2c1_slaves
,
1909 .slaves_cnt
= ARRAY_SIZE(omap3xxx_i2c1_slaves
),
1910 .class = &i2c_class
,
1911 .dev_attr
= &i2c1_dev_attr
,
1912 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1917 static struct omap_i2c_dev_attr i2c2_dev_attr
= {
1918 .fifo_depth
= 8, /* bytes */
1921 static struct omap_hwmod_irq_info i2c2_mpu_irqs
[] = {
1922 { .irq
= INT_24XX_I2C2_IRQ
, },
1925 static struct omap_hwmod_dma_info i2c2_sdma_reqs
[] = {
1926 { .name
= "tx", .dma_req
= OMAP24XX_DMA_I2C2_TX
},
1927 { .name
= "rx", .dma_req
= OMAP24XX_DMA_I2C2_RX
},
1930 static struct omap_hwmod_ocp_if
*omap3xxx_i2c2_slaves
[] = {
1931 &omap3_l4_core__i2c2
,
1934 static struct omap_hwmod omap3xxx_i2c2_hwmod
= {
1936 .mpu_irqs
= i2c2_mpu_irqs
,
1937 .mpu_irqs_cnt
= ARRAY_SIZE(i2c2_mpu_irqs
),
1938 .sdma_reqs
= i2c2_sdma_reqs
,
1939 .sdma_reqs_cnt
= ARRAY_SIZE(i2c2_sdma_reqs
),
1940 .main_clk
= "i2c2_fck",
1943 .module_offs
= CORE_MOD
,
1945 .module_bit
= OMAP3430_EN_I2C2_SHIFT
,
1947 .idlest_idle_bit
= OMAP3430_ST_I2C2_SHIFT
,
1950 .slaves
= omap3xxx_i2c2_slaves
,
1951 .slaves_cnt
= ARRAY_SIZE(omap3xxx_i2c2_slaves
),
1952 .class = &i2c_class
,
1953 .dev_attr
= &i2c2_dev_attr
,
1954 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1959 static struct omap_i2c_dev_attr i2c3_dev_attr
= {
1960 .fifo_depth
= 64, /* bytes */
1963 static struct omap_hwmod_irq_info i2c3_mpu_irqs
[] = {
1964 { .irq
= INT_34XX_I2C3_IRQ
, },
1967 static struct omap_hwmod_dma_info i2c3_sdma_reqs
[] = {
1968 { .name
= "tx", .dma_req
= OMAP34XX_DMA_I2C3_TX
},
1969 { .name
= "rx", .dma_req
= OMAP34XX_DMA_I2C3_RX
},
1972 static struct omap_hwmod_ocp_if
*omap3xxx_i2c3_slaves
[] = {
1973 &omap3_l4_core__i2c3
,
1976 static struct omap_hwmod omap3xxx_i2c3_hwmod
= {
1978 .mpu_irqs
= i2c3_mpu_irqs
,
1979 .mpu_irqs_cnt
= ARRAY_SIZE(i2c3_mpu_irqs
),
1980 .sdma_reqs
= i2c3_sdma_reqs
,
1981 .sdma_reqs_cnt
= ARRAY_SIZE(i2c3_sdma_reqs
),
1982 .main_clk
= "i2c3_fck",
1985 .module_offs
= CORE_MOD
,
1987 .module_bit
= OMAP3430_EN_I2C3_SHIFT
,
1989 .idlest_idle_bit
= OMAP3430_ST_I2C3_SHIFT
,
1992 .slaves
= omap3xxx_i2c3_slaves
,
1993 .slaves_cnt
= ARRAY_SIZE(omap3xxx_i2c3_slaves
),
1994 .class = &i2c_class
,
1995 .dev_attr
= &i2c3_dev_attr
,
1996 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1999 /* l4_wkup -> gpio1 */
2000 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs
[] = {
2002 .pa_start
= 0x48310000,
2003 .pa_end
= 0x483101ff,
2004 .flags
= ADDR_TYPE_RT
2008 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1
= {
2009 .master
= &omap3xxx_l4_wkup_hwmod
,
2010 .slave
= &omap3xxx_gpio1_hwmod
,
2011 .addr
= omap3xxx_gpio1_addrs
,
2012 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio1_addrs
),
2013 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2016 /* l4_per -> gpio2 */
2017 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs
[] = {
2019 .pa_start
= 0x49050000,
2020 .pa_end
= 0x490501ff,
2021 .flags
= ADDR_TYPE_RT
2025 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2
= {
2026 .master
= &omap3xxx_l4_per_hwmod
,
2027 .slave
= &omap3xxx_gpio2_hwmod
,
2028 .addr
= omap3xxx_gpio2_addrs
,
2029 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio2_addrs
),
2030 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2033 /* l4_per -> gpio3 */
2034 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs
[] = {
2036 .pa_start
= 0x49052000,
2037 .pa_end
= 0x490521ff,
2038 .flags
= ADDR_TYPE_RT
2042 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3
= {
2043 .master
= &omap3xxx_l4_per_hwmod
,
2044 .slave
= &omap3xxx_gpio3_hwmod
,
2045 .addr
= omap3xxx_gpio3_addrs
,
2046 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio3_addrs
),
2047 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2050 /* l4_per -> gpio4 */
2051 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs
[] = {
2053 .pa_start
= 0x49054000,
2054 .pa_end
= 0x490541ff,
2055 .flags
= ADDR_TYPE_RT
2059 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4
= {
2060 .master
= &omap3xxx_l4_per_hwmod
,
2061 .slave
= &omap3xxx_gpio4_hwmod
,
2062 .addr
= omap3xxx_gpio4_addrs
,
2063 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio4_addrs
),
2064 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2067 /* l4_per -> gpio5 */
2068 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs
[] = {
2070 .pa_start
= 0x49056000,
2071 .pa_end
= 0x490561ff,
2072 .flags
= ADDR_TYPE_RT
2076 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5
= {
2077 .master
= &omap3xxx_l4_per_hwmod
,
2078 .slave
= &omap3xxx_gpio5_hwmod
,
2079 .addr
= omap3xxx_gpio5_addrs
,
2080 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio5_addrs
),
2081 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2084 /* l4_per -> gpio6 */
2085 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs
[] = {
2087 .pa_start
= 0x49058000,
2088 .pa_end
= 0x490581ff,
2089 .flags
= ADDR_TYPE_RT
2093 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6
= {
2094 .master
= &omap3xxx_l4_per_hwmod
,
2095 .slave
= &omap3xxx_gpio6_hwmod
,
2096 .addr
= omap3xxx_gpio6_addrs
,
2097 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio6_addrs
),
2098 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2103 * general purpose io module
2106 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc
= {
2108 .sysc_offs
= 0x0010,
2109 .syss_offs
= 0x0014,
2110 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
2111 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
2112 SYSS_HAS_RESET_STATUS
),
2113 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2114 .sysc_fields
= &omap_hwmod_sysc_type1
,
2117 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class
= {
2119 .sysc
= &omap3xxx_gpio_sysc
,
2124 static struct omap_gpio_dev_attr gpio_dev_attr
= {
2130 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs
[] = {
2131 { .irq
= 29 }, /* INT_34XX_GPIO_BANK1 */
2134 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
2135 { .role
= "dbclk", .clk
= "gpio1_dbck", },
2138 static struct omap_hwmod_ocp_if
*omap3xxx_gpio1_slaves
[] = {
2139 &omap3xxx_l4_wkup__gpio1
,
2142 static struct omap_hwmod omap3xxx_gpio1_hwmod
= {
2144 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
2145 .mpu_irqs
= omap3xxx_gpio1_irqs
,
2146 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio1_irqs
),
2147 .main_clk
= "gpio1_ick",
2148 .opt_clks
= gpio1_opt_clks
,
2149 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
2153 .module_bit
= OMAP3430_EN_GPIO1_SHIFT
,
2154 .module_offs
= WKUP_MOD
,
2156 .idlest_idle_bit
= OMAP3430_ST_GPIO1_SHIFT
,
2159 .slaves
= omap3xxx_gpio1_slaves
,
2160 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio1_slaves
),
2161 .class = &omap3xxx_gpio_hwmod_class
,
2162 .dev_attr
= &gpio_dev_attr
,
2163 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2167 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs
[] = {
2168 { .irq
= 30 }, /* INT_34XX_GPIO_BANK2 */
2171 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
2172 { .role
= "dbclk", .clk
= "gpio2_dbck", },
2175 static struct omap_hwmod_ocp_if
*omap3xxx_gpio2_slaves
[] = {
2176 &omap3xxx_l4_per__gpio2
,
2179 static struct omap_hwmod omap3xxx_gpio2_hwmod
= {
2181 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
2182 .mpu_irqs
= omap3xxx_gpio2_irqs
,
2183 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio2_irqs
),
2184 .main_clk
= "gpio2_ick",
2185 .opt_clks
= gpio2_opt_clks
,
2186 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
2190 .module_bit
= OMAP3430_EN_GPIO2_SHIFT
,
2191 .module_offs
= OMAP3430_PER_MOD
,
2193 .idlest_idle_bit
= OMAP3430_ST_GPIO2_SHIFT
,
2196 .slaves
= omap3xxx_gpio2_slaves
,
2197 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio2_slaves
),
2198 .class = &omap3xxx_gpio_hwmod_class
,
2199 .dev_attr
= &gpio_dev_attr
,
2200 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2204 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs
[] = {
2205 { .irq
= 31 }, /* INT_34XX_GPIO_BANK3 */
2208 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
2209 { .role
= "dbclk", .clk
= "gpio3_dbck", },
2212 static struct omap_hwmod_ocp_if
*omap3xxx_gpio3_slaves
[] = {
2213 &omap3xxx_l4_per__gpio3
,
2216 static struct omap_hwmod omap3xxx_gpio3_hwmod
= {
2218 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
2219 .mpu_irqs
= omap3xxx_gpio3_irqs
,
2220 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio3_irqs
),
2221 .main_clk
= "gpio3_ick",
2222 .opt_clks
= gpio3_opt_clks
,
2223 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
2227 .module_bit
= OMAP3430_EN_GPIO3_SHIFT
,
2228 .module_offs
= OMAP3430_PER_MOD
,
2230 .idlest_idle_bit
= OMAP3430_ST_GPIO3_SHIFT
,
2233 .slaves
= omap3xxx_gpio3_slaves
,
2234 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio3_slaves
),
2235 .class = &omap3xxx_gpio_hwmod_class
,
2236 .dev_attr
= &gpio_dev_attr
,
2237 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2241 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs
[] = {
2242 { .irq
= 32 }, /* INT_34XX_GPIO_BANK4 */
2245 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
2246 { .role
= "dbclk", .clk
= "gpio4_dbck", },
2249 static struct omap_hwmod_ocp_if
*omap3xxx_gpio4_slaves
[] = {
2250 &omap3xxx_l4_per__gpio4
,
2253 static struct omap_hwmod omap3xxx_gpio4_hwmod
= {
2255 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
2256 .mpu_irqs
= omap3xxx_gpio4_irqs
,
2257 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio4_irqs
),
2258 .main_clk
= "gpio4_ick",
2259 .opt_clks
= gpio4_opt_clks
,
2260 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
2264 .module_bit
= OMAP3430_EN_GPIO4_SHIFT
,
2265 .module_offs
= OMAP3430_PER_MOD
,
2267 .idlest_idle_bit
= OMAP3430_ST_GPIO4_SHIFT
,
2270 .slaves
= omap3xxx_gpio4_slaves
,
2271 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio4_slaves
),
2272 .class = &omap3xxx_gpio_hwmod_class
,
2273 .dev_attr
= &gpio_dev_attr
,
2274 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2278 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs
[] = {
2279 { .irq
= 33 }, /* INT_34XX_GPIO_BANK5 */
2282 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
2283 { .role
= "dbclk", .clk
= "gpio5_dbck", },
2286 static struct omap_hwmod_ocp_if
*omap3xxx_gpio5_slaves
[] = {
2287 &omap3xxx_l4_per__gpio5
,
2290 static struct omap_hwmod omap3xxx_gpio5_hwmod
= {
2292 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
2293 .mpu_irqs
= omap3xxx_gpio5_irqs
,
2294 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio5_irqs
),
2295 .main_clk
= "gpio5_ick",
2296 .opt_clks
= gpio5_opt_clks
,
2297 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
2301 .module_bit
= OMAP3430_EN_GPIO5_SHIFT
,
2302 .module_offs
= OMAP3430_PER_MOD
,
2304 .idlest_idle_bit
= OMAP3430_ST_GPIO5_SHIFT
,
2307 .slaves
= omap3xxx_gpio5_slaves
,
2308 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio5_slaves
),
2309 .class = &omap3xxx_gpio_hwmod_class
,
2310 .dev_attr
= &gpio_dev_attr
,
2311 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2315 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs
[] = {
2316 { .irq
= 34 }, /* INT_34XX_GPIO_BANK6 */
2319 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
2320 { .role
= "dbclk", .clk
= "gpio6_dbck", },
2323 static struct omap_hwmod_ocp_if
*omap3xxx_gpio6_slaves
[] = {
2324 &omap3xxx_l4_per__gpio6
,
2327 static struct omap_hwmod omap3xxx_gpio6_hwmod
= {
2329 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
2330 .mpu_irqs
= omap3xxx_gpio6_irqs
,
2331 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio6_irqs
),
2332 .main_clk
= "gpio6_ick",
2333 .opt_clks
= gpio6_opt_clks
,
2334 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
2338 .module_bit
= OMAP3430_EN_GPIO6_SHIFT
,
2339 .module_offs
= OMAP3430_PER_MOD
,
2341 .idlest_idle_bit
= OMAP3430_ST_GPIO6_SHIFT
,
2344 .slaves
= omap3xxx_gpio6_slaves
,
2345 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio6_slaves
),
2346 .class = &omap3xxx_gpio_hwmod_class
,
2347 .dev_attr
= &gpio_dev_attr
,
2348 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2351 /* dma_system -> L3 */
2352 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3
= {
2353 .master
= &omap3xxx_dma_system_hwmod
,
2354 .slave
= &omap3xxx_l3_main_hwmod
,
2355 .clk
= "core_l3_ick",
2356 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2359 /* dma attributes */
2360 static struct omap_dma_dev_attr dma_dev_attr
= {
2361 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
2362 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
2366 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc
= {
2368 .sysc_offs
= 0x002c,
2369 .syss_offs
= 0x0028,
2370 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2371 SYSC_HAS_MIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
2372 SYSC_HAS_EMUFREE
| SYSC_HAS_AUTOIDLE
|
2373 SYSS_HAS_RESET_STATUS
),
2374 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2375 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
2376 .sysc_fields
= &omap_hwmod_sysc_type1
,
2379 static struct omap_hwmod_class omap3xxx_dma_hwmod_class
= {
2381 .sysc
= &omap3xxx_dma_sysc
,
2385 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs
[] = {
2386 { .name
= "0", .irq
= 12 }, /* INT_24XX_SDMA_IRQ0 */
2387 { .name
= "1", .irq
= 13 }, /* INT_24XX_SDMA_IRQ1 */
2388 { .name
= "2", .irq
= 14 }, /* INT_24XX_SDMA_IRQ2 */
2389 { .name
= "3", .irq
= 15 }, /* INT_24XX_SDMA_IRQ3 */
2392 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs
[] = {
2394 .pa_start
= 0x48056000,
2395 .pa_end
= 0x48056fff,
2396 .flags
= ADDR_TYPE_RT
2400 /* dma_system master ports */
2401 static struct omap_hwmod_ocp_if
*omap3xxx_dma_system_masters
[] = {
2402 &omap3xxx_dma_system__l3
,
2405 /* l4_cfg -> dma_system */
2406 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system
= {
2407 .master
= &omap3xxx_l4_core_hwmod
,
2408 .slave
= &omap3xxx_dma_system_hwmod
,
2409 .clk
= "core_l4_ick",
2410 .addr
= omap3xxx_dma_system_addrs
,
2411 .addr_cnt
= ARRAY_SIZE(omap3xxx_dma_system_addrs
),
2412 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2415 /* dma_system slave ports */
2416 static struct omap_hwmod_ocp_if
*omap3xxx_dma_system_slaves
[] = {
2417 &omap3xxx_l4_core__dma_system
,
2420 static struct omap_hwmod omap3xxx_dma_system_hwmod
= {
2422 .class = &omap3xxx_dma_hwmod_class
,
2423 .mpu_irqs
= omap3xxx_dma_system_irqs
,
2424 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_dma_system_irqs
),
2425 .main_clk
= "core_l3_ick",
2428 .module_offs
= CORE_MOD
,
2430 .module_bit
= OMAP3430_ST_SDMA_SHIFT
,
2432 .idlest_idle_bit
= OMAP3430_ST_SDMA_SHIFT
,
2435 .slaves
= omap3xxx_dma_system_slaves
,
2436 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dma_system_slaves
),
2437 .masters
= omap3xxx_dma_system_masters
,
2438 .masters_cnt
= ARRAY_SIZE(omap3xxx_dma_system_masters
),
2439 .dev_attr
= &dma_dev_attr
,
2440 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2441 .flags
= HWMOD_NO_IDLEST
,
2446 * multi channel buffered serial port controller
2449 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc
= {
2450 .sysc_offs
= 0x008c,
2451 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
2452 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2453 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2454 .sysc_fields
= &omap_hwmod_sysc_type1
,
2458 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class
= {
2460 .sysc
= &omap3xxx_mcbsp_sysc
,
2461 .rev
= MCBSP_CONFIG_TYPE3
,
2465 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs
[] = {
2466 { .name
= "irq", .irq
= 16 },
2467 { .name
= "tx", .irq
= 59 },
2468 { .name
= "rx", .irq
= 60 },
2471 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs
[] = {
2472 { .name
= "rx", .dma_req
= 32 },
2473 { .name
= "tx", .dma_req
= 31 },
2476 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs
[] = {
2479 .pa_start
= 0x48074000,
2480 .pa_end
= 0x480740ff,
2481 .flags
= ADDR_TYPE_RT
2485 /* l4_core -> mcbsp1 */
2486 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1
= {
2487 .master
= &omap3xxx_l4_core_hwmod
,
2488 .slave
= &omap3xxx_mcbsp1_hwmod
,
2489 .clk
= "mcbsp1_ick",
2490 .addr
= omap3xxx_mcbsp1_addrs
,
2491 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp1_addrs
),
2492 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2495 /* mcbsp1 slave ports */
2496 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp1_slaves
[] = {
2497 &omap3xxx_l4_core__mcbsp1
,
2500 static struct omap_hwmod omap3xxx_mcbsp1_hwmod
= {
2502 .class = &omap3xxx_mcbsp_hwmod_class
,
2503 .mpu_irqs
= omap3xxx_mcbsp1_irqs
,
2504 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp1_irqs
),
2505 .sdma_reqs
= omap3xxx_mcbsp1_sdma_chs
,
2506 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs
),
2507 .main_clk
= "mcbsp1_fck",
2511 .module_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
2512 .module_offs
= CORE_MOD
,
2514 .idlest_idle_bit
= OMAP3430_ST_MCBSP1_SHIFT
,
2517 .slaves
= omap3xxx_mcbsp1_slaves
,
2518 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp1_slaves
),
2519 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2523 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs
[] = {
2524 { .name
= "irq", .irq
= 17 },
2525 { .name
= "tx", .irq
= 62 },
2526 { .name
= "rx", .irq
= 63 },
2529 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs
[] = {
2530 { .name
= "rx", .dma_req
= 34 },
2531 { .name
= "tx", .dma_req
= 33 },
2534 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs
[] = {
2537 .pa_start
= 0x49022000,
2538 .pa_end
= 0x490220ff,
2539 .flags
= ADDR_TYPE_RT
2543 /* l4_per -> mcbsp2 */
2544 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2
= {
2545 .master
= &omap3xxx_l4_per_hwmod
,
2546 .slave
= &omap3xxx_mcbsp2_hwmod
,
2547 .clk
= "mcbsp2_ick",
2548 .addr
= omap3xxx_mcbsp2_addrs
,
2549 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_addrs
),
2550 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2553 /* mcbsp2 slave ports */
2554 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp2_slaves
[] = {
2555 &omap3xxx_l4_per__mcbsp2
,
2558 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr
= {
2559 .sidetone
= "mcbsp2_sidetone",
2562 static struct omap_hwmod omap3xxx_mcbsp2_hwmod
= {
2564 .class = &omap3xxx_mcbsp_hwmod_class
,
2565 .mpu_irqs
= omap3xxx_mcbsp2_irqs
,
2566 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_irqs
),
2567 .sdma_reqs
= omap3xxx_mcbsp2_sdma_chs
,
2568 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs
),
2569 .main_clk
= "mcbsp2_fck",
2573 .module_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2574 .module_offs
= OMAP3430_PER_MOD
,
2576 .idlest_idle_bit
= OMAP3430_ST_MCBSP2_SHIFT
,
2579 .slaves
= omap3xxx_mcbsp2_slaves
,
2580 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_slaves
),
2581 .dev_attr
= &omap34xx_mcbsp2_dev_attr
,
2582 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2586 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs
[] = {
2587 { .name
= "irq", .irq
= 22 },
2588 { .name
= "tx", .irq
= 89 },
2589 { .name
= "rx", .irq
= 90 },
2592 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs
[] = {
2593 { .name
= "rx", .dma_req
= 18 },
2594 { .name
= "tx", .dma_req
= 17 },
2597 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs
[] = {
2600 .pa_start
= 0x49024000,
2601 .pa_end
= 0x490240ff,
2602 .flags
= ADDR_TYPE_RT
2606 /* l4_per -> mcbsp3 */
2607 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3
= {
2608 .master
= &omap3xxx_l4_per_hwmod
,
2609 .slave
= &omap3xxx_mcbsp3_hwmod
,
2610 .clk
= "mcbsp3_ick",
2611 .addr
= omap3xxx_mcbsp3_addrs
,
2612 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_addrs
),
2613 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2616 /* mcbsp3 slave ports */
2617 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp3_slaves
[] = {
2618 &omap3xxx_l4_per__mcbsp3
,
2621 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr
= {
2622 .sidetone
= "mcbsp3_sidetone",
2625 static struct omap_hwmod omap3xxx_mcbsp3_hwmod
= {
2627 .class = &omap3xxx_mcbsp_hwmod_class
,
2628 .mpu_irqs
= omap3xxx_mcbsp3_irqs
,
2629 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_irqs
),
2630 .sdma_reqs
= omap3xxx_mcbsp3_sdma_chs
,
2631 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs
),
2632 .main_clk
= "mcbsp3_fck",
2636 .module_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2637 .module_offs
= OMAP3430_PER_MOD
,
2639 .idlest_idle_bit
= OMAP3430_ST_MCBSP3_SHIFT
,
2642 .slaves
= omap3xxx_mcbsp3_slaves
,
2643 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_slaves
),
2644 .dev_attr
= &omap34xx_mcbsp3_dev_attr
,
2645 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2649 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs
[] = {
2650 { .name
= "irq", .irq
= 23 },
2651 { .name
= "tx", .irq
= 54 },
2652 { .name
= "rx", .irq
= 55 },
2655 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs
[] = {
2656 { .name
= "rx", .dma_req
= 20 },
2657 { .name
= "tx", .dma_req
= 19 },
2660 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs
[] = {
2663 .pa_start
= 0x49026000,
2664 .pa_end
= 0x490260ff,
2665 .flags
= ADDR_TYPE_RT
2669 /* l4_per -> mcbsp4 */
2670 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4
= {
2671 .master
= &omap3xxx_l4_per_hwmod
,
2672 .slave
= &omap3xxx_mcbsp4_hwmod
,
2673 .clk
= "mcbsp4_ick",
2674 .addr
= omap3xxx_mcbsp4_addrs
,
2675 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp4_addrs
),
2676 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2679 /* mcbsp4 slave ports */
2680 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp4_slaves
[] = {
2681 &omap3xxx_l4_per__mcbsp4
,
2684 static struct omap_hwmod omap3xxx_mcbsp4_hwmod
= {
2686 .class = &omap3xxx_mcbsp_hwmod_class
,
2687 .mpu_irqs
= omap3xxx_mcbsp4_irqs
,
2688 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp4_irqs
),
2689 .sdma_reqs
= omap3xxx_mcbsp4_sdma_chs
,
2690 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs
),
2691 .main_clk
= "mcbsp4_fck",
2695 .module_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2696 .module_offs
= OMAP3430_PER_MOD
,
2698 .idlest_idle_bit
= OMAP3430_ST_MCBSP4_SHIFT
,
2701 .slaves
= omap3xxx_mcbsp4_slaves
,
2702 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp4_slaves
),
2703 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2707 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs
[] = {
2708 { .name
= "irq", .irq
= 27 },
2709 { .name
= "tx", .irq
= 81 },
2710 { .name
= "rx", .irq
= 82 },
2713 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs
[] = {
2714 { .name
= "rx", .dma_req
= 22 },
2715 { .name
= "tx", .dma_req
= 21 },
2718 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs
[] = {
2721 .pa_start
= 0x48096000,
2722 .pa_end
= 0x480960ff,
2723 .flags
= ADDR_TYPE_RT
2727 /* l4_core -> mcbsp5 */
2728 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5
= {
2729 .master
= &omap3xxx_l4_core_hwmod
,
2730 .slave
= &omap3xxx_mcbsp5_hwmod
,
2731 .clk
= "mcbsp5_ick",
2732 .addr
= omap3xxx_mcbsp5_addrs
,
2733 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp5_addrs
),
2734 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2737 /* mcbsp5 slave ports */
2738 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp5_slaves
[] = {
2739 &omap3xxx_l4_core__mcbsp5
,
2742 static struct omap_hwmod omap3xxx_mcbsp5_hwmod
= {
2744 .class = &omap3xxx_mcbsp_hwmod_class
,
2745 .mpu_irqs
= omap3xxx_mcbsp5_irqs
,
2746 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp5_irqs
),
2747 .sdma_reqs
= omap3xxx_mcbsp5_sdma_chs
,
2748 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs
),
2749 .main_clk
= "mcbsp5_fck",
2753 .module_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
2754 .module_offs
= CORE_MOD
,
2756 .idlest_idle_bit
= OMAP3430_ST_MCBSP5_SHIFT
,
2759 .slaves
= omap3xxx_mcbsp5_slaves
,
2760 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp5_slaves
),
2761 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2763 /* 'mcbsp sidetone' class */
2765 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc
= {
2766 .sysc_offs
= 0x0010,
2767 .sysc_flags
= SYSC_HAS_AUTOIDLE
,
2768 .sysc_fields
= &omap_hwmod_sysc_type1
,
2771 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class
= {
2772 .name
= "mcbsp_sidetone",
2773 .sysc
= &omap3xxx_mcbsp_sidetone_sysc
,
2776 /* mcbsp2_sidetone */
2777 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs
[] = {
2778 { .name
= "irq", .irq
= 4 },
2781 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs
[] = {
2784 .pa_start
= 0x49028000,
2785 .pa_end
= 0x490280ff,
2786 .flags
= ADDR_TYPE_RT
2790 /* l4_per -> mcbsp2_sidetone */
2791 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone
= {
2792 .master
= &omap3xxx_l4_per_hwmod
,
2793 .slave
= &omap3xxx_mcbsp2_sidetone_hwmod
,
2794 .clk
= "mcbsp2_ick",
2795 .addr
= omap3xxx_mcbsp2_sidetone_addrs
,
2796 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs
),
2797 .user
= OCP_USER_MPU
,
2800 /* mcbsp2_sidetone slave ports */
2801 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp2_sidetone_slaves
[] = {
2802 &omap3xxx_l4_per__mcbsp2_sidetone
,
2805 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod
= {
2806 .name
= "mcbsp2_sidetone",
2807 .class = &omap3xxx_mcbsp_sidetone_hwmod_class
,
2808 .mpu_irqs
= omap3xxx_mcbsp2_sidetone_irqs
,
2809 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs
),
2810 .main_clk
= "mcbsp2_fck",
2814 .module_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2815 .module_offs
= OMAP3430_PER_MOD
,
2817 .idlest_idle_bit
= OMAP3430_ST_MCBSP2_SHIFT
,
2820 .slaves
= omap3xxx_mcbsp2_sidetone_slaves
,
2821 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves
),
2822 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2825 /* mcbsp3_sidetone */
2826 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs
[] = {
2827 { .name
= "irq", .irq
= 5 },
2830 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs
[] = {
2833 .pa_start
= 0x4902A000,
2834 .pa_end
= 0x4902A0ff,
2835 .flags
= ADDR_TYPE_RT
2839 /* l4_per -> mcbsp3_sidetone */
2840 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone
= {
2841 .master
= &omap3xxx_l4_per_hwmod
,
2842 .slave
= &omap3xxx_mcbsp3_sidetone_hwmod
,
2843 .clk
= "mcbsp3_ick",
2844 .addr
= omap3xxx_mcbsp3_sidetone_addrs
,
2845 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs
),
2846 .user
= OCP_USER_MPU
,
2849 /* mcbsp3_sidetone slave ports */
2850 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp3_sidetone_slaves
[] = {
2851 &omap3xxx_l4_per__mcbsp3_sidetone
,
2854 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod
= {
2855 .name
= "mcbsp3_sidetone",
2856 .class = &omap3xxx_mcbsp_sidetone_hwmod_class
,
2857 .mpu_irqs
= omap3xxx_mcbsp3_sidetone_irqs
,
2858 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs
),
2859 .main_clk
= "mcbsp3_fck",
2863 .module_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2864 .module_offs
= OMAP3430_PER_MOD
,
2866 .idlest_idle_bit
= OMAP3430_ST_MCBSP3_SHIFT
,
2869 .slaves
= omap3xxx_mcbsp3_sidetone_slaves
,
2870 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves
),
2871 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2876 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields
= {
2880 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc
= {
2882 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_NO_CACHE
),
2883 .clockact
= CLOCKACT_TEST_ICLK
,
2884 .sysc_fields
= &omap34xx_sr_sysc_fields
,
2887 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class
= {
2888 .name
= "smartreflex",
2889 .sysc
= &omap34xx_sr_sysc
,
2893 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields
= {
2898 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc
= {
2900 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2901 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
2903 .sysc_fields
= &omap36xx_sr_sysc_fields
,
2906 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class
= {
2907 .name
= "smartreflex",
2908 .sysc
= &omap36xx_sr_sysc
,
2913 static struct omap_hwmod_ocp_if
*omap3_sr1_slaves
[] = {
2914 &omap3_l4_core__sr1
,
2917 static struct omap_hwmod omap34xx_sr1_hwmod
= {
2918 .name
= "sr1_hwmod",
2919 .class = &omap34xx_smartreflex_hwmod_class
,
2920 .main_clk
= "sr1_fck",
2925 .module_bit
= OMAP3430_EN_SR1_SHIFT
,
2926 .module_offs
= WKUP_MOD
,
2928 .idlest_idle_bit
= OMAP3430_EN_SR1_SHIFT
,
2931 .slaves
= omap3_sr1_slaves
,
2932 .slaves_cnt
= ARRAY_SIZE(omap3_sr1_slaves
),
2933 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2
|
2934 CHIP_IS_OMAP3430ES3_0
|
2935 CHIP_IS_OMAP3430ES3_1
),
2936 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
2939 static struct omap_hwmod omap36xx_sr1_hwmod
= {
2940 .name
= "sr1_hwmod",
2941 .class = &omap36xx_smartreflex_hwmod_class
,
2942 .main_clk
= "sr1_fck",
2947 .module_bit
= OMAP3430_EN_SR1_SHIFT
,
2948 .module_offs
= WKUP_MOD
,
2950 .idlest_idle_bit
= OMAP3430_EN_SR1_SHIFT
,
2953 .slaves
= omap3_sr1_slaves
,
2954 .slaves_cnt
= ARRAY_SIZE(omap3_sr1_slaves
),
2955 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1
),
2959 static struct omap_hwmod_ocp_if
*omap3_sr2_slaves
[] = {
2960 &omap3_l4_core__sr2
,
2963 static struct omap_hwmod omap34xx_sr2_hwmod
= {
2964 .name
= "sr2_hwmod",
2965 .class = &omap34xx_smartreflex_hwmod_class
,
2966 .main_clk
= "sr2_fck",
2971 .module_bit
= OMAP3430_EN_SR2_SHIFT
,
2972 .module_offs
= WKUP_MOD
,
2974 .idlest_idle_bit
= OMAP3430_EN_SR2_SHIFT
,
2977 .slaves
= omap3_sr2_slaves
,
2978 .slaves_cnt
= ARRAY_SIZE(omap3_sr2_slaves
),
2979 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2
|
2980 CHIP_IS_OMAP3430ES3_0
|
2981 CHIP_IS_OMAP3430ES3_1
),
2982 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
2985 static struct omap_hwmod omap36xx_sr2_hwmod
= {
2986 .name
= "sr2_hwmod",
2987 .class = &omap36xx_smartreflex_hwmod_class
,
2988 .main_clk
= "sr2_fck",
2993 .module_bit
= OMAP3430_EN_SR2_SHIFT
,
2994 .module_offs
= WKUP_MOD
,
2996 .idlest_idle_bit
= OMAP3430_EN_SR2_SHIFT
,
2999 .slaves
= omap3_sr2_slaves
,
3000 .slaves_cnt
= ARRAY_SIZE(omap3_sr2_slaves
),
3001 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1
),
3006 * mailbox module allowing communication between the on-chip processors
3007 * using a queued mailbox-interrupt mechanism.
3010 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc
= {
3014 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3015 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
3016 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3017 .sysc_fields
= &omap_hwmod_sysc_type1
,
3020 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class
= {
3022 .sysc
= &omap3xxx_mailbox_sysc
,
3025 static struct omap_hwmod omap3xxx_mailbox_hwmod
;
3026 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs
[] = {
3030 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs
[] = {
3032 .pa_start
= 0x48094000,
3033 .pa_end
= 0x480941ff,
3034 .flags
= ADDR_TYPE_RT
,
3038 /* l4_core -> mailbox */
3039 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox
= {
3040 .master
= &omap3xxx_l4_core_hwmod
,
3041 .slave
= &omap3xxx_mailbox_hwmod
,
3042 .addr
= omap3xxx_mailbox_addrs
,
3043 .addr_cnt
= ARRAY_SIZE(omap3xxx_mailbox_addrs
),
3044 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3047 /* mailbox slave ports */
3048 static struct omap_hwmod_ocp_if
*omap3xxx_mailbox_slaves
[] = {
3049 &omap3xxx_l4_core__mailbox
,
3052 static struct omap_hwmod omap3xxx_mailbox_hwmod
= {
3054 .class = &omap3xxx_mailbox_hwmod_class
,
3055 .mpu_irqs
= omap3xxx_mailbox_irqs
,
3056 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mailbox_irqs
),
3057 .main_clk
= "mailboxes_ick",
3061 .module_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
3062 .module_offs
= CORE_MOD
,
3064 .idlest_idle_bit
= OMAP3430_ST_MAILBOXES_SHIFT
,
3067 .slaves
= omap3xxx_mailbox_slaves
,
3068 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mailbox_slaves
),
3069 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3072 /* l4 core -> mcspi1 interface */
3073 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space
[] = {
3075 .pa_start
= 0x48098000,
3076 .pa_end
= 0x480980ff,
3077 .flags
= ADDR_TYPE_RT
,
3081 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1
= {
3082 .master
= &omap3xxx_l4_core_hwmod
,
3083 .slave
= &omap34xx_mcspi1
,
3084 .clk
= "mcspi1_ick",
3085 .addr
= omap34xx_mcspi1_addr_space
,
3086 .addr_cnt
= ARRAY_SIZE(omap34xx_mcspi1_addr_space
),
3087 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3090 /* l4 core -> mcspi2 interface */
3091 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space
[] = {
3093 .pa_start
= 0x4809a000,
3094 .pa_end
= 0x4809a0ff,
3095 .flags
= ADDR_TYPE_RT
,
3099 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2
= {
3100 .master
= &omap3xxx_l4_core_hwmod
,
3101 .slave
= &omap34xx_mcspi2
,
3102 .clk
= "mcspi2_ick",
3103 .addr
= omap34xx_mcspi2_addr_space
,
3104 .addr_cnt
= ARRAY_SIZE(omap34xx_mcspi2_addr_space
),
3105 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3108 /* l4 core -> mcspi3 interface */
3109 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space
[] = {
3111 .pa_start
= 0x480b8000,
3112 .pa_end
= 0x480b80ff,
3113 .flags
= ADDR_TYPE_RT
,
3117 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3
= {
3118 .master
= &omap3xxx_l4_core_hwmod
,
3119 .slave
= &omap34xx_mcspi3
,
3120 .clk
= "mcspi3_ick",
3121 .addr
= omap34xx_mcspi3_addr_space
,
3122 .addr_cnt
= ARRAY_SIZE(omap34xx_mcspi3_addr_space
),
3123 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3126 /* l4 core -> mcspi4 interface */
3127 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space
[] = {
3129 .pa_start
= 0x480ba000,
3130 .pa_end
= 0x480ba0ff,
3131 .flags
= ADDR_TYPE_RT
,
3135 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4
= {
3136 .master
= &omap3xxx_l4_core_hwmod
,
3137 .slave
= &omap34xx_mcspi4
,
3138 .clk
= "mcspi4_ick",
3139 .addr
= omap34xx_mcspi4_addr_space
,
3140 .addr_cnt
= ARRAY_SIZE(omap34xx_mcspi4_addr_space
),
3141 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3146 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3150 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc
= {
3152 .sysc_offs
= 0x0010,
3153 .syss_offs
= 0x0014,
3154 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3155 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3156 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
3157 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3158 .sysc_fields
= &omap_hwmod_sysc_type1
,
3161 static struct omap_hwmod_class omap34xx_mcspi_class
= {
3163 .sysc
= &omap34xx_mcspi_sysc
,
3164 .rev
= OMAP3_MCSPI_REV
,
3168 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs
[] = {
3169 { .name
= "irq", .irq
= 65 },
3172 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs
[] = {
3173 { .name
= "tx0", .dma_req
= 35 },
3174 { .name
= "rx0", .dma_req
= 36 },
3175 { .name
= "tx1", .dma_req
= 37 },
3176 { .name
= "rx1", .dma_req
= 38 },
3177 { .name
= "tx2", .dma_req
= 39 },
3178 { .name
= "rx2", .dma_req
= 40 },
3179 { .name
= "tx3", .dma_req
= 41 },
3180 { .name
= "rx3", .dma_req
= 42 },
3183 static struct omap_hwmod_ocp_if
*omap34xx_mcspi1_slaves
[] = {
3184 &omap34xx_l4_core__mcspi1
,
3187 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr
= {
3188 .num_chipselect
= 4,
3191 static struct omap_hwmod omap34xx_mcspi1
= {
3193 .mpu_irqs
= omap34xx_mcspi1_mpu_irqs
,
3194 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs
),
3195 .sdma_reqs
= omap34xx_mcspi1_sdma_reqs
,
3196 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs
),
3197 .main_clk
= "mcspi1_fck",
3200 .module_offs
= CORE_MOD
,
3202 .module_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
3204 .idlest_idle_bit
= OMAP3430_ST_MCSPI1_SHIFT
,
3207 .slaves
= omap34xx_mcspi1_slaves
,
3208 .slaves_cnt
= ARRAY_SIZE(omap34xx_mcspi1_slaves
),
3209 .class = &omap34xx_mcspi_class
,
3210 .dev_attr
= &omap_mcspi1_dev_attr
,
3211 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3215 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs
[] = {
3216 { .name
= "irq", .irq
= 66 },
3219 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs
[] = {
3220 { .name
= "tx0", .dma_req
= 43 },
3221 { .name
= "rx0", .dma_req
= 44 },
3222 { .name
= "tx1", .dma_req
= 45 },
3223 { .name
= "rx1", .dma_req
= 46 },
3226 static struct omap_hwmod_ocp_if
*omap34xx_mcspi2_slaves
[] = {
3227 &omap34xx_l4_core__mcspi2
,
3230 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr
= {
3231 .num_chipselect
= 2,
3234 static struct omap_hwmod omap34xx_mcspi2
= {
3236 .mpu_irqs
= omap34xx_mcspi2_mpu_irqs
,
3237 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs
),
3238 .sdma_reqs
= omap34xx_mcspi2_sdma_reqs
,
3239 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs
),
3240 .main_clk
= "mcspi2_fck",
3243 .module_offs
= CORE_MOD
,
3245 .module_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
3247 .idlest_idle_bit
= OMAP3430_ST_MCSPI2_SHIFT
,
3250 .slaves
= omap34xx_mcspi2_slaves
,
3251 .slaves_cnt
= ARRAY_SIZE(omap34xx_mcspi2_slaves
),
3252 .class = &omap34xx_mcspi_class
,
3253 .dev_attr
= &omap_mcspi2_dev_attr
,
3254 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3258 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs
[] = {
3259 { .name
= "irq", .irq
= 91 }, /* 91 */
3262 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs
[] = {
3263 { .name
= "tx0", .dma_req
= 15 },
3264 { .name
= "rx0", .dma_req
= 16 },
3265 { .name
= "tx1", .dma_req
= 23 },
3266 { .name
= "rx1", .dma_req
= 24 },
3269 static struct omap_hwmod_ocp_if
*omap34xx_mcspi3_slaves
[] = {
3270 &omap34xx_l4_core__mcspi3
,
3273 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr
= {
3274 .num_chipselect
= 2,
3277 static struct omap_hwmod omap34xx_mcspi3
= {
3279 .mpu_irqs
= omap34xx_mcspi3_mpu_irqs
,
3280 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs
),
3281 .sdma_reqs
= omap34xx_mcspi3_sdma_reqs
,
3282 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs
),
3283 .main_clk
= "mcspi3_fck",
3286 .module_offs
= CORE_MOD
,
3288 .module_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
3290 .idlest_idle_bit
= OMAP3430_ST_MCSPI3_SHIFT
,
3293 .slaves
= omap34xx_mcspi3_slaves
,
3294 .slaves_cnt
= ARRAY_SIZE(omap34xx_mcspi3_slaves
),
3295 .class = &omap34xx_mcspi_class
,
3296 .dev_attr
= &omap_mcspi3_dev_attr
,
3297 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3301 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs
[] = {
3302 { .name
= "irq", .irq
= INT_34XX_SPI4_IRQ
}, /* 48 */
3305 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs
[] = {
3306 { .name
= "tx0", .dma_req
= 70 }, /* DMA_SPI4_TX0 */
3307 { .name
= "rx0", .dma_req
= 71 }, /* DMA_SPI4_RX0 */
3310 static struct omap_hwmod_ocp_if
*omap34xx_mcspi4_slaves
[] = {
3311 &omap34xx_l4_core__mcspi4
,
3314 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr
= {
3315 .num_chipselect
= 1,
3318 static struct omap_hwmod omap34xx_mcspi4
= {
3320 .mpu_irqs
= omap34xx_mcspi4_mpu_irqs
,
3321 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs
),
3322 .sdma_reqs
= omap34xx_mcspi4_sdma_reqs
,
3323 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs
),
3324 .main_clk
= "mcspi4_fck",
3327 .module_offs
= CORE_MOD
,
3329 .module_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
3331 .idlest_idle_bit
= OMAP3430_ST_MCSPI4_SHIFT
,
3334 .slaves
= omap34xx_mcspi4_slaves
,
3335 .slaves_cnt
= ARRAY_SIZE(omap34xx_mcspi4_slaves
),
3336 .class = &omap34xx_mcspi_class
,
3337 .dev_attr
= &omap_mcspi4_dev_attr
,
3338 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3344 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc
= {
3346 .sysc_offs
= 0x0404,
3347 .syss_offs
= 0x0408,
3348 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
3349 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3351 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3352 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
3353 .sysc_fields
= &omap_hwmod_sysc_type1
,
3356 static struct omap_hwmod_class usbotg_class
= {
3358 .sysc
= &omap3xxx_usbhsotg_sysc
,
3361 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs
[] = {
3363 { .name
= "mc", .irq
= 92 },
3364 { .name
= "dma", .irq
= 93 },
3367 static struct omap_hwmod omap3xxx_usbhsotg_hwmod
= {
3368 .name
= "usb_otg_hs",
3369 .mpu_irqs
= omap3xxx_usbhsotg_mpu_irqs
,
3370 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs
),
3371 .main_clk
= "hsotgusb_ick",
3375 .module_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
3376 .module_offs
= CORE_MOD
,
3378 .idlest_idle_bit
= OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT
,
3379 .idlest_stdby_bit
= OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3382 .masters
= omap3xxx_usbhsotg_masters
,
3383 .masters_cnt
= ARRAY_SIZE(omap3xxx_usbhsotg_masters
),
3384 .slaves
= omap3xxx_usbhsotg_slaves
,
3385 .slaves_cnt
= ARRAY_SIZE(omap3xxx_usbhsotg_slaves
),
3386 .class = &usbotg_class
,
3389 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3390 * broken when autoidle is enabled
3391 * workaround is to disable the autoidle bit at module level.
3393 .flags
= HWMOD_NO_OCP_AUTOIDLE
| HWMOD_SWSUP_SIDLE
3394 | HWMOD_SWSUP_MSTANDBY
,
3395 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
3399 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs
[] = {
3401 { .name
= "mc", .irq
= 71 },
3404 static struct omap_hwmod_class am35xx_usbotg_class
= {
3405 .name
= "am35xx_usbotg",
3409 static struct omap_hwmod am35xx_usbhsotg_hwmod
= {
3410 .name
= "am35x_otg_hs",
3411 .mpu_irqs
= am35xx_usbhsotg_mpu_irqs
,
3412 .mpu_irqs_cnt
= ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs
),
3418 .masters
= am35xx_usbhsotg_masters
,
3419 .masters_cnt
= ARRAY_SIZE(am35xx_usbhsotg_masters
),
3420 .slaves
= am35xx_usbhsotg_slaves
,
3421 .slaves_cnt
= ARRAY_SIZE(am35xx_usbhsotg_slaves
),
3422 .class = &am35xx_usbotg_class
,
3423 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1
)
3426 /* MMC/SD/SDIO common */
3428 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc
= {
3432 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3433 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3434 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
3435 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3436 .sysc_fields
= &omap_hwmod_sysc_type1
,
3439 static struct omap_hwmod_class omap34xx_mmc_class
= {
3441 .sysc
= &omap34xx_mmc_sysc
,
3446 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs
[] = {
3450 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs
[] = {
3451 { .name
= "tx", .dma_req
= 61, },
3452 { .name
= "rx", .dma_req
= 62, },
3455 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks
[] = {
3456 { .role
= "dbck", .clk
= "omap_32k_fck", },
3459 static struct omap_hwmod_ocp_if
*omap3xxx_mmc1_slaves
[] = {
3460 &omap3xxx_l4_core__mmc1
,
3463 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
3464 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
3467 static struct omap_hwmod omap3xxx_mmc1_hwmod
= {
3469 .mpu_irqs
= omap34xx_mmc1_mpu_irqs
,
3470 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mmc1_mpu_irqs
),
3471 .sdma_reqs
= omap34xx_mmc1_sdma_reqs
,
3472 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mmc1_sdma_reqs
),
3473 .opt_clks
= omap34xx_mmc1_opt_clks
,
3474 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc1_opt_clks
),
3475 .main_clk
= "mmchs1_fck",
3478 .module_offs
= CORE_MOD
,
3480 .module_bit
= OMAP3430_EN_MMC1_SHIFT
,
3482 .idlest_idle_bit
= OMAP3430_ST_MMC1_SHIFT
,
3485 .dev_attr
= &mmc1_dev_attr
,
3486 .slaves
= omap3xxx_mmc1_slaves
,
3487 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mmc1_slaves
),
3488 .class = &omap34xx_mmc_class
,
3489 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3494 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs
[] = {
3495 { .irq
= INT_24XX_MMC2_IRQ
, },
3498 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs
[] = {
3499 { .name
= "tx", .dma_req
= 47, },
3500 { .name
= "rx", .dma_req
= 48, },
3503 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks
[] = {
3504 { .role
= "dbck", .clk
= "omap_32k_fck", },
3507 static struct omap_hwmod_ocp_if
*omap3xxx_mmc2_slaves
[] = {
3508 &omap3xxx_l4_core__mmc2
,
3511 static struct omap_hwmod omap3xxx_mmc2_hwmod
= {
3513 .mpu_irqs
= omap34xx_mmc2_mpu_irqs
,
3514 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mmc2_mpu_irqs
),
3515 .sdma_reqs
= omap34xx_mmc2_sdma_reqs
,
3516 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mmc2_sdma_reqs
),
3517 .opt_clks
= omap34xx_mmc2_opt_clks
,
3518 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc2_opt_clks
),
3519 .main_clk
= "mmchs2_fck",
3522 .module_offs
= CORE_MOD
,
3524 .module_bit
= OMAP3430_EN_MMC2_SHIFT
,
3526 .idlest_idle_bit
= OMAP3430_ST_MMC2_SHIFT
,
3529 .slaves
= omap3xxx_mmc2_slaves
,
3530 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mmc2_slaves
),
3531 .class = &omap34xx_mmc_class
,
3532 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3537 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs
[] = {
3541 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs
[] = {
3542 { .name
= "tx", .dma_req
= 77, },
3543 { .name
= "rx", .dma_req
= 78, },
3546 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks
[] = {
3547 { .role
= "dbck", .clk
= "omap_32k_fck", },
3550 static struct omap_hwmod_ocp_if
*omap3xxx_mmc3_slaves
[] = {
3551 &omap3xxx_l4_core__mmc3
,
3554 static struct omap_hwmod omap3xxx_mmc3_hwmod
= {
3556 .mpu_irqs
= omap34xx_mmc3_mpu_irqs
,
3557 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mmc3_mpu_irqs
),
3558 .sdma_reqs
= omap34xx_mmc3_sdma_reqs
,
3559 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mmc3_sdma_reqs
),
3560 .opt_clks
= omap34xx_mmc3_opt_clks
,
3561 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc3_opt_clks
),
3562 .main_clk
= "mmchs3_fck",
3566 .module_bit
= OMAP3430_EN_MMC3_SHIFT
,
3568 .idlest_idle_bit
= OMAP3430_ST_MMC3_SHIFT
,
3571 .slaves
= omap3xxx_mmc3_slaves
,
3572 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mmc3_slaves
),
3573 .class = &omap34xx_mmc_class
,
3574 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3577 static __initdata
struct omap_hwmod
*omap3xxx_hwmods
[] = {
3578 &omap3xxx_l3_main_hwmod
,
3579 &omap3xxx_l4_core_hwmod
,
3580 &omap3xxx_l4_per_hwmod
,
3581 &omap3xxx_l4_wkup_hwmod
,
3582 &omap3xxx_mmc1_hwmod
,
3583 &omap3xxx_mmc2_hwmod
,
3584 &omap3xxx_mmc3_hwmod
,
3585 &omap3xxx_mpu_hwmod
,
3586 &omap3xxx_iva_hwmod
,
3588 &omap3xxx_timer1_hwmod
,
3589 &omap3xxx_timer2_hwmod
,
3590 &omap3xxx_timer3_hwmod
,
3591 &omap3xxx_timer4_hwmod
,
3592 &omap3xxx_timer5_hwmod
,
3593 &omap3xxx_timer6_hwmod
,
3594 &omap3xxx_timer7_hwmod
,
3595 &omap3xxx_timer8_hwmod
,
3596 &omap3xxx_timer9_hwmod
,
3597 &omap3xxx_timer10_hwmod
,
3598 &omap3xxx_timer11_hwmod
,
3599 &omap3xxx_timer12_hwmod
,
3601 &omap3xxx_wd_timer2_hwmod
,
3602 &omap3xxx_uart1_hwmod
,
3603 &omap3xxx_uart2_hwmod
,
3604 &omap3xxx_uart3_hwmod
,
3605 &omap3xxx_uart4_hwmod
,
3607 &omap3430es1_dss_core_hwmod
,
3608 &omap3xxx_dss_core_hwmod
,
3609 &omap3xxx_dss_dispc_hwmod
,
3610 &omap3xxx_dss_dsi1_hwmod
,
3611 &omap3xxx_dss_rfbi_hwmod
,
3612 &omap3xxx_dss_venc_hwmod
,
3615 &omap3xxx_i2c1_hwmod
,
3616 &omap3xxx_i2c2_hwmod
,
3617 &omap3xxx_i2c3_hwmod
,
3618 &omap34xx_sr1_hwmod
,
3619 &omap34xx_sr2_hwmod
,
3620 &omap36xx_sr1_hwmod
,
3621 &omap36xx_sr2_hwmod
,
3625 &omap3xxx_gpio1_hwmod
,
3626 &omap3xxx_gpio2_hwmod
,
3627 &omap3xxx_gpio3_hwmod
,
3628 &omap3xxx_gpio4_hwmod
,
3629 &omap3xxx_gpio5_hwmod
,
3630 &omap3xxx_gpio6_hwmod
,
3632 /* dma_system class*/
3633 &omap3xxx_dma_system_hwmod
,
3636 &omap3xxx_mcbsp1_hwmod
,
3637 &omap3xxx_mcbsp2_hwmod
,
3638 &omap3xxx_mcbsp3_hwmod
,
3639 &omap3xxx_mcbsp4_hwmod
,
3640 &omap3xxx_mcbsp5_hwmod
,
3641 &omap3xxx_mcbsp2_sidetone_hwmod
,
3642 &omap3xxx_mcbsp3_sidetone_hwmod
,
3645 &omap3xxx_mailbox_hwmod
,
3654 &omap3xxx_usbhsotg_hwmod
,
3656 /* usbotg for am35x */
3657 &am35xx_usbhsotg_hwmod
,
3662 int __init
omap3xxx_hwmod_init(void)
3664 return omap_hwmod_register(omap3xxx_hwmods
);