2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * Implementation of transmit path.
23 #define BITS_PER_BYTE 8
24 #define OFDM_PLCP_BITS 22
25 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
32 #define HT_LTF(_ns) (4 * (_ns))
33 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 #define OFDM_SIFS_TIME 16
40 static u32 bits_per_symbol
[][2] = {
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
60 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
63 * Insert a chain of ath_buf (descriptors) on a txq and
64 * assume the descriptors are already chained together by caller.
65 * NB: must be called with txq lock held
68 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
69 struct list_head
*head
)
71 struct ath_hal
*ah
= sc
->sc_ah
;
75 * Insert the frame on the outbound list and
76 * pass it on to the hardware.
82 bf
= list_first_entry(head
, struct ath_buf
, list
);
84 list_splice_tail_init(head
, &txq
->axq_q
);
86 txq
->axq_totalqueued
++;
87 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
89 DPRINTF(sc
, ATH_DBG_QUEUE
,
90 "%s: txq depth = %d\n", __func__
, txq
->axq_depth
);
92 if (txq
->axq_link
== NULL
) {
93 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
94 DPRINTF(sc
, ATH_DBG_XMIT
,
95 "%s: TXDP[%u] = %llx (%p)\n",
96 __func__
, txq
->axq_qnum
,
97 ito64(bf
->bf_daddr
), bf
->bf_desc
);
99 *txq
->axq_link
= bf
->bf_daddr
;
100 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: link[%u] (%p)=%llx (%p)\n",
102 txq
->axq_qnum
, txq
->axq_link
,
103 ito64(bf
->bf_daddr
), bf
->bf_desc
);
105 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
106 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
109 /* Get transmit rate index using rate in Kbps */
111 static int ath_tx_findindex(const struct ath9k_rate_table
*rt
, int rate
)
116 for (i
= 0; i
< rt
->rateCount
; i
++) {
117 if (rt
->info
[i
].rateKbps
== rate
) {
126 /* Check if it's okay to send out aggregates */
128 static int ath_aggr_query(struct ath_softc
*sc
,
129 struct ath_node
*an
, u8 tidno
)
131 struct ath_atx_tid
*tid
;
132 tid
= ATH_AN_2_TID(an
, tidno
);
134 if (tid
->addba_exchangecomplete
|| tid
->addba_exchangeinprogress
)
140 /* Calculate Atheros packet type from IEEE80211 packet header */
142 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
144 struct ieee80211_hdr
*hdr
;
145 enum ath9k_pkt_type htype
;
148 hdr
= (struct ieee80211_hdr
*)skb
->data
;
149 fc
= hdr
->frame_control
;
151 if (ieee80211_is_beacon(fc
))
152 htype
= ATH9K_PKT_TYPE_BEACON
;
153 else if (ieee80211_is_probe_resp(fc
))
154 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
155 else if (ieee80211_is_atim(fc
))
156 htype
= ATH9K_PKT_TYPE_ATIM
;
157 else if (ieee80211_is_pspoll(fc
))
158 htype
= ATH9K_PKT_TYPE_PSPOLL
;
160 htype
= ATH9K_PKT_TYPE_NORMAL
;
165 static bool check_min_rate(struct sk_buff
*skb
)
167 struct ieee80211_hdr
*hdr
;
168 bool use_minrate
= false;
171 hdr
= (struct ieee80211_hdr
*)skb
->data
;
172 fc
= hdr
->frame_control
;
174 if (ieee80211_is_mgmt(fc
) || ieee80211_is_ctl(fc
)) {
176 } else if (ieee80211_is_data(fc
)) {
177 if (ieee80211_is_nullfunc(fc
) ||
178 /* Port Access Entity (IEEE 802.1X) */
179 (skb
->protocol
== cpu_to_be16(ETH_P_PAE
))) {
187 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
189 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
191 if (tx_info
->control
.hw_key
) {
192 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
193 return ATH9K_KEY_TYPE_WEP
;
194 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
195 return ATH9K_KEY_TYPE_TKIP
;
196 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
197 return ATH9K_KEY_TYPE_AES
;
200 return ATH9K_KEY_TYPE_CLEAR
;
203 static void setup_rate_retries(struct ath_softc
*sc
, struct sk_buff
*skb
)
205 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
206 struct ath_tx_info_priv
*tx_info_priv
;
207 struct ath_rc_series
*rcs
;
208 struct ieee80211_hdr
*hdr
;
209 const struct ath9k_rate_table
*rt
;
214 rt
= sc
->sc_currates
;
217 hdr
= (struct ieee80211_hdr
*)skb
->data
;
218 fc
= hdr
->frame_control
;
219 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->control
.vif
; /* HACK */
220 rcs
= tx_info_priv
->rcs
;
222 /* Check if min rates have to be used */
223 use_minrate
= check_min_rate(skb
);
225 if (ieee80211_is_data(fc
) && !use_minrate
) {
226 if (is_multicast_ether_addr(hdr
->addr1
)) {
228 ath_tx_findindex(rt
, tx_info_priv
->min_rate
);
229 /* mcast packets are not re-tried */
233 /* for management and control frames,
234 or for NULL and EAPOL frames */
236 rcs
[0].rix
= ath_rate_findrateix(sc
, tx_info_priv
->min_rate
);
239 rcs
[0].tries
= ATH_MGT_TXMAXTRY
;
244 if (ieee80211_has_morefrags(fc
) ||
245 (le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)) {
246 rcs
[1].tries
= rcs
[2].tries
= rcs
[3].tries
= 0;
247 rcs
[1].rix
= rcs
[2].rix
= rcs
[3].rix
= 0;
248 /* reset tries but keep rate index */
249 rcs
[0].tries
= ATH_TXMAXTRY
;
253 /* Called only when tx aggregation is enabled and HT is supported */
255 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
258 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
259 struct ieee80211_hdr
*hdr
;
261 struct ath_atx_tid
*tid
;
265 if (!tx_info
->control
.sta
)
268 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
269 hdr
= (struct ieee80211_hdr
*)skb
->data
;
270 fc
= hdr
->frame_control
;
274 if (ieee80211_is_data_qos(fc
)) {
275 qc
= ieee80211_get_qos_ctl(hdr
);
276 bf
->bf_tidno
= qc
[0] & 0xf;
281 if (ieee80211_is_data(fc
) && !check_min_rate(skb
)) {
282 /* For HT capable stations, we save tidno for later use.
283 * We also override seqno set by upper layer with the one
284 * in tx aggregation state.
286 * If fragmentation is on, the sequence number is
287 * not overridden, since it has been
288 * incremented by the fragmentation routine.
290 * FIXME: check if the fragmentation threshold exceeds
293 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
294 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
295 IEEE80211_SEQ_SEQ_SHIFT
);
296 bf
->bf_seqno
= tid
->seq_next
;
297 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
301 static int setup_tx_flags(struct ath_softc
*sc
, struct sk_buff
*skb
,
304 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
307 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
308 flags
|= ATH9K_TXDESC_INTREQ
;
310 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
311 flags
|= ATH9K_TXDESC_NOACK
;
312 if (tx_info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
313 flags
|= ATH9K_TXDESC_RTSENA
;
318 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
320 struct ath_buf
*bf
= NULL
;
322 spin_lock_bh(&sc
->sc_txbuflock
);
324 if (unlikely(list_empty(&sc
->sc_txbuf
))) {
325 spin_unlock_bh(&sc
->sc_txbuflock
);
329 bf
= list_first_entry(&sc
->sc_txbuf
, struct ath_buf
, list
);
332 spin_unlock_bh(&sc
->sc_txbuflock
);
337 /* To complete a chain of buffers associated a frame */
339 static void ath_tx_complete_buf(struct ath_softc
*sc
,
341 struct list_head
*bf_q
,
342 int txok
, int sendbar
)
344 struct sk_buff
*skb
= bf
->bf_mpdu
;
345 struct ath_xmit_status tx_status
;
348 * Set retry information.
349 * NB: Don't use the information in the descriptor, because the frame
350 * could be software retried.
352 tx_status
.retries
= bf
->bf_retries
;
356 tx_status
.flags
= ATH_TX_BAR
;
359 tx_status
.flags
|= ATH_TX_ERROR
;
361 if (bf_isxretried(bf
))
362 tx_status
.flags
|= ATH_TX_XRETRY
;
365 /* Unmap this frame */
366 pci_unmap_single(sc
->pdev
,
370 /* complete this frame */
371 ath_tx_complete(sc
, skb
, &tx_status
);
374 * Return the list of ath_buf of this mpdu to free queue
376 spin_lock_bh(&sc
->sc_txbuflock
);
377 list_splice_tail_init(bf_q
, &sc
->sc_txbuf
);
378 spin_unlock_bh(&sc
->sc_txbuflock
);
382 * queue up a dest/ac pair for tx scheduling
383 * NB: must be called with txq lock held
386 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
388 struct ath_atx_ac
*ac
= tid
->ac
;
391 * if tid is paused, hold off
397 * add tid to ac atmost once
403 list_add_tail(&tid
->list
, &ac
->tid_q
);
406 * add node ac to txq atmost once
412 list_add_tail(&ac
->list
, &txq
->axq_acq
);
417 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
419 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
421 spin_lock_bh(&txq
->axq_lock
);
425 spin_unlock_bh(&txq
->axq_lock
);
428 /* resume a tid and schedule aggregate */
430 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
432 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
434 ASSERT(tid
->paused
> 0);
435 spin_lock_bh(&txq
->axq_lock
);
442 if (list_empty(&tid
->buf_q
))
446 * Add this TID to scheduler and try to send out aggregates
448 ath_tx_queue_tid(txq
, tid
);
449 ath_txq_schedule(sc
, txq
);
451 spin_unlock_bh(&txq
->axq_lock
);
454 /* Compute the number of bad frames */
456 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
459 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
460 struct ath_desc
*ds
= bf_last
->bf_desc
;
462 u32 ba
[WME_BA_BMP_SIZE
>> 5];
467 if (ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
470 isaggr
= bf_isaggr(bf
);
472 seq_st
= ATH_DS_BA_SEQ(ds
);
473 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
477 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
478 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
487 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
490 struct ieee80211_hdr
*hdr
;
492 bf
->bf_state
.bf_type
|= BUF_RETRY
;
496 hdr
= (struct ieee80211_hdr
*)skb
->data
;
497 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
500 /* Update block ack window */
502 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
507 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
508 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
510 tid
->tx_buf
[cindex
] = NULL
;
512 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
513 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
514 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
519 * ath_pkt_dur - compute packet duration (NB: not NAV)
522 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
523 * width - 0 for 20 MHz, 1 for 40 MHz
524 * half_gi - to use 4us v/s 3.6 us for symbol time
527 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
528 int width
, int half_gi
, bool shortPreamble
)
530 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
531 u32 nbits
, nsymbits
, duration
, nsymbols
;
535 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
536 rc
= rt
->info
[rix
].rateCode
;
539 * for legacy rates, use old function to compute packet duration
542 return ath9k_hw_computetxtime(sc
->sc_ah
, rt
, pktlen
, rix
,
545 * find number of symbols: PLCP + data
547 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
548 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
549 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
552 duration
= SYMBOL_TIME(nsymbols
);
554 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
557 * addup duration for legacy/ht training and signal fields
559 streams
= HT_RC_2_STREAMS(rc
);
560 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
565 /* Rate module function to set rate related fields in tx descriptor */
567 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
569 struct ath_hal
*ah
= sc
->sc_ah
;
570 const struct ath9k_rate_table
*rt
;
571 struct ath_desc
*ds
= bf
->bf_desc
;
572 struct ath_desc
*lastds
= bf
->bf_lastbf
->bf_desc
;
573 struct ath9k_11n_rate_series series
[4];
574 int i
, flags
, rtsctsena
= 0;
576 u8 rix
= 0, cix
, ctsrate
= 0;
577 struct ath_node
*an
= NULL
;
579 struct ieee80211_tx_info
*tx_info
;
581 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
582 tx_info
= IEEE80211_SKB_CB(skb
);
584 if (tx_info
->control
.sta
)
585 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
588 * get the cix for the lowest valid rix.
590 rt
= sc
->sc_currates
;
592 if (bf
->bf_rcs
[i
].tries
) {
593 rix
= bf
->bf_rcs
[i
].rix
;
597 flags
= (bf
->bf_flags
& (ATH9K_TXDESC_RTSENA
| ATH9K_TXDESC_CTSENA
));
598 cix
= rt
->info
[rix
].controlRate
;
601 * If 802.11g protection is enabled, determine whether
602 * to use RTS/CTS or just CTS. Note that this is only
603 * done for OFDM/HT unicast frames.
605 if (sc
->sc_protmode
!= PROT_M_NONE
&&
606 (rt
->info
[rix
].phy
== PHY_OFDM
||
607 rt
->info
[rix
].phy
== PHY_HT
) &&
608 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
609 if (sc
->sc_protmode
== PROT_M_RTSCTS
)
610 flags
= ATH9K_TXDESC_RTSENA
;
611 else if (sc
->sc_protmode
== PROT_M_CTSONLY
)
612 flags
= ATH9K_TXDESC_CTSENA
;
614 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
618 /* For 11n, the default behavior is to enable RTS for
619 * hw retried frames. We enable the global flag here and
620 * let rate series flags determine which rates will actually
623 if ((ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) && bf_isdata(bf
)) {
625 * 802.11g protection not needed, use our default behavior
628 flags
= ATH9K_TXDESC_RTSENA
;
632 * Set protection if aggregate protection on
634 if (sc
->sc_config
.ath_aggr_prot
&&
635 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
636 flags
= ATH9K_TXDESC_RTSENA
;
637 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
642 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
644 if (bf_isaggr(bf
) && (bf
->bf_al
> ah
->ah_caps
.rts_aggr_limit
)) {
646 * Ensure that in the case of SM Dynamic power save
647 * while we are bursting the second aggregate the
650 flags
&= ~(ATH9K_TXDESC_RTSENA
);
654 * CTS transmit rate is derived from the transmit rate
655 * by looking in the h/w rate table. We must also factor
656 * in whether or not a short preamble is to be used.
657 * NB: cix is set above where RTS/CTS is enabled
660 ctsrate
= rt
->info
[cix
].rateCode
|
661 (bf_isshpreamble(bf
) ? rt
->info
[cix
].shortPreamble
: 0);
664 * Setup HAL rate series
666 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
668 for (i
= 0; i
< 4; i
++) {
669 if (!bf
->bf_rcs
[i
].tries
)
672 rix
= bf
->bf_rcs
[i
].rix
;
674 series
[i
].Rate
= rt
->info
[rix
].rateCode
|
675 (bf_isshpreamble(bf
) ? rt
->info
[rix
].shortPreamble
: 0);
677 series
[i
].Tries
= bf
->bf_rcs
[i
].tries
;
679 series
[i
].RateFlags
= (
680 (bf
->bf_rcs
[i
].flags
& ATH_RC_RTSCTS_FLAG
) ?
681 ATH9K_RATESERIES_RTS_CTS
: 0) |
682 ((bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) ?
683 ATH9K_RATESERIES_2040
: 0) |
684 ((bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
) ?
685 ATH9K_RATESERIES_HALFGI
: 0);
687 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
688 (bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) != 0,
689 (bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
),
690 bf_isshpreamble(bf
));
692 if (bf_isht(bf
) && an
)
693 series
[i
].ChSel
= ath_chainmask_sel_logic(sc
, an
);
695 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
698 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
702 * For non-HT devices, calculate RTS/CTS duration in software
703 * and disable multi-rate retry.
705 if (flags
&& !(ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
)) {
707 * Compute the transmit duration based on the frame
708 * size and the size of an ACK frame. We call into the
709 * HAL to do the computation since it depends on the
710 * characteristics of the actual PHY being used.
712 * NB: CTS is assumed the same size as an ACK so we can
713 * use the precalculated ACK durations.
715 if (flags
& ATH9K_TXDESC_RTSENA
) { /* SIFS + CTS */
716 ctsduration
+= bf_isshpreamble(bf
) ?
717 rt
->info
[cix
].spAckDuration
:
718 rt
->info
[cix
].lpAckDuration
;
721 ctsduration
+= series
[0].PktDuration
;
723 if ((bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) { /* SIFS + ACK */
724 ctsduration
+= bf_isshpreamble(bf
) ?
725 rt
->info
[rix
].spAckDuration
:
726 rt
->info
[rix
].lpAckDuration
;
730 * Disable multi-rate retry when using RTS/CTS by clearing
733 memset(&series
[1], 0, sizeof(struct ath9k_11n_rate_series
) * 3);
737 * set dur_update_en for l-sig computation except for PS-Poll frames
739 ath9k_hw_set11n_ratescenario(ah
, ds
, lastds
,
745 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
746 ath9k_hw_set11n_burstduration(ah
, ds
, 8192);
750 * Function to send a normal HT (non-AMPDU) frame
751 * NB: must be called with txq lock held
754 static int ath_tx_send_normal(struct ath_softc
*sc
,
756 struct ath_atx_tid
*tid
,
757 struct list_head
*bf_head
)
761 struct ieee80211_tx_info
*tx_info
;
762 struct ath_tx_info_priv
*tx_info_priv
;
764 BUG_ON(list_empty(bf_head
));
766 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
767 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
; /* regular HT frame */
769 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
770 tx_info
= IEEE80211_SKB_CB(skb
);
773 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->control
.vif
;
774 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
776 /* update starting sequence number for subsequent ADDBA request */
777 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
779 /* Queue to h/w without aggregation */
781 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
782 ath_buf_set_rate(sc
, bf
);
783 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
788 /* flush tid's software queue and send frames as non-ampdu's */
790 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
792 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
794 struct list_head bf_head
;
795 INIT_LIST_HEAD(&bf_head
);
797 ASSERT(tid
->paused
> 0);
798 spin_lock_bh(&txq
->axq_lock
);
802 if (tid
->paused
> 0) {
803 spin_unlock_bh(&txq
->axq_lock
);
807 while (!list_empty(&tid
->buf_q
)) {
808 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
809 ASSERT(!bf_isretried(bf
));
810 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
811 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
814 spin_unlock_bh(&txq
->axq_lock
);
817 /* Completion routine of an aggregate */
819 static void ath_tx_complete_aggr_rifs(struct ath_softc
*sc
,
822 struct list_head
*bf_q
,
825 struct ath_node
*an
= NULL
;
827 struct ieee80211_tx_info
*tx_info
;
828 struct ath_atx_tid
*tid
= NULL
;
829 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
830 struct ath_desc
*ds
= bf_last
->bf_desc
;
831 struct ath_buf
*bf_next
, *bf_lastq
= NULL
;
832 struct list_head bf_head
, bf_pending
;
834 u32 ba
[WME_BA_BMP_SIZE
>> 5];
835 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
837 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
838 tx_info
= IEEE80211_SKB_CB(skb
);
840 if (tx_info
->control
.sta
) {
841 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
842 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
845 isaggr
= bf_isaggr(bf
);
848 if (ATH_DS_TX_BA(ds
)) {
850 * extract starting sequence and
853 seq_st
= ATH_DS_BA_SEQ(ds
);
855 ATH_DS_BA_BITMAP(ds
),
856 WME_BA_BMP_SIZE
>> 3);
858 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
861 * AR5416 can become deaf/mute when BA
862 * issue happens. Chip needs to be reset.
863 * But AP code may have sychronization issues
864 * when perform internal reset in this routine.
865 * Only enable reset in STA mode for now.
867 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_STA
)
871 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
875 INIT_LIST_HEAD(&bf_pending
);
876 INIT_LIST_HEAD(&bf_head
);
879 txfail
= txpending
= 0;
880 bf_next
= bf
->bf_next
;
882 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
883 /* transmit completion, subframe is
884 * acked by block ack */
885 } else if (!isaggr
&& txok
) {
886 /* transmit completion */
889 if (!tid
->cleanup_inprogress
&&
890 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
891 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
892 ath_tx_set_retry(sc
, bf
);
895 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
901 * cleanup in progress, just fail
902 * the un-acked sub-frames
908 * Remove ath_buf's of this sub-frame from aggregate queue.
910 if (bf_next
== NULL
) { /* last subframe in the aggregate */
911 ASSERT(bf
->bf_lastfrm
== bf_last
);
914 * The last descriptor of the last sub frame could be
915 * a holding descriptor for h/w. If that's the case,
916 * bf->bf_lastfrm won't be in the bf_q.
917 * Make sure we handle bf_q properly here.
920 if (!list_empty(bf_q
)) {
921 bf_lastq
= list_entry(bf_q
->prev
,
922 struct ath_buf
, list
);
923 list_cut_position(&bf_head
,
924 bf_q
, &bf_lastq
->list
);
927 * XXX: if the last subframe only has one
928 * descriptor which is also being used as
929 * a holding descriptor. Then the ath_buf
930 * is not in the bf_q at all.
932 INIT_LIST_HEAD(&bf_head
);
935 ASSERT(!list_empty(bf_q
));
936 list_cut_position(&bf_head
,
937 bf_q
, &bf
->bf_lastfrm
->list
);
942 * complete the acked-ones/xretried ones; update
945 spin_lock_bh(&txq
->axq_lock
);
946 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
947 spin_unlock_bh(&txq
->axq_lock
);
949 /* complete this sub-frame */
950 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
953 * retry the un-acked ones
956 * XXX: if the last descriptor is holding descriptor,
957 * in order to requeue the frame to software queue, we
958 * need to allocate a new descriptor and
959 * copy the content of holding descriptor to it.
961 if (bf
->bf_next
== NULL
&&
962 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
965 /* allocate new descriptor */
966 spin_lock_bh(&sc
->sc_txbuflock
);
967 ASSERT(!list_empty((&sc
->sc_txbuf
)));
968 tbf
= list_first_entry(&sc
->sc_txbuf
,
969 struct ath_buf
, list
);
970 list_del(&tbf
->list
);
971 spin_unlock_bh(&sc
->sc_txbuflock
);
973 ATH_TXBUF_RESET(tbf
);
975 /* copy descriptor content */
976 tbf
->bf_mpdu
= bf_last
->bf_mpdu
;
977 tbf
->bf_buf_addr
= bf_last
->bf_buf_addr
;
978 *(tbf
->bf_desc
) = *(bf_last
->bf_desc
);
980 /* link it to the frame */
982 bf_lastq
->bf_desc
->ds_link
=
984 bf
->bf_lastfrm
= tbf
;
985 ath9k_hw_cleartxdesc(sc
->sc_ah
,
986 bf
->bf_lastfrm
->bf_desc
);
988 tbf
->bf_state
= bf_last
->bf_state
;
989 tbf
->bf_lastfrm
= tbf
;
990 ath9k_hw_cleartxdesc(sc
->sc_ah
,
991 tbf
->bf_lastfrm
->bf_desc
);
993 /* copy the DMA context */
995 bf_last
->bf_dmacontext
;
997 list_add_tail(&tbf
->list
, &bf_head
);
1000 * Clear descriptor status words for
1003 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1004 bf
->bf_lastfrm
->bf_desc
);
1008 * Put this buffer to the temporary pending
1009 * queue to retain ordering
1011 list_splice_tail_init(&bf_head
, &bf_pending
);
1017 if (tid
->cleanup_inprogress
) {
1018 /* check to see if we're done with cleaning the h/w queue */
1019 spin_lock_bh(&txq
->axq_lock
);
1021 if (tid
->baw_head
== tid
->baw_tail
) {
1022 tid
->addba_exchangecomplete
= 0;
1023 tid
->addba_exchangeattempts
= 0;
1024 spin_unlock_bh(&txq
->axq_lock
);
1026 tid
->cleanup_inprogress
= false;
1028 /* send buffered frames as singles */
1029 ath_tx_flush_tid(sc
, tid
);
1031 spin_unlock_bh(&txq
->axq_lock
);
1037 * prepend un-acked frames to the beginning of the pending frame queue
1039 if (!list_empty(&bf_pending
)) {
1040 spin_lock_bh(&txq
->axq_lock
);
1041 /* Note: we _prepend_, we _do_not_ at to
1042 * the end of the queue ! */
1043 list_splice(&bf_pending
, &tid
->buf_q
);
1044 ath_tx_queue_tid(txq
, tid
);
1045 spin_unlock_bh(&txq
->axq_lock
);
1049 ath_reset(sc
, false);
1054 /* Process completed xmit descriptors from the specified queue */
1056 static int ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1058 struct ath_hal
*ah
= sc
->sc_ah
;
1059 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
1060 struct list_head bf_head
;
1061 struct ath_desc
*ds
, *tmp_ds
;
1062 struct sk_buff
*skb
;
1063 struct ieee80211_tx_info
*tx_info
;
1064 struct ath_tx_info_priv
*tx_info_priv
;
1065 int nacked
, txok
, nbad
= 0, isrifs
= 0;
1068 DPRINTF(sc
, ATH_DBG_QUEUE
,
1069 "%s: tx queue %d (%x), link %p\n", __func__
,
1070 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
1075 spin_lock_bh(&txq
->axq_lock
);
1076 if (list_empty(&txq
->axq_q
)) {
1077 txq
->axq_link
= NULL
;
1078 txq
->axq_linkbuf
= NULL
;
1079 spin_unlock_bh(&txq
->axq_lock
);
1082 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1085 * There is a race condition that a BH gets scheduled
1086 * after sw writes TxE and before hw re-load the last
1087 * descriptor to get the newly chained one.
1088 * Software must keep the last DONE descriptor as a
1089 * holding descriptor - software does so by marking
1090 * it with the STALE flag.
1093 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1095 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1097 * The holding descriptor is the last
1098 * descriptor in queue. It's safe to remove
1099 * the last holding descriptor in BH context.
1101 spin_unlock_bh(&txq
->axq_lock
);
1104 /* Lets work with the next buffer now */
1105 bf
= list_entry(bf_held
->list
.next
,
1106 struct ath_buf
, list
);
1110 lastbf
= bf
->bf_lastbf
;
1111 ds
= lastbf
->bf_desc
; /* NB: last decriptor */
1113 status
= ath9k_hw_txprocdesc(ah
, ds
);
1114 if (status
== -EINPROGRESS
) {
1115 spin_unlock_bh(&txq
->axq_lock
);
1118 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1119 txq
->axq_lastdsWithCTS
= NULL
;
1120 if (ds
== txq
->axq_gatingds
)
1121 txq
->axq_gatingds
= NULL
;
1124 * Remove ath_buf's of the same transmit unit from txq,
1125 * however leave the last descriptor back as the holding
1126 * descriptor for hw.
1128 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1129 INIT_LIST_HEAD(&bf_head
);
1131 if (!list_is_singular(&lastbf
->list
))
1132 list_cut_position(&bf_head
,
1133 &txq
->axq_q
, lastbf
->list
.prev
);
1138 txq
->axq_aggr_depth
--;
1140 txok
= (ds
->ds_txstat
.ts_status
== 0);
1142 spin_unlock_bh(&txq
->axq_lock
);
1145 list_del(&bf_held
->list
);
1146 spin_lock_bh(&sc
->sc_txbuflock
);
1147 list_add_tail(&bf_held
->list
, &sc
->sc_txbuf
);
1148 spin_unlock_bh(&sc
->sc_txbuflock
);
1151 if (!bf_isampdu(bf
)) {
1153 * This frame is sent out as a single frame.
1154 * Use hardware retry status for this frame.
1156 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1157 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1158 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1161 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1164 tx_info
= IEEE80211_SKB_CB(skb
);
1167 tx_info_priv
= (struct ath_tx_info_priv
*) tx_info
->control
.vif
;
1168 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
1169 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1170 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
1171 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
1172 if (ds
->ds_txstat
.ts_status
== 0)
1175 if (bf_isdata(bf
)) {
1177 tmp_ds
= bf
->bf_rifslast
->bf_desc
;
1180 memcpy(&tx_info_priv
->tx
,
1182 sizeof(tx_info_priv
->tx
));
1183 tx_info_priv
->n_frames
= bf
->bf_nframes
;
1184 tx_info_priv
->n_bad_frames
= nbad
;
1189 * Complete this transmit unit
1192 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, txok
);
1194 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1196 /* Wake up mac80211 queue */
1198 spin_lock_bh(&txq
->axq_lock
);
1199 if (txq
->stopped
&& ath_txq_depth(sc
, txq
->axq_qnum
) <=
1202 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1204 ieee80211_wake_queue(sc
->hw
, qnum
);
1211 * schedule any pending packets if aggregation is enabled
1213 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1214 ath_txq_schedule(sc
, txq
);
1215 spin_unlock_bh(&txq
->axq_lock
);
1220 static void ath_tx_stopdma(struct ath_softc
*sc
, struct ath_txq
*txq
)
1222 struct ath_hal
*ah
= sc
->sc_ah
;
1224 (void) ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1225 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: tx queue [%u] %x, link %p\n",
1226 __func__
, txq
->axq_qnum
,
1227 ath9k_hw_gettxbuf(ah
, txq
->axq_qnum
), txq
->axq_link
);
1230 /* Drain only the data queues */
1232 static void ath_drain_txdataq(struct ath_softc
*sc
, bool retry_tx
)
1234 struct ath_hal
*ah
= sc
->sc_ah
;
1235 int i
, status
, npend
= 0;
1237 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
1238 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1239 if (ATH_TXQ_SETUP(sc
, i
)) {
1240 ath_tx_stopdma(sc
, &sc
->sc_txq
[i
]);
1241 /* The TxDMA may not really be stopped.
1242 * Double check the hal tx pending count */
1243 npend
+= ath9k_hw_numtxpending(ah
,
1244 sc
->sc_txq
[i
].axq_qnum
);
1250 /* TxDMA not stopped, reset the hal */
1251 DPRINTF(sc
, ATH_DBG_XMIT
,
1252 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__
);
1254 spin_lock_bh(&sc
->sc_resetlock
);
1255 if (!ath9k_hw_reset(ah
,
1256 sc
->sc_ah
->ah_curchan
,
1257 sc
->sc_ht_info
.tx_chan_width
,
1258 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1259 sc
->sc_ht_extprotspacing
, true, &status
)) {
1261 DPRINTF(sc
, ATH_DBG_FATAL
,
1262 "%s: unable to reset hardware; hal status %u\n",
1266 spin_unlock_bh(&sc
->sc_resetlock
);
1269 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1270 if (ATH_TXQ_SETUP(sc
, i
))
1271 ath_tx_draintxq(sc
, &sc
->sc_txq
[i
], retry_tx
);
1275 /* Add a sub-frame to block ack window */
1277 static void ath_tx_addto_baw(struct ath_softc
*sc
,
1278 struct ath_atx_tid
*tid
,
1283 if (bf_isretried(bf
))
1286 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
1287 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
1289 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
1290 tid
->tx_buf
[cindex
] = bf
;
1292 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
1293 (ATH_TID_MAX_BUFS
- 1))) {
1294 tid
->baw_tail
= cindex
;
1295 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
1300 * Function to send an A-MPDU
1301 * NB: must be called with txq lock held
1304 static int ath_tx_send_ampdu(struct ath_softc
*sc
,
1305 struct ath_atx_tid
*tid
,
1306 struct list_head
*bf_head
,
1307 struct ath_tx_control
*txctl
)
1310 struct sk_buff
*skb
;
1311 struct ieee80211_tx_info
*tx_info
;
1312 struct ath_tx_info_priv
*tx_info_priv
;
1314 BUG_ON(list_empty(bf_head
));
1316 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1317 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1320 * Do not queue to h/w when any of the following conditions is true:
1321 * - there are pending frames in software queue
1322 * - the TID is currently paused for ADDBA/BAR request
1323 * - seqno is not within block-ack window
1324 * - h/w queue depth exceeds low water mark
1326 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1327 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1328 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1330 * Add this frame to software queue for scheduling later
1333 list_splice_tail_init(bf_head
, &tid
->buf_q
);
1334 ath_tx_queue_tid(txctl
->txq
, tid
);
1338 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1339 tx_info
= IEEE80211_SKB_CB(skb
);
1341 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->control
.vif
;
1342 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1344 /* Add sub-frame to BAW */
1345 ath_tx_addto_baw(sc
, tid
, bf
);
1347 /* Queue to h/w without aggregation */
1349 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
1350 ath_buf_set_rate(sc
, bf
);
1351 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1358 * returns aggr limit based on lowest of the rates
1361 static u32
ath_lookup_rate(struct ath_softc
*sc
,
1363 struct ath_atx_tid
*tid
)
1365 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1366 struct sk_buff
*skb
;
1367 struct ieee80211_tx_info
*tx_info
;
1368 struct ath_tx_info_priv
*tx_info_priv
;
1369 u32 max_4ms_framelen
, frame_length
;
1370 u16 aggr_limit
, legacy
= 0, maxampdu
;
1373 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1374 tx_info
= IEEE80211_SKB_CB(skb
);
1375 tx_info_priv
= (struct ath_tx_info_priv
*)
1376 tx_info
->control
.vif
; /* XXX: HACK! */
1378 tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1381 * Find the lowest frame length among the rate series that will have a
1382 * 4ms transmit duration.
1383 * TODO - TXOP limit needs to be considered.
1385 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
1387 for (i
= 0; i
< 4; i
++) {
1388 if (bf
->bf_rcs
[i
].tries
) {
1389 frame_length
= bf
->bf_rcs
[i
].max_4ms_framelen
;
1391 if (rt
->info
[bf
->bf_rcs
[i
].rix
].phy
!= PHY_HT
) {
1396 max_4ms_framelen
= min(max_4ms_framelen
, frame_length
);
1401 * limit aggregate size by the minimum rate if rate selected is
1402 * not a probe rate, if rate selected is a probe rate then
1403 * avoid aggregation of this packet.
1405 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
1408 aggr_limit
= min(max_4ms_framelen
,
1409 (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
1412 * h/w can accept aggregates upto 16 bit lengths (65535).
1413 * The IE, however can hold upto 65536, which shows up here
1414 * as zero. Ignore 65536 since we are constrained by hw.
1416 maxampdu
= tid
->an
->maxampdu
;
1418 aggr_limit
= min(aggr_limit
, maxampdu
);
1424 * returns the number of delimiters to be added to
1425 * meet the minimum required mpdudensity.
1426 * caller should make sure that the rate is HT rate .
1429 static int ath_compute_num_delims(struct ath_softc
*sc
,
1430 struct ath_atx_tid
*tid
,
1434 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1435 u32 nsymbits
, nsymbols
, mpdudensity
;
1438 int width
, half_gi
, ndelim
, mindelim
;
1440 /* Select standard number of delimiters based on frame length alone */
1441 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
1444 * If encryption enabled, hardware requires some more padding between
1446 * TODO - this could be improved to be dependent on the rate.
1447 * The hardware can keep up at lower rates, but not higher rates
1449 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
1450 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
1453 * Convert desired mpdu density from microeconds to bytes based
1454 * on highest rate in rate series (i.e. first rate) to determine
1455 * required minimum length for subframe. Take into account
1456 * whether high rate is 20 or 40Mhz and half or full GI.
1458 mpdudensity
= tid
->an
->mpdudensity
;
1461 * If there is no mpdu density restriction, no further calculation
1464 if (mpdudensity
== 0)
1467 rix
= bf
->bf_rcs
[0].rix
;
1468 flags
= bf
->bf_rcs
[0].flags
;
1469 rc
= rt
->info
[rix
].rateCode
;
1470 width
= (flags
& ATH_RC_CW40_FLAG
) ? 1 : 0;
1471 half_gi
= (flags
& ATH_RC_SGI_FLAG
) ? 1 : 0;
1474 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
1476 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
1481 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1482 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
1484 /* Is frame shorter than required minimum length? */
1485 if (frmlen
< minlen
) {
1486 /* Get the minimum number of delimiters required. */
1487 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
1488 ndelim
= max(mindelim
, ndelim
);
1495 * For aggregation from software buffer queue.
1496 * NB: must be called with txq lock held
1499 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
1500 struct ath_atx_tid
*tid
,
1501 struct list_head
*bf_q
,
1502 struct ath_buf
**bf_last
,
1503 struct aggr_rifs_param
*param
,
1506 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1507 struct ath_buf
*bf
, *tbf
, *bf_first
, *bf_prev
= NULL
;
1508 struct list_head bf_head
;
1509 int rl
= 0, nframes
= 0, ndelim
;
1510 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
1511 al_delta
, h_baw
= tid
->baw_size
/ 2;
1512 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
1513 int prev_al
= 0, is_ds_rate
= 0;
1514 INIT_LIST_HEAD(&bf_head
);
1516 BUG_ON(list_empty(&tid
->buf_q
));
1518 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1521 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1524 * do not step over block-ack window
1526 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
1527 status
= ATH_AGGR_BAW_CLOSED
;
1532 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
1535 * Is rate dual stream
1538 (bf
->bf_rcs
[0].flags
& ATH_RC_DS_FLAG
) ? 1 : 0;
1542 * do not exceed aggregation limit
1544 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
1546 if (nframes
&& (aggr_limit
<
1547 (al
+ bpad
+ al_delta
+ prev_al
))) {
1548 status
= ATH_AGGR_LIMITED
;
1553 * do not exceed subframe limit
1555 if ((nframes
+ *prev_frames
) >=
1556 min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
1557 status
= ATH_AGGR_LIMITED
;
1562 * add padding for previous frame to aggregation length
1564 al
+= bpad
+ al_delta
;
1567 * Get the delimiters needed to meet the MPDU
1568 * density for this node.
1570 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
1572 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1575 bf
->bf_lastfrm
->bf_desc
->ds_link
= 0;
1578 * this packet is part of an aggregate
1579 * - remove all descriptors belonging to this frame from
1581 * - add it to block ack window
1582 * - set up descriptors for aggregation
1584 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1585 ath_tx_addto_baw(sc
, tid
, bf
);
1587 list_for_each_entry(tbf
, &bf_head
, list
) {
1588 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
,
1589 tbf
->bf_desc
, ndelim
);
1593 * link buffers of this frame to the aggregate
1595 list_splice_tail_init(&bf_head
, bf_q
);
1599 bf_prev
->bf_next
= bf
;
1600 bf_prev
->bf_lastfrm
->bf_desc
->ds_link
= bf
->bf_daddr
;
1606 * terminate aggregation on a small packet boundary
1608 if (bf
->bf_frmlen
< ATH_AGGR_MINPLEN
) {
1609 status
= ATH_AGGR_SHORTPKT
;
1613 } while (!list_empty(&tid
->buf_q
));
1615 bf_first
->bf_al
= al
;
1616 bf_first
->bf_nframes
= nframes
;
1623 * process pending frames possibly doing a-mpdu aggregation
1624 * NB: must be called with txq lock held
1627 static void ath_tx_sched_aggr(struct ath_softc
*sc
,
1628 struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
1630 struct ath_buf
*bf
, *tbf
, *bf_last
, *bf_lastaggr
= NULL
;
1631 enum ATH_AGGR_STATUS status
;
1632 struct list_head bf_q
;
1633 struct aggr_rifs_param param
= {0, 0, 0, 0, NULL
};
1634 int prev_frames
= 0;
1637 if (list_empty(&tid
->buf_q
))
1640 INIT_LIST_HEAD(&bf_q
);
1642 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
, &bf_lastaggr
, ¶m
,
1646 * no frames picked up to be aggregated; block-ack
1647 * window is not open
1649 if (list_empty(&bf_q
))
1652 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1653 bf_last
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1654 bf
->bf_lastbf
= bf_last
;
1657 * if only one frame, send as non-aggregate
1659 if (bf
->bf_nframes
== 1) {
1660 ASSERT(bf
->bf_lastfrm
== bf_last
);
1662 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1664 * clear aggr bits for every descriptor
1665 * XXX TODO: is there a way to optimize it?
1667 list_for_each_entry(tbf
, &bf_q
, list
) {
1668 ath9k_hw_clr11n_aggr(sc
->sc_ah
, tbf
->bf_desc
);
1671 ath_buf_set_rate(sc
, bf
);
1672 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1677 * setup first desc with rate and aggr info
1679 bf
->bf_state
.bf_type
|= BUF_AGGR
;
1680 ath_buf_set_rate(sc
, bf
);
1681 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
1684 * anchor last frame of aggregate correctly
1686 ASSERT(bf_lastaggr
);
1687 ASSERT(bf_lastaggr
->bf_lastfrm
== bf_last
);
1689 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1691 /* XXX: We don't enter into this loop, consider removing this */
1692 while (!list_empty(&bf_q
) && !list_is_last(&tbf
->list
, &bf_q
)) {
1693 tbf
= list_entry(tbf
->list
.next
, struct ath_buf
, list
);
1694 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1697 txq
->axq_aggr_depth
++;
1700 * Normal aggregate, queue to hardware
1702 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1704 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
1705 status
!= ATH_AGGR_BAW_CLOSED
);
1708 /* Called with txq lock held */
1710 static void ath_tid_drain(struct ath_softc
*sc
,
1711 struct ath_txq
*txq
,
1712 struct ath_atx_tid
*tid
)
1716 struct list_head bf_head
;
1717 INIT_LIST_HEAD(&bf_head
);
1720 if (list_empty(&tid
->buf_q
))
1722 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1724 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1726 /* update baw for software retried frame */
1727 if (bf_isretried(bf
))
1728 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1731 * do not indicate packets while holding txq spinlock.
1732 * unlock is intentional here
1734 spin_unlock(&txq
->axq_lock
);
1736 /* complete this sub-frame */
1737 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1739 spin_lock(&txq
->axq_lock
);
1743 * TODO: For frame(s) that are in the retry state, we will reuse the
1744 * sequence number(s) without setting the retry bit. The
1745 * alternative is to give up on these and BAR the receiver's window
1748 tid
->seq_next
= tid
->seq_start
;
1749 tid
->baw_tail
= tid
->baw_head
;
1753 * Drain all pending buffers
1754 * NB: must be called with txq lock held
1757 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1758 struct ath_txq
*txq
)
1760 struct ath_atx_ac
*ac
, *ac_tmp
;
1761 struct ath_atx_tid
*tid
, *tid_tmp
;
1763 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1764 list_del(&ac
->list
);
1766 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1767 list_del(&tid
->list
);
1769 ath_tid_drain(sc
, txq
, tid
);
1774 static void ath_tx_setup_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
,
1775 struct sk_buff
*skb
, struct scatterlist
*sg
,
1776 struct ath_tx_control
*txctl
)
1778 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1779 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1780 struct ath_tx_info_priv
*tx_info_priv
;
1781 struct ath_rc_series
*rcs
;
1785 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->control
.vif
;
1786 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1787 fc
= hdr
->frame_control
;
1788 rcs
= tx_info_priv
->rcs
;
1790 ATH_TXBUF_RESET(bf
);
1794 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
1796 ieee80211_is_data(fc
) ?
1797 (bf
->bf_state
.bf_type
|= BUF_DATA
) :
1798 (bf
->bf_state
.bf_type
&= ~BUF_DATA
);
1799 ieee80211_is_back_req(fc
) ?
1800 (bf
->bf_state
.bf_type
|= BUF_BAR
) :
1801 (bf
->bf_state
.bf_type
&= ~BUF_BAR
);
1802 ieee80211_is_pspoll(fc
) ?
1803 (bf
->bf_state
.bf_type
|= BUF_PSPOLL
) :
1804 (bf
->bf_state
.bf_type
&= ~BUF_PSPOLL
);
1805 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
) ?
1806 (bf
->bf_state
.bf_type
|= BUF_SHORT_PREAMBLE
) :
1807 (bf
->bf_state
.bf_type
&= ~BUF_SHORT_PREAMBLE
);
1808 (sc
->hw
->conf
.ht
.enabled
&&
1809 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) ?
1810 (bf
->bf_state
.bf_type
|= BUF_HT
) :
1811 (bf
->bf_state
.bf_type
&= ~BUF_HT
);
1813 bf
->bf_flags
= setup_tx_flags(sc
, skb
, txctl
->txq
);
1817 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1819 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1820 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1821 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1823 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1828 setup_rate_retries(sc
, skb
);
1830 bf
->bf_rcs
[0] = rcs
[0];
1831 bf
->bf_rcs
[1] = rcs
[1];
1832 bf
->bf_rcs
[2] = rcs
[2];
1833 bf
->bf_rcs
[3] = rcs
[3];
1835 /* Assign seqno, tidno */
1837 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
))
1838 assign_aggr_tid_seqno(skb
, bf
);
1843 bf
->bf_dmacontext
= pci_map_single(sc
->pdev
, skb
->data
,
1844 skb
->len
, PCI_DMA_TODEVICE
);
1845 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1848 /* FIXME: tx power */
1849 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1850 struct scatterlist
*sg
, u32 n_sg
,
1851 struct ath_tx_control
*txctl
)
1853 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1854 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1855 struct ath_node
*an
= NULL
;
1856 struct list_head bf_head
;
1857 struct ath_desc
*ds
;
1858 struct ath_atx_tid
*tid
;
1859 struct ath_hal
*ah
= sc
->sc_ah
;
1862 if (tx_info
->control
.sta
) {
1863 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1864 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1867 frm_type
= get_hw_packet_type(skb
);
1869 INIT_LIST_HEAD(&bf_head
);
1870 list_add_tail(&bf
->list
, &bf_head
);
1872 /* setup descriptor */
1876 ds
->ds_data
= bf
->bf_buf_addr
;
1878 /* Formulate first tx descriptor with tx controls */
1880 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1881 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1883 ath9k_hw_filltxdesc(ah
, ds
,
1884 sg_dma_len(sg
), /* segment length */
1885 true, /* first segment */
1886 (n_sg
== 1) ? true : false, /* last segment */
1887 ds
); /* first descriptor */
1889 bf
->bf_lastfrm
= bf
;
1891 spin_lock_bh(&txctl
->txq
->axq_lock
);
1893 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
)) {
1894 if (ath_aggr_query(sc
, an
, bf
->bf_tidno
)) {
1896 * Try aggregation if it's a unicast data frame
1897 * and the destination is HT capable.
1899 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1902 * Send this frame as regular when ADDBA
1903 * exchange is neither complete nor pending.
1905 ath_tx_send_normal(sc
, txctl
->txq
,
1912 ath_buf_set_rate(sc
, bf
);
1913 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
);
1916 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1919 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
1920 struct ath_tx_control
*txctl
)
1923 struct scatterlist sg
;
1925 /* Check if a tx buffer is available */
1927 bf
= ath_tx_get_buffer(sc
);
1929 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX buffers are full\n",
1934 ath_tx_setup_buffer(sc
, bf
, skb
, &sg
, txctl
);
1938 memset(&sg
, 0, sizeof(struct scatterlist
));
1939 sg_dma_address(&sg
) = bf
->bf_dmacontext
;
1940 sg_dma_len(&sg
) = skb
->len
;
1942 ath_tx_start_dma(sc
, bf
, &sg
, 1, txctl
);
1947 /* Initialize TX queue and h/w */
1949 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
1954 spin_lock_init(&sc
->sc_txbuflock
);
1956 /* Setup tx descriptors */
1957 error
= ath_descdma_setup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
,
1960 DPRINTF(sc
, ATH_DBG_FATAL
,
1961 "%s: failed to allocate tx descriptors: %d\n",
1966 /* XXX allocate beacon state together with vap */
1967 error
= ath_descdma_setup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
,
1968 "beacon", ATH_BCBUF
, 1);
1970 DPRINTF(sc
, ATH_DBG_FATAL
,
1971 "%s: failed to allocate "
1972 "beacon descripotrs: %d\n",
1985 /* Reclaim all tx queue resources */
1987 int ath_tx_cleanup(struct ath_softc
*sc
)
1989 /* cleanup beacon descriptors */
1990 if (sc
->sc_bdma
.dd_desc_len
!= 0)
1991 ath_descdma_cleanup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
);
1993 /* cleanup tx descriptors */
1994 if (sc
->sc_txdma
.dd_desc_len
!= 0)
1995 ath_descdma_cleanup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
);
2000 /* Setup a h/w transmit queue */
2002 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
2004 struct ath_hal
*ah
= sc
->sc_ah
;
2005 struct ath9k_tx_queue_info qi
;
2008 memset(&qi
, 0, sizeof(qi
));
2009 qi
.tqi_subtype
= subtype
;
2010 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
2011 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
2012 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
2013 qi
.tqi_physCompBuf
= 0;
2016 * Enable interrupts only for EOL and DESC conditions.
2017 * We mark tx descriptors to receive a DESC interrupt
2018 * when a tx queue gets deep; otherwise waiting for the
2019 * EOL to reap descriptors. Note that this is done to
2020 * reduce interrupt load and this only defers reaping
2021 * descriptors, never transmitting frames. Aside from
2022 * reducing interrupts this also permits more concurrency.
2023 * The only potential downside is if the tx queue backs
2024 * up in which case the top half of the kernel may backup
2025 * due to a lack of tx descriptors.
2027 * The UAPSD queue is an exception, since we take a desc-
2028 * based intr on the EOSP frames.
2030 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
2031 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
2033 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
2034 TXQ_FLAG_TXDESCINT_ENABLE
;
2035 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
2038 * NB: don't print a message, this happens
2039 * normally on parts with too few tx queues
2043 if (qnum
>= ARRAY_SIZE(sc
->sc_txq
)) {
2044 DPRINTF(sc
, ATH_DBG_FATAL
,
2045 "%s: hal qnum %u out of range, max %u!\n",
2046 __func__
, qnum
, (unsigned int)ARRAY_SIZE(sc
->sc_txq
));
2047 ath9k_hw_releasetxqueue(ah
, qnum
);
2050 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
2051 struct ath_txq
*txq
= &sc
->sc_txq
[qnum
];
2053 txq
->axq_qnum
= qnum
;
2054 txq
->axq_link
= NULL
;
2055 INIT_LIST_HEAD(&txq
->axq_q
);
2056 INIT_LIST_HEAD(&txq
->axq_acq
);
2057 spin_lock_init(&txq
->axq_lock
);
2059 txq
->axq_aggr_depth
= 0;
2060 txq
->axq_totalqueued
= 0;
2061 txq
->axq_linkbuf
= NULL
;
2062 sc
->sc_txqsetup
|= 1<<qnum
;
2064 return &sc
->sc_txq
[qnum
];
2067 /* Reclaim resources for a setup queue */
2069 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2071 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
2072 sc
->sc_txqsetup
&= ~(1<<txq
->axq_qnum
);
2076 * Setup a hardware data transmit queue for the specified
2077 * access control. The hal may not support all requested
2078 * queues in which case it will return a reference to a
2079 * previously setup queue. We record the mapping from ac's
2080 * to h/w queues for use by ath_tx_start and also track
2081 * the set of h/w queues being used to optimize work in the
2082 * transmit interrupt handler and related routines.
2085 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
2087 struct ath_txq
*txq
;
2089 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2090 DPRINTF(sc
, ATH_DBG_FATAL
,
2091 "%s: HAL AC %u out of range, max %zu!\n",
2092 __func__
, haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2095 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
2097 sc
->sc_haltype2q
[haltype
] = txq
->axq_qnum
;
2103 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
2108 case ATH9K_TX_QUEUE_DATA
:
2109 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2110 DPRINTF(sc
, ATH_DBG_FATAL
,
2111 "%s: HAL AC %u out of range, max %zu!\n",
2113 haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2116 qnum
= sc
->sc_haltype2q
[haltype
];
2118 case ATH9K_TX_QUEUE_BEACON
:
2119 qnum
= sc
->sc_bhalq
;
2121 case ATH9K_TX_QUEUE_CAB
:
2122 qnum
= sc
->sc_cabq
->axq_qnum
;
2130 /* Get a transmit queue, if available */
2132 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2134 struct ath_txq
*txq
= NULL
;
2137 qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
2138 txq
= &sc
->sc_txq
[qnum
];
2140 spin_lock_bh(&txq
->axq_lock
);
2142 /* Try to avoid running out of descriptors */
2143 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
2144 DPRINTF(sc
, ATH_DBG_FATAL
,
2145 "%s: TX queue: %d is full, depth: %d\n",
2146 __func__
, qnum
, txq
->axq_depth
);
2147 ieee80211_stop_queue(sc
->hw
, skb_get_queue_mapping(skb
));
2149 spin_unlock_bh(&txq
->axq_lock
);
2153 spin_unlock_bh(&txq
->axq_lock
);
2158 /* Update parameters for a transmit queue */
2160 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
2161 struct ath9k_tx_queue_info
*qinfo
)
2163 struct ath_hal
*ah
= sc
->sc_ah
;
2165 struct ath9k_tx_queue_info qi
;
2167 if (qnum
== sc
->sc_bhalq
) {
2169 * XXX: for beacon queue, we just save the parameter.
2170 * It will be picked up by ath_beaconq_config when
2173 sc
->sc_beacon_qi
= *qinfo
;
2177 ASSERT(sc
->sc_txq
[qnum
].axq_qnum
== qnum
);
2179 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
2180 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
2181 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
2182 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
2183 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
2184 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
2186 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
2187 DPRINTF(sc
, ATH_DBG_FATAL
,
2188 "%s: unable to update hardware queue %u!\n",
2192 ath9k_hw_resettxqueue(ah
, qnum
); /* push to h/w */
2198 int ath_cabq_update(struct ath_softc
*sc
)
2200 struct ath9k_tx_queue_info qi
;
2201 int qnum
= sc
->sc_cabq
->axq_qnum
;
2202 struct ath_beacon_config conf
;
2204 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
2206 * Ensure the readytime % is within the bounds.
2208 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
2209 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
2210 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
2211 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
2213 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
2215 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
2216 ath_txq_update(sc
, qnum
, &qi
);
2221 /* Deferred processing of transmit interrupt */
2223 void ath_tx_tasklet(struct ath_softc
*sc
)
2226 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2228 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2231 * Process each active queue.
2233 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2234 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2235 ath_tx_processq(sc
, &sc
->sc_txq
[i
]);
2239 void ath_tx_draintxq(struct ath_softc
*sc
,
2240 struct ath_txq
*txq
, bool retry_tx
)
2242 struct ath_buf
*bf
, *lastbf
;
2243 struct list_head bf_head
;
2245 INIT_LIST_HEAD(&bf_head
);
2248 * NB: this assumes output has been stopped and
2249 * we do not need to block ath_tx_tasklet
2252 spin_lock_bh(&txq
->axq_lock
);
2254 if (list_empty(&txq
->axq_q
)) {
2255 txq
->axq_link
= NULL
;
2256 txq
->axq_linkbuf
= NULL
;
2257 spin_unlock_bh(&txq
->axq_lock
);
2261 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2263 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
2264 list_del(&bf
->list
);
2265 spin_unlock_bh(&txq
->axq_lock
);
2267 spin_lock_bh(&sc
->sc_txbuflock
);
2268 list_add_tail(&bf
->list
, &sc
->sc_txbuf
);
2269 spin_unlock_bh(&sc
->sc_txbuflock
);
2273 lastbf
= bf
->bf_lastbf
;
2275 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
2276 ATH9K_TX_SW_ABORTED
;
2278 /* remove ath_buf's of the same mpdu from txq */
2279 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
2282 spin_unlock_bh(&txq
->axq_lock
);
2285 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, 0);
2287 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2290 /* flush any pending frames if aggregation is enabled */
2291 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2293 spin_lock_bh(&txq
->axq_lock
);
2294 ath_txq_drain_pending_buffers(sc
, txq
);
2295 spin_unlock_bh(&txq
->axq_lock
);
2300 /* Drain the transmit queues and reclaim resources */
2302 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
)
2304 /* stop beacon queue. The beacon will be freed when
2305 * we go to INIT state */
2306 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2307 (void) ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->sc_bhalq
);
2308 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: beacon queue %x\n", __func__
,
2309 ath9k_hw_gettxbuf(sc
->sc_ah
, sc
->sc_bhalq
));
2312 ath_drain_txdataq(sc
, retry_tx
);
2315 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
2317 return sc
->sc_txq
[qnum
].axq_depth
;
2320 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
)
2322 return sc
->sc_txq
[qnum
].axq_aggr_depth
;
2325 /* Check if an ADDBA is required. A valid node must be passed. */
2326 enum ATH_AGGR_CHECK
ath_tx_aggr_check(struct ath_softc
*sc
,
2327 struct ath_node
*an
,
2330 struct ath_atx_tid
*txtid
;
2332 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
2333 return AGGR_NOT_REQUIRED
;
2335 /* ADDBA exchange must be completed before sending aggregates */
2336 txtid
= ATH_AN_2_TID(an
, tidno
);
2338 if (txtid
->addba_exchangecomplete
)
2339 return AGGR_EXCHANGE_DONE
;
2341 if (txtid
->cleanup_inprogress
)
2342 return AGGR_CLEANUP_PROGRESS
;
2344 if (txtid
->addba_exchangeinprogress
)
2345 return AGGR_EXCHANGE_PROGRESS
;
2347 if (!txtid
->addba_exchangecomplete
) {
2348 if (!txtid
->addba_exchangeinprogress
&&
2349 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
2350 txtid
->addba_exchangeattempts
++;
2351 return AGGR_REQUIRED
;
2355 return AGGR_NOT_REQUIRED
;
2358 /* Start TX aggregation */
2360 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
2363 struct ath_atx_tid
*txtid
;
2364 struct ath_node
*an
;
2366 an
= (struct ath_node
*)sta
->drv_priv
;
2368 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2369 txtid
= ATH_AN_2_TID(an
, tid
);
2370 txtid
->addba_exchangeinprogress
= 1;
2371 ath_tx_pause_tid(sc
, txtid
);
2377 /* Stop tx aggregation */
2379 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2381 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
2383 ath_tx_aggr_teardown(sc
, an
, tid
);
2388 * Performs transmit side cleanup when TID changes from aggregated to
2390 * - Pause the TID and mark cleanup in progress
2391 * - Discard all retry frames from the s/w queue.
2394 void ath_tx_aggr_teardown(struct ath_softc
*sc
, struct ath_node
*an
, u8 tid
)
2396 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
2397 struct ath_txq
*txq
= &sc
->sc_txq
[txtid
->ac
->qnum
];
2399 struct list_head bf_head
;
2400 INIT_LIST_HEAD(&bf_head
);
2402 DPRINTF(sc
, ATH_DBG_AGGR
, "%s: teardown TX aggregation\n", __func__
);
2404 if (txtid
->cleanup_inprogress
) /* cleanup is in progress */
2407 if (!txtid
->addba_exchangecomplete
) {
2408 txtid
->addba_exchangeattempts
= 0;
2412 /* TID must be paused first */
2413 ath_tx_pause_tid(sc
, txtid
);
2415 /* drop all software retried frames and mark this TID */
2416 spin_lock_bh(&txq
->axq_lock
);
2417 while (!list_empty(&txtid
->buf_q
)) {
2418 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
2419 if (!bf_isretried(bf
)) {
2421 * NB: it's based on the assumption that
2422 * software retried frame will always stay
2423 * at the head of software queue.
2427 list_cut_position(&bf_head
,
2428 &txtid
->buf_q
, &bf
->bf_lastfrm
->list
);
2429 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
2431 /* complete this sub-frame */
2432 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2435 if (txtid
->baw_head
!= txtid
->baw_tail
) {
2436 spin_unlock_bh(&txq
->axq_lock
);
2437 txtid
->cleanup_inprogress
= true;
2439 txtid
->addba_exchangecomplete
= 0;
2440 txtid
->addba_exchangeattempts
= 0;
2441 spin_unlock_bh(&txq
->axq_lock
);
2442 ath_tx_flush_tid(sc
, txtid
);
2447 * Tx scheduling logic
2448 * NB: must be called with txq lock held
2451 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
2453 struct ath_atx_ac
*ac
;
2454 struct ath_atx_tid
*tid
;
2456 /* nothing to schedule */
2457 if (list_empty(&txq
->axq_acq
))
2460 * get the first node/ac pair on the queue
2462 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
2463 list_del(&ac
->list
);
2467 * process a single tid per destination
2470 /* nothing to schedule */
2471 if (list_empty(&ac
->tid_q
))
2474 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
2475 list_del(&tid
->list
);
2478 if (tid
->paused
) /* check next tid to keep h/w busy */
2481 if ((txq
->axq_depth
% 2) == 0)
2482 ath_tx_sched_aggr(sc
, txq
, tid
);
2485 * add tid to round-robin queue if more frames
2486 * are pending for the tid
2488 if (!list_empty(&tid
->buf_q
))
2489 ath_tx_queue_tid(txq
, tid
);
2491 /* only schedule one TID at a time */
2493 } while (!list_empty(&ac
->tid_q
));
2496 * schedule AC if more TIDs need processing
2498 if (!list_empty(&ac
->tid_q
)) {
2500 * add dest ac to txq if not already added
2504 list_add_tail(&ac
->list
, &txq
->axq_acq
);
2509 /* Initialize per-node transmit state */
2511 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2513 struct ath_atx_tid
*tid
;
2514 struct ath_atx_ac
*ac
;
2518 * Init per tid tx state
2520 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2521 tidno
< WME_NUM_TID
;
2525 tid
->seq_start
= tid
->seq_next
= 0;
2526 tid
->baw_size
= WME_MAX_BA
;
2527 tid
->baw_head
= tid
->baw_tail
= 0;
2529 tid
->paused
= false;
2530 tid
->cleanup_inprogress
= false;
2531 INIT_LIST_HEAD(&tid
->buf_q
);
2533 acno
= TID_TO_WME_AC(tidno
);
2534 tid
->ac
= &an
->an_aggr
.tx
.ac
[acno
];
2537 tid
->addba_exchangecomplete
= 0;
2538 tid
->addba_exchangeinprogress
= 0;
2539 tid
->addba_exchangeattempts
= 0;
2543 * Init per ac tx state
2545 for (acno
= 0, ac
= &an
->an_aggr
.tx
.ac
[acno
];
2546 acno
< WME_NUM_AC
; acno
++, ac
++) {
2548 INIT_LIST_HEAD(&ac
->tid_q
);
2552 ac
->qnum
= ath_tx_get_qnum(sc
,
2553 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2556 ac
->qnum
= ath_tx_get_qnum(sc
,
2557 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2560 ac
->qnum
= ath_tx_get_qnum(sc
,
2561 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2564 ac
->qnum
= ath_tx_get_qnum(sc
,
2565 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2571 /* Cleanupthe pending buffers for the node. */
2573 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2576 struct ath_atx_ac
*ac
, *ac_tmp
;
2577 struct ath_atx_tid
*tid
, *tid_tmp
;
2578 struct ath_txq
*txq
;
2579 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2580 if (ATH_TXQ_SETUP(sc
, i
)) {
2581 txq
= &sc
->sc_txq
[i
];
2583 spin_lock(&txq
->axq_lock
);
2585 list_for_each_entry_safe(ac
,
2586 ac_tmp
, &txq
->axq_acq
, list
) {
2587 tid
= list_first_entry(&ac
->tid_q
,
2588 struct ath_atx_tid
, list
);
2589 if (tid
&& tid
->an
!= an
)
2591 list_del(&ac
->list
);
2594 list_for_each_entry_safe(tid
,
2595 tid_tmp
, &ac
->tid_q
, list
) {
2596 list_del(&tid
->list
);
2598 ath_tid_drain(sc
, txq
, tid
);
2599 tid
->addba_exchangecomplete
= 0;
2600 tid
->addba_exchangeattempts
= 0;
2601 tid
->cleanup_inprogress
= false;
2605 spin_unlock(&txq
->axq_lock
);
2610 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2612 int hdrlen
, padsize
;
2613 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2614 struct ath_tx_control txctl
;
2616 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2619 * As a temporary workaround, assign seq# here; this will likely need
2620 * to be cleaned up to work better with Beacon transmission and virtual
2623 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2624 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2625 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2627 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2628 hdr
->seq_ctrl
|= cpu_to_le16(sc
->seq_no
);
2631 /* Add the padding after the header if this is not already done */
2632 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2634 padsize
= hdrlen
% 4;
2635 if (skb_headroom(skb
) < padsize
) {
2636 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX CABQ padding "
2637 "failed\n", __func__
);
2638 dev_kfree_skb_any(skb
);
2641 skb_push(skb
, padsize
);
2642 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2645 txctl
.txq
= sc
->sc_cabq
;
2647 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: transmitting CABQ packet, skb: %p\n",
2651 if (ath_tx_start(sc
, skb
, &txctl
) != 0) {
2652 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX failed\n", __func__
);
2658 dev_kfree_skb_any(skb
);