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[PATCH] dm-md-dependency-tree-in-sysfs-holders-slaves-subdirectory-tidy
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ns83820.c
blob0fede50abd3e276e743d066ccfcd3f1f56bbaecc
1 #define VERSION "0.22"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/config.h>
100 #include <linux/module.h>
101 #include <linux/moduleparam.h>
102 #include <linux/types.h>
103 #include <linux/pci.h>
104 #include <linux/dma-mapping.h>
105 #include <linux/netdevice.h>
106 #include <linux/etherdevice.h>
107 #include <linux/delay.h>
108 #include <linux/smp_lock.h>
109 #include <linux/workqueue.h>
110 #include <linux/init.h>
111 #include <linux/ip.h> /* for iph */
112 #include <linux/in.h> /* for IPPROTO_... */
113 #include <linux/compiler.h>
114 #include <linux/prefetch.h>
115 #include <linux/ethtool.h>
116 #include <linux/timer.h>
117 #include <linux/if_vlan.h>
118 #include <linux/rtnetlink.h>
119 #include <linux/jiffies.h>
120
121 #include <asm/io.h>
122 #include <asm/uaccess.h>
123 #include <asm/system.h>
124
125 #define DRV_NAME "ns83820"
126
127 /* Global parameters. See module_param near the bottom. */
128 static int ihr = 2;
129 static int reset_phy = 0;
130 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
131
132 /* Dprintk is used for more interesting debug events */
133 #undef Dprintk
134 #define Dprintk dprintk
135
136 /* tunables */
137 #define RX_BUF_SIZE 1500 /* 8192 */
138 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
139 #define NS83820_VLAN_ACCEL_SUPPORT
140 #endif
141
142 /* Must not exceed ~65000. */
143 #define NR_RX_DESC 64
144 #define NR_TX_DESC 128
145
146 /* not tunable */
147 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
148
149 #define MIN_TX_DESC_FREE 8
150
151 /* register defines */
152 #define CFGCS 0x04
153
154 #define CR_TXE 0x00000001
155 #define CR_TXD 0x00000002
156 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
157 * The Receive engine skips one descriptor and moves
158 * onto the next one!! */
159 #define CR_RXE 0x00000004
160 #define CR_RXD 0x00000008
161 #define CR_TXR 0x00000010
162 #define CR_RXR 0x00000020
163 #define CR_SWI 0x00000080
164 #define CR_RST 0x00000100
165
166 #define PTSCR_EEBIST_FAIL 0x00000001
167 #define PTSCR_EEBIST_EN 0x00000002
168 #define PTSCR_EELOAD_EN 0x00000004
169 #define PTSCR_RBIST_FAIL 0x000001b8
170 #define PTSCR_RBIST_DONE 0x00000200
171 #define PTSCR_RBIST_EN 0x00000400
172 #define PTSCR_RBIST_RST 0x00002000
173
174 #define MEAR_EEDI 0x00000001
175 #define MEAR_EEDO 0x00000002
176 #define MEAR_EECLK 0x00000004
177 #define MEAR_EESEL 0x00000008
178 #define MEAR_MDIO 0x00000010
179 #define MEAR_MDDIR 0x00000020
180 #define MEAR_MDC 0x00000040
181
182 #define ISR_TXDESC3 0x40000000
183 #define ISR_TXDESC2 0x20000000
184 #define ISR_TXDESC1 0x10000000
185 #define ISR_TXDESC0 0x08000000
186 #define ISR_RXDESC3 0x04000000
187 #define ISR_RXDESC2 0x02000000
188 #define ISR_RXDESC1 0x01000000
189 #define ISR_RXDESC0 0x00800000
190 #define ISR_TXRCMP 0x00400000
191 #define ISR_RXRCMP 0x00200000
192 #define ISR_DPERR 0x00100000
193 #define ISR_SSERR 0x00080000
194 #define ISR_RMABT 0x00040000
195 #define ISR_RTABT 0x00020000
196 #define ISR_RXSOVR 0x00010000
197 #define ISR_HIBINT 0x00008000
198 #define ISR_PHY 0x00004000
199 #define ISR_PME 0x00002000
200 #define ISR_SWI 0x00001000
201 #define ISR_MIB 0x00000800
202 #define ISR_TXURN 0x00000400
203 #define ISR_TXIDLE 0x00000200
204 #define ISR_TXERR 0x00000100
205 #define ISR_TXDESC 0x00000080
206 #define ISR_TXOK 0x00000040
207 #define ISR_RXORN 0x00000020
208 #define ISR_RXIDLE 0x00000010
209 #define ISR_RXEARLY 0x00000008
210 #define ISR_RXERR 0x00000004
211 #define ISR_RXDESC 0x00000002
212 #define ISR_RXOK 0x00000001
213
214 #define TXCFG_CSI 0x80000000
215 #define TXCFG_HBI 0x40000000
216 #define TXCFG_MLB 0x20000000
217 #define TXCFG_ATP 0x10000000
218 #define TXCFG_ECRETRY 0x00800000
219 #define TXCFG_BRST_DIS 0x00080000
220 #define TXCFG_MXDMA1024 0x00000000
221 #define TXCFG_MXDMA512 0x00700000
222 #define TXCFG_MXDMA256 0x00600000
223 #define TXCFG_MXDMA128 0x00500000
224 #define TXCFG_MXDMA64 0x00400000
225 #define TXCFG_MXDMA32 0x00300000
226 #define TXCFG_MXDMA16 0x00200000
227 #define TXCFG_MXDMA8 0x00100000
228
229 #define CFG_LNKSTS 0x80000000
230 #define CFG_SPDSTS 0x60000000
231 #define CFG_SPDSTS1 0x40000000
232 #define CFG_SPDSTS0 0x20000000
233 #define CFG_DUPSTS 0x10000000
234 #define CFG_TBI_EN 0x01000000
235 #define CFG_MODE_1000 0x00400000
236 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
237 * Read the Phy response and then configure the MAC accordingly */
238 #define CFG_AUTO_1000 0x00200000
239 #define CFG_PINT_CTL 0x001c0000
240 #define CFG_PINT_DUPSTS 0x00100000
241 #define CFG_PINT_LNKSTS 0x00080000
242 #define CFG_PINT_SPDSTS 0x00040000
243 #define CFG_TMRTEST 0x00020000
244 #define CFG_MRM_DIS 0x00010000
245 #define CFG_MWI_DIS 0x00008000
246 #define CFG_T64ADDR 0x00004000
247 #define CFG_PCI64_DET 0x00002000
248 #define CFG_DATA64_EN 0x00001000
249 #define CFG_M64ADDR 0x00000800
250 #define CFG_PHY_RST 0x00000400
251 #define CFG_PHY_DIS 0x00000200
252 #define CFG_EXTSTS_EN 0x00000100
253 #define CFG_REQALG 0x00000080
254 #define CFG_SB 0x00000040
255 #define CFG_POW 0x00000020
256 #define CFG_EXD 0x00000010
257 #define CFG_PESEL 0x00000008
258 #define CFG_BROM_DIS 0x00000004
259 #define CFG_EXT_125 0x00000002
260 #define CFG_BEM 0x00000001
261
262 #define EXTSTS_UDPPKT 0x00200000
263 #define EXTSTS_TCPPKT 0x00080000
264 #define EXTSTS_IPPKT 0x00020000
265 #define EXTSTS_VPKT 0x00010000
266 #define EXTSTS_VTG_MASK 0x0000ffff
267
268 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
269
270 #define MIBC_MIBS 0x00000008
271 #define MIBC_ACLR 0x00000004
272 #define MIBC_FRZ 0x00000002
273 #define MIBC_WRN 0x00000001
274
275 #define PCR_PSEN (1 << 31)
276 #define PCR_PS_MCAST (1 << 30)
277 #define PCR_PS_DA (1 << 29)
278 #define PCR_STHI_8 (3 << 23)
279 #define PCR_STLO_4 (1 << 23)
280 #define PCR_FFHI_8K (3 << 21)
281 #define PCR_FFLO_4K (1 << 21)
282 #define PCR_PAUSE_CNT 0xFFFE
283
284 #define RXCFG_AEP 0x80000000
285 #define RXCFG_ARP 0x40000000
286 #define RXCFG_STRIPCRC 0x20000000
287 #define RXCFG_RX_FD 0x10000000
288 #define RXCFG_ALP 0x08000000
289 #define RXCFG_AIRL 0x04000000
290 #define RXCFG_MXDMA512 0x00700000
291 #define RXCFG_DRTH 0x0000003e
292 #define RXCFG_DRTH0 0x00000002
293
294 #define RFCR_RFEN 0x80000000
295 #define RFCR_AAB 0x40000000
296 #define RFCR_AAM 0x20000000
297 #define RFCR_AAU 0x10000000
298 #define RFCR_APM 0x08000000
299 #define RFCR_APAT 0x07800000
300 #define RFCR_APAT3 0x04000000
301 #define RFCR_APAT2 0x02000000
302 #define RFCR_APAT1 0x01000000
303 #define RFCR_APAT0 0x00800000
304 #define RFCR_AARP 0x00400000
305 #define RFCR_MHEN 0x00200000
306 #define RFCR_UHEN 0x00100000
307 #define RFCR_ULM 0x00080000
308
309 #define VRCR_RUDPE 0x00000080
310 #define VRCR_RTCPE 0x00000040
311 #define VRCR_RIPE 0x00000020
312 #define VRCR_IPEN 0x00000010
313 #define VRCR_DUTF 0x00000008
314 #define VRCR_DVTF 0x00000004
315 #define VRCR_VTREN 0x00000002
316 #define VRCR_VTDEN 0x00000001
317
318 #define VTCR_PPCHK 0x00000008
319 #define VTCR_GCHK 0x00000004
320 #define VTCR_VPPTI 0x00000002
321 #define VTCR_VGTI 0x00000001
322
323 #define CR 0x00
324 #define CFG 0x04
325 #define MEAR 0x08
326 #define PTSCR 0x0c
327 #define ISR 0x10
328 #define IMR 0x14
329 #define IER 0x18
330 #define IHR 0x1c
331 #define TXDP 0x20
332 #define TXDP_HI 0x24
333 #define TXCFG 0x28
334 #define GPIOR 0x2c
335 #define RXDP 0x30
336 #define RXDP_HI 0x34
337 #define RXCFG 0x38
338 #define PQCR 0x3c
339 #define WCSR 0x40
340 #define PCR 0x44
341 #define RFCR 0x48
342 #define RFDR 0x4c
343
344 #define SRR 0x58
345
346 #define VRCR 0xbc
347 #define VTCR 0xc0
348 #define VDR 0xc4
349 #define CCSR 0xcc
350
351 #define TBICR 0xe0
352 #define TBISR 0xe4
353 #define TANAR 0xe8
354 #define TANLPAR 0xec
355 #define TANER 0xf0
356 #define TESR 0xf4
357
358 #define TBICR_MR_AN_ENABLE 0x00001000
359 #define TBICR_MR_RESTART_AN 0x00000200
360
361 #define TBISR_MR_LINK_STATUS 0x00000020
362 #define TBISR_MR_AN_COMPLETE 0x00000004
363
364 #define TANAR_PS2 0x00000100
365 #define TANAR_PS1 0x00000080
366 #define TANAR_HALF_DUP 0x00000040
367 #define TANAR_FULL_DUP 0x00000020
368
369 #define GPIOR_GP5_OE 0x00000200
370 #define GPIOR_GP4_OE 0x00000100
371 #define GPIOR_GP3_OE 0x00000080
372 #define GPIOR_GP2_OE 0x00000040
373 #define GPIOR_GP1_OE 0x00000020
374 #define GPIOR_GP3_OUT 0x00000004
375 #define GPIOR_GP1_OUT 0x00000001
376
377 #define LINK_AUTONEGOTIATE 0x01
378 #define LINK_DOWN 0x02
379 #define LINK_UP 0x04
380
381 #define HW_ADDR_LEN sizeof(dma_addr_t)
382 #define desc_addr_set(desc, addr) \
383 do { \
384 ((desc)[0] = cpu_to_le32(addr)); \
385 if (HW_ADDR_LEN == 8) \
386 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
387 } while(0)
388 #define desc_addr_get(desc) \
389 (le32_to_cpu((desc)[0]) | \
390 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
391
392 #define DESC_LINK 0
393 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
394 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
395 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
396
397 #define CMDSTS_OWN 0x80000000
398 #define CMDSTS_MORE 0x40000000
399 #define CMDSTS_INTR 0x20000000
400 #define CMDSTS_ERR 0x10000000
401 #define CMDSTS_OK 0x08000000
402 #define CMDSTS_RUNT 0x00200000
403 #define CMDSTS_LEN_MASK 0x0000ffff
404
405 #define CMDSTS_DEST_MASK 0x01800000
406 #define CMDSTS_DEST_SELF 0x00800000
407 #define CMDSTS_DEST_MULTI 0x01000000
408
409 #define DESC_SIZE 8 /* Should be cache line sized */
410
411 struct rx_info {
412 spinlock_t lock;
413 int up;
414 long idle;
415
416 struct sk_buff *skbs[NR_RX_DESC];
417
418 u32 *next_rx_desc;
419 u16 next_rx, next_empty;
420
421 u32 *descs;
422 dma_addr_t phy_descs;
423 };
424
425
426 struct ns83820 {
427 struct net_device_stats stats;
428 u8 __iomem *base;
429
430 struct pci_dev *pci_dev;
431
432 #ifdef NS83820_VLAN_ACCEL_SUPPORT
433 struct vlan_group *vlgrp;
434 #endif
435
436 struct rx_info rx_info;
437 struct tasklet_struct rx_tasklet;
438
439 unsigned ihr;
440 struct work_struct tq_refill;
441
442 /* protects everything below. irqsave when using. */
443 spinlock_t misc_lock;
444
445 u32 CFG_cache;
446
447 u32 MEAR_cache;
448 u32 IMR_cache;
449
450 unsigned linkstate;
451
452 spinlock_t tx_lock;
453
454 u16 tx_done_idx;
455 u16 tx_idx;
456 volatile u16 tx_free_idx; /* idx of free desc chain */
457 u16 tx_intr_idx;
458
459 atomic_t nr_tx_skbs;
460 struct sk_buff *tx_skbs[NR_TX_DESC];
461
462 char pad[16] __attribute__((aligned(16)));
463 u32 *tx_descs;
464 dma_addr_t tx_phy_descs;
465
466 struct timer_list tx_watchdog;
467 };
468
469 static inline struct ns83820 *PRIV(struct net_device *dev)
470 {
471 return netdev_priv(dev);
472 }
473
474 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
475
476 static inline void kick_rx(struct net_device *ndev)
477 {
478 struct ns83820 *dev = PRIV(ndev);
479 dprintk("kick_rx: maybe kicking\n");
480 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
481 dprintk("actually kicking\n");
482 writel(dev->rx_info.phy_descs +
483 (4 * DESC_SIZE * dev->rx_info.next_rx),
484 dev->base + RXDP);
485 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
486 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
487 ndev->name);
488 __kick_rx(dev);
489 }
490 }
491
492 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
493 #define start_tx_okay(dev) \
494 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
495
496
497 #ifdef NS83820_VLAN_ACCEL_SUPPORT
498 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
499 {
500 struct ns83820 *dev = PRIV(ndev);
501
502 spin_lock_irq(&dev->misc_lock);
503 spin_lock(&dev->tx_lock);
504
505 dev->vlgrp = grp;
506
507 spin_unlock(&dev->tx_lock);
508 spin_unlock_irq(&dev->misc_lock);
509 }
510
511 static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
512 {
513 struct ns83820 *dev = PRIV(ndev);
514
515 spin_lock_irq(&dev->misc_lock);
516 spin_lock(&dev->tx_lock);
517 if (dev->vlgrp)
518 dev->vlgrp->vlan_devices[vid] = NULL;
519 spin_unlock(&dev->tx_lock);
520 spin_unlock_irq(&dev->misc_lock);
521 }
522 #endif
523
524 /* Packet Receiver
525 *
526 * The hardware supports linked lists of receive descriptors for
527 * which ownership is transfered back and forth by means of an
528 * ownership bit. While the hardware does support the use of a
529 * ring for receive descriptors, we only make use of a chain in
530 * an attempt to reduce bus traffic under heavy load scenarios.
531 * This will also make bugs a bit more obvious. The current code
532 * only makes use of a single rx chain; I hope to implement
533 * priority based rx for version 1.0. Goal: even under overload
534 * conditions, still route realtime traffic with as low jitter as
535 * possible.
536 */
537 static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
538 {
539 desc_addr_set(desc + DESC_LINK, link);
540 desc_addr_set(desc + DESC_BUFPTR, buf);
541 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
542 mb();
543 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
544 }
545
546 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
547 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
548 {
549 unsigned next_empty;
550 u32 cmdsts;
551 u32 *sg;
552 dma_addr_t buf;
553
554 next_empty = dev->rx_info.next_empty;
555
556 /* don't overrun last rx marker */
557 if (unlikely(nr_rx_empty(dev) <= 2)) {
558 kfree_skb(skb);
559 return 1;
560 }
561
562 #if 0
563 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
564 dev->rx_info.next_empty,
565 dev->rx_info.nr_used,
566 dev->rx_info.next_rx
567 );
568 #endif
569
570 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
571 if (unlikely(NULL != dev->rx_info.skbs[next_empty]))
572 BUG();
573 dev->rx_info.skbs[next_empty] = skb;
574
575 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
576 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
577 buf = pci_map_single(dev->pci_dev, skb->data,
578 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
579 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
580 /* update link of previous rx */
581 if (likely(next_empty != dev->rx_info.next_rx))
582 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
583
584 return 0;
585 }
586
587 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
588 {
589 struct ns83820 *dev = PRIV(ndev);
590 unsigned i;
591 unsigned long flags = 0;
592
593 if (unlikely(nr_rx_empty(dev) <= 2))
594 return 0;
595
596 dprintk("rx_refill(%p)\n", ndev);
597 if (gfp == GFP_ATOMIC)
598 spin_lock_irqsave(&dev->rx_info.lock, flags);
599 for (i=0; i<NR_RX_DESC; i++) {
600 struct sk_buff *skb;
601 long res;
602 /* extra 16 bytes for alignment */
603 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
604 if (unlikely(!skb))
605 break;
606
607 res = (long)skb->data & 0xf;
608 res = 0x10 - res;
609 res &= 0xf;
610 skb_reserve(skb, res);
611
612 skb->dev = ndev;
613 if (gfp != GFP_ATOMIC)
614 spin_lock_irqsave(&dev->rx_info.lock, flags);
615 res = ns83820_add_rx_skb(dev, skb);
616 if (gfp != GFP_ATOMIC)
617 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
618 if (res) {
619 i = 1;
620 break;
621 }
622 }
623 if (gfp == GFP_ATOMIC)
624 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
625
626 return i ? 0 : -ENOMEM;
627 }
628
629 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
630 static void fastcall rx_refill_atomic(struct net_device *ndev)
631 {
632 rx_refill(ndev, GFP_ATOMIC);
633 }
634
635 /* REFILL */
636 static inline void queue_refill(void *_dev)
637 {
638 struct net_device *ndev = _dev;
639 struct ns83820 *dev = PRIV(ndev);
640
641 rx_refill(ndev, GFP_KERNEL);
642 if (dev->rx_info.up)
643 kick_rx(ndev);
644 }
645
646 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
647 {
648 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
649 }
650
651 static void FASTCALL(phy_intr(struct net_device *ndev));
652 static void fastcall phy_intr(struct net_device *ndev)
653 {
654 struct ns83820 *dev = PRIV(ndev);
655 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
656 u32 cfg, new_cfg;
657 u32 tbisr, tanar, tanlpar;
658 int speed, fullduplex, newlinkstate;
659
660 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
661
662 if (dev->CFG_cache & CFG_TBI_EN) {
663 /* we have an optical transceiver */
664 tbisr = readl(dev->base + TBISR);
665 tanar = readl(dev->base + TANAR);
666 tanlpar = readl(dev->base + TANLPAR);
667 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
668 tbisr, tanar, tanlpar);
669
670 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
671 && (tanar & TANAR_FULL_DUP)) ) {
672
673 /* both of us are full duplex */
674 writel(readl(dev->base + TXCFG)
675 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
676 dev->base + TXCFG);
677 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
678 dev->base + RXCFG);
679 /* Light up full duplex LED */
680 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
681 dev->base + GPIOR);
682
683 } else if(((tanlpar & TANAR_HALF_DUP)
684 && (tanar & TANAR_HALF_DUP))
685 || ((tanlpar & TANAR_FULL_DUP)
686 && (tanar & TANAR_HALF_DUP))
687 || ((tanlpar & TANAR_HALF_DUP)
688 && (tanar & TANAR_FULL_DUP))) {
689
690 /* one or both of us are half duplex */
691 writel((readl(dev->base + TXCFG)
692 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
693 dev->base + TXCFG);
694 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
695 dev->base + RXCFG);
696 /* Turn off full duplex LED */
697 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
698 dev->base + GPIOR);
699 }
700
701 speed = 4; /* 1000F */
702
703 } else {
704 /* we have a copper transceiver */
705 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
706
707 if (cfg & CFG_SPDSTS1)
708 new_cfg |= CFG_MODE_1000;
709 else
710 new_cfg &= ~CFG_MODE_1000;
711
712 speed = ((cfg / CFG_SPDSTS0) & 3);
713 fullduplex = (cfg & CFG_DUPSTS);
714
715 if (fullduplex) {
716 new_cfg |= CFG_SB;
717 writel(readl(dev->base + TXCFG)
718 | TXCFG_CSI | TXCFG_HBI,
719 dev->base + TXCFG);
720 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
721 dev->base + RXCFG);
722 } else {
723 writel(readl(dev->base + TXCFG)
724 & ~(TXCFG_CSI | TXCFG_HBI),
725 dev->base + TXCFG);
726 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
727 dev->base + RXCFG);
728 }
729
730 if ((cfg & CFG_LNKSTS) &&
731 ((new_cfg ^ dev->CFG_cache) != 0)) {
732 writel(new_cfg, dev->base + CFG);
733 dev->CFG_cache = new_cfg;
734 }
735
736 dev->CFG_cache &= ~CFG_SPDSTS;
737 dev->CFG_cache |= cfg & CFG_SPDSTS;
738 }
739
740 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
741
742 if (newlinkstate & LINK_UP
743 && dev->linkstate != newlinkstate) {
744 netif_start_queue(ndev);
745 netif_wake_queue(ndev);
746 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
747 ndev->name,
748 speeds[speed],
749 fullduplex ? "full" : "half");
750 } else if (newlinkstate & LINK_DOWN
751 && dev->linkstate != newlinkstate) {
752 netif_stop_queue(ndev);
753 printk(KERN_INFO "%s: link now down.\n", ndev->name);
754 }
755
756 dev->linkstate = newlinkstate;
757 }
758
759 static int ns83820_setup_rx(struct net_device *ndev)
760 {
761 struct ns83820 *dev = PRIV(ndev);
762 unsigned i;
763 int ret;
764
765 dprintk("ns83820_setup_rx(%p)\n", ndev);
766
767 dev->rx_info.idle = 1;
768 dev->rx_info.next_rx = 0;
769 dev->rx_info.next_rx_desc = dev->rx_info.descs;
770 dev->rx_info.next_empty = 0;
771
772 for (i=0; i<NR_RX_DESC; i++)
773 clear_rx_desc(dev, i);
774
775 writel(0, dev->base + RXDP_HI);
776 writel(dev->rx_info.phy_descs, dev->base + RXDP);
777
778 ret = rx_refill(ndev, GFP_KERNEL);
779 if (!ret) {
780 dprintk("starting receiver\n");
781 /* prevent the interrupt handler from stomping on us */
782 spin_lock_irq(&dev->rx_info.lock);
783
784 writel(0x0001, dev->base + CCSR);
785 writel(0, dev->base + RFCR);
786 writel(0x7fc00000, dev->base + RFCR);
787 writel(0xffc00000, dev->base + RFCR);
788
789 dev->rx_info.up = 1;
790
791 phy_intr(ndev);
792
793 /* Okay, let it rip */
794 spin_lock_irq(&dev->misc_lock);
795 dev->IMR_cache |= ISR_PHY;
796 dev->IMR_cache |= ISR_RXRCMP;
797 //dev->IMR_cache |= ISR_RXERR;
798 //dev->IMR_cache |= ISR_RXOK;
799 dev->IMR_cache |= ISR_RXORN;
800 dev->IMR_cache |= ISR_RXSOVR;
801 dev->IMR_cache |= ISR_RXDESC;
802 dev->IMR_cache |= ISR_RXIDLE;
803 dev->IMR_cache |= ISR_TXDESC;
804 dev->IMR_cache |= ISR_TXIDLE;
805
806 writel(dev->IMR_cache, dev->base + IMR);
807 writel(1, dev->base + IER);
808 spin_unlock_irq(&dev->misc_lock);
809
810 kick_rx(ndev);
811
812 spin_unlock_irq(&dev->rx_info.lock);
813 }
814 return ret;
815 }
816
817 static void ns83820_cleanup_rx(struct ns83820 *dev)
818 {
819 unsigned i;
820 unsigned long flags;
821
822 dprintk("ns83820_cleanup_rx(%p)\n", dev);
823
824 /* disable receive interrupts */
825 spin_lock_irqsave(&dev->misc_lock, flags);
826 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
827 writel(dev->IMR_cache, dev->base + IMR);
828 spin_unlock_irqrestore(&dev->misc_lock, flags);
829
830 /* synchronize with the interrupt handler and kill it */
831 dev->rx_info.up = 0;
832 synchronize_irq(dev->pci_dev->irq);
833
834 /* touch the pci bus... */
835 readl(dev->base + IMR);
836
837 /* assumes the transmitter is already disabled and reset */
838 writel(0, dev->base + RXDP_HI);
839 writel(0, dev->base + RXDP);
840
841 for (i=0; i<NR_RX_DESC; i++) {
842 struct sk_buff *skb = dev->rx_info.skbs[i];
843 dev->rx_info.skbs[i] = NULL;
844 clear_rx_desc(dev, i);
845 if (skb)
846 kfree_skb(skb);
847 }
848 }
849
850 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
851 static void fastcall ns83820_rx_kick(struct net_device *ndev)
852 {
853 struct ns83820 *dev = PRIV(ndev);
854 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
855 if (dev->rx_info.up) {
856 rx_refill_atomic(ndev);
857 kick_rx(ndev);
858 }
859 }
860
861 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
862 schedule_work(&dev->tq_refill);
863 else
864 kick_rx(ndev);
865 if (dev->rx_info.idle)
866 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
867 }
868
869 /* rx_irq
870 *
871 */
872 static void FASTCALL(rx_irq(struct net_device *ndev));
873 static void fastcall rx_irq(struct net_device *ndev)
874 {
875 struct ns83820 *dev = PRIV(ndev);
876 struct rx_info *info = &dev->rx_info;
877 unsigned next_rx;
878 int rx_rc, len;
879 u32 cmdsts, *desc;
880 unsigned long flags;
881 int nr = 0;
882
883 dprintk("rx_irq(%p)\n", ndev);
884 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
885 readl(dev->base + RXDP),
886 (long)(dev->rx_info.phy_descs),
887 (int)dev->rx_info.next_rx,
888 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
889 (int)dev->rx_info.next_empty,
890 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
891 );
892
893 spin_lock_irqsave(&info->lock, flags);
894 if (!info->up)
895 goto out;
896
897 dprintk("walking descs\n");
898 next_rx = info->next_rx;
899 desc = info->next_rx_desc;
900 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
901 (cmdsts != CMDSTS_OWN)) {
902 struct sk_buff *skb;
903 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
904 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
905
906 dprintk("cmdsts: %08x\n", cmdsts);
907 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
908 dprintk("extsts: %08x\n", extsts);
909
910 skb = info->skbs[next_rx];
911 info->skbs[next_rx] = NULL;
912 info->next_rx = (next_rx + 1) % NR_RX_DESC;
913
914 mb();
915 clear_rx_desc(dev, next_rx);
916
917 pci_unmap_single(dev->pci_dev, bufptr,
918 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
919 len = cmdsts & CMDSTS_LEN_MASK;
920 #ifdef NS83820_VLAN_ACCEL_SUPPORT
921 /* NH: As was mentioned below, this chip is kinda
922 * brain dead about vlan tag stripping. Frames
923 * that are 64 bytes with a vlan header appended
924 * like arp frames, or pings, are flagged as Runts
925 * when the tag is stripped and hardware. This
926 * also means that the OK bit in the descriptor
927 * is cleared when the frame comes in so we have
928 * to do a specific length check here to make sure
929 * the frame would have been ok, had we not stripped
930 * the tag.
931 */
932 if (likely((CMDSTS_OK & cmdsts) ||
933 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
934 #else
935 if (likely(CMDSTS_OK & cmdsts)) {
936 #endif
937 skb_put(skb, len);
938 if (unlikely(!skb))
939 goto netdev_mangle_me_harder_failed;
940 if (cmdsts & CMDSTS_DEST_MULTI)
941 dev->stats.multicast ++;
942 dev->stats.rx_packets ++;
943 dev->stats.rx_bytes += len;
944 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
945 skb->ip_summed = CHECKSUM_UNNECESSARY;
946 } else {
947 skb->ip_summed = CHECKSUM_NONE;
948 }
949 skb->protocol = eth_type_trans(skb, ndev);
950 #ifdef NS83820_VLAN_ACCEL_SUPPORT
951 if(extsts & EXTSTS_VPKT) {
952 unsigned short tag;
953 tag = ntohs(extsts & EXTSTS_VTG_MASK);
954 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
955 } else {
956 rx_rc = netif_rx(skb);
957 }
958 #else
959 rx_rc = netif_rx(skb);
960 #endif
961 if (NET_RX_DROP == rx_rc) {
962 netdev_mangle_me_harder_failed:
963 dev->stats.rx_dropped ++;
964 }
965 } else {
966 kfree_skb(skb);
967 }
968
969 nr++;
970 next_rx = info->next_rx;
971 desc = info->descs + (DESC_SIZE * next_rx);
972 }
973 info->next_rx = next_rx;
974 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
975
976 out:
977 if (0 && !nr) {
978 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
979 }
980
981 spin_unlock_irqrestore(&info->lock, flags);
982 }
983
984 static void rx_action(unsigned long _dev)
985 {
986 struct net_device *ndev = (void *)_dev;
987 struct ns83820 *dev = PRIV(ndev);
988 rx_irq(ndev);
989 writel(ihr, dev->base + IHR);
990
991 spin_lock_irq(&dev->misc_lock);
992 dev->IMR_cache |= ISR_RXDESC;
993 writel(dev->IMR_cache, dev->base + IMR);
994 spin_unlock_irq(&dev->misc_lock);
995
996 rx_irq(ndev);
997 ns83820_rx_kick(ndev);
998 }
999
1000 /* Packet Transmit code
1001 */
1002 static inline void kick_tx(struct ns83820 *dev)
1003 {
1004 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1005 dev, dev->tx_idx, dev->tx_free_idx);
1006 writel(CR_TXE, dev->base + CR);
1007 }
1008
1009 /* No spinlock needed on the transmit irq path as the interrupt handler is
1010 * serialized.
1011 */
1012 static void do_tx_done(struct net_device *ndev)
1013 {
1014 struct ns83820 *dev = PRIV(ndev);
1015 u32 cmdsts, tx_done_idx, *desc;
1016
1017 spin_lock_irq(&dev->tx_lock);
1018
1019 dprintk("do_tx_done(%p)\n", ndev);
1020 tx_done_idx = dev->tx_done_idx;
1021 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1022
1023 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1024 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1025 while ((tx_done_idx != dev->tx_free_idx) &&
1026 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1027 struct sk_buff *skb;
1028 unsigned len;
1029 dma_addr_t addr;
1030
1031 if (cmdsts & CMDSTS_ERR)
1032 dev->stats.tx_errors ++;
1033 if (cmdsts & CMDSTS_OK)
1034 dev->stats.tx_packets ++;
1035 if (cmdsts & CMDSTS_OK)
1036 dev->stats.tx_bytes += cmdsts & 0xffff;
1037
1038 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1039 tx_done_idx, dev->tx_free_idx, cmdsts);
1040 skb = dev->tx_skbs[tx_done_idx];
1041 dev->tx_skbs[tx_done_idx] = NULL;
1042 dprintk("done(%p)\n", skb);
1043
1044 len = cmdsts & CMDSTS_LEN_MASK;
1045 addr = desc_addr_get(desc + DESC_BUFPTR);
1046 if (skb) {
1047 pci_unmap_single(dev->pci_dev,
1048 addr,
1049 len,
1050 PCI_DMA_TODEVICE);
1051 dev_kfree_skb_irq(skb);
1052 atomic_dec(&dev->nr_tx_skbs);
1053 } else
1054 pci_unmap_page(dev->pci_dev,
1055 addr,
1056 len,
1057 PCI_DMA_TODEVICE);
1058
1059 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1060 dev->tx_done_idx = tx_done_idx;
1061 desc[DESC_CMDSTS] = cpu_to_le32(0);
1062 mb();
1063 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1064 }
1065
1066 /* Allow network stack to resume queueing packets after we've
1067 * finished transmitting at least 1/4 of the packets in the queue.
1068 */
1069 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1070 dprintk("start_queue(%p)\n", ndev);
1071 netif_start_queue(ndev);
1072 netif_wake_queue(ndev);
1073 }
1074 spin_unlock_irq(&dev->tx_lock);
1075 }
1076
1077 static void ns83820_cleanup_tx(struct ns83820 *dev)
1078 {
1079 unsigned i;
1080
1081 for (i=0; i<NR_TX_DESC; i++) {
1082 struct sk_buff *skb = dev->tx_skbs[i];
1083 dev->tx_skbs[i] = NULL;
1084 if (skb) {
1085 u32 *desc = dev->tx_descs + (i * DESC_SIZE);
1086 pci_unmap_single(dev->pci_dev,
1087 desc_addr_get(desc + DESC_BUFPTR),
1088 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1089 PCI_DMA_TODEVICE);
1090 dev_kfree_skb_irq(skb);
1091 atomic_dec(&dev->nr_tx_skbs);
1092 }
1093 }
1094
1095 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1096 }
1097
1098 /* transmit routine. This code relies on the network layer serializing
1099 * its calls in, but will run happily in parallel with the interrupt
1100 * handler. This code currently has provisions for fragmenting tx buffers
1101 * while trying to track down a bug in either the zero copy code or
1102 * the tx fifo (hence the MAX_FRAG_LEN).
1103 */
1104 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1105 {
1106 struct ns83820 *dev = PRIV(ndev);
1107 u32 free_idx, cmdsts, extsts;
1108 int nr_free, nr_frags;
1109 unsigned tx_done_idx, last_idx;
1110 dma_addr_t buf;
1111 unsigned len;
1112 skb_frag_t *frag;
1113 int stopped = 0;
1114 int do_intr = 0;
1115 volatile u32 *first_desc;
1116
1117 dprintk("ns83820_hard_start_xmit\n");
1118
1119 nr_frags = skb_shinfo(skb)->nr_frags;
1120 again:
1121 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1122 netif_stop_queue(ndev);
1123 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1124 return 1;
1125 netif_start_queue(ndev);
1126 }
1127
1128 last_idx = free_idx = dev->tx_free_idx;
1129 tx_done_idx = dev->tx_done_idx;
1130 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1131 nr_free -= 1;
1132 if (nr_free <= nr_frags) {
1133 dprintk("stop_queue - not enough(%p)\n", ndev);
1134 netif_stop_queue(ndev);
1135
1136 /* Check again: we may have raced with a tx done irq */
1137 if (dev->tx_done_idx != tx_done_idx) {
1138 dprintk("restart queue(%p)\n", ndev);
1139 netif_start_queue(ndev);
1140 goto again;
1141 }
1142 return 1;
1143 }
1144
1145 if (free_idx == dev->tx_intr_idx) {
1146 do_intr = 1;
1147 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1148 }
1149
1150 nr_free -= nr_frags;
1151 if (nr_free < MIN_TX_DESC_FREE) {
1152 dprintk("stop_queue - last entry(%p)\n", ndev);
1153 netif_stop_queue(ndev);
1154 stopped = 1;
1155 }
1156
1157 frag = skb_shinfo(skb)->frags;
1158 if (!nr_frags)
1159 frag = NULL;
1160 extsts = 0;
1161 if (skb->ip_summed == CHECKSUM_HW) {
1162 extsts |= EXTSTS_IPPKT;
1163 if (IPPROTO_TCP == skb->nh.iph->protocol)
1164 extsts |= EXTSTS_TCPPKT;
1165 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1166 extsts |= EXTSTS_UDPPKT;
1167 }
1168
1169 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1170 if(vlan_tx_tag_present(skb)) {
1171 /* fetch the vlan tag info out of the
1172 * ancilliary data if the vlan code
1173 * is using hw vlan acceleration
1174 */
1175 short tag = vlan_tx_tag_get(skb);
1176 extsts |= (EXTSTS_VPKT | htons(tag));
1177 }
1178 #endif
1179
1180 len = skb->len;
1181 if (nr_frags)
1182 len -= skb->data_len;
1183 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1184
1185 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1186
1187 for (;;) {
1188 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1189
1190 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1191 (unsigned long long)buf);
1192 last_idx = free_idx;
1193 free_idx = (free_idx + 1) % NR_TX_DESC;
1194 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1195 desc_addr_set(desc + DESC_BUFPTR, buf);
1196 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1197
1198 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1199 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1200 cmdsts |= len;
1201 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1202
1203 if (!nr_frags)
1204 break;
1205
1206 buf = pci_map_page(dev->pci_dev, frag->page,
1207 frag->page_offset,
1208 frag->size, PCI_DMA_TODEVICE);
1209 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1210 (long long)buf, (long) page_to_pfn(frag->page),
1211 frag->page_offset);
1212 len = frag->size;
1213 frag++;
1214 nr_frags--;
1215 }
1216 dprintk("done pkt\n");
1217
1218 spin_lock_irq(&dev->tx_lock);
1219 dev->tx_skbs[last_idx] = skb;
1220 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1221 dev->tx_free_idx = free_idx;
1222 atomic_inc(&dev->nr_tx_skbs);
1223 spin_unlock_irq(&dev->tx_lock);
1224
1225 kick_tx(dev);
1226
1227 /* Check again: we may have raced with a tx done irq */
1228 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1229 netif_start_queue(ndev);
1230
1231 /* set the transmit start time to catch transmit timeouts */
1232 ndev->trans_start = jiffies;
1233 return 0;
1234 }
1235
1236 static void ns83820_update_stats(struct ns83820 *dev)
1237 {
1238 u8 __iomem *base = dev->base;
1239
1240 /* the DP83820 will freeze counters, so we need to read all of them */
1241 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1242 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1243 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1244 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1245 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1246 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1247 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1248 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1249 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1250 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1251 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1252 }
1253
1254 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1255 {
1256 struct ns83820 *dev = PRIV(ndev);
1257
1258 /* somewhat overkill */
1259 spin_lock_irq(&dev->misc_lock);
1260 ns83820_update_stats(dev);
1261 spin_unlock_irq(&dev->misc_lock);
1262
1263 return &dev->stats;
1264 }
1265
1266 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1267 {
1268 struct ns83820 *dev = PRIV(ndev);
1269 strcpy(info->driver, "ns83820");
1270 strcpy(info->version, VERSION);
1271 strcpy(info->bus_info, pci_name(dev->pci_dev));
1272 }
1273
1274 static u32 ns83820_get_link(struct net_device *ndev)
1275 {
1276 struct ns83820 *dev = PRIV(ndev);
1277 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1278 return cfg & CFG_LNKSTS ? 1 : 0;
1279 }
1280
1281 static struct ethtool_ops ops = {
1282 .get_drvinfo = ns83820_get_drvinfo,
1283 .get_link = ns83820_get_link
1284 };
1285
1286 static void ns83820_mib_isr(struct ns83820 *dev)
1287 {
1288 spin_lock(&dev->misc_lock);
1289 ns83820_update_stats(dev);
1290 spin_unlock(&dev->misc_lock);
1291 }
1292
1293 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1294 static irqreturn_t ns83820_irq(int foo, void *data, struct pt_regs *regs)
1295 {
1296 struct net_device *ndev = data;
1297 struct ns83820 *dev = PRIV(ndev);
1298 u32 isr;
1299 dprintk("ns83820_irq(%p)\n", ndev);
1300
1301 dev->ihr = 0;
1302
1303 isr = readl(dev->base + ISR);
1304 dprintk("irq: %08x\n", isr);
1305 ns83820_do_isr(ndev, isr);
1306 return IRQ_HANDLED;
1307 }
1308
1309 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1310 {
1311 struct ns83820 *dev = PRIV(ndev);
1312 #ifdef DEBUG
1313 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1314 Dprintk("odd isr? 0x%08x\n", isr);
1315 #endif
1316
1317 if (ISR_RXIDLE & isr) {
1318 dev->rx_info.idle = 1;
1319 Dprintk("oh dear, we are idle\n");
1320 ns83820_rx_kick(ndev);
1321 }
1322
1323 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1324 prefetch(dev->rx_info.next_rx_desc);
1325
1326 spin_lock_irq(&dev->misc_lock);
1327 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1328 writel(dev->IMR_cache, dev->base + IMR);
1329 spin_unlock_irq(&dev->misc_lock);
1330
1331 tasklet_schedule(&dev->rx_tasklet);
1332 //rx_irq(ndev);
1333 //writel(4, dev->base + IHR);
1334 }
1335
1336 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1337 ns83820_rx_kick(ndev);
1338
1339 if (unlikely(ISR_RXSOVR & isr)) {
1340 //printk("overrun: rxsovr\n");
1341 dev->stats.rx_fifo_errors ++;
1342 }
1343
1344 if (unlikely(ISR_RXORN & isr)) {
1345 //printk("overrun: rxorn\n");
1346 dev->stats.rx_fifo_errors ++;
1347 }
1348
1349 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1350 writel(CR_RXE, dev->base + CR);
1351
1352 if (ISR_TXIDLE & isr) {
1353 u32 txdp;
1354 txdp = readl(dev->base + TXDP);
1355 dprintk("txdp: %08x\n", txdp);
1356 txdp -= dev->tx_phy_descs;
1357 dev->tx_idx = txdp / (DESC_SIZE * 4);
1358 if (dev->tx_idx >= NR_TX_DESC) {
1359 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1360 dev->tx_idx = 0;
1361 }
1362 /* The may have been a race between a pci originated read
1363 * and the descriptor update from the cpu. Just in case,
1364 * kick the transmitter if the hardware thinks it is on a
1365 * different descriptor than we are.
1366 */
1367 if (dev->tx_idx != dev->tx_free_idx)
1368 kick_tx(dev);
1369 }
1370
1371 /* Defer tx ring processing until more than a minimum amount of
1372 * work has accumulated
1373 */
1374 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1375 do_tx_done(ndev);
1376
1377 /* Disable TxOk if there are no outstanding tx packets.
1378 */
1379 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1380 (dev->IMR_cache & ISR_TXOK)) {
1381 spin_lock_irq(&dev->misc_lock);
1382 dev->IMR_cache &= ~ISR_TXOK;
1383 writel(dev->IMR_cache, dev->base + IMR);
1384 spin_unlock_irq(&dev->misc_lock);
1385 }
1386 }
1387
1388 /* The TxIdle interrupt can come in before the transmit has
1389 * completed. Normally we reap packets off of the combination
1390 * of TxDesc and TxIdle and leave TxOk disabled (since it
1391 * occurs on every packet), but when no further irqs of this
1392 * nature are expected, we must enable TxOk.
1393 */
1394 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1395 spin_lock_irq(&dev->misc_lock);
1396 dev->IMR_cache |= ISR_TXOK;
1397 writel(dev->IMR_cache, dev->base + IMR);
1398 spin_unlock_irq(&dev->misc_lock);
1399 }
1400
1401 /* MIB interrupt: one of the statistics counters is about to overflow */
1402 if (unlikely(ISR_MIB & isr))
1403 ns83820_mib_isr(dev);
1404
1405 /* PHY: Link up/down/negotiation state change */
1406 if (unlikely(ISR_PHY & isr))
1407 phy_intr(ndev);
1408
1409 #if 0 /* Still working on the interrupt mitigation strategy */
1410 if (dev->ihr)
1411 writel(dev->ihr, dev->base + IHR);
1412 #endif
1413 }
1414
1415 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1416 {
1417 Dprintk("resetting chip...\n");
1418 writel(which, dev->base + CR);
1419 do {
1420 schedule();
1421 } while (readl(dev->base + CR) & which);
1422 Dprintk("okay!\n");
1423 }
1424
1425 static int ns83820_stop(struct net_device *ndev)
1426 {
1427 struct ns83820 *dev = PRIV(ndev);
1428
1429 /* FIXME: protect against interrupt handler? */
1430 del_timer_sync(&dev->tx_watchdog);
1431
1432 /* disable interrupts */
1433 writel(0, dev->base + IMR);
1434 writel(0, dev->base + IER);
1435 readl(dev->base + IER);
1436
1437 dev->rx_info.up = 0;
1438 synchronize_irq(dev->pci_dev->irq);
1439
1440 ns83820_do_reset(dev, CR_RST);
1441
1442 synchronize_irq(dev->pci_dev->irq);
1443
1444 spin_lock_irq(&dev->misc_lock);
1445 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1446 spin_unlock_irq(&dev->misc_lock);
1447
1448 ns83820_cleanup_rx(dev);
1449 ns83820_cleanup_tx(dev);
1450
1451 return 0;
1452 }
1453
1454 static void ns83820_tx_timeout(struct net_device *ndev)
1455 {
1456 struct ns83820 *dev = PRIV(ndev);
1457 u32 tx_done_idx, *desc;
1458 unsigned long flags;
1459
1460 local_irq_save(flags);
1461
1462 tx_done_idx = dev->tx_done_idx;
1463 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1464
1465 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1466 ndev->name,
1467 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1468
1469 #if defined(DEBUG)
1470 {
1471 u32 isr;
1472 isr = readl(dev->base + ISR);
1473 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1474 ns83820_do_isr(ndev, isr);
1475 }
1476 #endif
1477
1478 do_tx_done(ndev);
1479
1480 tx_done_idx = dev->tx_done_idx;
1481 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1482
1483 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1484 ndev->name,
1485 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1486
1487 local_irq_restore(flags);
1488 }
1489
1490 static void ns83820_tx_watch(unsigned long data)
1491 {
1492 struct net_device *ndev = (void *)data;
1493 struct ns83820 *dev = PRIV(ndev);
1494
1495 #if defined(DEBUG)
1496 printk("ns83820_tx_watch: %u %u %d\n",
1497 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1498 );
1499 #endif
1500
1501 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1502 dev->tx_done_idx != dev->tx_free_idx) {
1503 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1504 ndev->name,
1505 dev->tx_done_idx, dev->tx_free_idx,
1506 atomic_read(&dev->nr_tx_skbs));
1507 ns83820_tx_timeout(ndev);
1508 }
1509
1510 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1511 }
1512
1513 static int ns83820_open(struct net_device *ndev)
1514 {
1515 struct ns83820 *dev = PRIV(ndev);
1516 unsigned i;
1517 u32 desc;
1518 int ret;
1519
1520 dprintk("ns83820_open\n");
1521
1522 writel(0, dev->base + PQCR);
1523
1524 ret = ns83820_setup_rx(ndev);
1525 if (ret)
1526 goto failed;
1527
1528 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1529 for (i=0; i<NR_TX_DESC; i++) {
1530 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1531 = cpu_to_le32(
1532 dev->tx_phy_descs
1533 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1534 }
1535
1536 dev->tx_idx = 0;
1537 dev->tx_done_idx = 0;
1538 desc = dev->tx_phy_descs;
1539 writel(0, dev->base + TXDP_HI);
1540 writel(desc, dev->base + TXDP);
1541
1542 init_timer(&dev->tx_watchdog);
1543 dev->tx_watchdog.data = (unsigned long)ndev;
1544 dev->tx_watchdog.function = ns83820_tx_watch;
1545 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1546
1547 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1548
1549 return 0;
1550
1551 failed:
1552 ns83820_stop(ndev);
1553 return ret;
1554 }
1555
1556 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1557 {
1558 unsigned i;
1559 for (i=0; i<3; i++) {
1560 u32 data;
1561
1562 /* Read from the perfect match memory: this is loaded by
1563 * the chip from the EEPROM via the EELOAD self test.
1564 */
1565 writel(i*2, dev->base + RFCR);
1566 data = readl(dev->base + RFDR);
1567
1568 *mac++ = data;
1569 *mac++ = data >> 8;
1570 }
1571 }
1572
1573 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1574 {
1575 if (new_mtu > RX_BUF_SIZE)
1576 return -EINVAL;
1577 ndev->mtu = new_mtu;
1578 return 0;
1579 }
1580
1581 static void ns83820_set_multicast(struct net_device *ndev)
1582 {
1583 struct ns83820 *dev = PRIV(ndev);
1584 u8 __iomem *rfcr = dev->base + RFCR;
1585 u32 and_mask = 0xffffffff;
1586 u32 or_mask = 0;
1587 u32 val;
1588
1589 if (ndev->flags & IFF_PROMISC)
1590 or_mask |= RFCR_AAU | RFCR_AAM;
1591 else
1592 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1593
1594 if (ndev->flags & IFF_ALLMULTI)
1595 or_mask |= RFCR_AAM;
1596 else
1597 and_mask &= ~RFCR_AAM;
1598
1599 spin_lock_irq(&dev->misc_lock);
1600 val = (readl(rfcr) & and_mask) | or_mask;
1601 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1602 writel(val & ~RFCR_RFEN, rfcr);
1603 writel(val, rfcr);
1604 spin_unlock_irq(&dev->misc_lock);
1605 }
1606
1607 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1608 {
1609 struct ns83820 *dev = PRIV(ndev);
1610 int timed_out = 0;
1611 unsigned long start;
1612 u32 status;
1613 int loops = 0;
1614
1615 dprintk("%s: start %s\n", ndev->name, name);
1616
1617 start = jiffies;
1618
1619 writel(enable, dev->base + PTSCR);
1620 for (;;) {
1621 loops++;
1622 status = readl(dev->base + PTSCR);
1623 if (!(status & enable))
1624 break;
1625 if (status & done)
1626 break;
1627 if (status & fail)
1628 break;
1629 if (time_after_eq(jiffies, start + HZ)) {
1630 timed_out = 1;
1631 break;
1632 }
1633 schedule_timeout_uninterruptible(1);
1634 }
1635
1636 if (status & fail)
1637 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1638 ndev->name, name, status, fail);
1639 else if (timed_out)
1640 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1641 ndev->name, name, status);
1642
1643 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1644 }
1645
1646 #ifdef PHY_CODE_IS_FINISHED
1647 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1648 {
1649 /* drive MDC low */
1650 dev->MEAR_cache &= ~MEAR_MDC;
1651 writel(dev->MEAR_cache, dev->base + MEAR);
1652 readl(dev->base + MEAR);
1653
1654 /* enable output, set bit */
1655 dev->MEAR_cache |= MEAR_MDDIR;
1656 if (bit)
1657 dev->MEAR_cache |= MEAR_MDIO;
1658 else
1659 dev->MEAR_cache &= ~MEAR_MDIO;
1660
1661 /* set the output bit */
1662 writel(dev->MEAR_cache, dev->base + MEAR);
1663 readl(dev->base + MEAR);
1664
1665 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1666 udelay(1);
1667
1668 /* drive MDC high causing the data bit to be latched */
1669 dev->MEAR_cache |= MEAR_MDC;
1670 writel(dev->MEAR_cache, dev->base + MEAR);
1671 readl(dev->base + MEAR);
1672
1673 /* Wait again... */
1674 udelay(1);
1675 }
1676
1677 static int ns83820_mii_read_bit(struct ns83820 *dev)
1678 {
1679 int bit;
1680
1681 /* drive MDC low, disable output */
1682 dev->MEAR_cache &= ~MEAR_MDC;
1683 dev->MEAR_cache &= ~MEAR_MDDIR;
1684 writel(dev->MEAR_cache, dev->base + MEAR);
1685 readl(dev->base + MEAR);
1686
1687 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1688 udelay(1);
1689
1690 /* drive MDC high causing the data bit to be latched */
1691 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1692 dev->MEAR_cache |= MEAR_MDC;
1693 writel(dev->MEAR_cache, dev->base + MEAR);
1694
1695 /* Wait again... */
1696 udelay(1);
1697
1698 return bit;
1699 }
1700
1701 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1702 {
1703 unsigned data = 0;
1704 int i;
1705
1706 /* read some garbage so that we eventually sync up */
1707 for (i=0; i<64; i++)
1708 ns83820_mii_read_bit(dev);
1709
1710 ns83820_mii_write_bit(dev, 0); /* start */
1711 ns83820_mii_write_bit(dev, 1);
1712 ns83820_mii_write_bit(dev, 1); /* opcode read */
1713 ns83820_mii_write_bit(dev, 0);
1714
1715 /* write out the phy address: 5 bits, msb first */
1716 for (i=0; i<5; i++)
1717 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1718
1719 /* write out the register address, 5 bits, msb first */
1720 for (i=0; i<5; i++)
1721 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1722
1723 ns83820_mii_read_bit(dev); /* turn around cycles */
1724 ns83820_mii_read_bit(dev);
1725
1726 /* read in the register data, 16 bits msb first */
1727 for (i=0; i<16; i++) {
1728 data <<= 1;
1729 data |= ns83820_mii_read_bit(dev);
1730 }
1731
1732 return data;
1733 }
1734
1735 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1736 {
1737 int i;
1738
1739 /* read some garbage so that we eventually sync up */
1740 for (i=0; i<64; i++)
1741 ns83820_mii_read_bit(dev);
1742
1743 ns83820_mii_write_bit(dev, 0); /* start */
1744 ns83820_mii_write_bit(dev, 1);
1745 ns83820_mii_write_bit(dev, 0); /* opcode read */
1746 ns83820_mii_write_bit(dev, 1);
1747
1748 /* write out the phy address: 5 bits, msb first */
1749 for (i=0; i<5; i++)
1750 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1751
1752 /* write out the register address, 5 bits, msb first */
1753 for (i=0; i<5; i++)
1754 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1755
1756 ns83820_mii_read_bit(dev); /* turn around cycles */
1757 ns83820_mii_read_bit(dev);
1758
1759 /* read in the register data, 16 bits msb first */
1760 for (i=0; i<16; i++)
1761 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1762
1763 return data;
1764 }
1765
1766 static void ns83820_probe_phy(struct net_device *ndev)
1767 {
1768 struct ns83820 *dev = PRIV(ndev);
1769 static int first;
1770 int i;
1771 #define MII_PHYIDR1 0x02
1772 #define MII_PHYIDR2 0x03
1773
1774 #if 0
1775 if (!first) {
1776 unsigned tmp;
1777 ns83820_mii_read_reg(dev, 1, 0x09);
1778 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1779
1780 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1781 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1782 udelay(1300);
1783 ns83820_mii_read_reg(dev, 1, 0x09);
1784 }
1785 #endif
1786 first = 1;
1787
1788 for (i=1; i<2; i++) {
1789 int j;
1790 unsigned a, b;
1791 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1792 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1793
1794 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1795 // ndev->name, i, a, b);
1796
1797 for (j=0; j<0x16; j+=4) {
1798 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1799 ndev->name, j,
1800 ns83820_mii_read_reg(dev, i, 0 + j),
1801 ns83820_mii_read_reg(dev, i, 1 + j),
1802 ns83820_mii_read_reg(dev, i, 2 + j),
1803 ns83820_mii_read_reg(dev, i, 3 + j)
1804 );
1805 }
1806 }
1807 {
1808 unsigned a, b;
1809 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1810 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1811 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1812 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1813
1814 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1815 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1816 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1817 dprintk("version: 0x%04x 0x%04x\n", a, b);
1818 }
1819 }
1820 #endif
1821
1822 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1823 {
1824 struct net_device *ndev;
1825 struct ns83820 *dev;
1826 long addr;
1827 int err;
1828 int using_dac = 0;
1829
1830 /* See if we can set the dma mask early on; failure is fatal. */
1831 if (sizeof(dma_addr_t) == 8 &&
1832 !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) {
1833 using_dac = 1;
1834 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) {
1835 using_dac = 0;
1836 } else {
1837 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n");
1838 return -ENODEV;
1839 }
1840
1841 ndev = alloc_etherdev(sizeof(struct ns83820));
1842 dev = PRIV(ndev);
1843 err = -ENOMEM;
1844 if (!dev)
1845 goto out;
1846
1847 spin_lock_init(&dev->rx_info.lock);
1848 spin_lock_init(&dev->tx_lock);
1849 spin_lock_init(&dev->misc_lock);
1850 dev->pci_dev = pci_dev;
1851
1852 SET_MODULE_OWNER(ndev);
1853 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1854
1855 INIT_WORK(&dev->tq_refill, queue_refill, ndev);
1856 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1857
1858 err = pci_enable_device(pci_dev);
1859 if (err) {
1860 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err);
1861 goto out_free;
1862 }
1863
1864 pci_set_master(pci_dev);
1865 addr = pci_resource_start(pci_dev, 1);
1866 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1867 dev->tx_descs = pci_alloc_consistent(pci_dev,
1868 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1869 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1870 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1871 err = -ENOMEM;
1872 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1873 goto out_disable;
1874
1875 dprintk("%p: %08lx %p: %08lx\n",
1876 dev->tx_descs, (long)dev->tx_phy_descs,
1877 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1878
1879 /* disable interrupts */
1880 writel(0, dev->base + IMR);
1881 writel(0, dev->base + IER);
1882 readl(dev->base + IER);
1883
1884 dev->IMR_cache = 0;
1885
1886 err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
1887 DRV_NAME, ndev);
1888 if (err) {
1889 printk(KERN_INFO "ns83820: unable to register irq %d\n",
1890 pci_dev->irq);
1891 goto out_disable;
1892 }
1893
1894 /*
1895 * FIXME: we are holding rtnl_lock() over obscenely long area only
1896 * because some of the setup code uses dev->name. It's Wrong(tm) -
1897 * we should be using driver-specific names for all that stuff.
1898 * For now that will do, but we really need to come back and kill
1899 * most of the dev_alloc_name() users later.
1900 */
1901 rtnl_lock();
1902 err = dev_alloc_name(ndev, ndev->name);
1903 if (err < 0) {
1904 printk(KERN_INFO "ns83820: unable to get netdev name: %d\n", err);
1905 goto out_free_irq;
1906 }
1907
1908 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1909 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1910 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1911
1912 ndev->open = ns83820_open;
1913 ndev->stop = ns83820_stop;
1914 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1915 ndev->get_stats = ns83820_get_stats;
1916 ndev->change_mtu = ns83820_change_mtu;
1917 ndev->set_multicast_list = ns83820_set_multicast;
1918 SET_ETHTOOL_OPS(ndev, &ops);
1919 ndev->tx_timeout = ns83820_tx_timeout;
1920 ndev->watchdog_timeo = 5 * HZ;
1921 pci_set_drvdata(pci_dev, ndev);
1922
1923 ns83820_do_reset(dev, CR_RST);
1924
1925 /* Must reset the ram bist before running it */
1926 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1927 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1928 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1929 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1930 PTSCR_EEBIST_FAIL);
1931 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1932
1933 /* I love config registers */
1934 dev->CFG_cache = readl(dev->base + CFG);
1935
1936 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1937 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1938 ndev->name);
1939 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1940 if (!(dev->CFG_cache & CFG_DATA64_EN))
1941 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1942 ndev->name);
1943 } else
1944 dev->CFG_cache &= ~(CFG_DATA64_EN);
1945
1946 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1947 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1948 CFG_M64ADDR);
1949 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1950 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1951 dev->CFG_cache |= CFG_REQALG;
1952 dev->CFG_cache |= CFG_POW;
1953 dev->CFG_cache |= CFG_TMRTEST;
1954
1955 /* When compiled with 64 bit addressing, we must always enable
1956 * the 64 bit descriptor format.
1957 */
1958 if (sizeof(dma_addr_t) == 8)
1959 dev->CFG_cache |= CFG_M64ADDR;
1960 if (using_dac)
1961 dev->CFG_cache |= CFG_T64ADDR;
1962
1963 /* Big endian mode does not seem to do what the docs suggest */
1964 dev->CFG_cache &= ~CFG_BEM;
1965
1966 /* setup optical transceiver if we have one */
1967 if (dev->CFG_cache & CFG_TBI_EN) {
1968 printk(KERN_INFO "%s: enabling optical transceiver\n",
1969 ndev->name);
1970 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1971
1972 /* setup auto negotiation feature advertisement */
1973 writel(readl(dev->base + TANAR)
1974 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1975 dev->base + TANAR);
1976
1977 /* start auto negotiation */
1978 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1979 dev->base + TBICR);
1980 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1981 dev->linkstate = LINK_AUTONEGOTIATE;
1982
1983 dev->CFG_cache |= CFG_MODE_1000;
1984 }
1985
1986 writel(dev->CFG_cache, dev->base + CFG);
1987 dprintk("CFG: %08x\n", dev->CFG_cache);
1988
1989 if (reset_phy) {
1990 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1991 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1992 msleep(10);
1993 writel(dev->CFG_cache, dev->base + CFG);
1994 }
1995
1996 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1997 * the PCI layer. FIXME.
1998 */
1999 if (readl(dev->base + SRR))
2000 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2001 #endif
2002
2003 /* Note! The DMA burst size interacts with packet
2004 * transmission, such that the largest packet that
2005 * can be transmitted is 8192 - FLTH - burst size.
2006 * If only the transmit fifo was larger...
2007 */
2008 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2009 * some DELL and COMPAQ SMP systems */
2010 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2011 | ((1600 / 32) * 0x100),
2012 dev->base + TXCFG);
2013
2014 /* Flush the interrupt holdoff timer */
2015 writel(0x000, dev->base + IHR);
2016 writel(0x100, dev->base + IHR);
2017 writel(0x000, dev->base + IHR);
2018
2019 /* Set Rx to full duplex, don't accept runt, errored, long or length
2020 * range errored packets. Use 512 byte DMA.
2021 */
2022 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2023 * some DELL and COMPAQ SMP systems
2024 * Turn on ALP, only we are accpeting Jumbo Packets */
2025 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2026 | RXCFG_STRIPCRC
2027 //| RXCFG_ALP
2028 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2029
2030 /* Disable priority queueing */
2031 writel(0, dev->base + PQCR);
2032
2033 /* Enable IP checksum validation and detetion of VLAN headers.
2034 * Note: do not set the reject options as at least the 0x102
2035 * revision of the chip does not properly accept IP fragments
2036 * at least for UDP.
2037 */
2038 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2039 * the MAC it calculates the packetsize AFTER stripping the VLAN
2040 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2041 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2042 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2043 * it discrards it!. These guys......
2044 * also turn on tag stripping if hardware acceleration is enabled
2045 */
2046 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2047 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2048 #else
2049 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2050 #endif
2051 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2052
2053 /* Enable per-packet TCP/UDP/IP checksumming
2054 * and per packet vlan tag insertion if
2055 * vlan hardware acceleration is enabled
2056 */
2057 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2058 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2059 #else
2060 #define VTCR_INIT_VALUE VTCR_PPCHK
2061 #endif
2062 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2063
2064 /* Ramit : Enable async and sync pause frames */
2065 /* writel(0, dev->base + PCR); */
2066 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2067 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2068 dev->base + PCR);
2069
2070 /* Disable Wake On Lan */
2071 writel(0, dev->base + WCSR);
2072
2073 ns83820_getmac(dev, ndev->dev_addr);
2074
2075 /* Yes, we support dumb IP checksum on transmit */
2076 ndev->features |= NETIF_F_SG;
2077 ndev->features |= NETIF_F_IP_CSUM;
2078
2079 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2080 /* We also support hardware vlan acceleration */
2081 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2082 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2083 ndev->vlan_rx_kill_vid = ns83820_vlan_rx_kill_vid;
2084 #endif
2085
2086 if (using_dac) {
2087 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2088 ndev->name);
2089 ndev->features |= NETIF_F_HIGHDMA;
2090 }
2091
2092 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2093 ndev->name,
2094 (unsigned)readl(dev->base + SRR) >> 8,
2095 (unsigned)readl(dev->base + SRR) & 0xff,
2096 ndev->dev_addr[0], ndev->dev_addr[1],
2097 ndev->dev_addr[2], ndev->dev_addr[3],
2098 ndev->dev_addr[4], ndev->dev_addr[5],
2099 addr, pci_dev->irq,
2100 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2101 );
2102
2103 #ifdef PHY_CODE_IS_FINISHED
2104 ns83820_probe_phy(ndev);
2105 #endif
2106
2107 err = register_netdevice(ndev);
2108 if (err) {
2109 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2110 goto out_cleanup;
2111 }
2112 rtnl_unlock();
2113
2114 return 0;
2115
2116 out_cleanup:
2117 writel(0, dev->base + IMR); /* paranoia */
2118 writel(0, dev->base + IER);
2119 readl(dev->base + IER);
2120 out_free_irq:
2121 rtnl_unlock();
2122 free_irq(pci_dev->irq, ndev);
2123 out_disable:
2124 if (dev->base)
2125 iounmap(dev->base);
2126 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2127 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2128 pci_disable_device(pci_dev);
2129 out_free:
2130 free_netdev(ndev);
2131 pci_set_drvdata(pci_dev, NULL);
2132 out:
2133 return err;
2134 }
2135
2136 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2137 {
2138 struct net_device *ndev = pci_get_drvdata(pci_dev);
2139 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2140
2141 if (!ndev) /* paranoia */
2142 return;
2143
2144 writel(0, dev->base + IMR); /* paranoia */
2145 writel(0, dev->base + IER);
2146 readl(dev->base + IER);
2147
2148 unregister_netdev(ndev);
2149 free_irq(dev->pci_dev->irq, ndev);
2150 iounmap(dev->base);
2151 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2152 dev->tx_descs, dev->tx_phy_descs);
2153 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2154 dev->rx_info.descs, dev->rx_info.phy_descs);
2155 pci_disable_device(dev->pci_dev);
2156 free_netdev(ndev);
2157 pci_set_drvdata(pci_dev, NULL);
2158 }
2159
2160 static struct pci_device_id ns83820_pci_tbl[] = {
2161 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2162 { 0, },
2163 };
2164
2165 static struct pci_driver driver = {
2166 .name = "ns83820",
2167 .id_table = ns83820_pci_tbl,
2168 .probe = ns83820_init_one,
2169 .remove = __devexit_p(ns83820_remove_one),
2170 #if 0 /* FIXME: implement */
2171 .suspend = ,
2172 .resume = ,
2173 #endif
2174 };
2175
2176
2177 static int __init ns83820_init(void)
2178 {
2179 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2180 return pci_module_init(&driver);
2181 }
2182
2183 static void __exit ns83820_exit(void)
2184 {
2185 pci_unregister_driver(&driver);
2186 }
2187
2188 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2189 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2190 MODULE_LICENSE("GPL");
2191
2192 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2193
2194 module_param(lnksts, int, 0);
2195 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2196
2197 module_param(ihr, int, 0);
2198 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2199
2200 module_param(reset_phy, int, 0);
2201 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2202
2203 module_init(ns83820_init);
2204 module_exit(ns83820_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree