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drm/radeon: fix XFX quirk
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
blobef6b426b1ee76d1e015751be76c7fa8222e58851
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54 /* from radeon_legacy_encoder.c */
55 extern void
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63 };
64
65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
67 {
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
74 int i, num_indices;
75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
87
88 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
89 if ((rdev->family == CHIP_R420) ||
90 (rdev->family == CHIP_R423) ||
91 (rdev->family == CHIP_RV410)) {
92 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
93 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
94 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
95 gpio->ucClkMaskShift = 0x19;
96 gpio->ucDataMaskShift = 0x18;
97 }
98 }
99
100 /* some evergreen boards have bad data for this entry */
101 if (ASIC_IS_DCE4(rdev)) {
102 if ((i == 7) &&
103 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
104 (gpio->sucI2cId.ucAccess == 0)) {
105 gpio->sucI2cId.ucAccess = 0x97;
106 gpio->ucDataMaskShift = 8;
107 gpio->ucDataEnShift = 8;
108 gpio->ucDataY_Shift = 8;
109 gpio->ucDataA_Shift = 8;
110 }
111 }
112
113 /* some DCE3 boards have bad data for this entry */
114 if (ASIC_IS_DCE3(rdev)) {
115 if ((i == 4) &&
116 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
117 (gpio->sucI2cId.ucAccess == 0x94))
118 gpio->sucI2cId.ucAccess = 0x14;
119 }
120
121 if (gpio->sucI2cId.ucAccess == id) {
122 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
123 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
124 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
125 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
126 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
127 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
128 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
129 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
130 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
131 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
132 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
133 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
134 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
135 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
136 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
137 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
138
139 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
140 i2c.hw_capable = true;
141 else
142 i2c.hw_capable = false;
143
144 if (gpio->sucI2cId.ucAccess == 0xa0)
145 i2c.mm_i2c = true;
146 else
147 i2c.mm_i2c = false;
148
149 i2c.i2c_id = gpio->sucI2cId.ucAccess;
150
151 if (i2c.mask_clk_reg)
152 i2c.valid = true;
153 break;
154 }
155 }
156 }
157
158 return i2c;
159 }
160
161 void radeon_atombios_i2c_init(struct radeon_device *rdev)
162 {
163 struct atom_context *ctx = rdev->mode_info.atom_context;
164 ATOM_GPIO_I2C_ASSIGMENT *gpio;
165 struct radeon_i2c_bus_rec i2c;
166 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
167 struct _ATOM_GPIO_I2C_INFO *i2c_info;
168 uint16_t data_offset, size;
169 int i, num_indices;
170 char stmp[32];
171
172 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
173
174 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
175 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
176
177 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
178 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
179
180 for (i = 0; i < num_indices; i++) {
181 gpio = &i2c_info->asGPIO_Info[i];
182 i2c.valid = false;
183
184 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
185 if ((rdev->family == CHIP_R420) ||
186 (rdev->family == CHIP_R423) ||
187 (rdev->family == CHIP_RV410)) {
188 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
189 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
190 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
191 gpio->ucClkMaskShift = 0x19;
192 gpio->ucDataMaskShift = 0x18;
193 }
194 }
195
196 /* some evergreen boards have bad data for this entry */
197 if (ASIC_IS_DCE4(rdev)) {
198 if ((i == 7) &&
199 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
200 (gpio->sucI2cId.ucAccess == 0)) {
201 gpio->sucI2cId.ucAccess = 0x97;
202 gpio->ucDataMaskShift = 8;
203 gpio->ucDataEnShift = 8;
204 gpio->ucDataY_Shift = 8;
205 gpio->ucDataA_Shift = 8;
206 }
207 }
208
209 /* some DCE3 boards have bad data for this entry */
210 if (ASIC_IS_DCE3(rdev)) {
211 if ((i == 4) &&
212 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
213 (gpio->sucI2cId.ucAccess == 0x94))
214 gpio->sucI2cId.ucAccess = 0x14;
215 }
216
217 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
218 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
219 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
220 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
221 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
222 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
223 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
224 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
225 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
226 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
227 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
228 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
229 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
230 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
231 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
232 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
233
234 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
235 i2c.hw_capable = true;
236 else
237 i2c.hw_capable = false;
238
239 if (gpio->sucI2cId.ucAccess == 0xa0)
240 i2c.mm_i2c = true;
241 else
242 i2c.mm_i2c = false;
243
244 i2c.i2c_id = gpio->sucI2cId.ucAccess;
245
246 if (i2c.mask_clk_reg) {
247 i2c.valid = true;
248 sprintf(stmp, "0x%x", i2c.i2c_id);
249 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
250 }
251 }
252 }
253 }
254
255 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
256 u8 id)
257 {
258 struct atom_context *ctx = rdev->mode_info.atom_context;
259 struct radeon_gpio_rec gpio;
260 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
261 struct _ATOM_GPIO_PIN_LUT *gpio_info;
262 ATOM_GPIO_PIN_ASSIGNMENT *pin;
263 u16 data_offset, size;
264 int i, num_indices;
265
266 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
267 gpio.valid = false;
268
269 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
270 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
271
272 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
273 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
274
275 for (i = 0; i < num_indices; i++) {
276 pin = &gpio_info->asGPIO_Pin[i];
277 if (id == pin->ucGPIO_ID) {
278 gpio.id = pin->ucGPIO_ID;
279 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
280 gpio.mask = (1 << pin->ucGpioPinBitShift);
281 gpio.valid = true;
282 break;
283 }
284 }
285 }
286
287 return gpio;
288 }
289
290 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
291 struct radeon_gpio_rec *gpio)
292 {
293 struct radeon_hpd hpd;
294 u32 reg;
295
296 memset(&hpd, 0, sizeof(struct radeon_hpd));
297
298 if (ASIC_IS_DCE4(rdev))
299 reg = EVERGREEN_DC_GPIO_HPD_A;
300 else
301 reg = AVIVO_DC_GPIO_HPD_A;
302
303 hpd.gpio = *gpio;
304 if (gpio->reg == reg) {
305 switch(gpio->mask) {
306 case (1 << 0):
307 hpd.hpd = RADEON_HPD_1;
308 break;
309 case (1 << 8):
310 hpd.hpd = RADEON_HPD_2;
311 break;
312 case (1 << 16):
313 hpd.hpd = RADEON_HPD_3;
314 break;
315 case (1 << 24):
316 hpd.hpd = RADEON_HPD_4;
317 break;
318 case (1 << 26):
319 hpd.hpd = RADEON_HPD_5;
320 break;
321 case (1 << 28):
322 hpd.hpd = RADEON_HPD_6;
323 break;
324 default:
325 hpd.hpd = RADEON_HPD_NONE;
326 break;
327 }
328 } else
329 hpd.hpd = RADEON_HPD_NONE;
330 return hpd;
331 }
332
333 static bool radeon_atom_apply_quirks(struct drm_device *dev,
334 uint32_t supported_device,
335 int *connector_type,
336 struct radeon_i2c_bus_rec *i2c_bus,
337 uint16_t *line_mux,
338 struct radeon_hpd *hpd)
339 {
340
341 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
342 if ((dev->pdev->device == 0x791e) &&
343 (dev->pdev->subsystem_vendor == 0x1043) &&
344 (dev->pdev->subsystem_device == 0x826d)) {
345 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
346 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
347 *connector_type = DRM_MODE_CONNECTOR_DVID;
348 }
349
350 /* Asrock RS600 board lists the DVI port as HDMI */
351 if ((dev->pdev->device == 0x7941) &&
352 (dev->pdev->subsystem_vendor == 0x1849) &&
353 (dev->pdev->subsystem_device == 0x7941)) {
354 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
355 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
356 *connector_type = DRM_MODE_CONNECTOR_DVID;
357 }
358
359 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
360 if ((dev->pdev->device == 0x796e) &&
361 (dev->pdev->subsystem_vendor == 0x1462) &&
362 (dev->pdev->subsystem_device == 0x7302)) {
363 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
364 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
365 return false;
366 }
367
368 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
369 if ((dev->pdev->device == 0x7941) &&
370 (dev->pdev->subsystem_vendor == 0x147b) &&
371 (dev->pdev->subsystem_device == 0x2412)) {
372 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
373 return false;
374 }
375
376 /* Falcon NW laptop lists vga ddc line for LVDS */
377 if ((dev->pdev->device == 0x5653) &&
378 (dev->pdev->subsystem_vendor == 0x1462) &&
379 (dev->pdev->subsystem_device == 0x0291)) {
380 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
381 i2c_bus->valid = false;
382 *line_mux = 53;
383 }
384 }
385
386 /* HIS X1300 is DVI+VGA, not DVI+DVI */
387 if ((dev->pdev->device == 0x7146) &&
388 (dev->pdev->subsystem_vendor == 0x17af) &&
389 (dev->pdev->subsystem_device == 0x2058)) {
390 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
391 return false;
392 }
393
394 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
395 if ((dev->pdev->device == 0x7142) &&
396 (dev->pdev->subsystem_vendor == 0x1458) &&
397 (dev->pdev->subsystem_device == 0x2134)) {
398 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
399 return false;
400 }
401
402
403 /* Funky macbooks */
404 if ((dev->pdev->device == 0x71C5) &&
405 (dev->pdev->subsystem_vendor == 0x106b) &&
406 (dev->pdev->subsystem_device == 0x0080)) {
407 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
408 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
409 return false;
410 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
411 *line_mux = 0x90;
412 }
413
414 /* mac rv630, rv730, others */
415 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
416 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
417 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
418 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
419 }
420
421 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
422 if ((dev->pdev->device == 0x9598) &&
423 (dev->pdev->subsystem_vendor == 0x1043) &&
424 (dev->pdev->subsystem_device == 0x01da)) {
425 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
426 *connector_type = DRM_MODE_CONNECTOR_DVII;
427 }
428 }
429
430 /* ASUS HD 3600 board lists the DVI port as HDMI */
431 if ((dev->pdev->device == 0x9598) &&
432 (dev->pdev->subsystem_vendor == 0x1043) &&
433 (dev->pdev->subsystem_device == 0x01e4)) {
434 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
435 *connector_type = DRM_MODE_CONNECTOR_DVII;
436 }
437 }
438
439 /* ASUS HD 3450 board lists the DVI port as HDMI */
440 if ((dev->pdev->device == 0x95C5) &&
441 (dev->pdev->subsystem_vendor == 0x1043) &&
442 (dev->pdev->subsystem_device == 0x01e2)) {
443 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
444 *connector_type = DRM_MODE_CONNECTOR_DVII;
445 }
446 }
447
448 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
449 * HDMI + VGA reporting as HDMI
450 */
451 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
452 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
453 *connector_type = DRM_MODE_CONNECTOR_VGA;
454 *line_mux = 0;
455 }
456 }
457
458 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
459 * on the laptop and a DVI port on the docking station and
460 * both share the same encoder, hpd pin, and ddc line.
461 * So while the bios table is technically correct,
462 * we drop the DVI port here since xrandr has no concept of
463 * encoders and will try and drive both connectors
464 * with different crtcs which isn't possible on the hardware
465 * side and leaves no crtcs for LVDS or VGA.
466 */
467 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
468 (dev->pdev->subsystem_vendor == 0x1025) &&
469 (dev->pdev->subsystem_device == 0x013c)) {
470 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
471 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
472 /* actually it's a DVI-D port not DVI-I */
473 *connector_type = DRM_MODE_CONNECTOR_DVID;
474 return false;
475 }
476 }
477
478 /* XFX Pine Group device rv730 reports no VGA DDC lines
479 * even though they are wired up to record 0x93
480 */
481 if ((dev->pdev->device == 0x9498) &&
482 (dev->pdev->subsystem_vendor == 0x1682) &&
483 (dev->pdev->subsystem_device == 0x2452) &&
484 (i2c_bus->valid == false) &&
485 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
486 struct radeon_device *rdev = dev->dev_private;
487 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
488 }
489
490 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
491 if ((dev->pdev->device == 0x9802) &&
492 (dev->pdev->subsystem_vendor == 0x1734) &&
493 (dev->pdev->subsystem_device == 0x11bd)) {
494 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
495 *connector_type = DRM_MODE_CONNECTOR_DVII;
496 *line_mux = 0x3103;
497 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
498 *connector_type = DRM_MODE_CONNECTOR_DVII;
499 }
500 }
501
502
503 return true;
504 }
505
506 const int supported_devices_connector_convert[] = {
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_DVII,
510 DRM_MODE_CONNECTOR_DVID,
511 DRM_MODE_CONNECTOR_DVIA,
512 DRM_MODE_CONNECTOR_SVIDEO,
513 DRM_MODE_CONNECTOR_Composite,
514 DRM_MODE_CONNECTOR_LVDS,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_Unknown,
517 DRM_MODE_CONNECTOR_HDMIA,
518 DRM_MODE_CONNECTOR_HDMIB,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_9PinDIN,
522 DRM_MODE_CONNECTOR_DisplayPort
523 };
524
525 const uint16_t supported_devices_connector_object_id_convert[] = {
526 CONNECTOR_OBJECT_ID_NONE,
527 CONNECTOR_OBJECT_ID_VGA,
528 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
529 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
530 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
531 CONNECTOR_OBJECT_ID_COMPOSITE,
532 CONNECTOR_OBJECT_ID_SVIDEO,
533 CONNECTOR_OBJECT_ID_LVDS,
534 CONNECTOR_OBJECT_ID_9PIN_DIN,
535 CONNECTOR_OBJECT_ID_9PIN_DIN,
536 CONNECTOR_OBJECT_ID_DISPLAYPORT,
537 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
538 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
539 CONNECTOR_OBJECT_ID_SVIDEO
540 };
541
542 const int object_connector_convert[] = {
543 DRM_MODE_CONNECTOR_Unknown,
544 DRM_MODE_CONNECTOR_DVII,
545 DRM_MODE_CONNECTOR_DVII,
546 DRM_MODE_CONNECTOR_DVID,
547 DRM_MODE_CONNECTOR_DVID,
548 DRM_MODE_CONNECTOR_VGA,
549 DRM_MODE_CONNECTOR_Composite,
550 DRM_MODE_CONNECTOR_SVIDEO,
551 DRM_MODE_CONNECTOR_Unknown,
552 DRM_MODE_CONNECTOR_Unknown,
553 DRM_MODE_CONNECTOR_9PinDIN,
554 DRM_MODE_CONNECTOR_Unknown,
555 DRM_MODE_CONNECTOR_HDMIA,
556 DRM_MODE_CONNECTOR_HDMIB,
557 DRM_MODE_CONNECTOR_LVDS,
558 DRM_MODE_CONNECTOR_9PinDIN,
559 DRM_MODE_CONNECTOR_Unknown,
560 DRM_MODE_CONNECTOR_Unknown,
561 DRM_MODE_CONNECTOR_Unknown,
562 DRM_MODE_CONNECTOR_DisplayPort,
563 DRM_MODE_CONNECTOR_eDP,
564 DRM_MODE_CONNECTOR_Unknown
565 };
566
567 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
568 {
569 struct radeon_device *rdev = dev->dev_private;
570 struct radeon_mode_info *mode_info = &rdev->mode_info;
571 struct atom_context *ctx = mode_info->atom_context;
572 int index = GetIndexIntoMasterTable(DATA, Object_Header);
573 u16 size, data_offset;
574 u8 frev, crev;
575 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
576 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
577 ATOM_OBJECT_TABLE *router_obj;
578 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
579 ATOM_OBJECT_HEADER *obj_header;
580 int i, j, k, path_size, device_support;
581 int connector_type;
582 u16 igp_lane_info, conn_id, connector_object_id;
583 struct radeon_i2c_bus_rec ddc_bus;
584 struct radeon_router router;
585 struct radeon_gpio_rec gpio;
586 struct radeon_hpd hpd;
587
588 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
589 return false;
590
591 if (crev < 2)
592 return false;
593
594 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
595 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
596 (ctx->bios + data_offset +
597 le16_to_cpu(obj_header->usDisplayPathTableOffset));
598 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
599 (ctx->bios + data_offset +
600 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
601 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
602 (ctx->bios + data_offset +
603 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
604 router_obj = (ATOM_OBJECT_TABLE *)
605 (ctx->bios + data_offset +
606 le16_to_cpu(obj_header->usRouterObjectTableOffset));
607 device_support = le16_to_cpu(obj_header->usDeviceSupport);
608
609 path_size = 0;
610 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
611 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
612 ATOM_DISPLAY_OBJECT_PATH *path;
613 addr += path_size;
614 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
615 path_size += le16_to_cpu(path->usSize);
616
617 if (device_support & le16_to_cpu(path->usDeviceTag)) {
618 uint8_t con_obj_id, con_obj_num, con_obj_type;
619
620 con_obj_id =
621 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
622 >> OBJECT_ID_SHIFT;
623 con_obj_num =
624 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
625 >> ENUM_ID_SHIFT;
626 con_obj_type =
627 (le16_to_cpu(path->usConnObjectId) &
628 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
629
630 /* TODO CV support */
631 if (le16_to_cpu(path->usDeviceTag) ==
632 ATOM_DEVICE_CV_SUPPORT)
633 continue;
634
635 /* IGP chips */
636 if ((rdev->flags & RADEON_IS_IGP) &&
637 (con_obj_id ==
638 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
639 uint16_t igp_offset = 0;
640 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
641
642 index =
643 GetIndexIntoMasterTable(DATA,
644 IntegratedSystemInfo);
645
646 if (atom_parse_data_header(ctx, index, &size, &frev,
647 &crev, &igp_offset)) {
648
649 if (crev >= 2) {
650 igp_obj =
651 (ATOM_INTEGRATED_SYSTEM_INFO_V2
652 *) (ctx->bios + igp_offset);
653
654 if (igp_obj) {
655 uint32_t slot_config, ct;
656
657 if (con_obj_num == 1)
658 slot_config =
659 igp_obj->
660 ulDDISlot1Config;
661 else
662 slot_config =
663 igp_obj->
664 ulDDISlot2Config;
665
666 ct = (slot_config >> 16) & 0xff;
667 connector_type =
668 object_connector_convert
669 [ct];
670 connector_object_id = ct;
671 igp_lane_info =
672 slot_config & 0xffff;
673 } else
674 continue;
675 } else
676 continue;
677 } else {
678 igp_lane_info = 0;
679 connector_type =
680 object_connector_convert[con_obj_id];
681 connector_object_id = con_obj_id;
682 }
683 } else {
684 igp_lane_info = 0;
685 connector_type =
686 object_connector_convert[con_obj_id];
687 connector_object_id = con_obj_id;
688 }
689
690 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
691 continue;
692
693 router.ddc_valid = false;
694 router.cd_valid = false;
695 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
696 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
697
698 grph_obj_id =
699 (le16_to_cpu(path->usGraphicObjIds[j]) &
700 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
701 grph_obj_num =
702 (le16_to_cpu(path->usGraphicObjIds[j]) &
703 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
704 grph_obj_type =
705 (le16_to_cpu(path->usGraphicObjIds[j]) &
706 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
707
708 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
709 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
710 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
711 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
712 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
713 (ctx->bios + data_offset +
714 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
715 ATOM_ENCODER_CAP_RECORD *cap_record;
716 u16 caps = 0;
717
718 while (record->ucRecordSize > 0 &&
719 record->ucRecordType > 0 &&
720 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
721 switch (record->ucRecordType) {
722 case ATOM_ENCODER_CAP_RECORD_TYPE:
723 cap_record =(ATOM_ENCODER_CAP_RECORD *)
724 record;
725 caps = le16_to_cpu(cap_record->usEncoderCap);
726 break;
727 }
728 record = (ATOM_COMMON_RECORD_HEADER *)
729 ((char *)record + record->ucRecordSize);
730 }
731 radeon_add_atom_encoder(dev,
732 encoder_obj,
733 le16_to_cpu
734 (path->
735 usDeviceTag),
736 caps);
737 }
738 }
739 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
740 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
741 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
742 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
743 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
744 (ctx->bios + data_offset +
745 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
746 ATOM_I2C_RECORD *i2c_record;
747 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
748 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
749 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
750 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
751 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
752 (ctx->bios + data_offset +
753 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
754 int enum_id;
755
756 router.router_id = router_obj_id;
757 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
758 enum_id++) {
759 if (le16_to_cpu(path->usConnObjectId) ==
760 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
761 break;
762 }
763
764 while (record->ucRecordSize > 0 &&
765 record->ucRecordType > 0 &&
766 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
767 switch (record->ucRecordType) {
768 case ATOM_I2C_RECORD_TYPE:
769 i2c_record =
770 (ATOM_I2C_RECORD *)
771 record;
772 i2c_config =
773 (ATOM_I2C_ID_CONFIG_ACCESS *)
774 &i2c_record->sucI2cId;
775 router.i2c_info =
776 radeon_lookup_i2c_gpio(rdev,
777 i2c_config->
778 ucAccess);
779 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
780 break;
781 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
782 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
783 record;
784 router.ddc_valid = true;
785 router.ddc_mux_type = ddc_path->ucMuxType;
786 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
787 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
788 break;
789 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
790 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
791 record;
792 router.cd_valid = true;
793 router.cd_mux_type = cd_path->ucMuxType;
794 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
795 router.cd_mux_state = cd_path->ucMuxState[enum_id];
796 break;
797 }
798 record = (ATOM_COMMON_RECORD_HEADER *)
799 ((char *)record + record->ucRecordSize);
800 }
801 }
802 }
803 }
804 }
805
806 /* look up gpio for ddc, hpd */
807 ddc_bus.valid = false;
808 hpd.hpd = RADEON_HPD_NONE;
809 if ((le16_to_cpu(path->usDeviceTag) &
810 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
811 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
812 if (le16_to_cpu(path->usConnObjectId) ==
813 le16_to_cpu(con_obj->asObjects[j].
814 usObjectID)) {
815 ATOM_COMMON_RECORD_HEADER
816 *record =
817 (ATOM_COMMON_RECORD_HEADER
818 *)
819 (ctx->bios + data_offset +
820 le16_to_cpu(con_obj->
821 asObjects[j].
822 usRecordOffset));
823 ATOM_I2C_RECORD *i2c_record;
824 ATOM_HPD_INT_RECORD *hpd_record;
825 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
826
827 while (record->ucRecordSize > 0 &&
828 record->ucRecordType > 0 &&
829 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
830 switch (record->ucRecordType) {
831 case ATOM_I2C_RECORD_TYPE:
832 i2c_record =
833 (ATOM_I2C_RECORD *)
834 record;
835 i2c_config =
836 (ATOM_I2C_ID_CONFIG_ACCESS *)
837 &i2c_record->sucI2cId;
838 ddc_bus = radeon_lookup_i2c_gpio(rdev,
839 i2c_config->
840 ucAccess);
841 break;
842 case ATOM_HPD_INT_RECORD_TYPE:
843 hpd_record =
844 (ATOM_HPD_INT_RECORD *)
845 record;
846 gpio = radeon_lookup_gpio(rdev,
847 hpd_record->ucHPDIntGPIOID);
848 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
849 hpd.plugged_state = hpd_record->ucPlugged_PinState;
850 break;
851 }
852 record =
853 (ATOM_COMMON_RECORD_HEADER
854 *) ((char *)record
855 +
856 record->
857 ucRecordSize);
858 }
859 break;
860 }
861 }
862 }
863
864 /* needed for aux chan transactions */
865 ddc_bus.hpd = hpd.hpd;
866
867 conn_id = le16_to_cpu(path->usConnObjectId);
868
869 if (!radeon_atom_apply_quirks
870 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
871 &ddc_bus, &conn_id, &hpd))
872 continue;
873
874 radeon_add_atom_connector(dev,
875 conn_id,
876 le16_to_cpu(path->
877 usDeviceTag),
878 connector_type, &ddc_bus,
879 igp_lane_info,
880 connector_object_id,
881 &hpd,
882 &router);
883
884 }
885 }
886
887 radeon_link_encoder_connector(dev);
888
889 return true;
890 }
891
892 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
893 int connector_type,
894 uint16_t devices)
895 {
896 struct radeon_device *rdev = dev->dev_private;
897
898 if (rdev->flags & RADEON_IS_IGP) {
899 return supported_devices_connector_object_id_convert
900 [connector_type];
901 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
902 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
903 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
904 struct radeon_mode_info *mode_info = &rdev->mode_info;
905 struct atom_context *ctx = mode_info->atom_context;
906 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
907 uint16_t size, data_offset;
908 uint8_t frev, crev;
909 ATOM_XTMDS_INFO *xtmds;
910
911 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
912 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
913
914 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
915 if (connector_type == DRM_MODE_CONNECTOR_DVII)
916 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
917 else
918 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
919 } else {
920 if (connector_type == DRM_MODE_CONNECTOR_DVII)
921 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
922 else
923 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
924 }
925 } else
926 return supported_devices_connector_object_id_convert
927 [connector_type];
928 } else {
929 return supported_devices_connector_object_id_convert
930 [connector_type];
931 }
932 }
933
934 struct bios_connector {
935 bool valid;
936 uint16_t line_mux;
937 uint16_t devices;
938 int connector_type;
939 struct radeon_i2c_bus_rec ddc_bus;
940 struct radeon_hpd hpd;
941 };
942
943 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
944 drm_device
945 *dev)
946 {
947 struct radeon_device *rdev = dev->dev_private;
948 struct radeon_mode_info *mode_info = &rdev->mode_info;
949 struct atom_context *ctx = mode_info->atom_context;
950 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
951 uint16_t size, data_offset;
952 uint8_t frev, crev;
953 uint16_t device_support;
954 uint8_t dac;
955 union atom_supported_devices *supported_devices;
956 int i, j, max_device;
957 struct bios_connector *bios_connectors;
958 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
959 struct radeon_router router;
960
961 router.ddc_valid = false;
962 router.cd_valid = false;
963
964 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
965 if (!bios_connectors)
966 return false;
967
968 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
969 &data_offset)) {
970 kfree(bios_connectors);
971 return false;
972 }
973
974 supported_devices =
975 (union atom_supported_devices *)(ctx->bios + data_offset);
976
977 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
978
979 if (frev > 1)
980 max_device = ATOM_MAX_SUPPORTED_DEVICE;
981 else
982 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
983
984 for (i = 0; i < max_device; i++) {
985 ATOM_CONNECTOR_INFO_I2C ci =
986 supported_devices->info.asConnInfo[i];
987
988 bios_connectors[i].valid = false;
989
990 if (!(device_support & (1 << i))) {
991 continue;
992 }
993
994 if (i == ATOM_DEVICE_CV_INDEX) {
995 DRM_DEBUG_KMS("Skipping Component Video\n");
996 continue;
997 }
998
999 bios_connectors[i].connector_type =
1000 supported_devices_connector_convert[ci.sucConnectorInfo.
1001 sbfAccess.
1002 bfConnectorType];
1003
1004 if (bios_connectors[i].connector_type ==
1005 DRM_MODE_CONNECTOR_Unknown)
1006 continue;
1007
1008 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
1009
1010 bios_connectors[i].line_mux =
1011 ci.sucI2cId.ucAccess;
1012
1013 /* give tv unique connector ids */
1014 if (i == ATOM_DEVICE_TV1_INDEX) {
1015 bios_connectors[i].ddc_bus.valid = false;
1016 bios_connectors[i].line_mux = 50;
1017 } else if (i == ATOM_DEVICE_TV2_INDEX) {
1018 bios_connectors[i].ddc_bus.valid = false;
1019 bios_connectors[i].line_mux = 51;
1020 } else if (i == ATOM_DEVICE_CV_INDEX) {
1021 bios_connectors[i].ddc_bus.valid = false;
1022 bios_connectors[i].line_mux = 52;
1023 } else
1024 bios_connectors[i].ddc_bus =
1025 radeon_lookup_i2c_gpio(rdev,
1026 bios_connectors[i].line_mux);
1027
1028 if ((crev > 1) && (frev > 1)) {
1029 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
1030 switch (isb) {
1031 case 0x4:
1032 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1033 break;
1034 case 0xa:
1035 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1036 break;
1037 default:
1038 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1039 break;
1040 }
1041 } else {
1042 if (i == ATOM_DEVICE_DFP1_INDEX)
1043 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1044 else if (i == ATOM_DEVICE_DFP2_INDEX)
1045 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1046 else
1047 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1048 }
1049
1050 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1051 * shared with a DVI port, we'll pick up the DVI connector when we
1052 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1053 */
1054 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1055 bios_connectors[i].connector_type =
1056 DRM_MODE_CONNECTOR_VGA;
1057
1058 if (!radeon_atom_apply_quirks
1059 (dev, (1 << i), &bios_connectors[i].connector_type,
1060 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1061 &bios_connectors[i].hpd))
1062 continue;
1063
1064 bios_connectors[i].valid = true;
1065 bios_connectors[i].devices = (1 << i);
1066
1067 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1068 radeon_add_atom_encoder(dev,
1069 radeon_get_encoder_enum(dev,
1070 (1 << i),
1071 dac),
1072 (1 << i),
1073 0);
1074 else
1075 radeon_add_legacy_encoder(dev,
1076 radeon_get_encoder_enum(dev,
1077 (1 << i),
1078 dac),
1079 (1 << i));
1080 }
1081
1082 /* combine shared connectors */
1083 for (i = 0; i < max_device; i++) {
1084 if (bios_connectors[i].valid) {
1085 for (j = 0; j < max_device; j++) {
1086 if (bios_connectors[j].valid && (i != j)) {
1087 if (bios_connectors[i].line_mux ==
1088 bios_connectors[j].line_mux) {
1089 /* make sure not to combine LVDS */
1090 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1091 bios_connectors[i].line_mux = 53;
1092 bios_connectors[i].ddc_bus.valid = false;
1093 continue;
1094 }
1095 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1096 bios_connectors[j].line_mux = 53;
1097 bios_connectors[j].ddc_bus.valid = false;
1098 continue;
1099 }
1100 /* combine analog and digital for DVI-I */
1101 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1102 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1103 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1104 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1105 bios_connectors[i].devices |=
1106 bios_connectors[j].devices;
1107 bios_connectors[i].connector_type =
1108 DRM_MODE_CONNECTOR_DVII;
1109 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1110 bios_connectors[i].hpd =
1111 bios_connectors[j].hpd;
1112 bios_connectors[j].valid = false;
1113 }
1114 }
1115 }
1116 }
1117 }
1118 }
1119
1120 /* add the connectors */
1121 for (i = 0; i < max_device; i++) {
1122 if (bios_connectors[i].valid) {
1123 uint16_t connector_object_id =
1124 atombios_get_connector_object_id(dev,
1125 bios_connectors[i].connector_type,
1126 bios_connectors[i].devices);
1127 radeon_add_atom_connector(dev,
1128 bios_connectors[i].line_mux,
1129 bios_connectors[i].devices,
1130 bios_connectors[i].
1131 connector_type,
1132 &bios_connectors[i].ddc_bus,
1133 0,
1134 connector_object_id,
1135 &bios_connectors[i].hpd,
1136 &router);
1137 }
1138 }
1139
1140 radeon_link_encoder_connector(dev);
1141
1142 kfree(bios_connectors);
1143 return true;
1144 }
1145
1146 union firmware_info {
1147 ATOM_FIRMWARE_INFO info;
1148 ATOM_FIRMWARE_INFO_V1_2 info_12;
1149 ATOM_FIRMWARE_INFO_V1_3 info_13;
1150 ATOM_FIRMWARE_INFO_V1_4 info_14;
1151 ATOM_FIRMWARE_INFO_V2_1 info_21;
1152 ATOM_FIRMWARE_INFO_V2_2 info_22;
1153 };
1154
1155 bool radeon_atom_get_clock_info(struct drm_device *dev)
1156 {
1157 struct radeon_device *rdev = dev->dev_private;
1158 struct radeon_mode_info *mode_info = &rdev->mode_info;
1159 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1160 union firmware_info *firmware_info;
1161 uint8_t frev, crev;
1162 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1163 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1164 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1165 struct radeon_pll *spll = &rdev->clock.spll;
1166 struct radeon_pll *mpll = &rdev->clock.mpll;
1167 uint16_t data_offset;
1168
1169 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1170 &frev, &crev, &data_offset)) {
1171 firmware_info =
1172 (union firmware_info *)(mode_info->atom_context->bios +
1173 data_offset);
1174 /* pixel clocks */
1175 p1pll->reference_freq =
1176 le16_to_cpu(firmware_info->info.usReferenceClock);
1177 p1pll->reference_div = 0;
1178
1179 if (crev < 2)
1180 p1pll->pll_out_min =
1181 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1182 else
1183 p1pll->pll_out_min =
1184 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1185 p1pll->pll_out_max =
1186 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1187
1188 if (crev >= 4) {
1189 p1pll->lcd_pll_out_min =
1190 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1191 if (p1pll->lcd_pll_out_min == 0)
1192 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1193 p1pll->lcd_pll_out_max =
1194 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1195 if (p1pll->lcd_pll_out_max == 0)
1196 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1197 } else {
1198 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1199 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1200 }
1201
1202 if (p1pll->pll_out_min == 0) {
1203 if (ASIC_IS_AVIVO(rdev))
1204 p1pll->pll_out_min = 64800;
1205 else
1206 p1pll->pll_out_min = 20000;
1207 }
1208
1209 p1pll->pll_in_min =
1210 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1211 p1pll->pll_in_max =
1212 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1213
1214 *p2pll = *p1pll;
1215
1216 /* system clock */
1217 if (ASIC_IS_DCE4(rdev))
1218 spll->reference_freq =
1219 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1220 else
1221 spll->reference_freq =
1222 le16_to_cpu(firmware_info->info.usReferenceClock);
1223 spll->reference_div = 0;
1224
1225 spll->pll_out_min =
1226 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1227 spll->pll_out_max =
1228 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1229
1230 /* ??? */
1231 if (spll->pll_out_min == 0) {
1232 if (ASIC_IS_AVIVO(rdev))
1233 spll->pll_out_min = 64800;
1234 else
1235 spll->pll_out_min = 20000;
1236 }
1237
1238 spll->pll_in_min =
1239 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1240 spll->pll_in_max =
1241 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1242
1243 /* memory clock */
1244 if (ASIC_IS_DCE4(rdev))
1245 mpll->reference_freq =
1246 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1247 else
1248 mpll->reference_freq =
1249 le16_to_cpu(firmware_info->info.usReferenceClock);
1250 mpll->reference_div = 0;
1251
1252 mpll->pll_out_min =
1253 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1254 mpll->pll_out_max =
1255 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1256
1257 /* ??? */
1258 if (mpll->pll_out_min == 0) {
1259 if (ASIC_IS_AVIVO(rdev))
1260 mpll->pll_out_min = 64800;
1261 else
1262 mpll->pll_out_min = 20000;
1263 }
1264
1265 mpll->pll_in_min =
1266 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1267 mpll->pll_in_max =
1268 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1269
1270 rdev->clock.default_sclk =
1271 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1272 rdev->clock.default_mclk =
1273 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1274
1275 if (ASIC_IS_DCE4(rdev)) {
1276 rdev->clock.default_dispclk =
1277 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1278 if (rdev->clock.default_dispclk == 0) {
1279 if (ASIC_IS_DCE5(rdev))
1280 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1281 else
1282 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1283 }
1284 rdev->clock.dp_extclk =
1285 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1286 }
1287 *dcpll = *p1pll;
1288
1289 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1290 if (rdev->clock.max_pixel_clock == 0)
1291 rdev->clock.max_pixel_clock = 40000;
1292
1293 return true;
1294 }
1295
1296 return false;
1297 }
1298
1299 union igp_info {
1300 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1301 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1302 };
1303
1304 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1305 {
1306 struct radeon_mode_info *mode_info = &rdev->mode_info;
1307 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1308 union igp_info *igp_info;
1309 u8 frev, crev;
1310 u16 data_offset;
1311
1312 /* sideport is AMD only */
1313 if (rdev->family == CHIP_RS600)
1314 return false;
1315
1316 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1317 &frev, &crev, &data_offset)) {
1318 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1319 data_offset);
1320 switch (crev) {
1321 case 1:
1322 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1323 return true;
1324 break;
1325 case 2:
1326 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1327 return true;
1328 break;
1329 default:
1330 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1331 break;
1332 }
1333 }
1334 return false;
1335 }
1336
1337 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1338 struct radeon_encoder_int_tmds *tmds)
1339 {
1340 struct drm_device *dev = encoder->base.dev;
1341 struct radeon_device *rdev = dev->dev_private;
1342 struct radeon_mode_info *mode_info = &rdev->mode_info;
1343 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1344 uint16_t data_offset;
1345 struct _ATOM_TMDS_INFO *tmds_info;
1346 uint8_t frev, crev;
1347 uint16_t maxfreq;
1348 int i;
1349
1350 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1351 &frev, &crev, &data_offset)) {
1352 tmds_info =
1353 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1354 data_offset);
1355
1356 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1357 for (i = 0; i < 4; i++) {
1358 tmds->tmds_pll[i].freq =
1359 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1360 tmds->tmds_pll[i].value =
1361 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1362 tmds->tmds_pll[i].value |=
1363 (tmds_info->asMiscInfo[i].
1364 ucPLL_VCO_Gain & 0x3f) << 6;
1365 tmds->tmds_pll[i].value |=
1366 (tmds_info->asMiscInfo[i].
1367 ucPLL_DutyCycle & 0xf) << 12;
1368 tmds->tmds_pll[i].value |=
1369 (tmds_info->asMiscInfo[i].
1370 ucPLL_VoltageSwing & 0xf) << 16;
1371
1372 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1373 tmds->tmds_pll[i].freq,
1374 tmds->tmds_pll[i].value);
1375
1376 if (maxfreq == tmds->tmds_pll[i].freq) {
1377 tmds->tmds_pll[i].freq = 0xffffffff;
1378 break;
1379 }
1380 }
1381 return true;
1382 }
1383 return false;
1384 }
1385
1386 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1387 struct radeon_atom_ss *ss,
1388 int id)
1389 {
1390 struct radeon_mode_info *mode_info = &rdev->mode_info;
1391 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1392 uint16_t data_offset, size;
1393 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1394 uint8_t frev, crev;
1395 int i, num_indices;
1396
1397 memset(ss, 0, sizeof(struct radeon_atom_ss));
1398 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1399 &frev, &crev, &data_offset)) {
1400 ss_info =
1401 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1402
1403 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1404 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1405
1406 for (i = 0; i < num_indices; i++) {
1407 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1408 ss->percentage =
1409 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1410 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1411 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1412 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1413 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1414 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1415 return true;
1416 }
1417 }
1418 }
1419 return false;
1420 }
1421
1422 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1423 struct radeon_atom_ss *ss,
1424 int id)
1425 {
1426 struct radeon_mode_info *mode_info = &rdev->mode_info;
1427 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1428 u16 data_offset, size;
1429 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1430 u8 frev, crev;
1431 u16 percentage = 0, rate = 0;
1432
1433 /* get any igp specific overrides */
1434 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1435 &frev, &crev, &data_offset)) {
1436 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1437 (mode_info->atom_context->bios + data_offset);
1438 switch (id) {
1439 case ASIC_INTERNAL_SS_ON_TMDS:
1440 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1441 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1442 break;
1443 case ASIC_INTERNAL_SS_ON_HDMI:
1444 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1445 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1446 break;
1447 case ASIC_INTERNAL_SS_ON_LVDS:
1448 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1449 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1450 break;
1451 }
1452 if (percentage)
1453 ss->percentage = percentage;
1454 if (rate)
1455 ss->rate = rate;
1456 }
1457 }
1458
1459 union asic_ss_info {
1460 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1461 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1462 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1463 };
1464
1465 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1466 struct radeon_atom_ss *ss,
1467 int id, u32 clock)
1468 {
1469 struct radeon_mode_info *mode_info = &rdev->mode_info;
1470 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1471 uint16_t data_offset, size;
1472 union asic_ss_info *ss_info;
1473 uint8_t frev, crev;
1474 int i, num_indices;
1475
1476 memset(ss, 0, sizeof(struct radeon_atom_ss));
1477 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1478 &frev, &crev, &data_offset)) {
1479
1480 ss_info =
1481 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1482
1483 switch (frev) {
1484 case 1:
1485 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1486 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1487
1488 for (i = 0; i < num_indices; i++) {
1489 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1490 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1491 ss->percentage =
1492 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1493 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1494 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1495 return true;
1496 }
1497 }
1498 break;
1499 case 2:
1500 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1501 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1502 for (i = 0; i < num_indices; i++) {
1503 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1504 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1505 ss->percentage =
1506 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1507 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1508 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1509 return true;
1510 }
1511 }
1512 break;
1513 case 3:
1514 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1515 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1516 for (i = 0; i < num_indices; i++) {
1517 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1518 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1519 ss->percentage =
1520 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1521 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1522 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1523 if (rdev->flags & RADEON_IS_IGP)
1524 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1525 return true;
1526 }
1527 }
1528 break;
1529 default:
1530 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1531 break;
1532 }
1533
1534 }
1535 return false;
1536 }
1537
1538 union lvds_info {
1539 struct _ATOM_LVDS_INFO info;
1540 struct _ATOM_LVDS_INFO_V12 info_12;
1541 };
1542
1543 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1544 radeon_encoder
1545 *encoder)
1546 {
1547 struct drm_device *dev = encoder->base.dev;
1548 struct radeon_device *rdev = dev->dev_private;
1549 struct radeon_mode_info *mode_info = &rdev->mode_info;
1550 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1551 uint16_t data_offset, misc;
1552 union lvds_info *lvds_info;
1553 uint8_t frev, crev;
1554 struct radeon_encoder_atom_dig *lvds = NULL;
1555 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1556
1557 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1558 &frev, &crev, &data_offset)) {
1559 lvds_info =
1560 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1561 lvds =
1562 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1563
1564 if (!lvds)
1565 return NULL;
1566
1567 lvds->native_mode.clock =
1568 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1569 lvds->native_mode.hdisplay =
1570 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1571 lvds->native_mode.vdisplay =
1572 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1573 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1574 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1575 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1576 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1577 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1578 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1579 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1580 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1581 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1582 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1583 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1584 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1585 lvds->panel_pwr_delay =
1586 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1587 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1588
1589 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1590 if (misc & ATOM_VSYNC_POLARITY)
1591 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1592 if (misc & ATOM_HSYNC_POLARITY)
1593 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1594 if (misc & ATOM_COMPOSITESYNC)
1595 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1596 if (misc & ATOM_INTERLACE)
1597 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1598 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1599 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1600
1601 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1602 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1603
1604 /* set crtc values */
1605 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1606
1607 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1608
1609 encoder->native_mode = lvds->native_mode;
1610
1611 if (encoder_enum == 2)
1612 lvds->linkb = true;
1613 else
1614 lvds->linkb = false;
1615
1616 /* parse the lcd record table */
1617 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1618 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1619 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1620 bool bad_record = false;
1621 u8 *record;
1622
1623 if ((frev == 1) && (crev < 2))
1624 /* absolute */
1625 record = (u8 *)(mode_info->atom_context->bios +
1626 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1627 else
1628 /* relative */
1629 record = (u8 *)(mode_info->atom_context->bios +
1630 data_offset +
1631 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1632 while (*record != ATOM_RECORD_END_TYPE) {
1633 switch (*record) {
1634 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1635 record += sizeof(ATOM_PATCH_RECORD_MODE);
1636 break;
1637 case LCD_RTS_RECORD_TYPE:
1638 record += sizeof(ATOM_LCD_RTS_RECORD);
1639 break;
1640 case LCD_CAP_RECORD_TYPE:
1641 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1642 break;
1643 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1644 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1645 if (fake_edid_record->ucFakeEDIDLength) {
1646 struct edid *edid;
1647 int edid_size =
1648 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1649 edid = kmalloc(edid_size, GFP_KERNEL);
1650 if (edid) {
1651 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1652 fake_edid_record->ucFakeEDIDLength);
1653
1654 if (drm_edid_is_valid(edid)) {
1655 rdev->mode_info.bios_hardcoded_edid = edid;
1656 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1657 } else
1658 kfree(edid);
1659 }
1660 }
1661 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1662 break;
1663 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1664 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1665 lvds->native_mode.width_mm = panel_res_record->usHSize;
1666 lvds->native_mode.height_mm = panel_res_record->usVSize;
1667 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1668 break;
1669 default:
1670 DRM_ERROR("Bad LCD record %d\n", *record);
1671 bad_record = true;
1672 break;
1673 }
1674 if (bad_record)
1675 break;
1676 }
1677 }
1678 }
1679 return lvds;
1680 }
1681
1682 struct radeon_encoder_primary_dac *
1683 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1684 {
1685 struct drm_device *dev = encoder->base.dev;
1686 struct radeon_device *rdev = dev->dev_private;
1687 struct radeon_mode_info *mode_info = &rdev->mode_info;
1688 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1689 uint16_t data_offset;
1690 struct _COMPASSIONATE_DATA *dac_info;
1691 uint8_t frev, crev;
1692 uint8_t bg, dac;
1693 struct radeon_encoder_primary_dac *p_dac = NULL;
1694
1695 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1696 &frev, &crev, &data_offset)) {
1697 dac_info = (struct _COMPASSIONATE_DATA *)
1698 (mode_info->atom_context->bios + data_offset);
1699
1700 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1701
1702 if (!p_dac)
1703 return NULL;
1704
1705 bg = dac_info->ucDAC1_BG_Adjustment;
1706 dac = dac_info->ucDAC1_DAC_Adjustment;
1707 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1708
1709 }
1710 return p_dac;
1711 }
1712
1713 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1714 struct drm_display_mode *mode)
1715 {
1716 struct radeon_mode_info *mode_info = &rdev->mode_info;
1717 ATOM_ANALOG_TV_INFO *tv_info;
1718 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1719 ATOM_DTD_FORMAT *dtd_timings;
1720 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1721 u8 frev, crev;
1722 u16 data_offset, misc;
1723
1724 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1725 &frev, &crev, &data_offset))
1726 return false;
1727
1728 switch (crev) {
1729 case 1:
1730 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1731 if (index >= MAX_SUPPORTED_TV_TIMING)
1732 return false;
1733
1734 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1735 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1736 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1737 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1738 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1739
1740 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1741 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1742 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1743 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1744 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1745
1746 mode->flags = 0;
1747 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1748 if (misc & ATOM_VSYNC_POLARITY)
1749 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1750 if (misc & ATOM_HSYNC_POLARITY)
1751 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1752 if (misc & ATOM_COMPOSITESYNC)
1753 mode->flags |= DRM_MODE_FLAG_CSYNC;
1754 if (misc & ATOM_INTERLACE)
1755 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1756 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1757 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1758
1759 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1760
1761 if (index == 1) {
1762 /* PAL timings appear to have wrong values for totals */
1763 mode->crtc_htotal -= 1;
1764 mode->crtc_vtotal -= 1;
1765 }
1766 break;
1767 case 2:
1768 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1769 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1770 return false;
1771
1772 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1773 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1774 le16_to_cpu(dtd_timings->usHBlanking_Time);
1775 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1776 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1777 le16_to_cpu(dtd_timings->usHSyncOffset);
1778 mode->crtc_hsync_end = mode->crtc_hsync_start +
1779 le16_to_cpu(dtd_timings->usHSyncWidth);
1780
1781 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1782 le16_to_cpu(dtd_timings->usVBlanking_Time);
1783 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1784 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1785 le16_to_cpu(dtd_timings->usVSyncOffset);
1786 mode->crtc_vsync_end = mode->crtc_vsync_start +
1787 le16_to_cpu(dtd_timings->usVSyncWidth);
1788
1789 mode->flags = 0;
1790 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1791 if (misc & ATOM_VSYNC_POLARITY)
1792 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1793 if (misc & ATOM_HSYNC_POLARITY)
1794 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1795 if (misc & ATOM_COMPOSITESYNC)
1796 mode->flags |= DRM_MODE_FLAG_CSYNC;
1797 if (misc & ATOM_INTERLACE)
1798 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1799 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1800 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1801
1802 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1803 break;
1804 }
1805 return true;
1806 }
1807
1808 enum radeon_tv_std
1809 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1810 {
1811 struct radeon_mode_info *mode_info = &rdev->mode_info;
1812 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1813 uint16_t data_offset;
1814 uint8_t frev, crev;
1815 struct _ATOM_ANALOG_TV_INFO *tv_info;
1816 enum radeon_tv_std tv_std = TV_STD_NTSC;
1817
1818 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1819 &frev, &crev, &data_offset)) {
1820
1821 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1822 (mode_info->atom_context->bios + data_offset);
1823
1824 switch (tv_info->ucTV_BootUpDefaultStandard) {
1825 case ATOM_TV_NTSC:
1826 tv_std = TV_STD_NTSC;
1827 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1828 break;
1829 case ATOM_TV_NTSCJ:
1830 tv_std = TV_STD_NTSC_J;
1831 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1832 break;
1833 case ATOM_TV_PAL:
1834 tv_std = TV_STD_PAL;
1835 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1836 break;
1837 case ATOM_TV_PALM:
1838 tv_std = TV_STD_PAL_M;
1839 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1840 break;
1841 case ATOM_TV_PALN:
1842 tv_std = TV_STD_PAL_N;
1843 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1844 break;
1845 case ATOM_TV_PALCN:
1846 tv_std = TV_STD_PAL_CN;
1847 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1848 break;
1849 case ATOM_TV_PAL60:
1850 tv_std = TV_STD_PAL_60;
1851 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1852 break;
1853 case ATOM_TV_SECAM:
1854 tv_std = TV_STD_SECAM;
1855 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1856 break;
1857 default:
1858 tv_std = TV_STD_NTSC;
1859 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1860 break;
1861 }
1862 }
1863 return tv_std;
1864 }
1865
1866 struct radeon_encoder_tv_dac *
1867 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1868 {
1869 struct drm_device *dev = encoder->base.dev;
1870 struct radeon_device *rdev = dev->dev_private;
1871 struct radeon_mode_info *mode_info = &rdev->mode_info;
1872 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1873 uint16_t data_offset;
1874 struct _COMPASSIONATE_DATA *dac_info;
1875 uint8_t frev, crev;
1876 uint8_t bg, dac;
1877 struct radeon_encoder_tv_dac *tv_dac = NULL;
1878
1879 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1880 &frev, &crev, &data_offset)) {
1881
1882 dac_info = (struct _COMPASSIONATE_DATA *)
1883 (mode_info->atom_context->bios + data_offset);
1884
1885 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1886
1887 if (!tv_dac)
1888 return NULL;
1889
1890 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1891 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1892 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1893
1894 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1895 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1896 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1897
1898 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1899 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1900 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1901
1902 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1903 }
1904 return tv_dac;
1905 }
1906
1907 static const char *thermal_controller_names[] = {
1908 "NONE",
1909 "lm63",
1910 "adm1032",
1911 "adm1030",
1912 "max6649",
1913 "lm64",
1914 "f75375",
1915 "asc7xxx",
1916 };
1917
1918 static const char *pp_lib_thermal_controller_names[] = {
1919 "NONE",
1920 "lm63",
1921 "adm1032",
1922 "adm1030",
1923 "max6649",
1924 "lm64",
1925 "f75375",
1926 "RV6xx",
1927 "RV770",
1928 "adt7473",
1929 "NONE",
1930 "External GPIO",
1931 "Evergreen",
1932 "emc2103",
1933 "Sumo",
1934 "Northern Islands",
1935 };
1936
1937 union power_info {
1938 struct _ATOM_POWERPLAY_INFO info;
1939 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1940 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1941 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1942 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1943 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1944 };
1945
1946 union pplib_clock_info {
1947 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1948 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1949 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1950 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1951 };
1952
1953 union pplib_power_state {
1954 struct _ATOM_PPLIB_STATE v1;
1955 struct _ATOM_PPLIB_STATE_V2 v2;
1956 };
1957
1958 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1959 int state_index,
1960 u32 misc, u32 misc2)
1961 {
1962 rdev->pm.power_state[state_index].misc = misc;
1963 rdev->pm.power_state[state_index].misc2 = misc2;
1964 /* order matters! */
1965 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1966 rdev->pm.power_state[state_index].type =
1967 POWER_STATE_TYPE_POWERSAVE;
1968 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1969 rdev->pm.power_state[state_index].type =
1970 POWER_STATE_TYPE_BATTERY;
1971 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1972 rdev->pm.power_state[state_index].type =
1973 POWER_STATE_TYPE_BATTERY;
1974 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1975 rdev->pm.power_state[state_index].type =
1976 POWER_STATE_TYPE_BALANCED;
1977 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1978 rdev->pm.power_state[state_index].type =
1979 POWER_STATE_TYPE_PERFORMANCE;
1980 rdev->pm.power_state[state_index].flags &=
1981 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1982 }
1983 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1984 rdev->pm.power_state[state_index].type =
1985 POWER_STATE_TYPE_BALANCED;
1986 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1987 rdev->pm.power_state[state_index].type =
1988 POWER_STATE_TYPE_DEFAULT;
1989 rdev->pm.default_power_state_index = state_index;
1990 rdev->pm.power_state[state_index].default_clock_mode =
1991 &rdev->pm.power_state[state_index].clock_info[0];
1992 } else if (state_index == 0) {
1993 rdev->pm.power_state[state_index].clock_info[0].flags |=
1994 RADEON_PM_MODE_NO_DISPLAY;
1995 }
1996 }
1997
1998 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1999 {
2000 struct radeon_mode_info *mode_info = &rdev->mode_info;
2001 u32 misc, misc2 = 0;
2002 int num_modes = 0, i;
2003 int state_index = 0;
2004 struct radeon_i2c_bus_rec i2c_bus;
2005 union power_info *power_info;
2006 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2007 u16 data_offset;
2008 u8 frev, crev;
2009
2010 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2011 &frev, &crev, &data_offset))
2012 return state_index;
2013 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2014
2015 /* add the i2c bus for thermal/fan chip */
2016 if (power_info->info.ucOverdriveThermalController > 0) {
2017 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2018 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2019 power_info->info.ucOverdriveControllerAddress >> 1);
2020 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2021 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2022 if (rdev->pm.i2c_bus) {
2023 struct i2c_board_info info = { };
2024 const char *name = thermal_controller_names[power_info->info.
2025 ucOverdriveThermalController];
2026 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2027 strlcpy(info.type, name, sizeof(info.type));
2028 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2029 }
2030 }
2031 num_modes = power_info->info.ucNumOfPowerModeEntries;
2032 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2033 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2034 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2035 if (!rdev->pm.power_state)
2036 return state_index;
2037 /* last mode is usually default, array is low to high */
2038 for (i = 0; i < num_modes; i++) {
2039 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2040 switch (frev) {
2041 case 1:
2042 rdev->pm.power_state[state_index].num_clock_modes = 1;
2043 rdev->pm.power_state[state_index].clock_info[0].mclk =
2044 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2045 rdev->pm.power_state[state_index].clock_info[0].sclk =
2046 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2047 /* skip invalid modes */
2048 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2049 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2050 continue;
2051 rdev->pm.power_state[state_index].pcie_lanes =
2052 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2053 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2054 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2055 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2056 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2057 VOLTAGE_GPIO;
2058 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2059 radeon_lookup_gpio(rdev,
2060 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2061 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2062 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2063 true;
2064 else
2065 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2066 false;
2067 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2068 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2069 VOLTAGE_VDDC;
2070 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2071 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2072 }
2073 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2074 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2075 state_index++;
2076 break;
2077 case 2:
2078 rdev->pm.power_state[state_index].num_clock_modes = 1;
2079 rdev->pm.power_state[state_index].clock_info[0].mclk =
2080 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2081 rdev->pm.power_state[state_index].clock_info[0].sclk =
2082 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2083 /* skip invalid modes */
2084 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2085 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2086 continue;
2087 rdev->pm.power_state[state_index].pcie_lanes =
2088 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2089 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2090 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2091 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2092 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2093 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2094 VOLTAGE_GPIO;
2095 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2096 radeon_lookup_gpio(rdev,
2097 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2098 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2099 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2100 true;
2101 else
2102 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2103 false;
2104 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2105 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2106 VOLTAGE_VDDC;
2107 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2108 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2109 }
2110 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2111 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2112 state_index++;
2113 break;
2114 case 3:
2115 rdev->pm.power_state[state_index].num_clock_modes = 1;
2116 rdev->pm.power_state[state_index].clock_info[0].mclk =
2117 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2118 rdev->pm.power_state[state_index].clock_info[0].sclk =
2119 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2120 /* skip invalid modes */
2121 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2122 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2123 continue;
2124 rdev->pm.power_state[state_index].pcie_lanes =
2125 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2126 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2127 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2128 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2129 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2130 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2131 VOLTAGE_GPIO;
2132 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2133 radeon_lookup_gpio(rdev,
2134 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2135 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2136 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2137 true;
2138 else
2139 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2140 false;
2141 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2142 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2143 VOLTAGE_VDDC;
2144 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2145 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2146 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2147 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2148 true;
2149 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2150 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2151 }
2152 }
2153 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2154 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2155 state_index++;
2156 break;
2157 }
2158 }
2159 /* last mode is usually default */
2160 if (rdev->pm.default_power_state_index == -1) {
2161 rdev->pm.power_state[state_index - 1].type =
2162 POWER_STATE_TYPE_DEFAULT;
2163 rdev->pm.default_power_state_index = state_index - 1;
2164 rdev->pm.power_state[state_index - 1].default_clock_mode =
2165 &rdev->pm.power_state[state_index - 1].clock_info[0];
2166 rdev->pm.power_state[state_index].flags &=
2167 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2168 rdev->pm.power_state[state_index].misc = 0;
2169 rdev->pm.power_state[state_index].misc2 = 0;
2170 }
2171 return state_index;
2172 }
2173
2174 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2175 ATOM_PPLIB_THERMALCONTROLLER *controller)
2176 {
2177 struct radeon_i2c_bus_rec i2c_bus;
2178
2179 /* add the i2c bus for thermal/fan chip */
2180 if (controller->ucType > 0) {
2181 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2182 DRM_INFO("Internal thermal controller %s fan control\n",
2183 (controller->ucFanParameters &
2184 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2185 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2186 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2187 DRM_INFO("Internal thermal controller %s fan control\n",
2188 (controller->ucFanParameters &
2189 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2190 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2191 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2192 DRM_INFO("Internal thermal controller %s fan control\n",
2193 (controller->ucFanParameters &
2194 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2195 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2196 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2197 DRM_INFO("Internal thermal controller %s fan control\n",
2198 (controller->ucFanParameters &
2199 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2200 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2201 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2202 DRM_INFO("Internal thermal controller %s fan control\n",
2203 (controller->ucFanParameters &
2204 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2205 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2206 } else if ((controller->ucType ==
2207 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2208 (controller->ucType ==
2209 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2210 (controller->ucType ==
2211 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2212 DRM_INFO("Special thermal controller config\n");
2213 } else {
2214 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2215 pp_lib_thermal_controller_names[controller->ucType],
2216 controller->ucI2cAddress >> 1,
2217 (controller->ucFanParameters &
2218 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2219 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2220 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2221 if (rdev->pm.i2c_bus) {
2222 struct i2c_board_info info = { };
2223 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2224 info.addr = controller->ucI2cAddress >> 1;
2225 strlcpy(info.type, name, sizeof(info.type));
2226 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2227 }
2228 }
2229 }
2230 }
2231
2232 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2233 u16 *vddc, u16 *vddci)
2234 {
2235 struct radeon_mode_info *mode_info = &rdev->mode_info;
2236 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2237 u8 frev, crev;
2238 u16 data_offset;
2239 union firmware_info *firmware_info;
2240
2241 *vddc = 0;
2242 *vddci = 0;
2243
2244 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2245 &frev, &crev, &data_offset)) {
2246 firmware_info =
2247 (union firmware_info *)(mode_info->atom_context->bios +
2248 data_offset);
2249 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2250 if ((frev == 2) && (crev >= 2))
2251 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2252 }
2253 }
2254
2255 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2256 int state_index, int mode_index,
2257 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2258 {
2259 int j;
2260 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2261 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2262 u16 vddc, vddci;
2263
2264 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2265
2266 rdev->pm.power_state[state_index].misc = misc;
2267 rdev->pm.power_state[state_index].misc2 = misc2;
2268 rdev->pm.power_state[state_index].pcie_lanes =
2269 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2270 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2271 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2272 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2273 rdev->pm.power_state[state_index].type =
2274 POWER_STATE_TYPE_BATTERY;
2275 break;
2276 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2277 rdev->pm.power_state[state_index].type =
2278 POWER_STATE_TYPE_BALANCED;
2279 break;
2280 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2281 rdev->pm.power_state[state_index].type =
2282 POWER_STATE_TYPE_PERFORMANCE;
2283 break;
2284 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2285 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2286 rdev->pm.power_state[state_index].type =
2287 POWER_STATE_TYPE_PERFORMANCE;
2288 break;
2289 }
2290 rdev->pm.power_state[state_index].flags = 0;
2291 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2292 rdev->pm.power_state[state_index].flags |=
2293 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2294 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2295 rdev->pm.power_state[state_index].type =
2296 POWER_STATE_TYPE_DEFAULT;
2297 rdev->pm.default_power_state_index = state_index;
2298 rdev->pm.power_state[state_index].default_clock_mode =
2299 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2300 if (ASIC_IS_DCE5(rdev)) {
2301 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2302 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2303 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2304 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2305 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2306 } else {
2307 /* patch the table values with the default slck/mclk from firmware info */
2308 for (j = 0; j < mode_index; j++) {
2309 rdev->pm.power_state[state_index].clock_info[j].mclk =
2310 rdev->clock.default_mclk;
2311 rdev->pm.power_state[state_index].clock_info[j].sclk =
2312 rdev->clock.default_sclk;
2313 if (vddc)
2314 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2315 vddc;
2316 }
2317 }
2318 }
2319 }
2320
2321 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2322 int state_index, int mode_index,
2323 union pplib_clock_info *clock_info)
2324 {
2325 u32 sclk, mclk;
2326
2327 if (rdev->flags & RADEON_IS_IGP) {
2328 if (rdev->family >= CHIP_PALM) {
2329 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2330 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2331 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2332 } else {
2333 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2334 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2335 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2336 }
2337 } else if (ASIC_IS_DCE4(rdev)) {
2338 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2339 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2340 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2341 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2342 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2343 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2344 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2345 VOLTAGE_SW;
2346 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2347 le16_to_cpu(clock_info->evergreen.usVDDC);
2348 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2349 le16_to_cpu(clock_info->evergreen.usVDDCI);
2350 } else {
2351 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2352 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2353 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2354 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2355 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2356 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2357 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2358 VOLTAGE_SW;
2359 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2360 le16_to_cpu(clock_info->r600.usVDDC);
2361 }
2362
2363 /* patch up vddc if necessary */
2364 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2365 u16 vddc;
2366
2367 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2368 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2369 }
2370
2371 if (rdev->flags & RADEON_IS_IGP) {
2372 /* skip invalid modes */
2373 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2374 return false;
2375 } else {
2376 /* skip invalid modes */
2377 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2378 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2379 return false;
2380 }
2381 return true;
2382 }
2383
2384 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2385 {
2386 struct radeon_mode_info *mode_info = &rdev->mode_info;
2387 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2388 union pplib_power_state *power_state;
2389 int i, j;
2390 int state_index = 0, mode_index = 0;
2391 union pplib_clock_info *clock_info;
2392 bool valid;
2393 union power_info *power_info;
2394 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2395 u16 data_offset;
2396 u8 frev, crev;
2397
2398 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2399 &frev, &crev, &data_offset))
2400 return state_index;
2401 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2402
2403 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2404 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2405 power_info->pplib.ucNumStates, GFP_KERNEL);
2406 if (!rdev->pm.power_state)
2407 return state_index;
2408 /* first mode is usually default, followed by low to high */
2409 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2410 mode_index = 0;
2411 power_state = (union pplib_power_state *)
2412 (mode_info->atom_context->bios + data_offset +
2413 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2414 i * power_info->pplib.ucStateEntrySize);
2415 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2416 (mode_info->atom_context->bios + data_offset +
2417 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2418 (power_state->v1.ucNonClockStateIndex *
2419 power_info->pplib.ucNonClockSize));
2420 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2421 clock_info = (union pplib_clock_info *)
2422 (mode_info->atom_context->bios + data_offset +
2423 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2424 (power_state->v1.ucClockStateIndices[j] *
2425 power_info->pplib.ucClockInfoSize));
2426 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2427 state_index, mode_index,
2428 clock_info);
2429 if (valid)
2430 mode_index++;
2431 }
2432 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2433 if (mode_index) {
2434 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2435 non_clock_info);
2436 state_index++;
2437 }
2438 }
2439 /* if multiple clock modes, mark the lowest as no display */
2440 for (i = 0; i < state_index; i++) {
2441 if (rdev->pm.power_state[i].num_clock_modes > 1)
2442 rdev->pm.power_state[i].clock_info[0].flags |=
2443 RADEON_PM_MODE_NO_DISPLAY;
2444 }
2445 /* first mode is usually default */
2446 if (rdev->pm.default_power_state_index == -1) {
2447 rdev->pm.power_state[0].type =
2448 POWER_STATE_TYPE_DEFAULT;
2449 rdev->pm.default_power_state_index = 0;
2450 rdev->pm.power_state[0].default_clock_mode =
2451 &rdev->pm.power_state[0].clock_info[0];
2452 }
2453 return state_index;
2454 }
2455
2456 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2457 {
2458 struct radeon_mode_info *mode_info = &rdev->mode_info;
2459 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2460 union pplib_power_state *power_state;
2461 int i, j, non_clock_array_index, clock_array_index;
2462 int state_index = 0, mode_index = 0;
2463 union pplib_clock_info *clock_info;
2464 struct StateArray *state_array;
2465 struct ClockInfoArray *clock_info_array;
2466 struct NonClockInfoArray *non_clock_info_array;
2467 bool valid;
2468 union power_info *power_info;
2469 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2470 u16 data_offset;
2471 u8 frev, crev;
2472
2473 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2474 &frev, &crev, &data_offset))
2475 return state_index;
2476 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2477
2478 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2479 state_array = (struct StateArray *)
2480 (mode_info->atom_context->bios + data_offset +
2481 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2482 clock_info_array = (struct ClockInfoArray *)
2483 (mode_info->atom_context->bios + data_offset +
2484 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2485 non_clock_info_array = (struct NonClockInfoArray *)
2486 (mode_info->atom_context->bios + data_offset +
2487 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2488 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2489 state_array->ucNumEntries, GFP_KERNEL);
2490 if (!rdev->pm.power_state)
2491 return state_index;
2492 for (i = 0; i < state_array->ucNumEntries; i++) {
2493 mode_index = 0;
2494 power_state = (union pplib_power_state *)&state_array->states[i];
2495 /* XXX this might be an inagua bug... */
2496 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2497 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2498 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2499 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2500 clock_array_index = power_state->v2.clockInfoIndex[j];
2501 /* XXX this might be an inagua bug... */
2502 if (clock_array_index >= clock_info_array->ucNumEntries)
2503 continue;
2504 clock_info = (union pplib_clock_info *)
2505 &clock_info_array->clockInfo[clock_array_index];
2506 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2507 state_index, mode_index,
2508 clock_info);
2509 if (valid)
2510 mode_index++;
2511 }
2512 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2513 if (mode_index) {
2514 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2515 non_clock_info);
2516 state_index++;
2517 }
2518 }
2519 /* if multiple clock modes, mark the lowest as no display */
2520 for (i = 0; i < state_index; i++) {
2521 if (rdev->pm.power_state[i].num_clock_modes > 1)
2522 rdev->pm.power_state[i].clock_info[0].flags |=
2523 RADEON_PM_MODE_NO_DISPLAY;
2524 }
2525 /* first mode is usually default */
2526 if (rdev->pm.default_power_state_index == -1) {
2527 rdev->pm.power_state[0].type =
2528 POWER_STATE_TYPE_DEFAULT;
2529 rdev->pm.default_power_state_index = 0;
2530 rdev->pm.power_state[0].default_clock_mode =
2531 &rdev->pm.power_state[0].clock_info[0];
2532 }
2533 return state_index;
2534 }
2535
2536 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2537 {
2538 struct radeon_mode_info *mode_info = &rdev->mode_info;
2539 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2540 u16 data_offset;
2541 u8 frev, crev;
2542 int state_index = 0;
2543
2544 rdev->pm.default_power_state_index = -1;
2545
2546 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2547 &frev, &crev, &data_offset)) {
2548 switch (frev) {
2549 case 1:
2550 case 2:
2551 case 3:
2552 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2553 break;
2554 case 4:
2555 case 5:
2556 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2557 break;
2558 case 6:
2559 state_index = radeon_atombios_parse_power_table_6(rdev);
2560 break;
2561 default:
2562 break;
2563 }
2564 } else {
2565 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2566 if (rdev->pm.power_state) {
2567 /* add the default mode */
2568 rdev->pm.power_state[state_index].type =
2569 POWER_STATE_TYPE_DEFAULT;
2570 rdev->pm.power_state[state_index].num_clock_modes = 1;
2571 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2572 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2573 rdev->pm.power_state[state_index].default_clock_mode =
2574 &rdev->pm.power_state[state_index].clock_info[0];
2575 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2576 rdev->pm.power_state[state_index].pcie_lanes = 16;
2577 rdev->pm.default_power_state_index = state_index;
2578 rdev->pm.power_state[state_index].flags = 0;
2579 state_index++;
2580 }
2581 }
2582
2583 rdev->pm.num_power_states = state_index;
2584
2585 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2586 rdev->pm.current_clock_mode_index = 0;
2587 if (rdev->pm.default_power_state_index >= 0)
2588 rdev->pm.current_vddc =
2589 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2590 else
2591 rdev->pm.current_vddc = 0;
2592 }
2593
2594 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2595 {
2596 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2597 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2598
2599 args.ucEnable = enable;
2600
2601 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2602 }
2603
2604 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2605 {
2606 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2607 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2608
2609 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2610 return le32_to_cpu(args.ulReturnEngineClock);
2611 }
2612
2613 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2614 {
2615 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2616 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2617
2618 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2619 return le32_to_cpu(args.ulReturnMemoryClock);
2620 }
2621
2622 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2623 uint32_t eng_clock)
2624 {
2625 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2626 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2627
2628 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2629
2630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2631 }
2632
2633 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2634 uint32_t mem_clock)
2635 {
2636 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2637 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2638
2639 if (rdev->flags & RADEON_IS_IGP)
2640 return;
2641
2642 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2643
2644 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2645 }
2646
2647 union set_voltage {
2648 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2649 struct _SET_VOLTAGE_PARAMETERS v1;
2650 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2651 };
2652
2653 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2654 {
2655 union set_voltage args;
2656 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2657 u8 frev, crev, volt_index = voltage_level;
2658
2659 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2660 return;
2661
2662 /* 0xff01 is a flag rather then an actual voltage */
2663 if (voltage_level == 0xff01)
2664 return;
2665
2666 switch (crev) {
2667 case 1:
2668 args.v1.ucVoltageType = voltage_type;
2669 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2670 args.v1.ucVoltageIndex = volt_index;
2671 break;
2672 case 2:
2673 args.v2.ucVoltageType = voltage_type;
2674 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2675 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2676 break;
2677 default:
2678 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2679 return;
2680 }
2681
2682 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2683 }
2684
2685 int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2686 u16 *voltage)
2687 {
2688 union set_voltage args;
2689 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2690 u8 frev, crev;
2691
2692 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2693 return -EINVAL;
2694
2695 switch (crev) {
2696 case 1:
2697 return -EINVAL;
2698 case 2:
2699 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2700 args.v2.ucVoltageMode = 0;
2701 args.v2.usVoltageLevel = 0;
2702
2703 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2704
2705 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2706 break;
2707 default:
2708 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2709 return -EINVAL;
2710 }
2711
2712 return 0;
2713 }
2714
2715 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2716 {
2717 struct radeon_device *rdev = dev->dev_private;
2718 uint32_t bios_2_scratch, bios_6_scratch;
2719
2720 if (rdev->family >= CHIP_R600) {
2721 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2722 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2723 } else {
2724 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2725 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2726 }
2727
2728 /* let the bios control the backlight */
2729 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2730
2731 /* tell the bios not to handle mode switching */
2732 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2733
2734 if (rdev->family >= CHIP_R600) {
2735 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2736 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2737 } else {
2738 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2739 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2740 }
2741
2742 }
2743
2744 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2745 {
2746 uint32_t scratch_reg;
2747 int i;
2748
2749 if (rdev->family >= CHIP_R600)
2750 scratch_reg = R600_BIOS_0_SCRATCH;
2751 else
2752 scratch_reg = RADEON_BIOS_0_SCRATCH;
2753
2754 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2755 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2756 }
2757
2758 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2759 {
2760 uint32_t scratch_reg;
2761 int i;
2762
2763 if (rdev->family >= CHIP_R600)
2764 scratch_reg = R600_BIOS_0_SCRATCH;
2765 else
2766 scratch_reg = RADEON_BIOS_0_SCRATCH;
2767
2768 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2769 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2770 }
2771
2772 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2773 {
2774 struct drm_device *dev = encoder->dev;
2775 struct radeon_device *rdev = dev->dev_private;
2776 uint32_t bios_6_scratch;
2777
2778 if (rdev->family >= CHIP_R600)
2779 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2780 else
2781 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2782
2783 if (lock) {
2784 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2785 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2786 } else {
2787 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2788 bios_6_scratch |= ATOM_S6_ACC_MODE;
2789 }
2790
2791 if (rdev->family >= CHIP_R600)
2792 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2793 else
2794 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2795 }
2796
2797 /* at some point we may want to break this out into individual functions */
2798 void
2799 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2800 struct drm_encoder *encoder,
2801 bool connected)
2802 {
2803 struct drm_device *dev = connector->dev;
2804 struct radeon_device *rdev = dev->dev_private;
2805 struct radeon_connector *radeon_connector =
2806 to_radeon_connector(connector);
2807 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2808 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2809
2810 if (rdev->family >= CHIP_R600) {
2811 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2812 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2813 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2814 } else {
2815 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2816 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2817 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2818 }
2819
2820 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2821 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2822 if (connected) {
2823 DRM_DEBUG_KMS("TV1 connected\n");
2824 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2825 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2826 } else {
2827 DRM_DEBUG_KMS("TV1 disconnected\n");
2828 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2829 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2830 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2831 }
2832 }
2833 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2834 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2835 if (connected) {
2836 DRM_DEBUG_KMS("CV connected\n");
2837 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2838 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2839 } else {
2840 DRM_DEBUG_KMS("CV disconnected\n");
2841 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2842 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2843 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2844 }
2845 }
2846 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2847 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2848 if (connected) {
2849 DRM_DEBUG_KMS("LCD1 connected\n");
2850 bios_0_scratch |= ATOM_S0_LCD1;
2851 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2852 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2853 } else {
2854 DRM_DEBUG_KMS("LCD1 disconnected\n");
2855 bios_0_scratch &= ~ATOM_S0_LCD1;
2856 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2857 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2858 }
2859 }
2860 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2861 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2862 if (connected) {
2863 DRM_DEBUG_KMS("CRT1 connected\n");
2864 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2865 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2866 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2867 } else {
2868 DRM_DEBUG_KMS("CRT1 disconnected\n");
2869 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2870 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2871 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2872 }
2873 }
2874 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2875 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2876 if (connected) {
2877 DRM_DEBUG_KMS("CRT2 connected\n");
2878 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2879 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2880 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2881 } else {
2882 DRM_DEBUG_KMS("CRT2 disconnected\n");
2883 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2884 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2885 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2886 }
2887 }
2888 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2889 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2890 if (connected) {
2891 DRM_DEBUG_KMS("DFP1 connected\n");
2892 bios_0_scratch |= ATOM_S0_DFP1;
2893 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2894 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2895 } else {
2896 DRM_DEBUG_KMS("DFP1 disconnected\n");
2897 bios_0_scratch &= ~ATOM_S0_DFP1;
2898 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2899 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2900 }
2901 }
2902 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2903 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2904 if (connected) {
2905 DRM_DEBUG_KMS("DFP2 connected\n");
2906 bios_0_scratch |= ATOM_S0_DFP2;
2907 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2908 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2909 } else {
2910 DRM_DEBUG_KMS("DFP2 disconnected\n");
2911 bios_0_scratch &= ~ATOM_S0_DFP2;
2912 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2913 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2914 }
2915 }
2916 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2917 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2918 if (connected) {
2919 DRM_DEBUG_KMS("DFP3 connected\n");
2920 bios_0_scratch |= ATOM_S0_DFP3;
2921 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2922 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2923 } else {
2924 DRM_DEBUG_KMS("DFP3 disconnected\n");
2925 bios_0_scratch &= ~ATOM_S0_DFP3;
2926 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2927 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2928 }
2929 }
2930 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2931 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2932 if (connected) {
2933 DRM_DEBUG_KMS("DFP4 connected\n");
2934 bios_0_scratch |= ATOM_S0_DFP4;
2935 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2936 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2937 } else {
2938 DRM_DEBUG_KMS("DFP4 disconnected\n");
2939 bios_0_scratch &= ~ATOM_S0_DFP4;
2940 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2941 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2942 }
2943 }
2944 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2945 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2946 if (connected) {
2947 DRM_DEBUG_KMS("DFP5 connected\n");
2948 bios_0_scratch |= ATOM_S0_DFP5;
2949 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2950 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2951 } else {
2952 DRM_DEBUG_KMS("DFP5 disconnected\n");
2953 bios_0_scratch &= ~ATOM_S0_DFP5;
2954 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2955 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2956 }
2957 }
2958
2959 if (rdev->family >= CHIP_R600) {
2960 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2961 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2962 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2963 } else {
2964 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2965 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2966 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2967 }
2968 }
2969
2970 void
2971 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2972 {
2973 struct drm_device *dev = encoder->dev;
2974 struct radeon_device *rdev = dev->dev_private;
2975 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2976 uint32_t bios_3_scratch;
2977
2978 if (rdev->family >= CHIP_R600)
2979 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2980 else
2981 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2982
2983 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2984 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2985 bios_3_scratch |= (crtc << 18);
2986 }
2987 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2988 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2989 bios_3_scratch |= (crtc << 24);
2990 }
2991 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2992 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2993 bios_3_scratch |= (crtc << 16);
2994 }
2995 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2996 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2997 bios_3_scratch |= (crtc << 20);
2998 }
2999 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3000 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3001 bios_3_scratch |= (crtc << 17);
3002 }
3003 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3004 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3005 bios_3_scratch |= (crtc << 19);
3006 }
3007 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3008 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3009 bios_3_scratch |= (crtc << 23);
3010 }
3011 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3012 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3013 bios_3_scratch |= (crtc << 25);
3014 }
3015
3016 if (rdev->family >= CHIP_R600)
3017 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3018 else
3019 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3020 }
3021
3022 void
3023 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3024 {
3025 struct drm_device *dev = encoder->dev;
3026 struct radeon_device *rdev = dev->dev_private;
3027 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3028 uint32_t bios_2_scratch;
3029
3030 if (rdev->family >= CHIP_R600)
3031 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3032 else
3033 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3034
3035 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3036 if (on)
3037 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3038 else
3039 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3040 }
3041 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3042 if (on)
3043 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3044 else
3045 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3046 }
3047 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3048 if (on)
3049 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3050 else
3051 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3052 }
3053 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3054 if (on)
3055 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3056 else
3057 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3058 }
3059 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3060 if (on)
3061 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3062 else
3063 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3064 }
3065 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3066 if (on)
3067 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3068 else
3069 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3070 }
3071 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3072 if (on)
3073 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3074 else
3075 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3076 }
3077 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3078 if (on)
3079 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3080 else
3081 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3082 }
3083 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3084 if (on)
3085 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3086 else
3087 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3088 }
3089 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3090 if (on)
3091 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3092 else
3093 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3094 }
3095
3096 if (rdev->family >= CHIP_R600)
3097 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3098 else
3099 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3100 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree