4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O
13 * APIC code. In particular, we now have separate
14 * handlers for edge and level triggered
16 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17 * allocation PCI to vector mapping, shared PCI
19 * 00/10/27 D. Mosberger Document things a bit more to make them more
20 * understandable. Clean up much of the old
22 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts
23 * and fixes for ACPI S5(SoftOff) support.
24 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
25 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt
26 * vectors in iosapic_set_affinity(),
27 * initializations for /proc/irq/#/smp_affinity
28 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
29 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
30 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to
31 * IOSAPIC mapping error
32 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
33 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system
34 * interrupt, vector, etc.)
35 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's
37 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
38 * Remove iosapic_address & gsi_base from
39 * external interfaces. Rationalize
40 * __init/__devinit attributes.
41 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
42 * Updated to work with irq migration necessary
46 * Here is what the interrupt logic between a PCI device and the kernel looks
49 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
50 * INTD). The device is uniquely identified by its bus-, and slot-number
51 * (the function number does not matter here because all functions share
52 * the same interrupt lines).
54 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
55 * controller. Multiple interrupt lines may have to share the same
56 * IOSAPIC pin (if they're level triggered and use the same polarity).
57 * Each interrupt line has a unique Global System Interrupt (GSI) number
58 * which can be calculated as the sum of the controller's base GSI number
59 * and the IOSAPIC pin number to which the line connects.
61 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
62 * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
65 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is
66 * used as architecture-independent interrupt handling mechanism in Linux.
67 * As an IRQ is a number, we have to have
68 * IA-64 interrupt vector number <-> IRQ number mapping. On smaller
69 * systems, we use one-to-one mapping between IA-64 vector and IRQ. A
70 * platform can implement platform_irq_to_vector(irq) and
71 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
72 * Please see also include/asm-ia64/hw_irq.h for those APIs.
74 * To sum up, there are three levels of mappings involved:
76 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
78 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
79 * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ
80 * (isa_irq) is the only exception in this source code.
83 #include <linux/acpi.h>
84 #include <linux/init.h>
85 #include <linux/irq.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/pci.h>
89 #include <linux/smp.h>
90 #include <linux/smp_lock.h>
91 #include <linux/string.h>
92 #include <linux/bootmem.h>
94 #include <asm/delay.h>
95 #include <asm/hw_irq.h>
97 #include <asm/iosapic.h>
98 #include <asm/machvec.h>
99 #include <asm/processor.h>
100 #include <asm/ptrace.h>
101 #include <asm/system.h>
103 #undef DEBUG_INTERRUPT_ROUTING
105 #ifdef DEBUG_INTERRUPT_ROUTING
106 #define DBG(fmt...) printk(fmt)
111 #define NR_PREALLOCATE_RTE_ENTRIES \
112 (PAGE_SIZE / sizeof(struct iosapic_rte_info))
113 #define RTE_PREALLOCATED (1)
115 static DEFINE_SPINLOCK(iosapic_lock
);
118 * These tables map IA-64 vectors to the IOSAPIC pin that generates this
122 struct iosapic_rte_info
{
123 struct list_head rte_list
; /* node in list of RTEs sharing the
125 char __iomem
*addr
; /* base address of IOSAPIC */
126 unsigned int gsi_base
; /* first GSI assigned to this
128 char rte_index
; /* IOSAPIC RTE index */
129 int refcnt
; /* reference counter */
130 unsigned int flags
; /* flags */
131 } ____cacheline_aligned
;
133 static struct iosapic_intr_info
{
134 struct list_head rtes
; /* RTEs using this vector (empty =>
135 * not an IOSAPIC interrupt) */
136 int count
; /* # of RTEs that shares this vector */
137 u32 low32
; /* current value of low word of
138 * Redirection table entry */
139 unsigned int dest
; /* destination CPU physical ID */
140 unsigned char dmode
: 3; /* delivery mode (see iosapic.h) */
141 unsigned char polarity
: 1; /* interrupt polarity
143 unsigned char trigger
: 1; /* trigger mode (see iosapic.h) */
144 } iosapic_intr_info
[IA64_NUM_VECTORS
];
146 static struct iosapic
{
147 char __iomem
*addr
; /* base address of IOSAPIC */
148 unsigned int gsi_base
; /* first GSI assigned to this
150 unsigned short num_rte
; /* # of RTEs on this IOSAPIC */
151 int rtes_inuse
; /* # of RTEs in use on this IOSAPIC */
153 unsigned short node
; /* numa node association via pxm */
155 } iosapic_lists
[NR_IOSAPICS
];
157 static unsigned char pcat_compat __devinitdata
; /* 8259 compatibility flag */
159 static int iosapic_kmalloc_ok
;
160 static LIST_HEAD(free_rte_list
);
163 * Find an IOSAPIC associated with a GSI
166 find_iosapic (unsigned int gsi
)
170 for (i
= 0; i
< NR_IOSAPICS
; i
++) {
171 if ((unsigned) (gsi
- iosapic_lists
[i
].gsi_base
) <
172 iosapic_lists
[i
].num_rte
)
180 _gsi_to_vector (unsigned int gsi
)
182 struct iosapic_intr_info
*info
;
183 struct iosapic_rte_info
*rte
;
185 for (info
= iosapic_intr_info
; info
<
186 iosapic_intr_info
+ IA64_NUM_VECTORS
; ++info
)
187 list_for_each_entry(rte
, &info
->rtes
, rte_list
)
188 if (rte
->gsi_base
+ rte
->rte_index
== gsi
)
189 return info
- iosapic_intr_info
;
194 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
195 * entry exists, return -1.
198 gsi_to_vector (unsigned int gsi
)
200 return _gsi_to_vector(gsi
);
204 gsi_to_irq (unsigned int gsi
)
209 * XXX fix me: this assumes an identity mapping between IA-64 vector
210 * and Linux irq numbers...
212 spin_lock_irqsave(&iosapic_lock
, flags
);
214 irq
= _gsi_to_vector(gsi
);
216 spin_unlock_irqrestore(&iosapic_lock
, flags
);
221 static struct iosapic_rte_info
*gsi_vector_to_rte(unsigned int gsi
,
224 struct iosapic_rte_info
*rte
;
226 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
)
227 if (rte
->gsi_base
+ rte
->rte_index
== gsi
)
233 set_rte (unsigned int gsi
, unsigned int vector
, unsigned int dest
, int mask
)
235 unsigned long pol
, trigger
, dmode
;
240 struct iosapic_rte_info
*rte
;
242 DBG(KERN_DEBUG
"IOSAPIC: routing vector %d to 0x%x\n", vector
, dest
);
244 rte
= gsi_vector_to_rte(gsi
, vector
);
246 return; /* not an IOSAPIC interrupt */
248 rte_index
= rte
->rte_index
;
250 pol
= iosapic_intr_info
[vector
].polarity
;
251 trigger
= iosapic_intr_info
[vector
].trigger
;
252 dmode
= iosapic_intr_info
[vector
].dmode
;
254 redir
= (dmode
== IOSAPIC_LOWEST_PRIORITY
) ? 1 : 0;
260 for (irq
= 0; irq
< NR_IRQS
; ++irq
)
261 if (irq_to_vector(irq
) == vector
) {
262 set_irq_affinity_info(irq
,
263 (int)(dest
& 0xffff),
270 low32
= ((pol
<< IOSAPIC_POLARITY_SHIFT
) |
271 (trigger
<< IOSAPIC_TRIGGER_SHIFT
) |
272 (dmode
<< IOSAPIC_DELIVERY_SHIFT
) |
273 ((mask
? 1 : 0) << IOSAPIC_MASK_SHIFT
) |
276 /* dest contains both id and eid */
277 high32
= (dest
<< IOSAPIC_DEST_SHIFT
);
279 iosapic_write(addr
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
280 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
281 iosapic_intr_info
[vector
].low32
= low32
;
282 iosapic_intr_info
[vector
].dest
= dest
;
286 nop (unsigned int irq
)
294 kexec_disable_iosapic(void)
296 struct iosapic_intr_info
*info
;
297 struct iosapic_rte_info
*rte
;
299 for (info
= iosapic_intr_info
; info
<
300 iosapic_intr_info
+ IA64_NUM_VECTORS
; ++info
, ++vec
) {
301 list_for_each_entry(rte
, &info
->rtes
,
303 iosapic_write(rte
->addr
,
304 IOSAPIC_RTE_LOW(rte
->rte_index
),
306 iosapic_eoi(rte
->addr
, vec
);
313 mask_irq (unsigned int irq
)
319 ia64_vector vec
= irq_to_vector(irq
);
320 struct iosapic_rte_info
*rte
;
322 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
323 return; /* not an IOSAPIC interrupt! */
325 spin_lock_irqsave(&iosapic_lock
, flags
);
327 /* set only the mask bit */
328 low32
= iosapic_intr_info
[vec
].low32
|= IOSAPIC_MASK
;
329 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
,
332 rte_index
= rte
->rte_index
;
333 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
336 spin_unlock_irqrestore(&iosapic_lock
, flags
);
340 unmask_irq (unsigned int irq
)
346 ia64_vector vec
= irq_to_vector(irq
);
347 struct iosapic_rte_info
*rte
;
349 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
350 return; /* not an IOSAPIC interrupt! */
352 spin_lock_irqsave(&iosapic_lock
, flags
);
354 low32
= iosapic_intr_info
[vec
].low32
&= ~IOSAPIC_MASK
;
355 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
,
358 rte_index
= rte
->rte_index
;
359 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
362 spin_unlock_irqrestore(&iosapic_lock
, flags
);
367 iosapic_set_affinity (unsigned int irq
, cpumask_t mask
)
374 int redir
= (irq
& IA64_IRQ_REDIRECTED
) ? 1 : 0;
376 struct iosapic_rte_info
*rte
;
378 irq
&= (~IA64_IRQ_REDIRECTED
);
379 vec
= irq_to_vector(irq
);
381 if (cpus_empty(mask
))
384 dest
= cpu_physical_id(first_cpu(mask
));
386 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
387 return; /* not an IOSAPIC interrupt */
389 set_irq_affinity_info(irq
, dest
, redir
);
391 /* dest contains both id and eid */
392 high32
= dest
<< IOSAPIC_DEST_SHIFT
;
394 spin_lock_irqsave(&iosapic_lock
, flags
);
396 low32
= iosapic_intr_info
[vec
].low32
&
397 ~(7 << IOSAPIC_DELIVERY_SHIFT
);
400 /* change delivery mode to lowest priority */
401 low32
|= (IOSAPIC_LOWEST_PRIORITY
<<
402 IOSAPIC_DELIVERY_SHIFT
);
404 /* change delivery mode to fixed */
405 low32
|= (IOSAPIC_FIXED
<< IOSAPIC_DELIVERY_SHIFT
);
407 iosapic_intr_info
[vec
].low32
= low32
;
408 iosapic_intr_info
[vec
].dest
= dest
;
409 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
,
412 rte_index
= rte
->rte_index
;
413 iosapic_write(addr
, IOSAPIC_RTE_HIGH(rte_index
),
415 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
418 spin_unlock_irqrestore(&iosapic_lock
, flags
);
423 * Handlers for level-triggered interrupts.
427 iosapic_startup_level_irq (unsigned int irq
)
434 iosapic_end_level_irq (unsigned int irq
)
436 ia64_vector vec
= irq_to_vector(irq
);
437 struct iosapic_rte_info
*rte
;
439 move_native_irq(irq
);
440 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
)
441 iosapic_eoi(rte
->addr
, vec
);
444 #define iosapic_shutdown_level_irq mask_irq
445 #define iosapic_enable_level_irq unmask_irq
446 #define iosapic_disable_level_irq mask_irq
447 #define iosapic_ack_level_irq nop
449 struct irq_chip irq_type_iosapic_level
= {
450 .name
= "IO-SAPIC-level",
451 .startup
= iosapic_startup_level_irq
,
452 .shutdown
= iosapic_shutdown_level_irq
,
453 .enable
= iosapic_enable_level_irq
,
454 .disable
= iosapic_disable_level_irq
,
455 .ack
= iosapic_ack_level_irq
,
456 .end
= iosapic_end_level_irq
,
458 .unmask
= unmask_irq
,
459 .set_affinity
= iosapic_set_affinity
463 * Handlers for edge-triggered interrupts.
467 iosapic_startup_edge_irq (unsigned int irq
)
471 * IOSAPIC simply drops interrupts pended while the
472 * corresponding pin was masked, so we can't know if an
473 * interrupt is pending already. Let's hope not...
479 iosapic_ack_edge_irq (unsigned int irq
)
481 irq_desc_t
*idesc
= irq_desc
+ irq
;
483 move_native_irq(irq
);
485 * Once we have recorded IRQ_PENDING already, we can mask the
486 * interrupt for real. This prevents IRQ storms from unhandled
489 if ((idesc
->status
& (IRQ_PENDING
|IRQ_DISABLED
)) ==
490 (IRQ_PENDING
|IRQ_DISABLED
))
494 #define iosapic_enable_edge_irq unmask_irq
495 #define iosapic_disable_edge_irq nop
496 #define iosapic_end_edge_irq nop
498 struct irq_chip irq_type_iosapic_edge
= {
499 .name
= "IO-SAPIC-edge",
500 .startup
= iosapic_startup_edge_irq
,
501 .shutdown
= iosapic_disable_edge_irq
,
502 .enable
= iosapic_enable_edge_irq
,
503 .disable
= iosapic_disable_edge_irq
,
504 .ack
= iosapic_ack_edge_irq
,
505 .end
= iosapic_end_edge_irq
,
507 .unmask
= unmask_irq
,
508 .set_affinity
= iosapic_set_affinity
512 iosapic_version (char __iomem
*addr
)
515 * IOSAPIC Version Register return 32 bit structure like:
517 * unsigned int version : 8;
518 * unsigned int reserved1 : 8;
519 * unsigned int max_redir : 8;
520 * unsigned int reserved2 : 8;
523 return iosapic_read(addr
, IOSAPIC_VERSION
);
526 static int iosapic_find_sharable_vector (unsigned long trigger
,
529 int i
, vector
= -1, min_count
= -1;
530 struct iosapic_intr_info
*info
;
533 * shared vectors for edge-triggered interrupts are not
536 if (trigger
== IOSAPIC_EDGE
)
539 for (i
= IA64_FIRST_DEVICE_VECTOR
; i
<= IA64_LAST_DEVICE_VECTOR
; i
++) {
540 info
= &iosapic_intr_info
[i
];
541 if (info
->trigger
== trigger
&& info
->polarity
== pol
&&
542 (info
->dmode
== IOSAPIC_FIXED
|| info
->dmode
==
543 IOSAPIC_LOWEST_PRIORITY
)) {
544 if (min_count
== -1 || info
->count
< min_count
) {
546 min_count
= info
->count
;
555 * if the given vector is already owned by other,
556 * assign a new vector for the other and make the vector available
559 iosapic_reassign_vector (int vector
)
563 if (!list_empty(&iosapic_intr_info
[vector
].rtes
)) {
564 new_vector
= assign_irq_vector(AUTO_ASSIGN
);
566 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
567 printk(KERN_INFO
"Reassigning vector %d to %d\n",
569 memcpy(&iosapic_intr_info
[new_vector
], &iosapic_intr_info
[vector
],
570 sizeof(struct iosapic_intr_info
));
571 INIT_LIST_HEAD(&iosapic_intr_info
[new_vector
].rtes
);
572 list_move(iosapic_intr_info
[vector
].rtes
.next
,
573 &iosapic_intr_info
[new_vector
].rtes
);
574 memset(&iosapic_intr_info
[vector
], 0,
575 sizeof(struct iosapic_intr_info
));
576 iosapic_intr_info
[vector
].low32
= IOSAPIC_MASK
;
577 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
581 static struct iosapic_rte_info
*iosapic_alloc_rte (void)
584 struct iosapic_rte_info
*rte
;
585 int preallocated
= 0;
587 if (!iosapic_kmalloc_ok
&& list_empty(&free_rte_list
)) {
588 rte
= alloc_bootmem(sizeof(struct iosapic_rte_info
) *
589 NR_PREALLOCATE_RTE_ENTRIES
);
592 for (i
= 0; i
< NR_PREALLOCATE_RTE_ENTRIES
; i
++, rte
++)
593 list_add(&rte
->rte_list
, &free_rte_list
);
596 if (!list_empty(&free_rte_list
)) {
597 rte
= list_entry(free_rte_list
.next
, struct iosapic_rte_info
,
599 list_del(&rte
->rte_list
);
602 rte
= kmalloc(sizeof(struct iosapic_rte_info
), GFP_ATOMIC
);
607 memset(rte
, 0, sizeof(struct iosapic_rte_info
));
609 rte
->flags
|= RTE_PREALLOCATED
;
614 static void iosapic_free_rte (struct iosapic_rte_info
*rte
)
616 if (rte
->flags
& RTE_PREALLOCATED
)
617 list_add_tail(&rte
->rte_list
, &free_rte_list
);
622 static inline int vector_is_shared (int vector
)
624 return (iosapic_intr_info
[vector
].count
> 1);
628 register_intr (unsigned int gsi
, int vector
, unsigned char delivery
,
629 unsigned long polarity
, unsigned long trigger
)
632 struct hw_interrupt_type
*irq_type
;
635 unsigned long gsi_base
;
636 void __iomem
*iosapic_address
;
637 struct iosapic_rte_info
*rte
;
639 index
= find_iosapic(gsi
);
641 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
646 iosapic_address
= iosapic_lists
[index
].addr
;
647 gsi_base
= iosapic_lists
[index
].gsi_base
;
649 rte
= gsi_vector_to_rte(gsi
, vector
);
651 rte
= iosapic_alloc_rte();
653 printk(KERN_WARNING
"%s: cannot allocate memory\n",
658 rte_index
= gsi
- gsi_base
;
659 rte
->rte_index
= rte_index
;
660 rte
->addr
= iosapic_address
;
661 rte
->gsi_base
= gsi_base
;
663 list_add_tail(&rte
->rte_list
, &iosapic_intr_info
[vector
].rtes
);
664 iosapic_intr_info
[vector
].count
++;
665 iosapic_lists
[index
].rtes_inuse
++;
667 else if (vector_is_shared(vector
)) {
668 struct iosapic_intr_info
*info
= &iosapic_intr_info
[vector
];
669 if (info
->trigger
!= trigger
|| info
->polarity
!= polarity
) {
671 "%s: cannot override the interrupt\n",
677 iosapic_intr_info
[vector
].polarity
= polarity
;
678 iosapic_intr_info
[vector
].dmode
= delivery
;
679 iosapic_intr_info
[vector
].trigger
= trigger
;
681 if (trigger
== IOSAPIC_EDGE
)
682 irq_type
= &irq_type_iosapic_edge
;
684 irq_type
= &irq_type_iosapic_level
;
686 idesc
= irq_desc
+ vector
;
687 if (idesc
->chip
!= irq_type
) {
688 if (idesc
->chip
!= &no_irq_type
)
690 "%s: changing vector %d from %s to %s\n",
691 __FUNCTION__
, vector
,
692 idesc
->chip
->name
, irq_type
->name
);
693 idesc
->chip
= irq_type
;
699 get_target_cpu (unsigned int gsi
, int vector
)
703 extern int cpe_vector
;
706 * In case of vector shared by multiple RTEs, all RTEs that
707 * share the vector need to use the same destination CPU.
709 if (!list_empty(&iosapic_intr_info
[vector
].rtes
))
710 return iosapic_intr_info
[vector
].dest
;
713 * If the platform supports redirection via XTP, let it
714 * distribute interrupts.
716 if (smp_int_redirect
& SMP_IRQ_REDIRECTION
)
717 return cpu_physical_id(smp_processor_id());
720 * Some interrupts (ACPI SCI, for instance) are registered
721 * before the BSP is marked as online.
723 if (!cpu_online(smp_processor_id()))
724 return cpu_physical_id(smp_processor_id());
727 if (cpe_vector
> 0 && vector
== IA64_CPEP_VECTOR
)
728 return get_cpei_target_cpu();
733 int num_cpus
, cpu_index
, iosapic_index
, numa_cpu
, i
= 0;
736 iosapic_index
= find_iosapic(gsi
);
737 if (iosapic_index
< 0 ||
738 iosapic_lists
[iosapic_index
].node
== MAX_NUMNODES
)
739 goto skip_numa_setup
;
741 cpu_mask
= node_to_cpumask(iosapic_lists
[iosapic_index
].node
);
743 for_each_cpu_mask(numa_cpu
, cpu_mask
) {
744 if (!cpu_online(numa_cpu
))
745 cpu_clear(numa_cpu
, cpu_mask
);
748 num_cpus
= cpus_weight(cpu_mask
);
751 goto skip_numa_setup
;
753 /* Use vector assignment to distribute across cpus in node */
754 cpu_index
= vector
% num_cpus
;
756 for (numa_cpu
= first_cpu(cpu_mask
) ; i
< cpu_index
; i
++)
757 numa_cpu
= next_cpu(numa_cpu
, cpu_mask
);
759 if (numa_cpu
!= NR_CPUS
)
760 return cpu_physical_id(numa_cpu
);
765 * Otherwise, round-robin interrupt vectors across all the
766 * processors. (It'd be nice if we could be smarter in the
770 if (++cpu
>= NR_CPUS
)
772 } while (!cpu_online(cpu
));
774 return cpu_physical_id(cpu
);
775 #else /* CONFIG_SMP */
776 return cpu_physical_id(smp_processor_id());
781 * ACPI can describe IOSAPIC interrupts via static tables and namespace
782 * methods. This provides an interface to register those interrupts and
783 * program the IOSAPIC RTE.
786 iosapic_register_intr (unsigned int gsi
,
787 unsigned long polarity
, unsigned long trigger
)
789 int vector
, mask
= 1, err
;
792 struct iosapic_rte_info
*rte
;
796 * If this GSI has already been registered (i.e., it's a
797 * shared interrupt, or we lost a race to register it),
798 * don't touch the RTE.
800 spin_lock_irqsave(&iosapic_lock
, flags
);
802 vector
= gsi_to_vector(gsi
);
804 rte
= gsi_vector_to_rte(gsi
, vector
);
806 spin_unlock_irqrestore(&iosapic_lock
, flags
);
810 spin_unlock_irqrestore(&iosapic_lock
, flags
);
812 /* If vector is running out, we try to find a sharable vector */
813 vector
= assign_irq_vector(AUTO_ASSIGN
);
815 vector
= iosapic_find_sharable_vector(trigger
, polarity
);
820 spin_lock_irqsave(&irq_desc
[vector
].lock
, flags
);
821 spin_lock(&iosapic_lock
);
823 if (gsi_to_vector(gsi
) > 0) {
824 if (list_empty(&iosapic_intr_info
[vector
].rtes
))
825 free_irq_vector(vector
);
826 spin_unlock(&iosapic_lock
);
827 spin_unlock_irqrestore(&irq_desc
[vector
].lock
,
832 dest
= get_target_cpu(gsi
, vector
);
833 err
= register_intr(gsi
, vector
, IOSAPIC_LOWEST_PRIORITY
,
836 spin_unlock(&iosapic_lock
);
837 spin_unlock_irqrestore(&irq_desc
[vector
].lock
,
843 * If the vector is shared and already unmasked for
844 * other interrupt sources, don't mask it.
846 low32
= iosapic_intr_info
[vector
].low32
;
847 if (vector_is_shared(vector
) && !(low32
& IOSAPIC_MASK
))
849 set_rte(gsi
, vector
, dest
, mask
);
851 spin_unlock(&iosapic_lock
);
852 spin_unlock_irqrestore(&irq_desc
[vector
].lock
, flags
);
854 printk(KERN_INFO
"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
855 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
856 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
857 cpu_logical_id(dest
), dest
, vector
);
863 iosapic_unregister_intr (unsigned int gsi
)
866 int irq
, vector
, index
;
869 unsigned long trigger
, polarity
;
871 struct iosapic_rte_info
*rte
;
874 * If the irq associated with the gsi is not found,
875 * iosapic_unregister_intr() is unbalanced. We need to check
876 * this again after getting locks.
878 irq
= gsi_to_irq(gsi
);
880 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n",
885 vector
= irq_to_vector(irq
);
887 idesc
= irq_desc
+ irq
;
888 spin_lock_irqsave(&idesc
->lock
, flags
);
889 spin_lock(&iosapic_lock
);
891 if ((rte
= gsi_vector_to_rte(gsi
, vector
)) == NULL
) {
893 "iosapic_unregister_intr(%u) unbalanced\n",
899 if (--rte
->refcnt
> 0)
902 /* Mask the interrupt */
903 low32
= iosapic_intr_info
[vector
].low32
| IOSAPIC_MASK
;
904 iosapic_write(rte
->addr
, IOSAPIC_RTE_LOW(rte
->rte_index
),
907 /* Remove the rte entry from the list */
908 list_del(&rte
->rte_list
);
909 iosapic_intr_info
[vector
].count
--;
910 iosapic_free_rte(rte
);
911 index
= find_iosapic(gsi
);
912 iosapic_lists
[index
].rtes_inuse
--;
913 WARN_ON(iosapic_lists
[index
].rtes_inuse
< 0);
915 trigger
= iosapic_intr_info
[vector
].trigger
;
916 polarity
= iosapic_intr_info
[vector
].polarity
;
917 dest
= iosapic_intr_info
[vector
].dest
;
919 "GSI %u (%s, %s) -> CPU %d (0x%04x)"
920 " vector %d unregistered\n",
921 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
922 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
923 cpu_logical_id(dest
), dest
, vector
);
925 if (list_empty(&iosapic_intr_info
[vector
].rtes
)) {
927 BUG_ON(iosapic_intr_info
[vector
].count
);
929 /* Clear the interrupt controller descriptor */
930 idesc
->chip
= &no_irq_type
;
934 cpus_setall(idesc
->affinity
);
937 /* Clear the interrupt information */
938 memset(&iosapic_intr_info
[vector
], 0,
939 sizeof(struct iosapic_intr_info
));
940 iosapic_intr_info
[vector
].low32
|= IOSAPIC_MASK
;
941 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
945 "interrupt handlers still exist on"
950 /* Free the interrupt vector */
951 free_irq_vector(vector
);
955 spin_unlock(&iosapic_lock
);
956 spin_unlock_irqrestore(&idesc
->lock
, flags
);
960 * ACPI calls this when it finds an entry for a platform interrupt.
963 iosapic_register_platform_intr (u32 int_type
, unsigned int gsi
,
964 int iosapic_vector
, u16 eid
, u16 id
,
965 unsigned long polarity
, unsigned long trigger
)
967 static const char * const name
[] = {"unknown", "PMI", "INIT", "CPEI"};
968 unsigned char delivery
;
969 int vector
, mask
= 0;
970 unsigned int dest
= ((id
<< 8) | eid
) & 0xffff;
973 case ACPI_INTERRUPT_PMI
:
974 vector
= iosapic_vector
;
976 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
977 * we need to make sure the vector is available
979 iosapic_reassign_vector(vector
);
980 delivery
= IOSAPIC_PMI
;
982 case ACPI_INTERRUPT_INIT
:
983 vector
= assign_irq_vector(AUTO_ASSIGN
);
985 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
986 delivery
= IOSAPIC_INIT
;
988 case ACPI_INTERRUPT_CPEI
:
989 vector
= IA64_CPE_VECTOR
;
990 delivery
= IOSAPIC_LOWEST_PRIORITY
;
994 printk(KERN_ERR
"%s: invalid int type 0x%x\n", __FUNCTION__
,
999 register_intr(gsi
, vector
, delivery
, polarity
, trigger
);
1002 "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
1004 int_type
< ARRAY_SIZE(name
) ? name
[int_type
] : "unknown",
1005 int_type
, gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
1006 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
1007 cpu_logical_id(dest
), dest
, vector
);
1009 set_rte(gsi
, vector
, dest
, mask
);
1014 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
1017 iosapic_override_isa_irq (unsigned int isa_irq
, unsigned int gsi
,
1018 unsigned long polarity
,
1019 unsigned long trigger
)
1022 unsigned int dest
= cpu_physical_id(smp_processor_id());
1024 vector
= isa_irq_to_vector(isa_irq
);
1026 register_intr(gsi
, vector
, IOSAPIC_LOWEST_PRIORITY
, polarity
, trigger
);
1028 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
1029 isa_irq
, gsi
, trigger
== IOSAPIC_EDGE
? "edge" : "level",
1030 polarity
== IOSAPIC_POL_HIGH
? "high" : "low",
1031 cpu_logical_id(dest
), dest
, vector
);
1033 set_rte(gsi
, vector
, dest
, 1);
1037 iosapic_system_init (int system_pcat_compat
)
1041 for (vector
= 0; vector
< IA64_NUM_VECTORS
; ++vector
) {
1042 iosapic_intr_info
[vector
].low32
= IOSAPIC_MASK
;
1043 /* mark as unused */
1044 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
1047 pcat_compat
= system_pcat_compat
;
1050 * Disable the compatibility mode interrupts (8259 style),
1051 * needs IN/OUT support enabled.
1054 "%s: Disabling PC-AT compatible 8259 interrupts\n",
1062 iosapic_alloc (void)
1066 for (index
= 0; index
< NR_IOSAPICS
; index
++)
1067 if (!iosapic_lists
[index
].addr
)
1070 printk(KERN_WARNING
"%s: failed to allocate iosapic\n", __FUNCTION__
);
1075 iosapic_free (int index
)
1077 memset(&iosapic_lists
[index
], 0, sizeof(iosapic_lists
[0]));
1081 iosapic_check_gsi_range (unsigned int gsi_base
, unsigned int ver
)
1084 unsigned int gsi_end
, base
, end
;
1086 /* check gsi range */
1087 gsi_end
= gsi_base
+ ((ver
>> 16) & 0xff);
1088 for (index
= 0; index
< NR_IOSAPICS
; index
++) {
1089 if (!iosapic_lists
[index
].addr
)
1092 base
= iosapic_lists
[index
].gsi_base
;
1093 end
= base
+ iosapic_lists
[index
].num_rte
- 1;
1095 if (gsi_end
< base
|| end
< gsi_base
)
1104 iosapic_init (unsigned long phys_addr
, unsigned int gsi_base
)
1106 int num_rte
, err
, index
;
1107 unsigned int isa_irq
, ver
;
1109 unsigned long flags
;
1111 spin_lock_irqsave(&iosapic_lock
, flags
);
1113 addr
= ioremap(phys_addr
, 0);
1114 ver
= iosapic_version(addr
);
1116 if ((err
= iosapic_check_gsi_range(gsi_base
, ver
))) {
1118 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1123 * The MAX_REDIR register holds the highest input pin
1124 * number (starting from 0).
1125 * We add 1 so that we can use it for number of pins (= RTEs)
1127 num_rte
= ((ver
>> 16) & 0xff) + 1;
1129 index
= iosapic_alloc();
1130 iosapic_lists
[index
].addr
= addr
;
1131 iosapic_lists
[index
].gsi_base
= gsi_base
;
1132 iosapic_lists
[index
].num_rte
= num_rte
;
1134 iosapic_lists
[index
].node
= MAX_NUMNODES
;
1137 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1139 if ((gsi_base
== 0) && pcat_compat
) {
1141 * Map the legacy ISA devices into the IOSAPIC data. Some of
1142 * these may get reprogrammed later on with data from the ACPI
1143 * Interrupt Source Override table.
1145 for (isa_irq
= 0; isa_irq
< 16; ++isa_irq
)
1146 iosapic_override_isa_irq(isa_irq
, isa_irq
,
1153 #ifdef CONFIG_HOTPLUG
1155 iosapic_remove (unsigned int gsi_base
)
1158 unsigned long flags
;
1160 spin_lock_irqsave(&iosapic_lock
, flags
);
1162 index
= find_iosapic(gsi_base
);
1164 printk(KERN_WARNING
"%s: No IOSAPIC for GSI base %u\n",
1165 __FUNCTION__
, gsi_base
);
1169 if (iosapic_lists
[index
].rtes_inuse
) {
1172 "%s: IOSAPIC for GSI base %u is busy\n",
1173 __FUNCTION__
, gsi_base
);
1177 iounmap(iosapic_lists
[index
].addr
);
1178 iosapic_free(index
);
1181 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1184 #endif /* CONFIG_HOTPLUG */
1188 map_iosapic_to_node(unsigned int gsi_base
, int node
)
1192 index
= find_iosapic(gsi_base
);
1194 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
1195 __FUNCTION__
, gsi_base
);
1198 iosapic_lists
[index
].node
= node
;
1203 static int __init
iosapic_enable_kmalloc (void)
1205 iosapic_kmalloc_ok
= 1;
1208 core_initcall (iosapic_enable_kmalloc
);