| blob | 112ac90f2ea7bc18cbcf92799581a0001f21ee6f |
1 /*
2 * TQM8548 Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
13 /dts-v1/;
15 / {
16 model = "tqc,tqm8548";
17 compatible = "tqc,tqm8548";
18 #address-cells = <1>;
19 #size-cells = <1>;
21 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
37 PowerPC,8548@0 {
38 device_type = "cpu";
39 reg = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
45 };
46 };
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 };
53 soc@e0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>;
60 compatible = "fsl,mpc8548-immr", "simple-bus";
62 memory-controller@2000 {
63 compatible = "fsl,mpc8548-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>;
66 interrupts = <18 2>;
67 };
69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,mpc8548-l2-cache-controller";
71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; // 32 bytes
73 cache-size = <0x80000>; // L2, 512K
74 interrupt-parent = <&mpic>;
75 interrupts = <16 2>;
76 };
78 i2c@3000 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 cell-index = <0>;
82 compatible = "fsl-i2c";
83 reg = <0x3000 0x100>;
84 interrupts = <43 2>;
85 interrupt-parent = <&mpic>;
86 dfsrr;
88 dtt@50 {
89 compatible = "national,lm75";
90 reg = <0x50>;
91 };
93 rtc@68 {
94 compatible = "dallas,ds1337";
95 reg = <0x68>;
96 };
97 };
99 i2c@3100 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 cell-index = <1>;
103 compatible = "fsl-i2c";
104 reg = <0x3100 0x100>;
105 interrupts = <43 2>;
106 interrupt-parent = <&mpic>;
107 dfsrr;
108 };
110 dma@21300 {
111 #address-cells = <1>;
112 #size-cells = <1>;
113 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
114 reg = <0x21300 0x4>;
115 ranges = <0x0 0x21100 0x200>;
116 cell-index = <0>;
117 dma-channel@0 {
118 compatible = "fsl,mpc8548-dma-channel",
119 "fsl,eloplus-dma-channel";
120 reg = <0x0 0x80>;
121 cell-index = <0>;
122 interrupt-parent = <&mpic>;
123 interrupts = <20 2>;
124 };
125 dma-channel@80 {
126 compatible = "fsl,mpc8548-dma-channel",
127 "fsl,eloplus-dma-channel";
128 reg = <0x80 0x80>;
129 cell-index = <1>;
130 interrupt-parent = <&mpic>;
131 interrupts = <21 2>;
132 };
133 dma-channel@100 {
134 compatible = "fsl,mpc8548-dma-channel",
135 "fsl,eloplus-dma-channel";
136 reg = <0x100 0x80>;
137 cell-index = <2>;
138 interrupt-parent = <&mpic>;
139 interrupts = <22 2>;
140 };
141 dma-channel@180 {
142 compatible = "fsl,mpc8548-dma-channel",
143 "fsl,eloplus-dma-channel";
144 reg = <0x180 0x80>;
145 cell-index = <3>;
146 interrupt-parent = <&mpic>;
147 interrupts = <23 2>;
148 };
149 };
151 mdio@24520 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 compatible = "fsl,gianfar-mdio";
155 reg = <0x24520 0x20>;
157 phy1: ethernet-phy@0 {
158 interrupt-parent = <&mpic>;
159 interrupts = <8 1>;
160 reg = <1>;
161 device_type = "ethernet-phy";
162 };
163 phy2: ethernet-phy@1 {
164 interrupt-parent = <&mpic>;
165 interrupts = <8 1>;
166 reg = <2>;
167 device_type = "ethernet-phy";
168 };
169 phy3: ethernet-phy@3 {
170 interrupt-parent = <&mpic>;
171 interrupts = <8 1>;
172 reg = <3>;
173 device_type = "ethernet-phy";
174 };
175 phy4: ethernet-phy@4 {
176 interrupt-parent = <&mpic>;
177 interrupts = <8 1>;
178 reg = <4>;
179 device_type = "ethernet-phy";
180 };
181 phy5: ethernet-phy@5 {
182 interrupt-parent = <&mpic>;
183 interrupts = <8 1>;
184 reg = <5>;
185 device_type = "ethernet-phy";
186 };
187 tbi0: tbi-phy@11 {
188 reg = <0x11>;
189 device_type = "tbi-phy";
190 };
191 };
193 mdio@25520 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,gianfar-tbi";
197 reg = <0x25520 0x20>;
199 tbi1: tbi-phy@11 {
200 reg = <0x11>;
201 device_type = "tbi-phy";
202 };
203 };
205 mdio@26520 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "fsl,gianfar-tbi";
209 reg = <0x26520 0x20>;
211 tbi2: tbi-phy@11 {
212 reg = <0x11>;
213 device_type = "tbi-phy";
214 };
215 };
217 mdio@27520 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl,gianfar-tbi";
221 reg = <0x27520 0x20>;
223 tbi3: tbi-phy@11 {
224 reg = <0x11>;
225 device_type = "tbi-phy";
226 };
227 };
229 enet0: ethernet@24000 {
230 cell-index = <0>;
231 device_type = "network";
232 model = "eTSEC";
233 compatible = "gianfar";
234 reg = <0x24000 0x1000>;
235 local-mac-address = [ 00 00 00 00 00 00 ];
236 interrupts = <29 2 30 2 34 2>;
237 interrupt-parent = <&mpic>;
238 tbi-handle = <&tbi0>;
239 phy-handle = <&phy2>;
240 };
242 enet1: ethernet@25000 {
243 cell-index = <1>;
244 device_type = "network";
245 model = "eTSEC";
246 compatible = "gianfar";
247 reg = <0x25000 0x1000>;
248 local-mac-address = [ 00 00 00 00 00 00 ];
249 interrupts = <35 2 36 2 40 2>;
250 interrupt-parent = <&mpic>;
251 tbi-handle = <&tbi1>;
252 phy-handle = <&phy1>;
253 };
255 enet2: ethernet@26000 {
256 cell-index = <2>;
257 device_type = "network";
258 model = "eTSEC";
259 compatible = "gianfar";
260 reg = <0x26000 0x1000>;
261 local-mac-address = [ 00 00 00 00 00 00 ];
262 interrupts = <31 2 32 2 33 2>;
263 interrupt-parent = <&mpic>;
264 tbi-handle = <&tbi2>;
265 phy-handle = <&phy3>;
266 };
268 enet3: ethernet@27000 {
269 cell-index = <3>;
270 device_type = "network";
271 model = "eTSEC";
272 compatible = "gianfar";
273 reg = <0x27000 0x1000>;
274 local-mac-address = [ 00 00 00 00 00 00 ];
275 interrupts = <37 2 38 2 39 2>;
276 interrupt-parent = <&mpic>;
277 tbi-handle = <&tbi3>;
278 phy-handle = <&phy4>;
279 };
281 serial0: serial@4500 {
282 cell-index = <0>;
283 device_type = "serial";
284 compatible = "ns16550";
285 reg = <0x4500 0x100>; // reg base, size
286 clock-frequency = <0>; // should we fill in in uboot?
287 current-speed = <115200>;
288 interrupts = <42 2>;
289 interrupt-parent = <&mpic>;
290 };
292 serial1: serial@4600 {
293 cell-index = <1>;
294 device_type = "serial";
295 compatible = "ns16550";
296 reg = <0x4600 0x100>; // reg base, size
297 clock-frequency = <0>; // should we fill in in uboot?
298 current-speed = <115200>;
299 interrupts = <42 2>;
300 interrupt-parent = <&mpic>;
301 };
303 global-utilities@e0000 { // global utilities reg
304 compatible = "fsl,mpc8548-guts";
305 reg = <0xe0000 0x1000>;
306 fsl,has-rstcr;
307 };
309 mpic: pic@40000 {
310 interrupt-controller;
311 #address-cells = <0>;
312 #interrupt-cells = <2>;
313 reg = <0x40000 0x40000>;
314 compatible = "chrp,open-pic";
315 device_type = "open-pic";
316 };
317 };
319 localbus@e0005000 {
320 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
321 "simple-bus";
322 #address-cells = <2>;
323 #size-cells = <1>;
324 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
326 ranges = <
327 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
328 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
329 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
330 3 0x0 0xe3010000 0x00008000 // NAND FLASH
332 >;
334 flash@1,0 {
335 #address-cells = <1>;
336 #size-cells = <1>;
337 compatible = "cfi-flash";
338 reg = <1 0x0 0x8000000>;
339 bank-width = <4>;
340 device-width = <1>;
342 partition@0 {
343 label = "kernel";
344 reg = <0x00000000 0x00200000>;
345 };
346 partition@200000 {
347 label = "root";
348 reg = <0x00200000 0x00300000>;
349 };
350 partition@500000 {
351 label = "user";
352 reg = <0x00500000 0x07a00000>;
353 };
354 partition@7f00000 {
355 label = "env1";
356 reg = <0x07f00000 0x00040000>;
357 };
358 partition@7f40000 {
359 label = "env2";
360 reg = <0x07f40000 0x00040000>;
361 };
362 partition@7f80000 {
363 label = "u-boot";
364 reg = <0x07f80000 0x00080000>;
365 read-only;
366 };
367 };
369 /* Note: CAN support needs be enabled in U-Boot */
370 can0@2,0 {
371 compatible = "intel,82527"; // Bosch CC770
372 reg = <2 0x0 0x100>;
373 interrupts = <4 1>;
374 interrupt-parent = <&mpic>;
375 };
377 can1@2,100 {
378 compatible = "intel,82527"; // Bosch CC770
379 reg = <2 0x100 0x100>;
380 interrupts = <4 1>;
381 interrupt-parent = <&mpic>;
382 };
384 /* Note: NAND support needs to be enabled in U-Boot */
385 upm@3,0 {
386 #address-cells = <0>;
387 #size-cells = <0>;
388 compatible = "fsl,upm-nand";
389 reg = <3 0x0 0x800>;
390 fsl,upm-addr-offset = <0x10>;
391 fsl,upm-cmd-offset = <0x08>;
392 chip-delay = <25>; // in micro-seconds
394 nand@0 {
395 #address-cells = <1>;
396 #size-cells = <1>;
398 partition@0 {
399 label = "fs";
400 reg = <0x00000000 0x01000000>;
401 };
402 };
403 };
404 };
406 pci0: pci@e0008000 {
407 cell-index = <0>;
408 #interrupt-cells = <1>;
409 #size-cells = <2>;
410 #address-cells = <3>;
411 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
412 device_type = "pci";
413 reg = <0xe0008000 0x1000>;
414 clock-frequency = <33333333>;
415 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
416 interrupt-map = <
417 /* IDSEL 28 */
418 0xe000 0 0 1 &mpic 2 1
419 0xe000 0 0 2 &mpic 3 1>;
421 interrupt-parent = <&mpic>;
422 interrupts = <24 2>;
423 bus-range = <0 0>;
424 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
425 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
426 };
428 pci1: pcie@e000a000 {
429 cell-index = <2>;
430 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
431 interrupt-map = <
432 /* IDSEL 0x0 (PEX) */
433 0x00000 0 0 1 &mpic 0 1
434 0x00000 0 0 2 &mpic 1 1
435 0x00000 0 0 3 &mpic 2 1
436 0x00000 0 0 4 &mpic 3 1>;
438 interrupt-parent = <&mpic>;
439 interrupts = <26 2>;
440 bus-range = <0 0xff>;
441 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
442 0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
443 clock-frequency = <33333333>;
444 #interrupt-cells = <1>;
445 #size-cells = <2>;
446 #address-cells = <3>;
447 reg = <0xe000a000 0x1000>;
448 compatible = "fsl,mpc8548-pcie";
449 device_type = "pci";
450 pcie@0 {
451 reg = <0 0 0 0 0>;
452 #size-cells = <2>;
453 #address-cells = <3>;
454 device_type = "pci";
455 ranges = <0x02000000 0 0xc0000000 0x02000000 0
456 0xc0000000 0 0x20000000
457 0x01000000 0 0x00000000 0x01000000 0
458 0x00000000 0 0x08000000>;
459 };
460 };
461 };