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drm/i915: Allow LVDS on pipe A on gen4+
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blobeb4a265861ec0bb8f9c6e816eb1d44380c3228af
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include "drmP.h"
32 #include "intel_drv.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "drm_dp_helper.h"
36
37 #include "drm_crtc_helper.h"
38
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
40
41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
42 static void intel_update_watermarks(struct drm_device *dev);
43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
44
45 typedef struct {
46 /* given values */
47 int n;
48 int m1, m2;
49 int p1, p2;
50 /* derived values */
51 int dot;
52 int vco;
53 int m;
54 int p;
55 } intel_clock_t;
56
57 typedef struct {
58 int min, max;
59 } intel_range_t;
60
61 typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64 } intel_p2_t;
65
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t;
68 struct intel_limit {
69 intel_range_t dot, vco, n, m, m1, m2, p, p1;
70 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
73 };
74
75 #define I8XX_DOT_MIN 25000
76 #define I8XX_DOT_MAX 350000
77 #define I8XX_VCO_MIN 930000
78 #define I8XX_VCO_MAX 1400000
79 #define I8XX_N_MIN 3
80 #define I8XX_N_MAX 16
81 #define I8XX_M_MIN 96
82 #define I8XX_M_MAX 140
83 #define I8XX_M1_MIN 18
84 #define I8XX_M1_MAX 26
85 #define I8XX_M2_MIN 6
86 #define I8XX_M2_MAX 16
87 #define I8XX_P_MIN 4
88 #define I8XX_P_MAX 128
89 #define I8XX_P1_MIN 2
90 #define I8XX_P1_MAX 33
91 #define I8XX_P1_LVDS_MIN 1
92 #define I8XX_P1_LVDS_MAX 6
93 #define I8XX_P2_SLOW 4
94 #define I8XX_P2_FAST 2
95 #define I8XX_P2_LVDS_SLOW 14
96 #define I8XX_P2_LVDS_FAST 7
97 #define I8XX_P2_SLOW_LIMIT 165000
98
99 #define I9XX_DOT_MIN 20000
100 #define I9XX_DOT_MAX 400000
101 #define I9XX_VCO_MIN 1400000
102 #define I9XX_VCO_MAX 2800000
103 #define PINEVIEW_VCO_MIN 1700000
104 #define PINEVIEW_VCO_MAX 3500000
105 #define I9XX_N_MIN 1
106 #define I9XX_N_MAX 6
107 /* Pineview's Ncounter is a ring counter */
108 #define PINEVIEW_N_MIN 3
109 #define PINEVIEW_N_MAX 6
110 #define I9XX_M_MIN 70
111 #define I9XX_M_MAX 120
112 #define PINEVIEW_M_MIN 2
113 #define PINEVIEW_M_MAX 256
114 #define I9XX_M1_MIN 10
115 #define I9XX_M1_MAX 22
116 #define I9XX_M2_MIN 5
117 #define I9XX_M2_MAX 9
118 /* Pineview M1 is reserved, and must be 0 */
119 #define PINEVIEW_M1_MIN 0
120 #define PINEVIEW_M1_MAX 0
121 #define PINEVIEW_M2_MIN 0
122 #define PINEVIEW_M2_MAX 254
123 #define I9XX_P_SDVO_DAC_MIN 5
124 #define I9XX_P_SDVO_DAC_MAX 80
125 #define I9XX_P_LVDS_MIN 7
126 #define I9XX_P_LVDS_MAX 98
127 #define PINEVIEW_P_LVDS_MIN 7
128 #define PINEVIEW_P_LVDS_MAX 112
129 #define I9XX_P1_MIN 1
130 #define I9XX_P1_MAX 8
131 #define I9XX_P2_SDVO_DAC_SLOW 10
132 #define I9XX_P2_SDVO_DAC_FAST 5
133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
134 #define I9XX_P2_LVDS_SLOW 14
135 #define I9XX_P2_LVDS_FAST 7
136 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
137
138 /*The parameter is for SDVO on G4x platform*/
139 #define G4X_DOT_SDVO_MIN 25000
140 #define G4X_DOT_SDVO_MAX 270000
141 #define G4X_VCO_MIN 1750000
142 #define G4X_VCO_MAX 3500000
143 #define G4X_N_SDVO_MIN 1
144 #define G4X_N_SDVO_MAX 4
145 #define G4X_M_SDVO_MIN 104
146 #define G4X_M_SDVO_MAX 138
147 #define G4X_M1_SDVO_MIN 17
148 #define G4X_M1_SDVO_MAX 23
149 #define G4X_M2_SDVO_MIN 5
150 #define G4X_M2_SDVO_MAX 11
151 #define G4X_P_SDVO_MIN 10
152 #define G4X_P_SDVO_MAX 30
153 #define G4X_P1_SDVO_MIN 1
154 #define G4X_P1_SDVO_MAX 3
155 #define G4X_P2_SDVO_SLOW 10
156 #define G4X_P2_SDVO_FAST 10
157 #define G4X_P2_SDVO_LIMIT 270000
158
159 /*The parameter is for HDMI_DAC on G4x platform*/
160 #define G4X_DOT_HDMI_DAC_MIN 22000
161 #define G4X_DOT_HDMI_DAC_MAX 400000
162 #define G4X_N_HDMI_DAC_MIN 1
163 #define G4X_N_HDMI_DAC_MAX 4
164 #define G4X_M_HDMI_DAC_MIN 104
165 #define G4X_M_HDMI_DAC_MAX 138
166 #define G4X_M1_HDMI_DAC_MIN 16
167 #define G4X_M1_HDMI_DAC_MAX 23
168 #define G4X_M2_HDMI_DAC_MIN 5
169 #define G4X_M2_HDMI_DAC_MAX 11
170 #define G4X_P_HDMI_DAC_MIN 5
171 #define G4X_P_HDMI_DAC_MAX 80
172 #define G4X_P1_HDMI_DAC_MIN 1
173 #define G4X_P1_HDMI_DAC_MAX 8
174 #define G4X_P2_HDMI_DAC_SLOW 10
175 #define G4X_P2_HDMI_DAC_FAST 5
176 #define G4X_P2_HDMI_DAC_LIMIT 165000
177
178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
196
197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
215
216 /*The parameter is for DISPLAY PORT on G4x platform*/
217 #define G4X_DOT_DISPLAY_PORT_MIN 161670
218 #define G4X_DOT_DISPLAY_PORT_MAX 227000
219 #define G4X_N_DISPLAY_PORT_MIN 1
220 #define G4X_N_DISPLAY_PORT_MAX 2
221 #define G4X_M_DISPLAY_PORT_MIN 97
222 #define G4X_M_DISPLAY_PORT_MAX 108
223 #define G4X_M1_DISPLAY_PORT_MIN 0x10
224 #define G4X_M1_DISPLAY_PORT_MAX 0x12
225 #define G4X_M2_DISPLAY_PORT_MIN 0x05
226 #define G4X_M2_DISPLAY_PORT_MAX 0x06
227 #define G4X_P_DISPLAY_PORT_MIN 10
228 #define G4X_P_DISPLAY_PORT_MAX 20
229 #define G4X_P1_DISPLAY_PORT_MIN 1
230 #define G4X_P1_DISPLAY_PORT_MAX 2
231 #define G4X_P2_DISPLAY_PORT_SLOW 10
232 #define G4X_P2_DISPLAY_PORT_FAST 10
233 #define G4X_P2_DISPLAY_PORT_LIMIT 0
234
235 /* Ironlake / Sandybridge */
236 /* as we calculate clock using (register_value + 2) for
237 N/M1/M2, so here the range value for them is (actual_value-2).
238 */
239 #define IRONLAKE_DOT_MIN 25000
240 #define IRONLAKE_DOT_MAX 350000
241 #define IRONLAKE_VCO_MIN 1760000
242 #define IRONLAKE_VCO_MAX 3510000
243 #define IRONLAKE_M1_MIN 12
244 #define IRONLAKE_M1_MAX 22
245 #define IRONLAKE_M2_MIN 5
246 #define IRONLAKE_M2_MAX 9
247 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
248
249 /* We have parameter ranges for different type of outputs. */
250
251 /* DAC & HDMI Refclk 120Mhz */
252 #define IRONLAKE_DAC_N_MIN 1
253 #define IRONLAKE_DAC_N_MAX 5
254 #define IRONLAKE_DAC_M_MIN 79
255 #define IRONLAKE_DAC_M_MAX 127
256 #define IRONLAKE_DAC_P_MIN 5
257 #define IRONLAKE_DAC_P_MAX 80
258 #define IRONLAKE_DAC_P1_MIN 1
259 #define IRONLAKE_DAC_P1_MAX 8
260 #define IRONLAKE_DAC_P2_SLOW 10
261 #define IRONLAKE_DAC_P2_FAST 5
262
263 /* LVDS single-channel 120Mhz refclk */
264 #define IRONLAKE_LVDS_S_N_MIN 1
265 #define IRONLAKE_LVDS_S_N_MAX 3
266 #define IRONLAKE_LVDS_S_M_MIN 79
267 #define IRONLAKE_LVDS_S_M_MAX 118
268 #define IRONLAKE_LVDS_S_P_MIN 28
269 #define IRONLAKE_LVDS_S_P_MAX 112
270 #define IRONLAKE_LVDS_S_P1_MIN 2
271 #define IRONLAKE_LVDS_S_P1_MAX 8
272 #define IRONLAKE_LVDS_S_P2_SLOW 14
273 #define IRONLAKE_LVDS_S_P2_FAST 14
274
275 /* LVDS dual-channel 120Mhz refclk */
276 #define IRONLAKE_LVDS_D_N_MIN 1
277 #define IRONLAKE_LVDS_D_N_MAX 3
278 #define IRONLAKE_LVDS_D_M_MIN 79
279 #define IRONLAKE_LVDS_D_M_MAX 127
280 #define IRONLAKE_LVDS_D_P_MIN 14
281 #define IRONLAKE_LVDS_D_P_MAX 56
282 #define IRONLAKE_LVDS_D_P1_MIN 2
283 #define IRONLAKE_LVDS_D_P1_MAX 8
284 #define IRONLAKE_LVDS_D_P2_SLOW 7
285 #define IRONLAKE_LVDS_D_P2_FAST 7
286
287 /* LVDS single-channel 100Mhz refclk */
288 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
289 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
290 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
291 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
292 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
293 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
294 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
295 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
297 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
298
299 /* LVDS dual-channel 100Mhz refclk */
300 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
301 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
302 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
303 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
304 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
305 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
306 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
307 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
309 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
310
311 /* DisplayPort */
312 #define IRONLAKE_DP_N_MIN 1
313 #define IRONLAKE_DP_N_MAX 2
314 #define IRONLAKE_DP_M_MIN 81
315 #define IRONLAKE_DP_M_MAX 90
316 #define IRONLAKE_DP_P_MIN 10
317 #define IRONLAKE_DP_P_MAX 20
318 #define IRONLAKE_DP_P2_FAST 10
319 #define IRONLAKE_DP_P2_SLOW 10
320 #define IRONLAKE_DP_P2_LIMIT 0
321 #define IRONLAKE_DP_P1_MIN 1
322 #define IRONLAKE_DP_P1_MAX 2
323
324 static bool
325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
326 int target, int refclk, intel_clock_t *best_clock);
327 static bool
328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
329 int target, int refclk, intel_clock_t *best_clock);
330
331 static bool
332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static const intel_limit_t intel_limits_i8xx_dvo = {
339 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
340 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
341 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
342 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
343 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
344 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
345 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
346 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
347 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
348 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
349 .find_pll = intel_find_best_PLL,
350 };
351
352 static const intel_limit_t intel_limits_i8xx_lvds = {
353 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
354 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
355 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
356 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
357 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
358 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
359 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
360 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
361 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
362 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
363 .find_pll = intel_find_best_PLL,
364 };
365
366 static const intel_limit_t intel_limits_i9xx_sdvo = {
367 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
368 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
369 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
370 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
371 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
372 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
373 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
374 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
375 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
376 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
377 .find_pll = intel_find_best_PLL,
378 };
379
380 static const intel_limit_t intel_limits_i9xx_lvds = {
381 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
382 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
383 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
384 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
385 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
386 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
387 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
388 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
389 /* The single-channel range is 25-112Mhz, and dual-channel
390 * is 80-224Mhz. Prefer single channel as much as possible.
391 */
392 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
394 .find_pll = intel_find_best_PLL,
395 };
396
397 /* below parameter and function is for G4X Chipset Family*/
398 static const intel_limit_t intel_limits_g4x_sdvo = {
399 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
400 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
401 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
402 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
403 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
404 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
405 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
406 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
407 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
408 .p2_slow = G4X_P2_SDVO_SLOW,
409 .p2_fast = G4X_P2_SDVO_FAST
410 },
411 .find_pll = intel_g4x_find_best_PLL,
412 };
413
414 static const intel_limit_t intel_limits_g4x_hdmi = {
415 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
416 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
417 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
418 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
419 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
420 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
421 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
422 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
423 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
424 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
425 .p2_fast = G4X_P2_HDMI_DAC_FAST
426 },
427 .find_pll = intel_g4x_find_best_PLL,
428 };
429
430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
431 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
432 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
433 .vco = { .min = G4X_VCO_MIN,
434 .max = G4X_VCO_MAX },
435 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
436 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
437 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
438 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
439 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
440 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
441 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
442 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
443 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
444 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
445 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
447 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
448 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
449 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
450 },
451 .find_pll = intel_g4x_find_best_PLL,
452 };
453
454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
455 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
456 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
457 .vco = { .min = G4X_VCO_MIN,
458 .max = G4X_VCO_MAX },
459 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
460 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
461 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
462 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
463 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
464 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
465 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
466 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
467 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
468 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
469 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
471 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
472 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
473 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
474 },
475 .find_pll = intel_g4x_find_best_PLL,
476 };
477
478 static const intel_limit_t intel_limits_g4x_display_port = {
479 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
480 .max = G4X_DOT_DISPLAY_PORT_MAX },
481 .vco = { .min = G4X_VCO_MIN,
482 .max = G4X_VCO_MAX},
483 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
484 .max = G4X_N_DISPLAY_PORT_MAX },
485 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
486 .max = G4X_M_DISPLAY_PORT_MAX },
487 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
488 .max = G4X_M1_DISPLAY_PORT_MAX },
489 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
490 .max = G4X_M2_DISPLAY_PORT_MAX },
491 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
492 .max = G4X_P_DISPLAY_PORT_MAX },
493 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
494 .max = G4X_P1_DISPLAY_PORT_MAX},
495 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
496 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
497 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
498 .find_pll = intel_find_pll_g4x_dp,
499 };
500
501 static const intel_limit_t intel_limits_pineview_sdvo = {
502 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
503 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
504 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
505 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
506 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
507 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
508 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
509 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
510 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
511 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
512 .find_pll = intel_find_best_PLL,
513 };
514
515 static const intel_limit_t intel_limits_pineview_lvds = {
516 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
517 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
518 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
519 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
520 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
521 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
522 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
523 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
524 /* Pineview only supports single-channel mode. */
525 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
526 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
527 .find_pll = intel_find_best_PLL,
528 };
529
530 static const intel_limit_t intel_limits_ironlake_dac = {
531 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
532 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
533 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
534 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
535 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
536 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
537 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
538 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
539 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
540 .p2_slow = IRONLAKE_DAC_P2_SLOW,
541 .p2_fast = IRONLAKE_DAC_P2_FAST },
542 .find_pll = intel_g4x_find_best_PLL,
543 };
544
545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
546 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
547 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
548 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
549 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
550 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
551 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
552 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
553 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
554 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
555 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
556 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
557 .find_pll = intel_g4x_find_best_PLL,
558 };
559
560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
561 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
562 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
563 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
564 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
565 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
566 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
567 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
568 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
569 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
570 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
571 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
572 .find_pll = intel_g4x_find_best_PLL,
573 };
574
575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
576 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
577 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
578 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
579 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
580 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
581 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
582 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
583 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
584 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
585 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
586 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
587 .find_pll = intel_g4x_find_best_PLL,
588 };
589
590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
591 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
592 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
593 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
594 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
595 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
596 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
597 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
598 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
599 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
600 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
601 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
602 .find_pll = intel_g4x_find_best_PLL,
603 };
604
605 static const intel_limit_t intel_limits_ironlake_display_port = {
606 .dot = { .min = IRONLAKE_DOT_MIN,
607 .max = IRONLAKE_DOT_MAX },
608 .vco = { .min = IRONLAKE_VCO_MIN,
609 .max = IRONLAKE_VCO_MAX},
610 .n = { .min = IRONLAKE_DP_N_MIN,
611 .max = IRONLAKE_DP_N_MAX },
612 .m = { .min = IRONLAKE_DP_M_MIN,
613 .max = IRONLAKE_DP_M_MAX },
614 .m1 = { .min = IRONLAKE_M1_MIN,
615 .max = IRONLAKE_M1_MAX },
616 .m2 = { .min = IRONLAKE_M2_MIN,
617 .max = IRONLAKE_M2_MAX },
618 .p = { .min = IRONLAKE_DP_P_MIN,
619 .max = IRONLAKE_DP_P_MAX },
620 .p1 = { .min = IRONLAKE_DP_P1_MIN,
621 .max = IRONLAKE_DP_P1_MAX},
622 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
623 .p2_slow = IRONLAKE_DP_P2_SLOW,
624 .p2_fast = IRONLAKE_DP_P2_FAST },
625 .find_pll = intel_find_pll_ironlake_dp,
626 };
627
628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
629 {
630 struct drm_device *dev = crtc->dev;
631 struct drm_i915_private *dev_priv = dev->dev_private;
632 const intel_limit_t *limit;
633 int refclk = 120;
634
635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
636 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
637 refclk = 100;
638
639 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
640 LVDS_CLKB_POWER_UP) {
641 /* LVDS dual channel */
642 if (refclk == 100)
643 limit = &intel_limits_ironlake_dual_lvds_100m;
644 else
645 limit = &intel_limits_ironlake_dual_lvds;
646 } else {
647 if (refclk == 100)
648 limit = &intel_limits_ironlake_single_lvds_100m;
649 else
650 limit = &intel_limits_ironlake_single_lvds;
651 }
652 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
653 HAS_eDP)
654 limit = &intel_limits_ironlake_display_port;
655 else
656 limit = &intel_limits_ironlake_dac;
657
658 return limit;
659 }
660
661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
662 {
663 struct drm_device *dev = crtc->dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
665 const intel_limit_t *limit;
666
667 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
668 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
669 LVDS_CLKB_POWER_UP)
670 /* LVDS with dual channel */
671 limit = &intel_limits_g4x_dual_channel_lvds;
672 else
673 /* LVDS with dual channel */
674 limit = &intel_limits_g4x_single_channel_lvds;
675 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
676 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
677 limit = &intel_limits_g4x_hdmi;
678 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
679 limit = &intel_limits_g4x_sdvo;
680 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
681 limit = &intel_limits_g4x_display_port;
682 } else /* The option is for other outputs */
683 limit = &intel_limits_i9xx_sdvo;
684
685 return limit;
686 }
687
688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
689 {
690 struct drm_device *dev = crtc->dev;
691 const intel_limit_t *limit;
692
693 if (HAS_PCH_SPLIT(dev))
694 limit = intel_ironlake_limit(crtc);
695 else if (IS_G4X(dev)) {
696 limit = intel_g4x_limit(crtc);
697 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
698 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
699 limit = &intel_limits_i9xx_lvds;
700 else
701 limit = &intel_limits_i9xx_sdvo;
702 } else if (IS_PINEVIEW(dev)) {
703 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
704 limit = &intel_limits_pineview_lvds;
705 else
706 limit = &intel_limits_pineview_sdvo;
707 } else {
708 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
709 limit = &intel_limits_i8xx_lvds;
710 else
711 limit = &intel_limits_i8xx_dvo;
712 }
713 return limit;
714 }
715
716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
717 static void pineview_clock(int refclk, intel_clock_t *clock)
718 {
719 clock->m = clock->m2 + 2;
720 clock->p = clock->p1 * clock->p2;
721 clock->vco = refclk * clock->m / clock->n;
722 clock->dot = clock->vco / clock->p;
723 }
724
725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
726 {
727 if (IS_PINEVIEW(dev)) {
728 pineview_clock(refclk, clock);
729 return;
730 }
731 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
732 clock->p = clock->p1 * clock->p2;
733 clock->vco = refclk * clock->m / (clock->n + 2);
734 clock->dot = clock->vco / clock->p;
735 }
736
737 /**
738 * Returns whether any output on the specified pipe is of the specified type
739 */
740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
741 {
742 struct drm_device *dev = crtc->dev;
743 struct drm_mode_config *mode_config = &dev->mode_config;
744 struct drm_encoder *l_entry;
745
746 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
747 if (l_entry && l_entry->crtc == crtc) {
748 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
749 if (intel_encoder->type == type)
750 return true;
751 }
752 }
753 return false;
754 }
755
756 static struct drm_connector *
757 intel_pipe_get_connector (struct drm_crtc *crtc)
758 {
759 struct drm_device *dev = crtc->dev;
760 struct drm_mode_config *mode_config = &dev->mode_config;
761 struct drm_connector *l_entry, *ret = NULL;
762
763 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
764 if (l_entry->encoder &&
765 l_entry->encoder->crtc == crtc) {
766 ret = l_entry;
767 break;
768 }
769 }
770 return ret;
771 }
772
773 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
774 /**
775 * Returns whether the given set of divisors are valid for a given refclk with
776 * the given connectors.
777 */
778
779 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
780 {
781 const intel_limit_t *limit = intel_limit (crtc);
782 struct drm_device *dev = crtc->dev;
783
784 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
785 INTELPllInvalid ("p1 out of range\n");
786 if (clock->p < limit->p.min || limit->p.max < clock->p)
787 INTELPllInvalid ("p out of range\n");
788 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
789 INTELPllInvalid ("m2 out of range\n");
790 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
791 INTELPllInvalid ("m1 out of range\n");
792 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
793 INTELPllInvalid ("m1 <= m2\n");
794 if (clock->m < limit->m.min || limit->m.max < clock->m)
795 INTELPllInvalid ("m out of range\n");
796 if (clock->n < limit->n.min || limit->n.max < clock->n)
797 INTELPllInvalid ("n out of range\n");
798 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
799 INTELPllInvalid ("vco out of range\n");
800 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
801 * connector, etc., rather than just a single range.
802 */
803 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
804 INTELPllInvalid ("dot out of range\n");
805
806 return true;
807 }
808
809 static bool
810 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
811 int target, int refclk, intel_clock_t *best_clock)
812
813 {
814 struct drm_device *dev = crtc->dev;
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 intel_clock_t clock;
817 int err = target;
818
819 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
820 (I915_READ(LVDS)) != 0) {
821 /*
822 * For LVDS, if the panel is on, just rely on its current
823 * settings for dual-channel. We haven't figured out how to
824 * reliably set up different single/dual channel state, if we
825 * even can.
826 */
827 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
828 LVDS_CLKB_POWER_UP)
829 clock.p2 = limit->p2.p2_fast;
830 else
831 clock.p2 = limit->p2.p2_slow;
832 } else {
833 if (target < limit->p2.dot_limit)
834 clock.p2 = limit->p2.p2_slow;
835 else
836 clock.p2 = limit->p2.p2_fast;
837 }
838
839 memset (best_clock, 0, sizeof (*best_clock));
840
841 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
842 clock.m1++) {
843 for (clock.m2 = limit->m2.min;
844 clock.m2 <= limit->m2.max; clock.m2++) {
845 /* m1 is always 0 in Pineview */
846 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
847 break;
848 for (clock.n = limit->n.min;
849 clock.n <= limit->n.max; clock.n++) {
850 for (clock.p1 = limit->p1.min;
851 clock.p1 <= limit->p1.max; clock.p1++) {
852 int this_err;
853
854 intel_clock(dev, refclk, &clock);
855
856 if (!intel_PLL_is_valid(crtc, &clock))
857 continue;
858
859 this_err = abs(clock.dot - target);
860 if (this_err < err) {
861 *best_clock = clock;
862 err = this_err;
863 }
864 }
865 }
866 }
867 }
868
869 return (err != target);
870 }
871
872 static bool
873 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
874 int target, int refclk, intel_clock_t *best_clock)
875 {
876 struct drm_device *dev = crtc->dev;
877 struct drm_i915_private *dev_priv = dev->dev_private;
878 intel_clock_t clock;
879 int max_n;
880 bool found;
881 /* approximately equals target * 0.00488 */
882 int err_most = (target >> 8) + (target >> 10);
883 found = false;
884
885 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
886 int lvds_reg;
887
888 if (HAS_PCH_SPLIT(dev))
889 lvds_reg = PCH_LVDS;
890 else
891 lvds_reg = LVDS;
892 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
893 LVDS_CLKB_POWER_UP)
894 clock.p2 = limit->p2.p2_fast;
895 else
896 clock.p2 = limit->p2.p2_slow;
897 } else {
898 if (target < limit->p2.dot_limit)
899 clock.p2 = limit->p2.p2_slow;
900 else
901 clock.p2 = limit->p2.p2_fast;
902 }
903
904 memset(best_clock, 0, sizeof(*best_clock));
905 max_n = limit->n.max;
906 /* based on hardware requriment prefer smaller n to precision */
907 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
908 /* based on hardware requirment prefere larger m1,m2 */
909 for (clock.m1 = limit->m1.max;
910 clock.m1 >= limit->m1.min; clock.m1--) {
911 for (clock.m2 = limit->m2.max;
912 clock.m2 >= limit->m2.min; clock.m2--) {
913 for (clock.p1 = limit->p1.max;
914 clock.p1 >= limit->p1.min; clock.p1--) {
915 int this_err;
916
917 intel_clock(dev, refclk, &clock);
918 if (!intel_PLL_is_valid(crtc, &clock))
919 continue;
920 this_err = abs(clock.dot - target) ;
921 if (this_err < err_most) {
922 *best_clock = clock;
923 err_most = this_err;
924 max_n = clock.n;
925 found = true;
926 }
927 }
928 }
929 }
930 }
931 return found;
932 }
933
934 static bool
935 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
936 int target, int refclk, intel_clock_t *best_clock)
937 {
938 struct drm_device *dev = crtc->dev;
939 intel_clock_t clock;
940
941 /* return directly when it is eDP */
942 if (HAS_eDP)
943 return true;
944
945 if (target < 200000) {
946 clock.n = 1;
947 clock.p1 = 2;
948 clock.p2 = 10;
949 clock.m1 = 12;
950 clock.m2 = 9;
951 } else {
952 clock.n = 2;
953 clock.p1 = 1;
954 clock.p2 = 10;
955 clock.m1 = 14;
956 clock.m2 = 8;
957 }
958 intel_clock(dev, refclk, &clock);
959 memcpy(best_clock, &clock, sizeof(intel_clock_t));
960 return true;
961 }
962
963 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
964 static bool
965 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
966 int target, int refclk, intel_clock_t *best_clock)
967 {
968 intel_clock_t clock;
969 if (target < 200000) {
970 clock.p1 = 2;
971 clock.p2 = 10;
972 clock.n = 2;
973 clock.m1 = 23;
974 clock.m2 = 8;
975 } else {
976 clock.p1 = 1;
977 clock.p2 = 10;
978 clock.n = 1;
979 clock.m1 = 14;
980 clock.m2 = 2;
981 }
982 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
983 clock.p = (clock.p1 * clock.p2);
984 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
985 clock.vco = 0;
986 memcpy(best_clock, &clock, sizeof(intel_clock_t));
987 return true;
988 }
989
990 void
991 intel_wait_for_vblank(struct drm_device *dev)
992 {
993 /* Wait for 20ms, i.e. one cycle at 50hz. */
994 msleep(20);
995 }
996
997 /* Parameters have changed, update FBC info */
998 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
999 {
1000 struct drm_device *dev = crtc->dev;
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002 struct drm_framebuffer *fb = crtc->fb;
1003 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1004 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006 int plane, i;
1007 u32 fbc_ctl, fbc_ctl2;
1008
1009 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1010
1011 if (fb->pitch < dev_priv->cfb_pitch)
1012 dev_priv->cfb_pitch = fb->pitch;
1013
1014 /* FBC_CTL wants 64B units */
1015 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1016 dev_priv->cfb_fence = obj_priv->fence_reg;
1017 dev_priv->cfb_plane = intel_crtc->plane;
1018 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1019
1020 /* Clear old tags */
1021 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1022 I915_WRITE(FBC_TAG + (i * 4), 0);
1023
1024 /* Set it up... */
1025 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1026 if (obj_priv->tiling_mode != I915_TILING_NONE)
1027 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1028 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1029 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1030
1031 /* enable it... */
1032 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1033 if (IS_I945GM(dev))
1034 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1035 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1036 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1037 if (obj_priv->tiling_mode != I915_TILING_NONE)
1038 fbc_ctl |= dev_priv->cfb_fence;
1039 I915_WRITE(FBC_CONTROL, fbc_ctl);
1040
1041 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1042 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1043 }
1044
1045 void i8xx_disable_fbc(struct drm_device *dev)
1046 {
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048 u32 fbc_ctl;
1049
1050 if (!I915_HAS_FBC(dev))
1051 return;
1052
1053 /* Disable compression */
1054 fbc_ctl = I915_READ(FBC_CONTROL);
1055 fbc_ctl &= ~FBC_CTL_EN;
1056 I915_WRITE(FBC_CONTROL, fbc_ctl);
1057
1058 /* Wait for compressing bit to clear */
1059 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1060 ; /* nothing */
1061
1062 intel_wait_for_vblank(dev);
1063
1064 DRM_DEBUG_KMS("disabled FBC\n");
1065 }
1066
1067 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1068 {
1069 struct drm_device *dev = crtc->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071
1072 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1073 }
1074
1075 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1076 {
1077 struct drm_device *dev = crtc->dev;
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 struct drm_framebuffer *fb = crtc->fb;
1080 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1081 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1084 DPFC_CTL_PLANEB);
1085 unsigned long stall_watermark = 200;
1086 u32 dpfc_ctl;
1087
1088 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089 dev_priv->cfb_fence = obj_priv->fence_reg;
1090 dev_priv->cfb_plane = intel_crtc->plane;
1091
1092 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1093 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1094 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1095 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1096 } else {
1097 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1098 }
1099
1100 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1101 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1102 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1103 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1104 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1105
1106 /* enable it... */
1107 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1108
1109 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1110 }
1111
1112 void g4x_disable_fbc(struct drm_device *dev)
1113 {
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 u32 dpfc_ctl;
1116
1117 /* Disable compression */
1118 dpfc_ctl = I915_READ(DPFC_CONTROL);
1119 dpfc_ctl &= ~DPFC_CTL_EN;
1120 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121 intel_wait_for_vblank(dev);
1122
1123 DRM_DEBUG_KMS("disabled FBC\n");
1124 }
1125
1126 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1127 {
1128 struct drm_device *dev = crtc->dev;
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130
1131 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1132 }
1133
1134 /**
1135 * intel_update_fbc - enable/disable FBC as needed
1136 * @crtc: CRTC to point the compressor at
1137 * @mode: mode in use
1138 *
1139 * Set up the framebuffer compression hardware at mode set time. We
1140 * enable it if possible:
1141 * - plane A only (on pre-965)
1142 * - no pixel mulitply/line duplication
1143 * - no alpha buffer discard
1144 * - no dual wide
1145 * - framebuffer <= 2048 in width, 1536 in height
1146 *
1147 * We can't assume that any compression will take place (worst case),
1148 * so the compressed buffer has to be the same size as the uncompressed
1149 * one. It also must reside (along with the line length buffer) in
1150 * stolen memory.
1151 *
1152 * We need to enable/disable FBC on a global basis.
1153 */
1154 static void intel_update_fbc(struct drm_crtc *crtc,
1155 struct drm_display_mode *mode)
1156 {
1157 struct drm_device *dev = crtc->dev;
1158 struct drm_i915_private *dev_priv = dev->dev_private;
1159 struct drm_framebuffer *fb = crtc->fb;
1160 struct intel_framebuffer *intel_fb;
1161 struct drm_i915_gem_object *obj_priv;
1162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1163 int plane = intel_crtc->plane;
1164
1165 if (!i915_powersave)
1166 return;
1167
1168 if (!dev_priv->display.fbc_enabled ||
1169 !dev_priv->display.enable_fbc ||
1170 !dev_priv->display.disable_fbc)
1171 return;
1172
1173 if (!crtc->fb)
1174 return;
1175
1176 intel_fb = to_intel_framebuffer(fb);
1177 obj_priv = to_intel_bo(intel_fb->obj);
1178
1179 /*
1180 * If FBC is already on, we just have to verify that we can
1181 * keep it that way...
1182 * Need to disable if:
1183 * - changing FBC params (stride, fence, mode)
1184 * - new fb is too large to fit in compressed buffer
1185 * - going to an unsupported config (interlace, pixel multiply, etc.)
1186 */
1187 if (intel_fb->obj->size > dev_priv->cfb_size) {
1188 DRM_DEBUG_KMS("framebuffer too large, disabling "
1189 "compression\n");
1190 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1191 goto out_disable;
1192 }
1193 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1194 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1195 DRM_DEBUG_KMS("mode incompatible with compression, "
1196 "disabling\n");
1197 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1198 goto out_disable;
1199 }
1200 if ((mode->hdisplay > 2048) ||
1201 (mode->vdisplay > 1536)) {
1202 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1203 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1204 goto out_disable;
1205 }
1206 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1207 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1208 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1209 goto out_disable;
1210 }
1211 if (obj_priv->tiling_mode != I915_TILING_X) {
1212 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1213 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1214 goto out_disable;
1215 }
1216
1217 if (dev_priv->display.fbc_enabled(crtc)) {
1218 /* We can re-enable it in this case, but need to update pitch */
1219 if (fb->pitch > dev_priv->cfb_pitch)
1220 dev_priv->display.disable_fbc(dev);
1221 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1222 dev_priv->display.disable_fbc(dev);
1223 if (plane != dev_priv->cfb_plane)
1224 dev_priv->display.disable_fbc(dev);
1225 }
1226
1227 if (!dev_priv->display.fbc_enabled(crtc)) {
1228 /* Now try to turn it back on if possible */
1229 dev_priv->display.enable_fbc(crtc, 500);
1230 }
1231
1232 return;
1233
1234 out_disable:
1235 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1236 /* Multiple disables should be harmless */
1237 if (dev_priv->display.fbc_enabled(crtc))
1238 dev_priv->display.disable_fbc(dev);
1239 }
1240
1241 static int
1242 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1243 {
1244 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1245 u32 alignment;
1246 int ret;
1247
1248 switch (obj_priv->tiling_mode) {
1249 case I915_TILING_NONE:
1250 alignment = 64 * 1024;
1251 break;
1252 case I915_TILING_X:
1253 /* pin() will align the object as required by fence */
1254 alignment = 0;
1255 break;
1256 case I915_TILING_Y:
1257 /* FIXME: Is this true? */
1258 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1259 return -EINVAL;
1260 default:
1261 BUG();
1262 }
1263
1264 ret = i915_gem_object_pin(obj, alignment);
1265 if (ret != 0)
1266 return ret;
1267
1268 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1269 * fence, whereas 965+ only requires a fence if using
1270 * framebuffer compression. For simplicity, we always install
1271 * a fence as the cost is not that onerous.
1272 */
1273 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1274 obj_priv->tiling_mode != I915_TILING_NONE) {
1275 ret = i915_gem_object_get_fence_reg(obj);
1276 if (ret != 0) {
1277 i915_gem_object_unpin(obj);
1278 return ret;
1279 }
1280 }
1281
1282 return 0;
1283 }
1284
1285 static int
1286 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1287 struct drm_framebuffer *old_fb)
1288 {
1289 struct drm_device *dev = crtc->dev;
1290 struct drm_i915_private *dev_priv = dev->dev_private;
1291 struct drm_i915_master_private *master_priv;
1292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1293 struct intel_framebuffer *intel_fb;
1294 struct drm_i915_gem_object *obj_priv;
1295 struct drm_gem_object *obj;
1296 int pipe = intel_crtc->pipe;
1297 int plane = intel_crtc->plane;
1298 unsigned long Start, Offset;
1299 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1300 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1301 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1302 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1303 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1304 u32 dspcntr;
1305 int ret;
1306
1307 /* no fb bound */
1308 if (!crtc->fb) {
1309 DRM_DEBUG_KMS("No FB bound\n");
1310 return 0;
1311 }
1312
1313 switch (plane) {
1314 case 0:
1315 case 1:
1316 break;
1317 default:
1318 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1319 return -EINVAL;
1320 }
1321
1322 intel_fb = to_intel_framebuffer(crtc->fb);
1323 obj = intel_fb->obj;
1324 obj_priv = to_intel_bo(obj);
1325
1326 mutex_lock(&dev->struct_mutex);
1327 ret = intel_pin_and_fence_fb_obj(dev, obj);
1328 if (ret != 0) {
1329 mutex_unlock(&dev->struct_mutex);
1330 return ret;
1331 }
1332
1333 ret = i915_gem_object_set_to_display_plane(obj);
1334 if (ret != 0) {
1335 i915_gem_object_unpin(obj);
1336 mutex_unlock(&dev->struct_mutex);
1337 return ret;
1338 }
1339
1340 dspcntr = I915_READ(dspcntr_reg);
1341 /* Mask out pixel format bits in case we change it */
1342 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1343 switch (crtc->fb->bits_per_pixel) {
1344 case 8:
1345 dspcntr |= DISPPLANE_8BPP;
1346 break;
1347 case 16:
1348 if (crtc->fb->depth == 15)
1349 dspcntr |= DISPPLANE_15_16BPP;
1350 else
1351 dspcntr |= DISPPLANE_16BPP;
1352 break;
1353 case 24:
1354 case 32:
1355 if (crtc->fb->depth == 30)
1356 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1357 else
1358 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1359 break;
1360 default:
1361 DRM_ERROR("Unknown color depth\n");
1362 i915_gem_object_unpin(obj);
1363 mutex_unlock(&dev->struct_mutex);
1364 return -EINVAL;
1365 }
1366 if (IS_I965G(dev)) {
1367 if (obj_priv->tiling_mode != I915_TILING_NONE)
1368 dspcntr |= DISPPLANE_TILED;
1369 else
1370 dspcntr &= ~DISPPLANE_TILED;
1371 }
1372
1373 if (HAS_PCH_SPLIT(dev))
1374 /* must disable */
1375 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1376
1377 I915_WRITE(dspcntr_reg, dspcntr);
1378
1379 Start = obj_priv->gtt_offset;
1380 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1381
1382 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1383 I915_WRITE(dspstride, crtc->fb->pitch);
1384 if (IS_I965G(dev)) {
1385 I915_WRITE(dspbase, Offset);
1386 I915_READ(dspbase);
1387 I915_WRITE(dspsurf, Start);
1388 I915_READ(dspsurf);
1389 I915_WRITE(dsptileoff, (y << 16) | x);
1390 } else {
1391 I915_WRITE(dspbase, Start + Offset);
1392 I915_READ(dspbase);
1393 }
1394
1395 if ((IS_I965G(dev) || plane == 0))
1396 intel_update_fbc(crtc, &crtc->mode);
1397
1398 intel_wait_for_vblank(dev);
1399
1400 if (old_fb) {
1401 intel_fb = to_intel_framebuffer(old_fb);
1402 obj_priv = to_intel_bo(intel_fb->obj);
1403 i915_gem_object_unpin(intel_fb->obj);
1404 }
1405 intel_increase_pllclock(crtc, true);
1406
1407 mutex_unlock(&dev->struct_mutex);
1408
1409 if (!dev->primary->master)
1410 return 0;
1411
1412 master_priv = dev->primary->master->driver_priv;
1413 if (!master_priv->sarea_priv)
1414 return 0;
1415
1416 if (pipe) {
1417 master_priv->sarea_priv->pipeB_x = x;
1418 master_priv->sarea_priv->pipeB_y = y;
1419 } else {
1420 master_priv->sarea_priv->pipeA_x = x;
1421 master_priv->sarea_priv->pipeA_y = y;
1422 }
1423
1424 return 0;
1425 }
1426
1427 /* Disable the VGA plane that we never use */
1428 static void i915_disable_vga (struct drm_device *dev)
1429 {
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 u8 sr1;
1432 u32 vga_reg;
1433
1434 if (HAS_PCH_SPLIT(dev))
1435 vga_reg = CPU_VGACNTRL;
1436 else
1437 vga_reg = VGACNTRL;
1438
1439 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1440 return;
1441
1442 I915_WRITE8(VGA_SR_INDEX, 1);
1443 sr1 = I915_READ8(VGA_SR_DATA);
1444 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1445 udelay(100);
1446
1447 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1448 }
1449
1450 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1451 {
1452 struct drm_device *dev = crtc->dev;
1453 struct drm_i915_private *dev_priv = dev->dev_private;
1454 u32 dpa_ctl;
1455
1456 DRM_DEBUG_KMS("\n");
1457 dpa_ctl = I915_READ(DP_A);
1458 dpa_ctl &= ~DP_PLL_ENABLE;
1459 I915_WRITE(DP_A, dpa_ctl);
1460 }
1461
1462 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1463 {
1464 struct drm_device *dev = crtc->dev;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466 u32 dpa_ctl;
1467
1468 dpa_ctl = I915_READ(DP_A);
1469 dpa_ctl |= DP_PLL_ENABLE;
1470 I915_WRITE(DP_A, dpa_ctl);
1471 udelay(200);
1472 }
1473
1474
1475 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1476 {
1477 struct drm_device *dev = crtc->dev;
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1479 u32 dpa_ctl;
1480
1481 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1482 dpa_ctl = I915_READ(DP_A);
1483 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1484
1485 if (clock < 200000) {
1486 u32 temp;
1487 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1488 /* workaround for 160Mhz:
1489 1) program 0x4600c bits 15:0 = 0x8124
1490 2) program 0x46010 bit 0 = 1
1491 3) program 0x46034 bit 24 = 1
1492 4) program 0x64000 bit 14 = 1
1493 */
1494 temp = I915_READ(0x4600c);
1495 temp &= 0xffff0000;
1496 I915_WRITE(0x4600c, temp | 0x8124);
1497
1498 temp = I915_READ(0x46010);
1499 I915_WRITE(0x46010, temp | 1);
1500
1501 temp = I915_READ(0x46034);
1502 I915_WRITE(0x46034, temp | (1 << 24));
1503 } else {
1504 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1505 }
1506 I915_WRITE(DP_A, dpa_ctl);
1507
1508 udelay(500);
1509 }
1510
1511 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1512 {
1513 struct drm_device *dev = crtc->dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1516 int pipe = intel_crtc->pipe;
1517 int plane = intel_crtc->plane;
1518 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1519 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1520 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1521 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1522 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1523 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1524 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1525 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1526 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1527 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1528 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1529 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1530 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1531 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1532 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1533 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1534 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1535 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1536 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1537 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1538 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1539 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1540 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1541 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1542 u32 temp;
1543 int tries = 5, j, n;
1544 u32 pipe_bpc;
1545
1546 temp = I915_READ(pipeconf_reg);
1547 pipe_bpc = temp & PIPE_BPC_MASK;
1548
1549 /* XXX: When our outputs are all unaware of DPMS modes other than off
1550 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1551 */
1552 switch (mode) {
1553 case DRM_MODE_DPMS_ON:
1554 case DRM_MODE_DPMS_STANDBY:
1555 case DRM_MODE_DPMS_SUSPEND:
1556 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1557
1558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1559 temp = I915_READ(PCH_LVDS);
1560 if ((temp & LVDS_PORT_EN) == 0) {
1561 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1562 POSTING_READ(PCH_LVDS);
1563 }
1564 }
1565
1566 if (HAS_eDP) {
1567 /* enable eDP PLL */
1568 ironlake_enable_pll_edp(crtc);
1569 } else {
1570 /* enable PCH DPLL */
1571 temp = I915_READ(pch_dpll_reg);
1572 if ((temp & DPLL_VCO_ENABLE) == 0) {
1573 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1574 I915_READ(pch_dpll_reg);
1575 }
1576
1577 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1578 temp = I915_READ(fdi_rx_reg);
1579 /*
1580 * make the BPC in FDI Rx be consistent with that in
1581 * pipeconf reg.
1582 */
1583 temp &= ~(0x7 << 16);
1584 temp |= (pipe_bpc << 11);
1585 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1586 FDI_SEL_PCDCLK |
1587 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1588 I915_READ(fdi_rx_reg);
1589 udelay(200);
1590
1591 /* Enable CPU FDI TX PLL, always on for Ironlake */
1592 temp = I915_READ(fdi_tx_reg);
1593 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1594 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1595 I915_READ(fdi_tx_reg);
1596 udelay(100);
1597 }
1598 }
1599
1600 /* Enable panel fitting for LVDS */
1601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1602 temp = I915_READ(pf_ctl_reg);
1603 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1604
1605 /* currently full aspect */
1606 I915_WRITE(pf_win_pos, 0);
1607
1608 I915_WRITE(pf_win_size,
1609 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1610 (dev_priv->panel_fixed_mode->vdisplay));
1611 }
1612
1613 /* Enable CPU pipe */
1614 temp = I915_READ(pipeconf_reg);
1615 if ((temp & PIPEACONF_ENABLE) == 0) {
1616 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1617 I915_READ(pipeconf_reg);
1618 udelay(100);
1619 }
1620
1621 /* configure and enable CPU plane */
1622 temp = I915_READ(dspcntr_reg);
1623 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1624 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1625 /* Flush the plane changes */
1626 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1627 }
1628
1629 if (!HAS_eDP) {
1630 /* enable CPU FDI TX and PCH FDI RX */
1631 temp = I915_READ(fdi_tx_reg);
1632 temp |= FDI_TX_ENABLE;
1633 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1634 temp &= ~FDI_LINK_TRAIN_NONE;
1635 temp |= FDI_LINK_TRAIN_PATTERN_1;
1636 I915_WRITE(fdi_tx_reg, temp);
1637 I915_READ(fdi_tx_reg);
1638
1639 temp = I915_READ(fdi_rx_reg);
1640 temp &= ~FDI_LINK_TRAIN_NONE;
1641 temp |= FDI_LINK_TRAIN_PATTERN_1;
1642 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1643 I915_READ(fdi_rx_reg);
1644
1645 udelay(150);
1646
1647 /* Train FDI. */
1648 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1649 for train result */
1650 temp = I915_READ(fdi_rx_imr_reg);
1651 temp &= ~FDI_RX_SYMBOL_LOCK;
1652 temp &= ~FDI_RX_BIT_LOCK;
1653 I915_WRITE(fdi_rx_imr_reg, temp);
1654 I915_READ(fdi_rx_imr_reg);
1655 udelay(150);
1656
1657 temp = I915_READ(fdi_rx_iir_reg);
1658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1659
1660 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1661 for (j = 0; j < tries; j++) {
1662 temp = I915_READ(fdi_rx_iir_reg);
1663 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1664 temp);
1665 if (temp & FDI_RX_BIT_LOCK)
1666 break;
1667 udelay(200);
1668 }
1669 if (j != tries)
1670 I915_WRITE(fdi_rx_iir_reg,
1671 temp | FDI_RX_BIT_LOCK);
1672 else
1673 DRM_DEBUG_KMS("train 1 fail\n");
1674 } else {
1675 I915_WRITE(fdi_rx_iir_reg,
1676 temp | FDI_RX_BIT_LOCK);
1677 DRM_DEBUG_KMS("train 1 ok 2!\n");
1678 }
1679 temp = I915_READ(fdi_tx_reg);
1680 temp &= ~FDI_LINK_TRAIN_NONE;
1681 temp |= FDI_LINK_TRAIN_PATTERN_2;
1682 I915_WRITE(fdi_tx_reg, temp);
1683
1684 temp = I915_READ(fdi_rx_reg);
1685 temp &= ~FDI_LINK_TRAIN_NONE;
1686 temp |= FDI_LINK_TRAIN_PATTERN_2;
1687 I915_WRITE(fdi_rx_reg, temp);
1688
1689 udelay(150);
1690
1691 temp = I915_READ(fdi_rx_iir_reg);
1692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1693
1694 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1695 for (j = 0; j < tries; j++) {
1696 temp = I915_READ(fdi_rx_iir_reg);
1697 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1698 temp);
1699 if (temp & FDI_RX_SYMBOL_LOCK)
1700 break;
1701 udelay(200);
1702 }
1703 if (j != tries) {
1704 I915_WRITE(fdi_rx_iir_reg,
1705 temp | FDI_RX_SYMBOL_LOCK);
1706 DRM_DEBUG_KMS("train 2 ok 1!\n");
1707 } else
1708 DRM_DEBUG_KMS("train 2 fail\n");
1709 } else {
1710 I915_WRITE(fdi_rx_iir_reg,
1711 temp | FDI_RX_SYMBOL_LOCK);
1712 DRM_DEBUG_KMS("train 2 ok 2!\n");
1713 }
1714 DRM_DEBUG_KMS("train done\n");
1715
1716 /* set transcoder timing */
1717 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1718 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1719 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1720
1721 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1722 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1723 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1724
1725 /* enable PCH transcoder */
1726 temp = I915_READ(transconf_reg);
1727 /*
1728 * make the BPC in transcoder be consistent with
1729 * that in pipeconf reg.
1730 */
1731 temp &= ~PIPE_BPC_MASK;
1732 temp |= pipe_bpc;
1733 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1734 I915_READ(transconf_reg);
1735
1736 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1737 ;
1738
1739 /* enable normal */
1740
1741 temp = I915_READ(fdi_tx_reg);
1742 temp &= ~FDI_LINK_TRAIN_NONE;
1743 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1744 FDI_TX_ENHANCE_FRAME_ENABLE);
1745 I915_READ(fdi_tx_reg);
1746
1747 temp = I915_READ(fdi_rx_reg);
1748 temp &= ~FDI_LINK_TRAIN_NONE;
1749 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1750 FDI_RX_ENHANCE_FRAME_ENABLE);
1751 I915_READ(fdi_rx_reg);
1752
1753 /* wait one idle pattern time */
1754 udelay(100);
1755
1756 }
1757
1758 intel_crtc_load_lut(crtc);
1759
1760 break;
1761 case DRM_MODE_DPMS_OFF:
1762 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1763
1764 drm_vblank_off(dev, pipe);
1765 /* Disable display plane */
1766 temp = I915_READ(dspcntr_reg);
1767 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1768 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1769 /* Flush the plane changes */
1770 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1771 I915_READ(dspbase_reg);
1772 }
1773
1774 i915_disable_vga(dev);
1775
1776 /* disable cpu pipe, disable after all planes disabled */
1777 temp = I915_READ(pipeconf_reg);
1778 if ((temp & PIPEACONF_ENABLE) != 0) {
1779 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1780 I915_READ(pipeconf_reg);
1781 n = 0;
1782 /* wait for cpu pipe off, pipe state */
1783 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1784 n++;
1785 if (n < 60) {
1786 udelay(500);
1787 continue;
1788 } else {
1789 DRM_DEBUG_KMS("pipe %d off delay\n",
1790 pipe);
1791 break;
1792 }
1793 }
1794 } else
1795 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1796
1797 udelay(100);
1798
1799 /* Disable PF */
1800 temp = I915_READ(pf_ctl_reg);
1801 if ((temp & PF_ENABLE) != 0) {
1802 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1803 I915_READ(pf_ctl_reg);
1804 }
1805 I915_WRITE(pf_win_size, 0);
1806
1807 /* disable CPU FDI tx and PCH FDI rx */
1808 temp = I915_READ(fdi_tx_reg);
1809 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1810 I915_READ(fdi_tx_reg);
1811
1812 temp = I915_READ(fdi_rx_reg);
1813 /* BPC in FDI rx is consistent with that in pipeconf */
1814 temp &= ~(0x07 << 16);
1815 temp |= (pipe_bpc << 11);
1816 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1817 I915_READ(fdi_rx_reg);
1818
1819 udelay(100);
1820
1821 /* still set train pattern 1 */
1822 temp = I915_READ(fdi_tx_reg);
1823 temp &= ~FDI_LINK_TRAIN_NONE;
1824 temp |= FDI_LINK_TRAIN_PATTERN_1;
1825 I915_WRITE(fdi_tx_reg, temp);
1826
1827 temp = I915_READ(fdi_rx_reg);
1828 temp &= ~FDI_LINK_TRAIN_NONE;
1829 temp |= FDI_LINK_TRAIN_PATTERN_1;
1830 I915_WRITE(fdi_rx_reg, temp);
1831
1832 udelay(100);
1833
1834 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1835 temp = I915_READ(PCH_LVDS);
1836 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1837 I915_READ(PCH_LVDS);
1838 udelay(100);
1839 }
1840
1841 /* disable PCH transcoder */
1842 temp = I915_READ(transconf_reg);
1843 if ((temp & TRANS_ENABLE) != 0) {
1844 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1845 I915_READ(transconf_reg);
1846 n = 0;
1847 /* wait for PCH transcoder off, transcoder state */
1848 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1849 n++;
1850 if (n < 60) {
1851 udelay(500);
1852 continue;
1853 } else {
1854 DRM_DEBUG_KMS("transcoder %d off "
1855 "delay\n", pipe);
1856 break;
1857 }
1858 }
1859 }
1860 temp = I915_READ(transconf_reg);
1861 /* BPC in transcoder is consistent with that in pipeconf */
1862 temp &= ~PIPE_BPC_MASK;
1863 temp |= pipe_bpc;
1864 I915_WRITE(transconf_reg, temp);
1865 I915_READ(transconf_reg);
1866 udelay(100);
1867
1868 /* disable PCH DPLL */
1869 temp = I915_READ(pch_dpll_reg);
1870 if ((temp & DPLL_VCO_ENABLE) != 0) {
1871 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1872 I915_READ(pch_dpll_reg);
1873 }
1874
1875 if (HAS_eDP) {
1876 ironlake_disable_pll_edp(crtc);
1877 }
1878
1879 temp = I915_READ(fdi_rx_reg);
1880 temp &= ~FDI_SEL_PCDCLK;
1881 I915_WRITE(fdi_rx_reg, temp);
1882 I915_READ(fdi_rx_reg);
1883
1884 temp = I915_READ(fdi_rx_reg);
1885 temp &= ~FDI_RX_PLL_ENABLE;
1886 I915_WRITE(fdi_rx_reg, temp);
1887 I915_READ(fdi_rx_reg);
1888
1889 /* Disable CPU FDI TX PLL */
1890 temp = I915_READ(fdi_tx_reg);
1891 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1892 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1893 I915_READ(fdi_tx_reg);
1894 udelay(100);
1895 }
1896
1897 /* Wait for the clocks to turn off. */
1898 udelay(100);
1899 break;
1900 }
1901 }
1902
1903 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1904 {
1905 struct intel_overlay *overlay;
1906 int ret;
1907
1908 if (!enable && intel_crtc->overlay) {
1909 overlay = intel_crtc->overlay;
1910 mutex_lock(&overlay->dev->struct_mutex);
1911 for (;;) {
1912 ret = intel_overlay_switch_off(overlay);
1913 if (ret == 0)
1914 break;
1915
1916 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1917 if (ret != 0) {
1918 /* overlay doesn't react anymore. Usually
1919 * results in a black screen and an unkillable
1920 * X server. */
1921 BUG();
1922 overlay->hw_wedged = HW_WEDGED;
1923 break;
1924 }
1925 }
1926 mutex_unlock(&overlay->dev->struct_mutex);
1927 }
1928 /* Let userspace switch the overlay on again. In most cases userspace
1929 * has to recompute where to put it anyway. */
1930
1931 return;
1932 }
1933
1934 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1935 {
1936 struct drm_device *dev = crtc->dev;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1939 int pipe = intel_crtc->pipe;
1940 int plane = intel_crtc->plane;
1941 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1942 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1943 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1944 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1945 u32 temp;
1946
1947 /* XXX: When our outputs are all unaware of DPMS modes other than off
1948 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1949 */
1950 switch (mode) {
1951 case DRM_MODE_DPMS_ON:
1952 case DRM_MODE_DPMS_STANDBY:
1953 case DRM_MODE_DPMS_SUSPEND:
1954 intel_update_watermarks(dev);
1955
1956 /* Enable the DPLL */
1957 temp = I915_READ(dpll_reg);
1958 if ((temp & DPLL_VCO_ENABLE) == 0) {
1959 I915_WRITE(dpll_reg, temp);
1960 I915_READ(dpll_reg);
1961 /* Wait for the clocks to stabilize. */
1962 udelay(150);
1963 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1964 I915_READ(dpll_reg);
1965 /* Wait for the clocks to stabilize. */
1966 udelay(150);
1967 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1968 I915_READ(dpll_reg);
1969 /* Wait for the clocks to stabilize. */
1970 udelay(150);
1971 }
1972
1973 /* Enable the pipe */
1974 temp = I915_READ(pipeconf_reg);
1975 if ((temp & PIPEACONF_ENABLE) == 0)
1976 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1977
1978 /* Enable the plane */
1979 temp = I915_READ(dspcntr_reg);
1980 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1981 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1982 /* Flush the plane changes */
1983 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1984 }
1985
1986 intel_crtc_load_lut(crtc);
1987
1988 if ((IS_I965G(dev) || plane == 0))
1989 intel_update_fbc(crtc, &crtc->mode);
1990
1991 /* Give the overlay scaler a chance to enable if it's on this pipe */
1992 intel_crtc_dpms_overlay(intel_crtc, true);
1993 break;
1994 case DRM_MODE_DPMS_OFF:
1995 intel_update_watermarks(dev);
1996
1997 /* Give the overlay scaler a chance to disable if it's on this pipe */
1998 intel_crtc_dpms_overlay(intel_crtc, false);
1999 drm_vblank_off(dev, pipe);
2000
2001 if (dev_priv->cfb_plane == plane &&
2002 dev_priv->display.disable_fbc)
2003 dev_priv->display.disable_fbc(dev);
2004
2005 /* Disable the VGA plane that we never use */
2006 i915_disable_vga(dev);
2007
2008 /* Disable display plane */
2009 temp = I915_READ(dspcntr_reg);
2010 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2011 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2012 /* Flush the plane changes */
2013 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2014 I915_READ(dspbase_reg);
2015 }
2016
2017 if (!IS_I9XX(dev)) {
2018 /* Wait for vblank for the disable to take effect */
2019 intel_wait_for_vblank(dev);
2020 }
2021
2022 /* Next, disable display pipes */
2023 temp = I915_READ(pipeconf_reg);
2024 if ((temp & PIPEACONF_ENABLE) != 0) {
2025 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2026 I915_READ(pipeconf_reg);
2027 }
2028
2029 /* Wait for vblank for the disable to take effect. */
2030 intel_wait_for_vblank(dev);
2031
2032 temp = I915_READ(dpll_reg);
2033 if ((temp & DPLL_VCO_ENABLE) != 0) {
2034 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2035 I915_READ(dpll_reg);
2036 }
2037
2038 /* Wait for the clocks to turn off. */
2039 udelay(150);
2040 break;
2041 }
2042 }
2043
2044 /**
2045 * Sets the power management mode of the pipe and plane.
2046 *
2047 * This code should probably grow support for turning the cursor off and back
2048 * on appropriately at the same time as we're turning the pipe off/on.
2049 */
2050 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2051 {
2052 struct drm_device *dev = crtc->dev;
2053 struct drm_i915_private *dev_priv = dev->dev_private;
2054 struct drm_i915_master_private *master_priv;
2055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2056 int pipe = intel_crtc->pipe;
2057 bool enabled;
2058
2059 dev_priv->display.dpms(crtc, mode);
2060
2061 intel_crtc->dpms_mode = mode;
2062
2063 if (!dev->primary->master)
2064 return;
2065
2066 master_priv = dev->primary->master->driver_priv;
2067 if (!master_priv->sarea_priv)
2068 return;
2069
2070 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2071
2072 switch (pipe) {
2073 case 0:
2074 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2075 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2076 break;
2077 case 1:
2078 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2079 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2080 break;
2081 default:
2082 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2083 break;
2084 }
2085 }
2086
2087 static void intel_crtc_prepare (struct drm_crtc *crtc)
2088 {
2089 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2090 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2091 }
2092
2093 static void intel_crtc_commit (struct drm_crtc *crtc)
2094 {
2095 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2096 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2097 }
2098
2099 void intel_encoder_prepare (struct drm_encoder *encoder)
2100 {
2101 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2102 /* lvds has its own version of prepare see intel_lvds_prepare */
2103 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2104 }
2105
2106 void intel_encoder_commit (struct drm_encoder *encoder)
2107 {
2108 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2109 /* lvds has its own version of commit see intel_lvds_commit */
2110 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2111 }
2112
2113 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2114 struct drm_display_mode *mode,
2115 struct drm_display_mode *adjusted_mode)
2116 {
2117 struct drm_device *dev = crtc->dev;
2118 if (HAS_PCH_SPLIT(dev)) {
2119 /* FDI link clock is fixed at 2.7G */
2120 if (mode->clock * 3 > 27000 * 4)
2121 return MODE_CLOCK_HIGH;
2122 }
2123 return true;
2124 }
2125
2126 static int i945_get_display_clock_speed(struct drm_device *dev)
2127 {
2128 return 400000;
2129 }
2130
2131 static int i915_get_display_clock_speed(struct drm_device *dev)
2132 {
2133 return 333000;
2134 }
2135
2136 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2137 {
2138 return 200000;
2139 }
2140
2141 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2142 {
2143 u16 gcfgc = 0;
2144
2145 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2146
2147 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2148 return 133000;
2149 else {
2150 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2151 case GC_DISPLAY_CLOCK_333_MHZ:
2152 return 333000;
2153 default:
2154 case GC_DISPLAY_CLOCK_190_200_MHZ:
2155 return 190000;
2156 }
2157 }
2158 }
2159
2160 static int i865_get_display_clock_speed(struct drm_device *dev)
2161 {
2162 return 266000;
2163 }
2164
2165 static int i855_get_display_clock_speed(struct drm_device *dev)
2166 {
2167 u16 hpllcc = 0;
2168 /* Assume that the hardware is in the high speed state. This
2169 * should be the default.
2170 */
2171 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2172 case GC_CLOCK_133_200:
2173 case GC_CLOCK_100_200:
2174 return 200000;
2175 case GC_CLOCK_166_250:
2176 return 250000;
2177 case GC_CLOCK_100_133:
2178 return 133000;
2179 }
2180
2181 /* Shouldn't happen */
2182 return 0;
2183 }
2184
2185 static int i830_get_display_clock_speed(struct drm_device *dev)
2186 {
2187 return 133000;
2188 }
2189
2190 /**
2191 * Return the pipe currently connected to the panel fitter,
2192 * or -1 if the panel fitter is not present or not in use
2193 */
2194 int intel_panel_fitter_pipe (struct drm_device *dev)
2195 {
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2197 u32 pfit_control;
2198
2199 /* i830 doesn't have a panel fitter */
2200 if (IS_I830(dev))
2201 return -1;
2202
2203 pfit_control = I915_READ(PFIT_CONTROL);
2204
2205 /* See if the panel fitter is in use */
2206 if ((pfit_control & PFIT_ENABLE) == 0)
2207 return -1;
2208
2209 /* 965 can place panel fitter on either pipe */
2210 if (IS_I965G(dev))
2211 return (pfit_control >> 29) & 0x3;
2212
2213 /* older chips can only use pipe 1 */
2214 return 1;
2215 }
2216
2217 struct fdi_m_n {
2218 u32 tu;
2219 u32 gmch_m;
2220 u32 gmch_n;
2221 u32 link_m;
2222 u32 link_n;
2223 };
2224
2225 static void
2226 fdi_reduce_ratio(u32 *num, u32 *den)
2227 {
2228 while (*num > 0xffffff || *den > 0xffffff) {
2229 *num >>= 1;
2230 *den >>= 1;
2231 }
2232 }
2233
2234 #define DATA_N 0x800000
2235 #define LINK_N 0x80000
2236
2237 static void
2238 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2239 int link_clock, struct fdi_m_n *m_n)
2240 {
2241 u64 temp;
2242
2243 m_n->tu = 64; /* default size */
2244
2245 temp = (u64) DATA_N * pixel_clock;
2246 temp = div_u64(temp, link_clock);
2247 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2248 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2249 m_n->gmch_n = DATA_N;
2250 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2251
2252 temp = (u64) LINK_N * pixel_clock;
2253 m_n->link_m = div_u64(temp, link_clock);
2254 m_n->link_n = LINK_N;
2255 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2256 }
2257
2258
2259 struct intel_watermark_params {
2260 unsigned long fifo_size;
2261 unsigned long max_wm;
2262 unsigned long default_wm;
2263 unsigned long guard_size;
2264 unsigned long cacheline_size;
2265 };
2266
2267 /* Pineview has different values for various configs */
2268 static struct intel_watermark_params pineview_display_wm = {
2269 PINEVIEW_DISPLAY_FIFO,
2270 PINEVIEW_MAX_WM,
2271 PINEVIEW_DFT_WM,
2272 PINEVIEW_GUARD_WM,
2273 PINEVIEW_FIFO_LINE_SIZE
2274 };
2275 static struct intel_watermark_params pineview_display_hplloff_wm = {
2276 PINEVIEW_DISPLAY_FIFO,
2277 PINEVIEW_MAX_WM,
2278 PINEVIEW_DFT_HPLLOFF_WM,
2279 PINEVIEW_GUARD_WM,
2280 PINEVIEW_FIFO_LINE_SIZE
2281 };
2282 static struct intel_watermark_params pineview_cursor_wm = {
2283 PINEVIEW_CURSOR_FIFO,
2284 PINEVIEW_CURSOR_MAX_WM,
2285 PINEVIEW_CURSOR_DFT_WM,
2286 PINEVIEW_CURSOR_GUARD_WM,
2287 PINEVIEW_FIFO_LINE_SIZE,
2288 };
2289 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2290 PINEVIEW_CURSOR_FIFO,
2291 PINEVIEW_CURSOR_MAX_WM,
2292 PINEVIEW_CURSOR_DFT_WM,
2293 PINEVIEW_CURSOR_GUARD_WM,
2294 PINEVIEW_FIFO_LINE_SIZE
2295 };
2296 static struct intel_watermark_params g4x_wm_info = {
2297 G4X_FIFO_SIZE,
2298 G4X_MAX_WM,
2299 G4X_MAX_WM,
2300 2,
2301 G4X_FIFO_LINE_SIZE,
2302 };
2303 static struct intel_watermark_params i945_wm_info = {
2304 I945_FIFO_SIZE,
2305 I915_MAX_WM,
2306 1,
2307 2,
2308 I915_FIFO_LINE_SIZE
2309 };
2310 static struct intel_watermark_params i915_wm_info = {
2311 I915_FIFO_SIZE,
2312 I915_MAX_WM,
2313 1,
2314 2,
2315 I915_FIFO_LINE_SIZE
2316 };
2317 static struct intel_watermark_params i855_wm_info = {
2318 I855GM_FIFO_SIZE,
2319 I915_MAX_WM,
2320 1,
2321 2,
2322 I830_FIFO_LINE_SIZE
2323 };
2324 static struct intel_watermark_params i830_wm_info = {
2325 I830_FIFO_SIZE,
2326 I915_MAX_WM,
2327 1,
2328 2,
2329 I830_FIFO_LINE_SIZE
2330 };
2331
2332 /**
2333 * intel_calculate_wm - calculate watermark level
2334 * @clock_in_khz: pixel clock
2335 * @wm: chip FIFO params
2336 * @pixel_size: display pixel size
2337 * @latency_ns: memory latency for the platform
2338 *
2339 * Calculate the watermark level (the level at which the display plane will
2340 * start fetching from memory again). Each chip has a different display
2341 * FIFO size and allocation, so the caller needs to figure that out and pass
2342 * in the correct intel_watermark_params structure.
2343 *
2344 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2345 * on the pixel size. When it reaches the watermark level, it'll start
2346 * fetching FIFO line sized based chunks from memory until the FIFO fills
2347 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2348 * will occur, and a display engine hang could result.
2349 */
2350 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2351 struct intel_watermark_params *wm,
2352 int pixel_size,
2353 unsigned long latency_ns)
2354 {
2355 long entries_required, wm_size;
2356
2357 /*
2358 * Note: we need to make sure we don't overflow for various clock &
2359 * latency values.
2360 * clocks go from a few thousand to several hundred thousand.
2361 * latency is usually a few thousand
2362 */
2363 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2364 1000;
2365 entries_required /= wm->cacheline_size;
2366
2367 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2368
2369 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2370
2371 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2372
2373 /* Don't promote wm_size to unsigned... */
2374 if (wm_size > (long)wm->max_wm)
2375 wm_size = wm->max_wm;
2376 if (wm_size <= 0)
2377 wm_size = wm->default_wm;
2378 return wm_size;
2379 }
2380
2381 struct cxsr_latency {
2382 int is_desktop;
2383 unsigned long fsb_freq;
2384 unsigned long mem_freq;
2385 unsigned long display_sr;
2386 unsigned long display_hpll_disable;
2387 unsigned long cursor_sr;
2388 unsigned long cursor_hpll_disable;
2389 };
2390
2391 static struct cxsr_latency cxsr_latency_table[] = {
2392 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2393 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2394 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2395
2396 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2397 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2398 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2399
2400 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2401 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2402 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2403
2404 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2405 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2406 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2407
2408 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2409 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2410 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2411
2412 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2413 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2414 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2415 };
2416
2417 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2418 int mem)
2419 {
2420 int i;
2421 struct cxsr_latency *latency;
2422
2423 if (fsb == 0 || mem == 0)
2424 return NULL;
2425
2426 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2427 latency = &cxsr_latency_table[i];
2428 if (is_desktop == latency->is_desktop &&
2429 fsb == latency->fsb_freq && mem == latency->mem_freq)
2430 return latency;
2431 }
2432
2433 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2434
2435 return NULL;
2436 }
2437
2438 static void pineview_disable_cxsr(struct drm_device *dev)
2439 {
2440 struct drm_i915_private *dev_priv = dev->dev_private;
2441 u32 reg;
2442
2443 /* deactivate cxsr */
2444 reg = I915_READ(DSPFW3);
2445 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2446 I915_WRITE(DSPFW3, reg);
2447 DRM_INFO("Big FIFO is disabled\n");
2448 }
2449
2450 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2451 int pixel_size)
2452 {
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 u32 reg;
2455 unsigned long wm;
2456 struct cxsr_latency *latency;
2457
2458 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2459 dev_priv->mem_freq);
2460 if (!latency) {
2461 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2462 pineview_disable_cxsr(dev);
2463 return;
2464 }
2465
2466 /* Display SR */
2467 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2468 latency->display_sr);
2469 reg = I915_READ(DSPFW1);
2470 reg &= 0x7fffff;
2471 reg |= wm << 23;
2472 I915_WRITE(DSPFW1, reg);
2473 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2474
2475 /* cursor SR */
2476 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2477 latency->cursor_sr);
2478 reg = I915_READ(DSPFW3);
2479 reg &= ~(0x3f << 24);
2480 reg |= (wm & 0x3f) << 24;
2481 I915_WRITE(DSPFW3, reg);
2482
2483 /* Display HPLL off SR */
2484 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2485 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2486 reg = I915_READ(DSPFW3);
2487 reg &= 0xfffffe00;
2488 reg |= wm & 0x1ff;
2489 I915_WRITE(DSPFW3, reg);
2490
2491 /* cursor HPLL off SR */
2492 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2493 latency->cursor_hpll_disable);
2494 reg = I915_READ(DSPFW3);
2495 reg &= ~(0x3f << 16);
2496 reg |= (wm & 0x3f) << 16;
2497 I915_WRITE(DSPFW3, reg);
2498 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2499
2500 /* activate cxsr */
2501 reg = I915_READ(DSPFW3);
2502 reg |= PINEVIEW_SELF_REFRESH_EN;
2503 I915_WRITE(DSPFW3, reg);
2504
2505 DRM_INFO("Big FIFO is enabled\n");
2506
2507 return;
2508 }
2509
2510 /*
2511 * Latency for FIFO fetches is dependent on several factors:
2512 * - memory configuration (speed, channels)
2513 * - chipset
2514 * - current MCH state
2515 * It can be fairly high in some situations, so here we assume a fairly
2516 * pessimal value. It's a tradeoff between extra memory fetches (if we
2517 * set this value too high, the FIFO will fetch frequently to stay full)
2518 * and power consumption (set it too low to save power and we might see
2519 * FIFO underruns and display "flicker").
2520 *
2521 * A value of 5us seems to be a good balance; safe for very low end
2522 * platforms but not overly aggressive on lower latency configs.
2523 */
2524 static const int latency_ns = 5000;
2525
2526 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2527 {
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 uint32_t dsparb = I915_READ(DSPARB);
2530 int size;
2531
2532 if (plane == 0)
2533 size = dsparb & 0x7f;
2534 else
2535 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2536 (dsparb & 0x7f);
2537
2538 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2539 plane ? "B" : "A", size);
2540
2541 return size;
2542 }
2543
2544 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2545 {
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547 uint32_t dsparb = I915_READ(DSPARB);
2548 int size;
2549
2550 if (plane == 0)
2551 size = dsparb & 0x1ff;
2552 else
2553 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2554 (dsparb & 0x1ff);
2555 size >>= 1; /* Convert to cachelines */
2556
2557 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2558 plane ? "B" : "A", size);
2559
2560 return size;
2561 }
2562
2563 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2564 {
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566 uint32_t dsparb = I915_READ(DSPARB);
2567 int size;
2568
2569 size = dsparb & 0x7f;
2570 size >>= 2; /* Convert to cachelines */
2571
2572 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2573 plane ? "B" : "A",
2574 size);
2575
2576 return size;
2577 }
2578
2579 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2580 {
2581 struct drm_i915_private *dev_priv = dev->dev_private;
2582 uint32_t dsparb = I915_READ(DSPARB);
2583 int size;
2584
2585 size = dsparb & 0x7f;
2586 size >>= 1; /* Convert to cachelines */
2587
2588 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2589 plane ? "B" : "A", size);
2590
2591 return size;
2592 }
2593
2594 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2595 int planeb_clock, int sr_hdisplay, int pixel_size)
2596 {
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 int total_size, cacheline_size;
2599 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2600 struct intel_watermark_params planea_params, planeb_params;
2601 unsigned long line_time_us;
2602 int sr_clock, sr_entries = 0, entries_required;
2603
2604 /* Create copies of the base settings for each pipe */
2605 planea_params = planeb_params = g4x_wm_info;
2606
2607 /* Grab a couple of global values before we overwrite them */
2608 total_size = planea_params.fifo_size;
2609 cacheline_size = planea_params.cacheline_size;
2610
2611 /*
2612 * Note: we need to make sure we don't overflow for various clock &
2613 * latency values.
2614 * clocks go from a few thousand to several hundred thousand.
2615 * latency is usually a few thousand
2616 */
2617 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2618 1000;
2619 entries_required /= G4X_FIFO_LINE_SIZE;
2620 planea_wm = entries_required + planea_params.guard_size;
2621
2622 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2623 1000;
2624 entries_required /= G4X_FIFO_LINE_SIZE;
2625 planeb_wm = entries_required + planeb_params.guard_size;
2626
2627 cursora_wm = cursorb_wm = 16;
2628 cursor_sr = 32;
2629
2630 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2631
2632 /* Calc sr entries for one plane configs */
2633 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2634 /* self-refresh has much higher latency */
2635 static const int sr_latency_ns = 12000;
2636
2637 sr_clock = planea_clock ? planea_clock : planeb_clock;
2638 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2639
2640 /* Use ns/us then divide to preserve precision */
2641 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2642 pixel_size * sr_hdisplay) / 1000;
2643 sr_entries = roundup(sr_entries / cacheline_size, 1);
2644 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2645 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2646 } else {
2647 /* Turn off self refresh if both pipes are enabled */
2648 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2649 & ~FW_BLC_SELF_EN);
2650 }
2651
2652 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2653 planea_wm, planeb_wm, sr_entries);
2654
2655 planea_wm &= 0x3f;
2656 planeb_wm &= 0x3f;
2657
2658 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2659 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2660 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2661 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2662 (cursora_wm << DSPFW_CURSORA_SHIFT));
2663 /* HPLL off in SR has some issues on G4x... disable it */
2664 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2665 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2666 }
2667
2668 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2669 int planeb_clock, int sr_hdisplay, int pixel_size)
2670 {
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 unsigned long line_time_us;
2673 int sr_clock, sr_entries, srwm = 1;
2674
2675 /* Calc sr entries for one plane configs */
2676 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2677 /* self-refresh has much higher latency */
2678 static const int sr_latency_ns = 12000;
2679
2680 sr_clock = planea_clock ? planea_clock : planeb_clock;
2681 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2682
2683 /* Use ns/us then divide to preserve precision */
2684 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2685 pixel_size * sr_hdisplay) / 1000;
2686 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2687 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2688 srwm = I945_FIFO_SIZE - sr_entries;
2689 if (srwm < 0)
2690 srwm = 1;
2691 srwm &= 0x3f;
2692 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2693 } else {
2694 /* Turn off self refresh if both pipes are enabled */
2695 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2696 & ~FW_BLC_SELF_EN);
2697 }
2698
2699 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2700 srwm);
2701
2702 /* 965 has limitations... */
2703 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2704 (8 << 0));
2705 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2706 }
2707
2708 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2709 int planeb_clock, int sr_hdisplay, int pixel_size)
2710 {
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 uint32_t fwater_lo;
2713 uint32_t fwater_hi;
2714 int total_size, cacheline_size, cwm, srwm = 1;
2715 int planea_wm, planeb_wm;
2716 struct intel_watermark_params planea_params, planeb_params;
2717 unsigned long line_time_us;
2718 int sr_clock, sr_entries = 0;
2719
2720 /* Create copies of the base settings for each pipe */
2721 if (IS_I965GM(dev) || IS_I945GM(dev))
2722 planea_params = planeb_params = i945_wm_info;
2723 else if (IS_I9XX(dev))
2724 planea_params = planeb_params = i915_wm_info;
2725 else
2726 planea_params = planeb_params = i855_wm_info;
2727
2728 /* Grab a couple of global values before we overwrite them */
2729 total_size = planea_params.fifo_size;
2730 cacheline_size = planea_params.cacheline_size;
2731
2732 /* Update per-plane FIFO sizes */
2733 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2734 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2735
2736 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2737 pixel_size, latency_ns);
2738 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2739 pixel_size, latency_ns);
2740 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2741
2742 /*
2743 * Overlay gets an aggressive default since video jitter is bad.
2744 */
2745 cwm = 2;
2746
2747 /* Calc sr entries for one plane configs */
2748 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2749 (!planea_clock || !planeb_clock)) {
2750 /* self-refresh has much higher latency */
2751 static const int sr_latency_ns = 6000;
2752
2753 sr_clock = planea_clock ? planea_clock : planeb_clock;
2754 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2755
2756 /* Use ns/us then divide to preserve precision */
2757 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2758 pixel_size * sr_hdisplay) / 1000;
2759 sr_entries = roundup(sr_entries / cacheline_size, 1);
2760 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2761 srwm = total_size - sr_entries;
2762 if (srwm < 0)
2763 srwm = 1;
2764
2765 if (IS_I945G(dev) || IS_I945GM(dev))
2766 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2767 else if (IS_I915GM(dev)) {
2768 /* 915M has a smaller SRWM field */
2769 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2770 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2771 }
2772 } else {
2773 /* Turn off self refresh if both pipes are enabled */
2774 if (IS_I945G(dev) || IS_I945GM(dev)) {
2775 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2776 & ~FW_BLC_SELF_EN);
2777 } else if (IS_I915GM(dev)) {
2778 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2779 }
2780 }
2781
2782 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2783 planea_wm, planeb_wm, cwm, srwm);
2784
2785 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2786 fwater_hi = (cwm & 0x1f);
2787
2788 /* Set request length to 8 cachelines per fetch */
2789 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2790 fwater_hi = fwater_hi | (1 << 8);
2791
2792 I915_WRITE(FW_BLC, fwater_lo);
2793 I915_WRITE(FW_BLC2, fwater_hi);
2794 }
2795
2796 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2797 int unused2, int pixel_size)
2798 {
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2801 int planea_wm;
2802
2803 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2804
2805 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2806 pixel_size, latency_ns);
2807 fwater_lo |= (3<<8) | planea_wm;
2808
2809 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2810
2811 I915_WRITE(FW_BLC, fwater_lo);
2812 }
2813
2814 /**
2815 * intel_update_watermarks - update FIFO watermark values based on current modes
2816 *
2817 * Calculate watermark values for the various WM regs based on current mode
2818 * and plane configuration.
2819 *
2820 * There are several cases to deal with here:
2821 * - normal (i.e. non-self-refresh)
2822 * - self-refresh (SR) mode
2823 * - lines are large relative to FIFO size (buffer can hold up to 2)
2824 * - lines are small relative to FIFO size (buffer can hold more than 2
2825 * lines), so need to account for TLB latency
2826 *
2827 * The normal calculation is:
2828 * watermark = dotclock * bytes per pixel * latency
2829 * where latency is platform & configuration dependent (we assume pessimal
2830 * values here).
2831 *
2832 * The SR calculation is:
2833 * watermark = (trunc(latency/line time)+1) * surface width *
2834 * bytes per pixel
2835 * where
2836 * line time = htotal / dotclock
2837 * and latency is assumed to be high, as above.
2838 *
2839 * The final value programmed to the register should always be rounded up,
2840 * and include an extra 2 entries to account for clock crossings.
2841 *
2842 * We don't use the sprite, so we can ignore that. And on Crestline we have
2843 * to set the non-SR watermarks to 8.
2844 */
2845 static void intel_update_watermarks(struct drm_device *dev)
2846 {
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848 struct drm_crtc *crtc;
2849 struct intel_crtc *intel_crtc;
2850 int sr_hdisplay = 0;
2851 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2852 int enabled = 0, pixel_size = 0;
2853
2854 if (!dev_priv->display.update_wm)
2855 return;
2856
2857 /* Get the clock config from both planes */
2858 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2859 intel_crtc = to_intel_crtc(crtc);
2860 if (crtc->enabled) {
2861 enabled++;
2862 if (intel_crtc->plane == 0) {
2863 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2864 intel_crtc->pipe, crtc->mode.clock);
2865 planea_clock = crtc->mode.clock;
2866 } else {
2867 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2868 intel_crtc->pipe, crtc->mode.clock);
2869 planeb_clock = crtc->mode.clock;
2870 }
2871 sr_hdisplay = crtc->mode.hdisplay;
2872 sr_clock = crtc->mode.clock;
2873 if (crtc->fb)
2874 pixel_size = crtc->fb->bits_per_pixel / 8;
2875 else
2876 pixel_size = 4; /* by default */
2877 }
2878 }
2879
2880 if (enabled <= 0)
2881 return;
2882
2883 /* Single plane configs can enable self refresh */
2884 if (enabled == 1 && IS_PINEVIEW(dev))
2885 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2886 else if (IS_PINEVIEW(dev))
2887 pineview_disable_cxsr(dev);
2888
2889 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2890 sr_hdisplay, pixel_size);
2891 }
2892
2893 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2894 struct drm_display_mode *mode,
2895 struct drm_display_mode *adjusted_mode,
2896 int x, int y,
2897 struct drm_framebuffer *old_fb)
2898 {
2899 struct drm_device *dev = crtc->dev;
2900 struct drm_i915_private *dev_priv = dev->dev_private;
2901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2902 int pipe = intel_crtc->pipe;
2903 int plane = intel_crtc->plane;
2904 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2905 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2906 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2907 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2908 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2909 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2910 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2911 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2912 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2913 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2914 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2915 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2916 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2917 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2918 int refclk, num_connectors = 0;
2919 intel_clock_t clock, reduced_clock;
2920 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2921 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2922 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2923 bool is_edp = false;
2924 struct drm_mode_config *mode_config = &dev->mode_config;
2925 struct drm_encoder *encoder;
2926 struct intel_encoder *intel_encoder;
2927 const intel_limit_t *limit;
2928 int ret;
2929 struct fdi_m_n m_n = {0};
2930 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2931 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2932 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2933 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2934 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2935 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2936 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2937 int lvds_reg = LVDS;
2938 u32 temp;
2939 int sdvo_pixel_multiply;
2940 int target_clock;
2941
2942 drm_vblank_pre_modeset(dev, pipe);
2943
2944 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2945
2946 if (!encoder || encoder->crtc != crtc)
2947 continue;
2948
2949 intel_encoder = enc_to_intel_encoder(encoder);
2950
2951 switch (intel_encoder->type) {
2952 case INTEL_OUTPUT_LVDS:
2953 is_lvds = true;
2954 break;
2955 case INTEL_OUTPUT_SDVO:
2956 case INTEL_OUTPUT_HDMI:
2957 is_sdvo = true;
2958 if (intel_encoder->needs_tv_clock)
2959 is_tv = true;
2960 break;
2961 case INTEL_OUTPUT_DVO:
2962 is_dvo = true;
2963 break;
2964 case INTEL_OUTPUT_TVOUT:
2965 is_tv = true;
2966 break;
2967 case INTEL_OUTPUT_ANALOG:
2968 is_crt = true;
2969 break;
2970 case INTEL_OUTPUT_DISPLAYPORT:
2971 is_dp = true;
2972 break;
2973 case INTEL_OUTPUT_EDP:
2974 is_edp = true;
2975 break;
2976 }
2977
2978 num_connectors++;
2979 }
2980
2981 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
2982 refclk = dev_priv->lvds_ssc_freq * 1000;
2983 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2984 refclk / 1000);
2985 } else if (IS_I9XX(dev)) {
2986 refclk = 96000;
2987 if (HAS_PCH_SPLIT(dev))
2988 refclk = 120000; /* 120Mhz refclk */
2989 } else {
2990 refclk = 48000;
2991 }
2992
2993
2994 /*
2995 * Returns a set of divisors for the desired target clock with the given
2996 * refclk, or FALSE. The returned values represent the clock equation:
2997 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2998 */
2999 limit = intel_limit(crtc);
3000 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3001 if (!ok) {
3002 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3003 drm_vblank_post_modeset(dev, pipe);
3004 return -EINVAL;
3005 }
3006
3007 if (is_lvds && dev_priv->lvds_downclock_avail) {
3008 has_reduced_clock = limit->find_pll(limit, crtc,
3009 dev_priv->lvds_downclock,
3010 refclk,
3011 &reduced_clock);
3012 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3013 /*
3014 * If the different P is found, it means that we can't
3015 * switch the display clock by using the FP0/FP1.
3016 * In such case we will disable the LVDS downclock
3017 * feature.
3018 */
3019 DRM_DEBUG_KMS("Different P is found for "
3020 "LVDS clock/downclock\n");
3021 has_reduced_clock = 0;
3022 }
3023 }
3024 /* SDVO TV has fixed PLL values depend on its clock range,
3025 this mirrors vbios setting. */
3026 if (is_sdvo && is_tv) {
3027 if (adjusted_mode->clock >= 100000
3028 && adjusted_mode->clock < 140500) {
3029 clock.p1 = 2;
3030 clock.p2 = 10;
3031 clock.n = 3;
3032 clock.m1 = 16;
3033 clock.m2 = 8;
3034 } else if (adjusted_mode->clock >= 140500
3035 && adjusted_mode->clock <= 200000) {
3036 clock.p1 = 1;
3037 clock.p2 = 10;
3038 clock.n = 6;
3039 clock.m1 = 12;
3040 clock.m2 = 8;
3041 }
3042 }
3043
3044 /* FDI link */
3045 if (HAS_PCH_SPLIT(dev)) {
3046 int lane, link_bw, bpp;
3047 /* eDP doesn't require FDI link, so just set DP M/N
3048 according to current link config */
3049 if (is_edp) {
3050 struct drm_connector *edp;
3051 target_clock = mode->clock;
3052 edp = intel_pipe_get_connector(crtc);
3053 intel_edp_link_config(to_intel_encoder(edp),
3054 &lane, &link_bw);
3055 } else {
3056 /* DP over FDI requires target mode clock
3057 instead of link clock */
3058 if (is_dp)
3059 target_clock = mode->clock;
3060 else
3061 target_clock = adjusted_mode->clock;
3062 lane = 4;
3063 link_bw = 270000;
3064 }
3065
3066 /* determine panel color depth */
3067 temp = I915_READ(pipeconf_reg);
3068 temp &= ~PIPE_BPC_MASK;
3069 if (is_lvds) {
3070 int lvds_reg = I915_READ(PCH_LVDS);
3071 /* the BPC will be 6 if it is 18-bit LVDS panel */
3072 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3073 temp |= PIPE_8BPC;
3074 else
3075 temp |= PIPE_6BPC;
3076 } else if (is_edp) {
3077 switch (dev_priv->edp_bpp/3) {
3078 case 8:
3079 temp |= PIPE_8BPC;
3080 break;
3081 case 10:
3082 temp |= PIPE_10BPC;
3083 break;
3084 case 6:
3085 temp |= PIPE_6BPC;
3086 break;
3087 case 12:
3088 temp |= PIPE_12BPC;
3089 break;
3090 }
3091 } else
3092 temp |= PIPE_8BPC;
3093 I915_WRITE(pipeconf_reg, temp);
3094 I915_READ(pipeconf_reg);
3095
3096 switch (temp & PIPE_BPC_MASK) {
3097 case PIPE_8BPC:
3098 bpp = 24;
3099 break;
3100 case PIPE_10BPC:
3101 bpp = 30;
3102 break;
3103 case PIPE_6BPC:
3104 bpp = 18;
3105 break;
3106 case PIPE_12BPC:
3107 bpp = 36;
3108 break;
3109 default:
3110 DRM_ERROR("unknown pipe bpc value\n");
3111 bpp = 24;
3112 }
3113
3114 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3115 }
3116
3117 /* Ironlake: try to setup display ref clock before DPLL
3118 * enabling. This is only under driver's control after
3119 * PCH B stepping, previous chipset stepping should be
3120 * ignoring this setting.
3121 */
3122 if (HAS_PCH_SPLIT(dev)) {
3123 temp = I915_READ(PCH_DREF_CONTROL);
3124 /* Always enable nonspread source */
3125 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3126 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3127 I915_WRITE(PCH_DREF_CONTROL, temp);
3128 POSTING_READ(PCH_DREF_CONTROL);
3129
3130 temp &= ~DREF_SSC_SOURCE_MASK;
3131 temp |= DREF_SSC_SOURCE_ENABLE;
3132 I915_WRITE(PCH_DREF_CONTROL, temp);
3133 POSTING_READ(PCH_DREF_CONTROL);
3134
3135 udelay(200);
3136
3137 if (is_edp) {
3138 if (dev_priv->lvds_use_ssc) {
3139 temp |= DREF_SSC1_ENABLE;
3140 I915_WRITE(PCH_DREF_CONTROL, temp);
3141 POSTING_READ(PCH_DREF_CONTROL);
3142
3143 udelay(200);
3144
3145 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3146 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3147 I915_WRITE(PCH_DREF_CONTROL, temp);
3148 POSTING_READ(PCH_DREF_CONTROL);
3149 } else {
3150 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3151 I915_WRITE(PCH_DREF_CONTROL, temp);
3152 POSTING_READ(PCH_DREF_CONTROL);
3153 }
3154 }
3155 }
3156
3157 if (IS_PINEVIEW(dev)) {
3158 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3159 if (has_reduced_clock)
3160 fp2 = (1 << reduced_clock.n) << 16 |
3161 reduced_clock.m1 << 8 | reduced_clock.m2;
3162 } else {
3163 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3164 if (has_reduced_clock)
3165 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3166 reduced_clock.m2;
3167 }
3168
3169 if (!HAS_PCH_SPLIT(dev))
3170 dpll = DPLL_VGA_MODE_DIS;
3171
3172 if (IS_I9XX(dev)) {
3173 if (is_lvds)
3174 dpll |= DPLLB_MODE_LVDS;
3175 else
3176 dpll |= DPLLB_MODE_DAC_SERIAL;
3177 if (is_sdvo) {
3178 dpll |= DPLL_DVO_HIGH_SPEED;
3179 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3180 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3181 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3182 else if (HAS_PCH_SPLIT(dev))
3183 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3184 }
3185 if (is_dp)
3186 dpll |= DPLL_DVO_HIGH_SPEED;
3187
3188 /* compute bitmask from p1 value */
3189 if (IS_PINEVIEW(dev))
3190 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3191 else {
3192 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3193 /* also FPA1 */
3194 if (HAS_PCH_SPLIT(dev))
3195 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3196 if (IS_G4X(dev) && has_reduced_clock)
3197 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3198 }
3199 switch (clock.p2) {
3200 case 5:
3201 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3202 break;
3203 case 7:
3204 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3205 break;
3206 case 10:
3207 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3208 break;
3209 case 14:
3210 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3211 break;
3212 }
3213 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3214 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3215 } else {
3216 if (is_lvds) {
3217 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3218 } else {
3219 if (clock.p1 == 2)
3220 dpll |= PLL_P1_DIVIDE_BY_TWO;
3221 else
3222 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3223 if (clock.p2 == 4)
3224 dpll |= PLL_P2_DIVIDE_BY_4;
3225 }
3226 }
3227
3228 if (is_sdvo && is_tv)
3229 dpll |= PLL_REF_INPUT_TVCLKINBC;
3230 else if (is_tv)
3231 /* XXX: just matching BIOS for now */
3232 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3233 dpll |= 3;
3234 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3235 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3236 else
3237 dpll |= PLL_REF_INPUT_DREFCLK;
3238
3239 /* setup pipeconf */
3240 pipeconf = I915_READ(pipeconf_reg);
3241
3242 /* Set up the display plane register */
3243 dspcntr = DISPPLANE_GAMMA_ENABLE;
3244
3245 /* Ironlake's plane is forced to pipe, bit 24 is to
3246 enable color space conversion */
3247 if (!HAS_PCH_SPLIT(dev)) {
3248 if (pipe == 0)
3249 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3250 else
3251 dspcntr |= DISPPLANE_SEL_PIPE_B;
3252 }
3253
3254 if (pipe == 0 && !IS_I965G(dev)) {
3255 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3256 * core speed.
3257 *
3258 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3259 * pipe == 0 check?
3260 */
3261 if (mode->clock >
3262 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3263 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3264 else
3265 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3266 }
3267
3268 dspcntr |= DISPLAY_PLANE_ENABLE;
3269 pipeconf |= PIPEACONF_ENABLE;
3270 dpll |= DPLL_VCO_ENABLE;
3271
3272
3273 /* Disable the panel fitter if it was on our pipe */
3274 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3275 I915_WRITE(PFIT_CONTROL, 0);
3276
3277 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3278 drm_mode_debug_printmodeline(mode);
3279
3280 /* assign to Ironlake registers */
3281 if (HAS_PCH_SPLIT(dev)) {
3282 fp_reg = pch_fp_reg;
3283 dpll_reg = pch_dpll_reg;
3284 }
3285
3286 if (is_edp) {
3287 ironlake_disable_pll_edp(crtc);
3288 } else if ((dpll & DPLL_VCO_ENABLE)) {
3289 I915_WRITE(fp_reg, fp);
3290 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3291 I915_READ(dpll_reg);
3292 udelay(150);
3293 }
3294
3295 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3296 * This is an exception to the general rule that mode_set doesn't turn
3297 * things on.
3298 */
3299 if (is_lvds) {
3300 u32 lvds;
3301
3302 if (HAS_PCH_SPLIT(dev))
3303 lvds_reg = PCH_LVDS;
3304
3305 lvds = I915_READ(lvds_reg);
3306 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3307 if (pipe == 1)
3308 lvds |= LVDS_PIPEB_SELECT;
3309 /* set the corresponsding LVDS_BORDER bit */
3310 lvds |= dev_priv->lvds_border_bits;
3311 /* Set the B0-B3 data pairs corresponding to whether we're going to
3312 * set the DPLLs for dual-channel mode or not.
3313 */
3314 if (clock.p2 == 7)
3315 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3316 else
3317 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3318
3319 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3320 * appropriately here, but we need to look more thoroughly into how
3321 * panels behave in the two modes.
3322 */
3323 /* set the dithering flag */
3324 if (IS_I965G(dev)) {
3325 if (dev_priv->lvds_dither) {
3326 if (HAS_PCH_SPLIT(dev))
3327 pipeconf |= PIPE_ENABLE_DITHER;
3328 else
3329 lvds |= LVDS_ENABLE_DITHER;
3330 } else {
3331 if (HAS_PCH_SPLIT(dev))
3332 pipeconf &= ~PIPE_ENABLE_DITHER;
3333 else
3334 lvds &= ~LVDS_ENABLE_DITHER;
3335 }
3336 }
3337 I915_WRITE(lvds_reg, lvds);
3338 I915_READ(lvds_reg);
3339 }
3340 if (is_dp)
3341 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3342
3343 if (!is_edp) {
3344 I915_WRITE(fp_reg, fp);
3345 I915_WRITE(dpll_reg, dpll);
3346 I915_READ(dpll_reg);
3347 /* Wait for the clocks to stabilize. */
3348 udelay(150);
3349
3350 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3351 if (is_sdvo) {
3352 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3353 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3354 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3355 } else
3356 I915_WRITE(dpll_md_reg, 0);
3357 } else {
3358 /* write it again -- the BIOS does, after all */
3359 I915_WRITE(dpll_reg, dpll);
3360 }
3361 I915_READ(dpll_reg);
3362 /* Wait for the clocks to stabilize. */
3363 udelay(150);
3364 }
3365
3366 if (is_lvds && has_reduced_clock && i915_powersave) {
3367 I915_WRITE(fp_reg + 4, fp2);
3368 intel_crtc->lowfreq_avail = true;
3369 if (HAS_PIPE_CXSR(dev)) {
3370 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3371 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3372 }
3373 } else {
3374 I915_WRITE(fp_reg + 4, fp);
3375 intel_crtc->lowfreq_avail = false;
3376 if (HAS_PIPE_CXSR(dev)) {
3377 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3378 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3379 }
3380 }
3381
3382 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3383 ((adjusted_mode->crtc_htotal - 1) << 16));
3384 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3385 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3386 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3387 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3388 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3389 ((adjusted_mode->crtc_vtotal - 1) << 16));
3390 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3391 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3392 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3393 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3394 /* pipesrc and dspsize control the size that is scaled from, which should
3395 * always be the user's requested size.
3396 */
3397 if (!HAS_PCH_SPLIT(dev)) {
3398 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3399 (mode->hdisplay - 1));
3400 I915_WRITE(dsppos_reg, 0);
3401 }
3402 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3403
3404 if (HAS_PCH_SPLIT(dev)) {
3405 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3406 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3407 I915_WRITE(link_m1_reg, m_n.link_m);
3408 I915_WRITE(link_n1_reg, m_n.link_n);
3409
3410 if (is_edp) {
3411 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3412 } else {
3413 /* enable FDI RX PLL too */
3414 temp = I915_READ(fdi_rx_reg);
3415 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3416 udelay(200);
3417 }
3418 }
3419
3420 I915_WRITE(pipeconf_reg, pipeconf);
3421 I915_READ(pipeconf_reg);
3422
3423 intel_wait_for_vblank(dev);
3424
3425 if (IS_IRONLAKE(dev)) {
3426 /* enable address swizzle for tiling buffer */
3427 temp = I915_READ(DISP_ARB_CTL);
3428 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3429 }
3430
3431 I915_WRITE(dspcntr_reg, dspcntr);
3432
3433 /* Flush the plane changes */
3434 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3435
3436 if ((IS_I965G(dev) || plane == 0))
3437 intel_update_fbc(crtc, &crtc->mode);
3438
3439 intel_update_watermarks(dev);
3440
3441 drm_vblank_post_modeset(dev, pipe);
3442
3443 return ret;
3444 }
3445
3446 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3447 void intel_crtc_load_lut(struct drm_crtc *crtc)
3448 {
3449 struct drm_device *dev = crtc->dev;
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3453 int i;
3454
3455 /* The clocks have to be on to load the palette. */
3456 if (!crtc->enabled)
3457 return;
3458
3459 /* use legacy palette for Ironlake */
3460 if (HAS_PCH_SPLIT(dev))
3461 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3462 LGC_PALETTE_B;
3463
3464 for (i = 0; i < 256; i++) {
3465 I915_WRITE(palreg + 4 * i,
3466 (intel_crtc->lut_r[i] << 16) |
3467 (intel_crtc->lut_g[i] << 8) |
3468 intel_crtc->lut_b[i]);
3469 }
3470 }
3471
3472 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3473 struct drm_file *file_priv,
3474 uint32_t handle,
3475 uint32_t width, uint32_t height)
3476 {
3477 struct drm_device *dev = crtc->dev;
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480 struct drm_gem_object *bo;
3481 struct drm_i915_gem_object *obj_priv;
3482 int pipe = intel_crtc->pipe;
3483 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3484 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3485 uint32_t temp = I915_READ(control);
3486 size_t addr;
3487 int ret;
3488
3489 DRM_DEBUG_KMS("\n");
3490
3491 /* if we want to turn off the cursor ignore width and height */
3492 if (!handle) {
3493 DRM_DEBUG_KMS("cursor off\n");
3494 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3495 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3496 temp |= CURSOR_MODE_DISABLE;
3497 } else {
3498 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3499 }
3500 addr = 0;
3501 bo = NULL;
3502 mutex_lock(&dev->struct_mutex);
3503 goto finish;
3504 }
3505
3506 /* Currently we only support 64x64 cursors */
3507 if (width != 64 || height != 64) {
3508 DRM_ERROR("we currently only support 64x64 cursors\n");
3509 return -EINVAL;
3510 }
3511
3512 bo = drm_gem_object_lookup(dev, file_priv, handle);
3513 if (!bo)
3514 return -ENOENT;
3515
3516 obj_priv = to_intel_bo(bo);
3517
3518 if (bo->size < width * height * 4) {
3519 DRM_ERROR("buffer is to small\n");
3520 ret = -ENOMEM;
3521 goto fail;
3522 }
3523
3524 /* we only need to pin inside GTT if cursor is non-phy */
3525 mutex_lock(&dev->struct_mutex);
3526 if (!dev_priv->info->cursor_needs_physical) {
3527 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3528 if (ret) {
3529 DRM_ERROR("failed to pin cursor bo\n");
3530 goto fail_locked;
3531 }
3532 addr = obj_priv->gtt_offset;
3533 } else {
3534 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3535 if (ret) {
3536 DRM_ERROR("failed to attach phys object\n");
3537 goto fail_locked;
3538 }
3539 addr = obj_priv->phys_obj->handle->busaddr;
3540 }
3541
3542 if (!IS_I9XX(dev))
3543 I915_WRITE(CURSIZE, (height << 12) | width);
3544
3545 /* Hooray for CUR*CNTR differences */
3546 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3547 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3548 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3549 temp |= (pipe << 28); /* Connect to correct pipe */
3550 } else {
3551 temp &= ~(CURSOR_FORMAT_MASK);
3552 temp |= CURSOR_ENABLE;
3553 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3554 }
3555
3556 finish:
3557 I915_WRITE(control, temp);
3558 I915_WRITE(base, addr);
3559
3560 if (intel_crtc->cursor_bo) {
3561 if (dev_priv->info->cursor_needs_physical) {
3562 if (intel_crtc->cursor_bo != bo)
3563 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3564 } else
3565 i915_gem_object_unpin(intel_crtc->cursor_bo);
3566 drm_gem_object_unreference(intel_crtc->cursor_bo);
3567 }
3568
3569 mutex_unlock(&dev->struct_mutex);
3570
3571 intel_crtc->cursor_addr = addr;
3572 intel_crtc->cursor_bo = bo;
3573
3574 return 0;
3575 fail_locked:
3576 mutex_unlock(&dev->struct_mutex);
3577 fail:
3578 drm_gem_object_unreference_unlocked(bo);
3579 return ret;
3580 }
3581
3582 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3583 {
3584 struct drm_device *dev = crtc->dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3587 struct intel_framebuffer *intel_fb;
3588 int pipe = intel_crtc->pipe;
3589 uint32_t temp = 0;
3590 uint32_t adder;
3591
3592 if (crtc->fb) {
3593 intel_fb = to_intel_framebuffer(crtc->fb);
3594 intel_mark_busy(dev, intel_fb->obj);
3595 }
3596
3597 if (x < 0) {
3598 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3599 x = -x;
3600 }
3601 if (y < 0) {
3602 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3603 y = -y;
3604 }
3605
3606 temp |= x << CURSOR_X_SHIFT;
3607 temp |= y << CURSOR_Y_SHIFT;
3608
3609 adder = intel_crtc->cursor_addr;
3610 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3611 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3612
3613 return 0;
3614 }
3615
3616 /** Sets the color ramps on behalf of RandR */
3617 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3618 u16 blue, int regno)
3619 {
3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621
3622 intel_crtc->lut_r[regno] = red >> 8;
3623 intel_crtc->lut_g[regno] = green >> 8;
3624 intel_crtc->lut_b[regno] = blue >> 8;
3625 }
3626
3627 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3628 u16 *blue, int regno)
3629 {
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631
3632 *red = intel_crtc->lut_r[regno] << 8;
3633 *green = intel_crtc->lut_g[regno] << 8;
3634 *blue = intel_crtc->lut_b[regno] << 8;
3635 }
3636
3637 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3638 u16 *blue, uint32_t size)
3639 {
3640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3641 int i;
3642
3643 if (size != 256)
3644 return;
3645
3646 for (i = 0; i < 256; i++) {
3647 intel_crtc->lut_r[i] = red[i] >> 8;
3648 intel_crtc->lut_g[i] = green[i] >> 8;
3649 intel_crtc->lut_b[i] = blue[i] >> 8;
3650 }
3651
3652 intel_crtc_load_lut(crtc);
3653 }
3654
3655 /**
3656 * Get a pipe with a simple mode set on it for doing load-based monitor
3657 * detection.
3658 *
3659 * It will be up to the load-detect code to adjust the pipe as appropriate for
3660 * its requirements. The pipe will be connected to no other encoders.
3661 *
3662 * Currently this code will only succeed if there is a pipe with no encoders
3663 * configured for it. In the future, it could choose to temporarily disable
3664 * some outputs to free up a pipe for its use.
3665 *
3666 * \return crtc, or NULL if no pipes are available.
3667 */
3668
3669 /* VESA 640x480x72Hz mode to set on the pipe */
3670 static struct drm_display_mode load_detect_mode = {
3671 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3672 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3673 };
3674
3675 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3676 struct drm_connector *connector,
3677 struct drm_display_mode *mode,
3678 int *dpms_mode)
3679 {
3680 struct intel_crtc *intel_crtc;
3681 struct drm_crtc *possible_crtc;
3682 struct drm_crtc *supported_crtc =NULL;
3683 struct drm_encoder *encoder = &intel_encoder->enc;
3684 struct drm_crtc *crtc = NULL;
3685 struct drm_device *dev = encoder->dev;
3686 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3687 struct drm_crtc_helper_funcs *crtc_funcs;
3688 int i = -1;
3689
3690 /*
3691 * Algorithm gets a little messy:
3692 * - if the connector already has an assigned crtc, use it (but make
3693 * sure it's on first)
3694 * - try to find the first unused crtc that can drive this connector,
3695 * and use that if we find one
3696 * - if there are no unused crtcs available, try to use the first
3697 * one we found that supports the connector
3698 */
3699
3700 /* See if we already have a CRTC for this connector */
3701 if (encoder->crtc) {
3702 crtc = encoder->crtc;
3703 /* Make sure the crtc and connector are running */
3704 intel_crtc = to_intel_crtc(crtc);
3705 *dpms_mode = intel_crtc->dpms_mode;
3706 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3707 crtc_funcs = crtc->helper_private;
3708 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3709 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3710 }
3711 return crtc;
3712 }
3713
3714 /* Find an unused one (if possible) */
3715 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3716 i++;
3717 if (!(encoder->possible_crtcs & (1 << i)))
3718 continue;
3719 if (!possible_crtc->enabled) {
3720 crtc = possible_crtc;
3721 break;
3722 }
3723 if (!supported_crtc)
3724 supported_crtc = possible_crtc;
3725 }
3726
3727 /*
3728 * If we didn't find an unused CRTC, don't use any.
3729 */
3730 if (!crtc) {
3731 return NULL;
3732 }
3733
3734 encoder->crtc = crtc;
3735 connector->encoder = encoder;
3736 intel_encoder->load_detect_temp = true;
3737
3738 intel_crtc = to_intel_crtc(crtc);
3739 *dpms_mode = intel_crtc->dpms_mode;
3740
3741 if (!crtc->enabled) {
3742 if (!mode)
3743 mode = &load_detect_mode;
3744 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3745 } else {
3746 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3747 crtc_funcs = crtc->helper_private;
3748 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3749 }
3750
3751 /* Add this connector to the crtc */
3752 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3753 encoder_funcs->commit(encoder);
3754 }
3755 /* let the connector get through one full cycle before testing */
3756 intel_wait_for_vblank(dev);
3757
3758 return crtc;
3759 }
3760
3761 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
3762 struct drm_connector *connector, int dpms_mode)
3763 {
3764 struct drm_encoder *encoder = &intel_encoder->enc;
3765 struct drm_device *dev = encoder->dev;
3766 struct drm_crtc *crtc = encoder->crtc;
3767 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3768 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3769
3770 if (intel_encoder->load_detect_temp) {
3771 encoder->crtc = NULL;
3772 connector->encoder = NULL;
3773 intel_encoder->load_detect_temp = false;
3774 crtc->enabled = drm_helper_crtc_in_use(crtc);
3775 drm_helper_disable_unused_functions(dev);
3776 }
3777
3778 /* Switch crtc and encoder back off if necessary */
3779 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3780 if (encoder->crtc == crtc)
3781 encoder_funcs->dpms(encoder, dpms_mode);
3782 crtc_funcs->dpms(crtc, dpms_mode);
3783 }
3784 }
3785
3786 /* Returns the clock of the currently programmed mode of the given pipe. */
3787 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3788 {
3789 struct drm_i915_private *dev_priv = dev->dev_private;
3790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3791 int pipe = intel_crtc->pipe;
3792 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3793 u32 fp;
3794 intel_clock_t clock;
3795
3796 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3797 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3798 else
3799 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3800
3801 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3802 if (IS_PINEVIEW(dev)) {
3803 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3804 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3805 } else {
3806 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3807 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3808 }
3809
3810 if (IS_I9XX(dev)) {
3811 if (IS_PINEVIEW(dev))
3812 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3813 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3814 else
3815 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3816 DPLL_FPA01_P1_POST_DIV_SHIFT);
3817
3818 switch (dpll & DPLL_MODE_MASK) {
3819 case DPLLB_MODE_DAC_SERIAL:
3820 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3821 5 : 10;
3822 break;
3823 case DPLLB_MODE_LVDS:
3824 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3825 7 : 14;
3826 break;
3827 default:
3828 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3829 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3830 return 0;
3831 }
3832
3833 /* XXX: Handle the 100Mhz refclk */
3834 intel_clock(dev, 96000, &clock);
3835 } else {
3836 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3837
3838 if (is_lvds) {
3839 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3840 DPLL_FPA01_P1_POST_DIV_SHIFT);
3841 clock.p2 = 14;
3842
3843 if ((dpll & PLL_REF_INPUT_MASK) ==
3844 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3845 /* XXX: might not be 66MHz */
3846 intel_clock(dev, 66000, &clock);
3847 } else
3848 intel_clock(dev, 48000, &clock);
3849 } else {
3850 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3851 clock.p1 = 2;
3852 else {
3853 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3854 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3855 }
3856 if (dpll & PLL_P2_DIVIDE_BY_4)
3857 clock.p2 = 4;
3858 else
3859 clock.p2 = 2;
3860
3861 intel_clock(dev, 48000, &clock);
3862 }
3863 }
3864
3865 /* XXX: It would be nice to validate the clocks, but we can't reuse
3866 * i830PllIsValid() because it relies on the xf86_config connector
3867 * configuration being accurate, which it isn't necessarily.
3868 */
3869
3870 return clock.dot;
3871 }
3872
3873 /** Returns the currently programmed mode of the given pipe. */
3874 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3875 struct drm_crtc *crtc)
3876 {
3877 struct drm_i915_private *dev_priv = dev->dev_private;
3878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3879 int pipe = intel_crtc->pipe;
3880 struct drm_display_mode *mode;
3881 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3882 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3883 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3884 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3885
3886 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3887 if (!mode)
3888 return NULL;
3889
3890 mode->clock = intel_crtc_clock_get(dev, crtc);
3891 mode->hdisplay = (htot & 0xffff) + 1;
3892 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3893 mode->hsync_start = (hsync & 0xffff) + 1;
3894 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3895 mode->vdisplay = (vtot & 0xffff) + 1;
3896 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3897 mode->vsync_start = (vsync & 0xffff) + 1;
3898 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3899
3900 drm_mode_set_name(mode);
3901 drm_mode_set_crtcinfo(mode, 0);
3902
3903 return mode;
3904 }
3905
3906 #define GPU_IDLE_TIMEOUT 500 /* ms */
3907
3908 /* When this timer fires, we've been idle for awhile */
3909 static void intel_gpu_idle_timer(unsigned long arg)
3910 {
3911 struct drm_device *dev = (struct drm_device *)arg;
3912 drm_i915_private_t *dev_priv = dev->dev_private;
3913
3914 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3915
3916 dev_priv->busy = false;
3917
3918 queue_work(dev_priv->wq, &dev_priv->idle_work);
3919 }
3920
3921 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3922
3923 static void intel_crtc_idle_timer(unsigned long arg)
3924 {
3925 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3926 struct drm_crtc *crtc = &intel_crtc->base;
3927 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3928
3929 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3930
3931 intel_crtc->busy = false;
3932
3933 queue_work(dev_priv->wq, &dev_priv->idle_work);
3934 }
3935
3936 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3937 {
3938 struct drm_device *dev = crtc->dev;
3939 drm_i915_private_t *dev_priv = dev->dev_private;
3940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3941 int pipe = intel_crtc->pipe;
3942 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3943 int dpll = I915_READ(dpll_reg);
3944
3945 if (HAS_PCH_SPLIT(dev))
3946 return;
3947
3948 if (!dev_priv->lvds_downclock_avail)
3949 return;
3950
3951 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3952 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3953
3954 /* Unlock panel regs */
3955 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3956
3957 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3958 I915_WRITE(dpll_reg, dpll);
3959 dpll = I915_READ(dpll_reg);
3960 intel_wait_for_vblank(dev);
3961 dpll = I915_READ(dpll_reg);
3962 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3963 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3964
3965 /* ...and lock them again */
3966 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3967 }
3968
3969 /* Schedule downclock */
3970 if (schedule)
3971 mod_timer(&intel_crtc->idle_timer, jiffies +
3972 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3973 }
3974
3975 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3976 {
3977 struct drm_device *dev = crtc->dev;
3978 drm_i915_private_t *dev_priv = dev->dev_private;
3979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3980 int pipe = intel_crtc->pipe;
3981 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3982 int dpll = I915_READ(dpll_reg);
3983
3984 if (HAS_PCH_SPLIT(dev))
3985 return;
3986
3987 if (!dev_priv->lvds_downclock_avail)
3988 return;
3989
3990 /*
3991 * Since this is called by a timer, we should never get here in
3992 * the manual case.
3993 */
3994 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3995 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3996
3997 /* Unlock panel regs */
3998 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3999
4000 dpll |= DISPLAY_RATE_SELECT_FPA1;
4001 I915_WRITE(dpll_reg, dpll);
4002 dpll = I915_READ(dpll_reg);
4003 intel_wait_for_vblank(dev);
4004 dpll = I915_READ(dpll_reg);
4005 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4006 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4007
4008 /* ...and lock them again */
4009 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4010 }
4011
4012 }
4013
4014 /**
4015 * intel_idle_update - adjust clocks for idleness
4016 * @work: work struct
4017 *
4018 * Either the GPU or display (or both) went idle. Check the busy status
4019 * here and adjust the CRTC and GPU clocks as necessary.
4020 */
4021 static void intel_idle_update(struct work_struct *work)
4022 {
4023 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4024 idle_work);
4025 struct drm_device *dev = dev_priv->dev;
4026 struct drm_crtc *crtc;
4027 struct intel_crtc *intel_crtc;
4028
4029 if (!i915_powersave)
4030 return;
4031
4032 mutex_lock(&dev->struct_mutex);
4033
4034 if (IS_I945G(dev) || IS_I945GM(dev)) {
4035 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4036 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4037 }
4038
4039 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4040 /* Skip inactive CRTCs */
4041 if (!crtc->fb)
4042 continue;
4043
4044 intel_crtc = to_intel_crtc(crtc);
4045 if (!intel_crtc->busy)
4046 intel_decrease_pllclock(crtc);
4047 }
4048
4049 mutex_unlock(&dev->struct_mutex);
4050 }
4051
4052 /**
4053 * intel_mark_busy - mark the GPU and possibly the display busy
4054 * @dev: drm device
4055 * @obj: object we're operating on
4056 *
4057 * Callers can use this function to indicate that the GPU is busy processing
4058 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4059 * buffer), we'll also mark the display as busy, so we know to increase its
4060 * clock frequency.
4061 */
4062 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4063 {
4064 drm_i915_private_t *dev_priv = dev->dev_private;
4065 struct drm_crtc *crtc = NULL;
4066 struct intel_framebuffer *intel_fb;
4067 struct intel_crtc *intel_crtc;
4068
4069 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4070 return;
4071
4072 if (!dev_priv->busy) {
4073 if (IS_I945G(dev) || IS_I945GM(dev)) {
4074 u32 fw_blc_self;
4075
4076 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4077 fw_blc_self = I915_READ(FW_BLC_SELF);
4078 fw_blc_self &= ~FW_BLC_SELF_EN;
4079 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4080 }
4081 dev_priv->busy = true;
4082 } else
4083 mod_timer(&dev_priv->idle_timer, jiffies +
4084 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4085
4086 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4087 if (!crtc->fb)
4088 continue;
4089
4090 intel_crtc = to_intel_crtc(crtc);
4091 intel_fb = to_intel_framebuffer(crtc->fb);
4092 if (intel_fb->obj == obj) {
4093 if (!intel_crtc->busy) {
4094 if (IS_I945G(dev) || IS_I945GM(dev)) {
4095 u32 fw_blc_self;
4096
4097 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4098 fw_blc_self = I915_READ(FW_BLC_SELF);
4099 fw_blc_self &= ~FW_BLC_SELF_EN;
4100 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4101 }
4102 /* Non-busy -> busy, upclock */
4103 intel_increase_pllclock(crtc, true);
4104 intel_crtc->busy = true;
4105 } else {
4106 /* Busy -> busy, put off timer */
4107 mod_timer(&intel_crtc->idle_timer, jiffies +
4108 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4109 }
4110 }
4111 }
4112 }
4113
4114 static void intel_crtc_destroy(struct drm_crtc *crtc)
4115 {
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117
4118 drm_crtc_cleanup(crtc);
4119 kfree(intel_crtc);
4120 }
4121
4122 struct intel_unpin_work {
4123 struct work_struct work;
4124 struct drm_device *dev;
4125 struct drm_gem_object *old_fb_obj;
4126 struct drm_gem_object *pending_flip_obj;
4127 struct drm_pending_vblank_event *event;
4128 int pending;
4129 };
4130
4131 static void intel_unpin_work_fn(struct work_struct *__work)
4132 {
4133 struct intel_unpin_work *work =
4134 container_of(__work, struct intel_unpin_work, work);
4135
4136 mutex_lock(&work->dev->struct_mutex);
4137 i915_gem_object_unpin(work->old_fb_obj);
4138 drm_gem_object_unreference(work->pending_flip_obj);
4139 drm_gem_object_unreference(work->old_fb_obj);
4140 mutex_unlock(&work->dev->struct_mutex);
4141 kfree(work);
4142 }
4143
4144 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4145 {
4146 drm_i915_private_t *dev_priv = dev->dev_private;
4147 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4149 struct intel_unpin_work *work;
4150 struct drm_i915_gem_object *obj_priv;
4151 struct drm_pending_vblank_event *e;
4152 struct timeval now;
4153 unsigned long flags;
4154
4155 /* Ignore early vblank irqs */
4156 if (intel_crtc == NULL)
4157 return;
4158
4159 spin_lock_irqsave(&dev->event_lock, flags);
4160 work = intel_crtc->unpin_work;
4161 if (work == NULL || !work->pending) {
4162 if (work && !work->pending) {
4163 obj_priv = to_intel_bo(work->pending_flip_obj);
4164 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4165 obj_priv,
4166 atomic_read(&obj_priv->pending_flip));
4167 }
4168 spin_unlock_irqrestore(&dev->event_lock, flags);
4169 return;
4170 }
4171
4172 intel_crtc->unpin_work = NULL;
4173 drm_vblank_put(dev, intel_crtc->pipe);
4174
4175 if (work->event) {
4176 e = work->event;
4177 do_gettimeofday(&now);
4178 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4179 e->event.tv_sec = now.tv_sec;
4180 e->event.tv_usec = now.tv_usec;
4181 list_add_tail(&e->base.link,
4182 &e->base.file_priv->event_list);
4183 wake_up_interruptible(&e->base.file_priv->event_wait);
4184 }
4185
4186 spin_unlock_irqrestore(&dev->event_lock, flags);
4187
4188 obj_priv = to_intel_bo(work->pending_flip_obj);
4189
4190 /* Initial scanout buffer will have a 0 pending flip count */
4191 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4192 atomic_dec_and_test(&obj_priv->pending_flip))
4193 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4194 schedule_work(&work->work);
4195 }
4196
4197 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4198 {
4199 drm_i915_private_t *dev_priv = dev->dev_private;
4200 struct intel_crtc *intel_crtc =
4201 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4202 unsigned long flags;
4203
4204 spin_lock_irqsave(&dev->event_lock, flags);
4205 if (intel_crtc->unpin_work) {
4206 intel_crtc->unpin_work->pending = 1;
4207 } else {
4208 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4209 }
4210 spin_unlock_irqrestore(&dev->event_lock, flags);
4211 }
4212
4213 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4214 struct drm_framebuffer *fb,
4215 struct drm_pending_vblank_event *event)
4216 {
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct intel_framebuffer *intel_fb;
4220 struct drm_i915_gem_object *obj_priv;
4221 struct drm_gem_object *obj;
4222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223 struct intel_unpin_work *work;
4224 unsigned long flags;
4225 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4226 int ret, pipesrc;
4227 RING_LOCALS;
4228
4229 work = kzalloc(sizeof *work, GFP_KERNEL);
4230 if (work == NULL)
4231 return -ENOMEM;
4232
4233 mutex_lock(&dev->struct_mutex);
4234
4235 work->event = event;
4236 work->dev = crtc->dev;
4237 intel_fb = to_intel_framebuffer(crtc->fb);
4238 work->old_fb_obj = intel_fb->obj;
4239 INIT_WORK(&work->work, intel_unpin_work_fn);
4240
4241 /* We borrow the event spin lock for protecting unpin_work */
4242 spin_lock_irqsave(&dev->event_lock, flags);
4243 if (intel_crtc->unpin_work) {
4244 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4245 spin_unlock_irqrestore(&dev->event_lock, flags);
4246 kfree(work);
4247 mutex_unlock(&dev->struct_mutex);
4248 return -EBUSY;
4249 }
4250 intel_crtc->unpin_work = work;
4251 spin_unlock_irqrestore(&dev->event_lock, flags);
4252
4253 intel_fb = to_intel_framebuffer(fb);
4254 obj = intel_fb->obj;
4255
4256 ret = intel_pin_and_fence_fb_obj(dev, obj);
4257 if (ret != 0) {
4258 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4259 to_intel_bo(obj));
4260 kfree(work);
4261 intel_crtc->unpin_work = NULL;
4262 mutex_unlock(&dev->struct_mutex);
4263 return ret;
4264 }
4265
4266 /* Reference the objects for the scheduled work. */
4267 drm_gem_object_reference(work->old_fb_obj);
4268 drm_gem_object_reference(obj);
4269
4270 crtc->fb = fb;
4271 i915_gem_object_flush_write_domain(obj);
4272 drm_vblank_get(dev, intel_crtc->pipe);
4273 obj_priv = to_intel_bo(obj);
4274 atomic_inc(&obj_priv->pending_flip);
4275 work->pending_flip_obj = obj;
4276
4277 BEGIN_LP_RING(4);
4278 OUT_RING(MI_DISPLAY_FLIP |
4279 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4280 OUT_RING(fb->pitch);
4281 if (IS_I965G(dev)) {
4282 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4283 pipesrc = I915_READ(pipesrc_reg);
4284 OUT_RING(pipesrc & 0x0fff0fff);
4285 } else {
4286 OUT_RING(obj_priv->gtt_offset);
4287 OUT_RING(MI_NOOP);
4288 }
4289 ADVANCE_LP_RING();
4290
4291 mutex_unlock(&dev->struct_mutex);
4292
4293 return 0;
4294 }
4295
4296 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4297 .dpms = intel_crtc_dpms,
4298 .mode_fixup = intel_crtc_mode_fixup,
4299 .mode_set = intel_crtc_mode_set,
4300 .mode_set_base = intel_pipe_set_base,
4301 .prepare = intel_crtc_prepare,
4302 .commit = intel_crtc_commit,
4303 .load_lut = intel_crtc_load_lut,
4304 };
4305
4306 static const struct drm_crtc_funcs intel_crtc_funcs = {
4307 .cursor_set = intel_crtc_cursor_set,
4308 .cursor_move = intel_crtc_cursor_move,
4309 .gamma_set = intel_crtc_gamma_set,
4310 .set_config = drm_crtc_helper_set_config,
4311 .destroy = intel_crtc_destroy,
4312 .page_flip = intel_crtc_page_flip,
4313 };
4314
4315
4316 static void intel_crtc_init(struct drm_device *dev, int pipe)
4317 {
4318 drm_i915_private_t *dev_priv = dev->dev_private;
4319 struct intel_crtc *intel_crtc;
4320 int i;
4321
4322 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4323 if (intel_crtc == NULL)
4324 return;
4325
4326 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4327
4328 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4329 intel_crtc->pipe = pipe;
4330 intel_crtc->plane = pipe;
4331 for (i = 0; i < 256; i++) {
4332 intel_crtc->lut_r[i] = i;
4333 intel_crtc->lut_g[i] = i;
4334 intel_crtc->lut_b[i] = i;
4335 }
4336
4337 /* Swap pipes & planes for FBC on pre-965 */
4338 intel_crtc->pipe = pipe;
4339 intel_crtc->plane = pipe;
4340 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4341 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4342 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4343 }
4344
4345 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4346 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4347 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4348 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4349
4350 intel_crtc->cursor_addr = 0;
4351 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4352 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4353
4354 intel_crtc->busy = false;
4355
4356 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4357 (unsigned long)intel_crtc);
4358 }
4359
4360 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4361 struct drm_file *file_priv)
4362 {
4363 drm_i915_private_t *dev_priv = dev->dev_private;
4364 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4365 struct drm_mode_object *drmmode_obj;
4366 struct intel_crtc *crtc;
4367
4368 if (!dev_priv) {
4369 DRM_ERROR("called with no initialization\n");
4370 return -EINVAL;
4371 }
4372
4373 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4374 DRM_MODE_OBJECT_CRTC);
4375
4376 if (!drmmode_obj) {
4377 DRM_ERROR("no such CRTC id\n");
4378 return -EINVAL;
4379 }
4380
4381 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4382 pipe_from_crtc_id->pipe = crtc->pipe;
4383
4384 return 0;
4385 }
4386
4387 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4388 {
4389 struct drm_crtc *crtc = NULL;
4390
4391 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4393 if (intel_crtc->pipe == pipe)
4394 break;
4395 }
4396 return crtc;
4397 }
4398
4399 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4400 {
4401 int index_mask = 0;
4402 struct drm_encoder *encoder;
4403 int entry = 0;
4404
4405 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4406 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4407 if (type_mask & intel_encoder->clone_mask)
4408 index_mask |= (1 << entry);
4409 entry++;
4410 }
4411 return index_mask;
4412 }
4413
4414
4415 static void intel_setup_outputs(struct drm_device *dev)
4416 {
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418 struct drm_encoder *encoder;
4419
4420 intel_crt_init(dev);
4421
4422 /* Set up integrated LVDS */
4423 if (IS_MOBILE(dev) && !IS_I830(dev))
4424 intel_lvds_init(dev);
4425
4426 if (HAS_PCH_SPLIT(dev)) {
4427 int found;
4428
4429 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4430 intel_dp_init(dev, DP_A);
4431
4432 if (I915_READ(HDMIB) & PORT_DETECTED) {
4433 /* check SDVOB */
4434 /* found = intel_sdvo_init(dev, HDMIB); */
4435 found = 0;
4436 if (!found)
4437 intel_hdmi_init(dev, HDMIB);
4438 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4439 intel_dp_init(dev, PCH_DP_B);
4440 }
4441
4442 if (I915_READ(HDMIC) & PORT_DETECTED)
4443 intel_hdmi_init(dev, HDMIC);
4444
4445 if (I915_READ(HDMID) & PORT_DETECTED)
4446 intel_hdmi_init(dev, HDMID);
4447
4448 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4449 intel_dp_init(dev, PCH_DP_C);
4450
4451 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4452 intel_dp_init(dev, PCH_DP_D);
4453
4454 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4455 bool found = false;
4456
4457 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4458 DRM_DEBUG_KMS("probing SDVOB\n");
4459 found = intel_sdvo_init(dev, SDVOB);
4460 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4461 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4462 intel_hdmi_init(dev, SDVOB);
4463 }
4464
4465 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4466 DRM_DEBUG_KMS("probing DP_B\n");
4467 intel_dp_init(dev, DP_B);
4468 }
4469 }
4470
4471 /* Before G4X SDVOC doesn't have its own detect register */
4472
4473 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4474 DRM_DEBUG_KMS("probing SDVOC\n");
4475 found = intel_sdvo_init(dev, SDVOC);
4476 }
4477
4478 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4479
4480 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4481 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4482 intel_hdmi_init(dev, SDVOC);
4483 }
4484 if (SUPPORTS_INTEGRATED_DP(dev)) {
4485 DRM_DEBUG_KMS("probing DP_C\n");
4486 intel_dp_init(dev, DP_C);
4487 }
4488 }
4489
4490 if (SUPPORTS_INTEGRATED_DP(dev) &&
4491 (I915_READ(DP_D) & DP_DETECTED)) {
4492 DRM_DEBUG_KMS("probing DP_D\n");
4493 intel_dp_init(dev, DP_D);
4494 }
4495 } else if (IS_GEN2(dev))
4496 intel_dvo_init(dev);
4497
4498 if (SUPPORTS_TV(dev))
4499 intel_tv_init(dev);
4500
4501 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4502 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4503
4504 encoder->possible_crtcs = intel_encoder->crtc_mask;
4505 encoder->possible_clones = intel_encoder_clones(dev,
4506 intel_encoder->clone_mask);
4507 }
4508 }
4509
4510 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4511 {
4512 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4513 struct drm_device *dev = fb->dev;
4514
4515 if (fb->fbdev)
4516 intelfb_remove(dev, fb);
4517
4518 drm_framebuffer_cleanup(fb);
4519 drm_gem_object_unreference_unlocked(intel_fb->obj);
4520
4521 kfree(intel_fb);
4522 }
4523
4524 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4525 struct drm_file *file_priv,
4526 unsigned int *handle)
4527 {
4528 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4529 struct drm_gem_object *object = intel_fb->obj;
4530
4531 return drm_gem_handle_create(file_priv, object, handle);
4532 }
4533
4534 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4535 .destroy = intel_user_framebuffer_destroy,
4536 .create_handle = intel_user_framebuffer_create_handle,
4537 };
4538
4539 int intel_framebuffer_create(struct drm_device *dev,
4540 struct drm_mode_fb_cmd *mode_cmd,
4541 struct drm_framebuffer **fb,
4542 struct drm_gem_object *obj)
4543 {
4544 struct intel_framebuffer *intel_fb;
4545 int ret;
4546
4547 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4548 if (!intel_fb)
4549 return -ENOMEM;
4550
4551 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4552 if (ret) {
4553 DRM_ERROR("framebuffer init failed %d\n", ret);
4554 return ret;
4555 }
4556
4557 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4558
4559 intel_fb->obj = obj;
4560
4561 *fb = &intel_fb->base;
4562
4563 return 0;
4564 }
4565
4566
4567 static struct drm_framebuffer *
4568 intel_user_framebuffer_create(struct drm_device *dev,
4569 struct drm_file *filp,
4570 struct drm_mode_fb_cmd *mode_cmd)
4571 {
4572 struct drm_gem_object *obj;
4573 struct drm_framebuffer *fb;
4574 int ret;
4575
4576 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4577 if (!obj)
4578 return NULL;
4579
4580 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4581 if (ret) {
4582 drm_gem_object_unreference_unlocked(obj);
4583 return NULL;
4584 }
4585
4586 return fb;
4587 }
4588
4589 static const struct drm_mode_config_funcs intel_mode_funcs = {
4590 .fb_create = intel_user_framebuffer_create,
4591 .fb_changed = intelfb_probe,
4592 };
4593
4594 static struct drm_gem_object *
4595 intel_alloc_power_context(struct drm_device *dev)
4596 {
4597 struct drm_gem_object *pwrctx;
4598 int ret;
4599
4600 pwrctx = drm_gem_object_alloc(dev, 4096);
4601 if (!pwrctx) {
4602 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4603 return NULL;
4604 }
4605
4606 mutex_lock(&dev->struct_mutex);
4607 ret = i915_gem_object_pin(pwrctx, 4096);
4608 if (ret) {
4609 DRM_ERROR("failed to pin power context: %d\n", ret);
4610 goto err_unref;
4611 }
4612
4613 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4614 if (ret) {
4615 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4616 goto err_unpin;
4617 }
4618 mutex_unlock(&dev->struct_mutex);
4619
4620 return pwrctx;
4621
4622 err_unpin:
4623 i915_gem_object_unpin(pwrctx);
4624 err_unref:
4625 drm_gem_object_unreference(pwrctx);
4626 mutex_unlock(&dev->struct_mutex);
4627 return NULL;
4628 }
4629
4630 void ironlake_enable_drps(struct drm_device *dev)
4631 {
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633 u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4634 u8 fmax, fmin, fstart, vstart;
4635 int i = 0;
4636
4637 /* 100ms RC evaluation intervals */
4638 I915_WRITE(RCUPEI, 100000);
4639 I915_WRITE(RCDNEI, 100000);
4640
4641 /* Set max/min thresholds to 90ms and 80ms respectively */
4642 I915_WRITE(RCBMAXAVG, 90000);
4643 I915_WRITE(RCBMINAVG, 80000);
4644
4645 I915_WRITE(MEMIHYST, 1);
4646
4647 /* Set up min, max, and cur for interrupt handling */
4648 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4649 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4650 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4651 MEMMODE_FSTART_SHIFT;
4652 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4653 PXVFREQ_PX_SHIFT;
4654
4655 dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4656 dev_priv->min_delay = fmin;
4657 dev_priv->cur_delay = fstart;
4658
4659 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4660
4661 /*
4662 * Interrupts will be enabled in ironlake_irq_postinstall
4663 */
4664
4665 I915_WRITE(VIDSTART, vstart);
4666 POSTING_READ(VIDSTART);
4667
4668 rgvmodectl |= MEMMODE_SWMODE_EN;
4669 I915_WRITE(MEMMODECTL, rgvmodectl);
4670
4671 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4672 if (i++ > 100) {
4673 DRM_ERROR("stuck trying to change perf mode\n");
4674 break;
4675 }
4676 msleep(1);
4677 }
4678 msleep(1);
4679
4680 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4681 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4682 I915_WRITE(MEMSWCTL, rgvswctl);
4683 POSTING_READ(MEMSWCTL);
4684
4685 rgvswctl |= MEMCTL_CMD_STS;
4686 I915_WRITE(MEMSWCTL, rgvswctl);
4687 }
4688
4689 void ironlake_disable_drps(struct drm_device *dev)
4690 {
4691 struct drm_i915_private *dev_priv = dev->dev_private;
4692 u32 rgvswctl;
4693 u8 fstart;
4694
4695 /* Ack interrupts, disable EFC interrupt */
4696 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4697 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4698 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4699 I915_WRITE(DEIIR, DE_PCU_EVENT);
4700 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4701
4702 /* Go back to the starting frequency */
4703 fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4704 MEMMODE_FSTART_SHIFT;
4705 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4706 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4707 I915_WRITE(MEMSWCTL, rgvswctl);
4708 msleep(1);
4709 rgvswctl |= MEMCTL_CMD_STS;
4710 I915_WRITE(MEMSWCTL, rgvswctl);
4711 msleep(1);
4712
4713 }
4714
4715 void intel_init_clock_gating(struct drm_device *dev)
4716 {
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718
4719 /*
4720 * Disable clock gating reported to work incorrectly according to the
4721 * specs, but enable as much else as we can.
4722 */
4723 if (HAS_PCH_SPLIT(dev)) {
4724 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
4725
4726 if (IS_IRONLAKE(dev)) {
4727 /* Required for FBC */
4728 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
4729 /* Required for CxSR */
4730 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
4731
4732 I915_WRITE(PCH_3DCGDIS0,
4733 MARIUNIT_CLOCK_GATE_DISABLE |
4734 SVSMUNIT_CLOCK_GATE_DISABLE);
4735 }
4736
4737 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
4738 return;
4739 } else if (IS_G4X(dev)) {
4740 uint32_t dspclk_gate;
4741 I915_WRITE(RENCLK_GATE_D1, 0);
4742 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4743 GS_UNIT_CLOCK_GATE_DISABLE |
4744 CL_UNIT_CLOCK_GATE_DISABLE);
4745 I915_WRITE(RAMCLK_GATE_D, 0);
4746 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4747 OVRUNIT_CLOCK_GATE_DISABLE |
4748 OVCUNIT_CLOCK_GATE_DISABLE;
4749 if (IS_GM45(dev))
4750 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4751 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4752 } else if (IS_I965GM(dev)) {
4753 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4754 I915_WRITE(RENCLK_GATE_D2, 0);
4755 I915_WRITE(DSPCLK_GATE_D, 0);
4756 I915_WRITE(RAMCLK_GATE_D, 0);
4757 I915_WRITE16(DEUC, 0);
4758 } else if (IS_I965G(dev)) {
4759 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4760 I965_RCC_CLOCK_GATE_DISABLE |
4761 I965_RCPB_CLOCK_GATE_DISABLE |
4762 I965_ISC_CLOCK_GATE_DISABLE |
4763 I965_FBC_CLOCK_GATE_DISABLE);
4764 I915_WRITE(RENCLK_GATE_D2, 0);
4765 } else if (IS_I9XX(dev)) {
4766 u32 dstate = I915_READ(D_STATE);
4767
4768 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4769 DSTATE_DOT_CLOCK_GATING;
4770 I915_WRITE(D_STATE, dstate);
4771 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4772 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4773 } else if (IS_I830(dev)) {
4774 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4775 }
4776
4777 /*
4778 * GPU can automatically power down the render unit if given a page
4779 * to save state.
4780 */
4781 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4782 struct drm_i915_gem_object *obj_priv = NULL;
4783
4784 if (dev_priv->pwrctx) {
4785 obj_priv = to_intel_bo(dev_priv->pwrctx);
4786 } else {
4787 struct drm_gem_object *pwrctx;
4788
4789 pwrctx = intel_alloc_power_context(dev);
4790 if (pwrctx) {
4791 dev_priv->pwrctx = pwrctx;
4792 obj_priv = to_intel_bo(pwrctx);
4793 }
4794 }
4795
4796 if (obj_priv) {
4797 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4798 I915_WRITE(MCHBAR_RENDER_STANDBY,
4799 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4800 }
4801 }
4802 }
4803
4804 /* Set up chip specific display functions */
4805 static void intel_init_display(struct drm_device *dev)
4806 {
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808
4809 /* We always want a DPMS function */
4810 if (HAS_PCH_SPLIT(dev))
4811 dev_priv->display.dpms = ironlake_crtc_dpms;
4812 else
4813 dev_priv->display.dpms = i9xx_crtc_dpms;
4814
4815 /* Only mobile has FBC, leave pointers NULL for other chips */
4816 if (IS_MOBILE(dev)) {
4817 if (IS_GM45(dev)) {
4818 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4819 dev_priv->display.enable_fbc = g4x_enable_fbc;
4820 dev_priv->display.disable_fbc = g4x_disable_fbc;
4821 } else if (IS_I965GM(dev)) {
4822 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4823 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4824 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4825 }
4826 /* 855GM needs testing */
4827 }
4828
4829 /* Returns the core display clock speed */
4830 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4831 dev_priv->display.get_display_clock_speed =
4832 i945_get_display_clock_speed;
4833 else if (IS_I915G(dev))
4834 dev_priv->display.get_display_clock_speed =
4835 i915_get_display_clock_speed;
4836 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4837 dev_priv->display.get_display_clock_speed =
4838 i9xx_misc_get_display_clock_speed;
4839 else if (IS_I915GM(dev))
4840 dev_priv->display.get_display_clock_speed =
4841 i915gm_get_display_clock_speed;
4842 else if (IS_I865G(dev))
4843 dev_priv->display.get_display_clock_speed =
4844 i865_get_display_clock_speed;
4845 else if (IS_I85X(dev))
4846 dev_priv->display.get_display_clock_speed =
4847 i855_get_display_clock_speed;
4848 else /* 852, 830 */
4849 dev_priv->display.get_display_clock_speed =
4850 i830_get_display_clock_speed;
4851
4852 /* For FIFO watermark updates */
4853 if (HAS_PCH_SPLIT(dev))
4854 dev_priv->display.update_wm = NULL;
4855 else if (IS_G4X(dev))
4856 dev_priv->display.update_wm = g4x_update_wm;
4857 else if (IS_I965G(dev))
4858 dev_priv->display.update_wm = i965_update_wm;
4859 else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4860 dev_priv->display.update_wm = i9xx_update_wm;
4861 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4862 } else {
4863 if (IS_I85X(dev))
4864 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4865 else if (IS_845G(dev))
4866 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4867 else
4868 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4869 dev_priv->display.update_wm = i830_update_wm;
4870 }
4871 }
4872
4873 void intel_modeset_init(struct drm_device *dev)
4874 {
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 int num_pipe;
4877 int i;
4878
4879 drm_mode_config_init(dev);
4880
4881 dev->mode_config.min_width = 0;
4882 dev->mode_config.min_height = 0;
4883
4884 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4885
4886 intel_init_display(dev);
4887
4888 if (IS_I965G(dev)) {
4889 dev->mode_config.max_width = 8192;
4890 dev->mode_config.max_height = 8192;
4891 } else if (IS_I9XX(dev)) {
4892 dev->mode_config.max_width = 4096;
4893 dev->mode_config.max_height = 4096;
4894 } else {
4895 dev->mode_config.max_width = 2048;
4896 dev->mode_config.max_height = 2048;
4897 }
4898
4899 /* set memory base */
4900 if (IS_I9XX(dev))
4901 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4902 else
4903 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4904
4905 if (IS_MOBILE(dev) || IS_I9XX(dev))
4906 num_pipe = 2;
4907 else
4908 num_pipe = 1;
4909 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4910 num_pipe, num_pipe > 1 ? "s" : "");
4911
4912 for (i = 0; i < num_pipe; i++) {
4913 intel_crtc_init(dev, i);
4914 }
4915
4916 intel_setup_outputs(dev);
4917
4918 intel_init_clock_gating(dev);
4919
4920 if (IS_IRONLAKE_M(dev))
4921 ironlake_enable_drps(dev);
4922
4923 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4924 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4925 (unsigned long)dev);
4926
4927 intel_setup_overlay(dev);
4928
4929 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4930 dev_priv->fsb_freq,
4931 dev_priv->mem_freq))
4932 DRM_INFO("failed to find known CxSR latency "
4933 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4934 dev_priv->fsb_freq, dev_priv->mem_freq);
4935 }
4936
4937 void intel_modeset_cleanup(struct drm_device *dev)
4938 {
4939 struct drm_i915_private *dev_priv = dev->dev_private;
4940 struct drm_crtc *crtc;
4941 struct intel_crtc *intel_crtc;
4942
4943 mutex_lock(&dev->struct_mutex);
4944
4945 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4946 /* Skip inactive CRTCs */
4947 if (!crtc->fb)
4948 continue;
4949
4950 intel_crtc = to_intel_crtc(crtc);
4951 intel_increase_pllclock(crtc, false);
4952 del_timer_sync(&intel_crtc->idle_timer);
4953 }
4954
4955 del_timer_sync(&dev_priv->idle_timer);
4956
4957 if (dev_priv->display.disable_fbc)
4958 dev_priv->display.disable_fbc(dev);
4959
4960 if (dev_priv->pwrctx) {
4961 struct drm_i915_gem_object *obj_priv;
4962
4963 obj_priv = to_intel_bo(dev_priv->pwrctx);
4964 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4965 I915_READ(PWRCTXA);
4966 i915_gem_object_unpin(dev_priv->pwrctx);
4967 drm_gem_object_unreference(dev_priv->pwrctx);
4968 }
4969
4970 if (IS_IRONLAKE_M(dev))
4971 ironlake_disable_drps(dev);
4972
4973 mutex_unlock(&dev->struct_mutex);
4974
4975 drm_mode_config_cleanup(dev);
4976 }
4977
4978
4979 /* current intel driver doesn't take advantage of encoders
4980 always give back the encoder for the connector
4981 */
4982 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4983 {
4984 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4985
4986 return &intel_encoder->enc;
4987 }
4988
4989 /*
4990 * Return which encoder is currently attached for connector.
4991 */
4992 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
4993 {
4994 struct drm_mode_object *obj;
4995 struct drm_encoder *encoder;
4996 int i;
4997
4998 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
4999 if (connector->encoder_ids[i] == 0)
5000 break;
5001
5002 obj = drm_mode_object_find(connector->dev,
5003 connector->encoder_ids[i],
5004 DRM_MODE_OBJECT_ENCODER);
5005 if (!obj)
5006 continue;
5007
5008 encoder = obj_to_encoder(obj);
5009 return encoder;
5010 }
5011 return NULL;
5012 }
5013
5014 /*
5015 * set vga decode state - true == enable VGA decode
5016 */
5017 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5018 {
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5020 u16 gmch_ctrl;
5021
5022 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5023 if (state)
5024 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5025 else
5026 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5027 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5028 return 0;
5029 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree