| blob | 4778620347c491003fc3ff3fd02550e61d597c19 |
1 /*
2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
29 /*
30 Module: rt2800
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
33 */
35 #ifndef RT2800_H
36 #define RT2800_H
38 /*
39 * RF chip defines.
40 *
41 * RF2820 2.4G 2T3R
42 * RF2850 2.4G/5G 2T3R
43 * RF2720 2.4G 1T2R
44 * RF2750 2.4G/5G 1T2R
45 * RF3020 2.4G 1T1R
46 * RF2020 2.4G B/G
47 * RF3021 2.4G 1T2R
48 * RF3022 2.4G 2T2R
49 * RF3052 2.4G/5G 2T2R
50 * RF2853 2.4G/5G 3T3R
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5370 2.4G 1T1R
55 * RF5390 2.4G 1T1R
56 */
57 #define RF2820 0x0001
58 #define RF2850 0x0002
59 #define RF2720 0x0003
60 #define RF2750 0x0004
61 #define RF3020 0x0005
62 #define RF2020 0x0006
63 #define RF3021 0x0007
64 #define RF3022 0x0008
65 #define RF3052 0x0009
66 #define RF2853 0x000a
67 #define RF3320 0x000b
68 #define RF3322 0x000c
69 #define RF3853 0x000d
70 #define RF5370 0x5370
71 #define RF5390 0x5390
73 /*
74 * Chipset revisions.
75 */
76 #define REV_RT2860C 0x0100
77 #define REV_RT2860D 0x0101
78 #define REV_RT2872E 0x0200
79 #define REV_RT3070E 0x0200
80 #define REV_RT3070F 0x0201
81 #define REV_RT3071E 0x0211
82 #define REV_RT3090E 0x0211
83 #define REV_RT3390E 0x0211
84 #define REV_RT5390F 0x0502
86 /*
87 * Signal information.
88 * Default offset is required for RSSI <-> dBm conversion.
89 */
90 #define DEFAULT_RSSI_OFFSET 120
92 /*
93 * Register layout information.
94 */
95 #define CSR_REG_BASE 0x1000
96 #define CSR_REG_SIZE 0x0800
97 #define EEPROM_BASE 0x0000
98 #define EEPROM_SIZE 0x0110
99 #define BBP_BASE 0x0000
100 #define BBP_SIZE 0x0080
101 #define RF_BASE 0x0004
102 #define RF_SIZE 0x0010
104 /*
105 * Number of TX queues.
106 */
107 #define NUM_TX_QUEUES 4
109 /*
110 * Registers.
111 */
113 /*
114 * E2PROM_CSR: PCI EEPROM control register.
115 * RELOAD: Write 1 to reload eeprom content.
116 * TYPE: 0: 93c46, 1:93c66.
117 * LOAD_STATUS: 1:loading, 0:done.
118 */
119 #define E2PROM_CSR 0x0004
120 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
121 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
122 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
123 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
124 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
125 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
126 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
128 /*
129 * AUX_CTRL: Aux/PCI-E related configuration
130 */
131 #define AUX_CTRL 0x10c
132 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
133 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
135 /*
136 * OPT_14: Unknown register used by rt3xxx devices.
137 */
138 #define OPT_14_CSR 0x0114
139 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
141 /*
142 * INT_SOURCE_CSR: Interrupt source register.
143 * Write one to clear corresponding bit.
144 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
145 */
146 #define INT_SOURCE_CSR 0x0200
147 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
148 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
149 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
150 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
151 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
152 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
153 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
154 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
155 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
156 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
157 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
158 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
159 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
160 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
161 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
162 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
163 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
164 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
166 /*
167 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
168 */
169 #define INT_MASK_CSR 0x0204
170 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
171 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
172 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
173 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
174 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
175 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
176 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
177 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
178 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
179 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
180 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
181 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
182 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
183 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
184 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
185 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
186 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
187 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
189 /*
190 * WPDMA_GLO_CFG
191 */
192 #define WPDMA_GLO_CFG 0x0208
193 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
194 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
195 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
196 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
197 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
198 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
199 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
200 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
201 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
203 /*
204 * WPDMA_RST_IDX
205 */
206 #define WPDMA_RST_IDX 0x020c
207 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
208 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
209 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
210 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
211 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
212 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
213 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
215 /*
216 * DELAY_INT_CFG
217 */
218 #define DELAY_INT_CFG 0x0210
219 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
220 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
221 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
222 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
223 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
224 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
226 /*
227 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
228 * AIFSN0: AC_VO
229 * AIFSN1: AC_VI
230 * AIFSN2: AC_BE
231 * AIFSN3: AC_BK
232 */
233 #define WMM_AIFSN_CFG 0x0214
234 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
235 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
236 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
237 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
239 /*
240 * WMM_CWMIN_CSR: CWmin for each EDCA AC
241 * CWMIN0: AC_VO
242 * CWMIN1: AC_VI
243 * CWMIN2: AC_BE
244 * CWMIN3: AC_BK
245 */
246 #define WMM_CWMIN_CFG 0x0218
247 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
248 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
249 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
250 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
252 /*
253 * WMM_CWMAX_CSR: CWmax for each EDCA AC
254 * CWMAX0: AC_VO
255 * CWMAX1: AC_VI
256 * CWMAX2: AC_BE
257 * CWMAX3: AC_BK
258 */
259 #define WMM_CWMAX_CFG 0x021c
260 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
261 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
262 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
263 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
265 /*
266 * AC_TXOP0: AC_VO/AC_VI TXOP register
267 * AC0TXOP: AC_VO in unit of 32us
268 * AC1TXOP: AC_VI in unit of 32us
269 */
270 #define WMM_TXOP0_CFG 0x0220
271 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
272 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
274 /*
275 * AC_TXOP1: AC_BE/AC_BK TXOP register
276 * AC2TXOP: AC_BE in unit of 32us
277 * AC3TXOP: AC_BK in unit of 32us
278 */
279 #define WMM_TXOP1_CFG 0x0224
280 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
281 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
283 /*
284 * GPIO_CTRL_CFG:
285 * GPIOD: GPIO direction, 0: Output, 1: Input
286 */
287 #define GPIO_CTRL_CFG 0x0228
288 #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
289 #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
290 #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
291 #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
292 #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
293 #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
294 #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
295 #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
296 #define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100)
297 #define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200)
298 #define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400)
299 #define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800)
300 #define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000)
301 #define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000)
302 #define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000)
303 #define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000)
305 /*
306 * MCU_CMD_CFG
307 */
308 #define MCU_CMD_CFG 0x022c
310 /*
311 * AC_VO register offsets
312 */
313 #define TX_BASE_PTR0 0x0230
314 #define TX_MAX_CNT0 0x0234
315 #define TX_CTX_IDX0 0x0238
316 #define TX_DTX_IDX0 0x023c
318 /*
319 * AC_VI register offsets
320 */
321 #define TX_BASE_PTR1 0x0240
322 #define TX_MAX_CNT1 0x0244
323 #define TX_CTX_IDX1 0x0248
324 #define TX_DTX_IDX1 0x024c
326 /*
327 * AC_BE register offsets
328 */
329 #define TX_BASE_PTR2 0x0250
330 #define TX_MAX_CNT2 0x0254
331 #define TX_CTX_IDX2 0x0258
332 #define TX_DTX_IDX2 0x025c
334 /*
335 * AC_BK register offsets
336 */
337 #define TX_BASE_PTR3 0x0260
338 #define TX_MAX_CNT3 0x0264
339 #define TX_CTX_IDX3 0x0268
340 #define TX_DTX_IDX3 0x026c
342 /*
343 * HCCA register offsets
344 */
345 #define TX_BASE_PTR4 0x0270
346 #define TX_MAX_CNT4 0x0274
347 #define TX_CTX_IDX4 0x0278
348 #define TX_DTX_IDX4 0x027c
350 /*
351 * MGMT register offsets
352 */
353 #define TX_BASE_PTR5 0x0280
354 #define TX_MAX_CNT5 0x0284
355 #define TX_CTX_IDX5 0x0288
356 #define TX_DTX_IDX5 0x028c
358 /*
359 * RX register offsets
360 */
361 #define RX_BASE_PTR 0x0290
362 #define RX_MAX_CNT 0x0294
363 #define RX_CRX_IDX 0x0298
364 #define RX_DRX_IDX 0x029c
366 /*
367 * USB_DMA_CFG
368 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
369 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
370 * PHY_CLEAR: phy watch dog enable.
371 * TX_CLEAR: Clear USB DMA TX path.
372 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
373 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
374 * RX_BULK_EN: Enable USB DMA Rx.
375 * TX_BULK_EN: Enable USB DMA Tx.
376 * EP_OUT_VALID: OUT endpoint data valid.
377 * RX_BUSY: USB DMA RX FSM busy.
378 * TX_BUSY: USB DMA TX FSM busy.
379 */
380 #define USB_DMA_CFG 0x02a0
381 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
382 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
383 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
384 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
385 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
386 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
387 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
388 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
389 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
390 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
391 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
393 /*
394 * US_CYC_CNT
395 * BT_MODE_EN: Bluetooth mode enable
396 * CLOCK CYCLE: Clock cycle count in 1us.
397 * PCI:0x21, PCIE:0x7d, USB:0x1e
398 */
399 #define US_CYC_CNT 0x02a4
400 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
401 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
403 /*
404 * PBF_SYS_CTRL
405 * HOST_RAM_WRITE: enable Host program ram write selection
406 */
407 #define PBF_SYS_CTRL 0x0400
408 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
409 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
411 /*
412 * HOST-MCU shared memory
413 */
414 #define HOST_CMD_CSR 0x0404
415 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
417 /*
418 * PBF registers
419 * Most are for debug. Driver doesn't touch PBF register.
420 */
421 #define PBF_CFG 0x0408
422 #define PBF_MAX_PCNT 0x040c
423 #define PBF_CTRL 0x0410
424 #define PBF_INT_STA 0x0414
425 #define PBF_INT_ENA 0x0418
427 /*
428 * BCN_OFFSET0:
429 */
430 #define BCN_OFFSET0 0x042c
431 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
432 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
433 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
434 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
436 /*
437 * BCN_OFFSET1:
438 */
439 #define BCN_OFFSET1 0x0430
440 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
441 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
442 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
443 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
445 /*
446 * TXRXQ_PCNT: PBF register
447 * PCNT_TX0Q: Page count for TX hardware queue 0
448 * PCNT_TX1Q: Page count for TX hardware queue 1
449 * PCNT_TX2Q: Page count for TX hardware queue 2
450 * PCNT_RX0Q: Page count for RX hardware queue
451 */
452 #define TXRXQ_PCNT 0x0438
453 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
454 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
455 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
456 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
458 /*
459 * PBF register
460 * Debug. Driver doesn't touch PBF register.
461 */
462 #define PBF_DBG 0x043c
464 /*
465 * RF registers
466 */
467 #define RF_CSR_CFG 0x0500
468 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
469 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
470 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
471 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
473 /*
474 * EFUSE_CSR: RT30x0 EEPROM
475 */
476 #define EFUSE_CTRL 0x0580
477 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
478 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
479 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
480 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
482 /*
483 * EFUSE_DATA0
484 */
485 #define EFUSE_DATA0 0x0590
487 /*
488 * EFUSE_DATA1
489 */
490 #define EFUSE_DATA1 0x0594
492 /*
493 * EFUSE_DATA2
494 */
495 #define EFUSE_DATA2 0x0598
497 /*
498 * EFUSE_DATA3
499 */
500 #define EFUSE_DATA3 0x059c
502 /*
503 * LDO_CFG0
504 */
505 #define LDO_CFG0 0x05d4
506 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
507 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
508 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
509 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
510 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
511 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
512 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
514 /*
515 * GPIO_SWITCH
516 */
517 #define GPIO_SWITCH 0x05dc
518 #define GPIO_SWITCH_0 FIELD32(0x00000001)
519 #define GPIO_SWITCH_1 FIELD32(0x00000002)
520 #define GPIO_SWITCH_2 FIELD32(0x00000004)
521 #define GPIO_SWITCH_3 FIELD32(0x00000008)
522 #define GPIO_SWITCH_4 FIELD32(0x00000010)
523 #define GPIO_SWITCH_5 FIELD32(0x00000020)
524 #define GPIO_SWITCH_6 FIELD32(0x00000040)
525 #define GPIO_SWITCH_7 FIELD32(0x00000080)
527 /*
528 * MAC Control/Status Registers(CSR).
529 * Some values are set in TU, whereas 1 TU == 1024 us.
530 */
532 /*
533 * MAC_CSR0: ASIC revision number.
534 * ASIC_REV: 0
535 * ASIC_VER: 2860 or 2870
536 */
537 #define MAC_CSR0 0x1000
538 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
539 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
541 /*
542 * MAC_SYS_CTRL:
543 */
544 #define MAC_SYS_CTRL 0x1004
545 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
546 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
547 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
548 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
549 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
550 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
551 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
552 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
554 /*
555 * MAC_ADDR_DW0: STA MAC register 0
556 */
557 #define MAC_ADDR_DW0 0x1008
558 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
559 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
560 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
561 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
563 /*
564 * MAC_ADDR_DW1: STA MAC register 1
565 * UNICAST_TO_ME_MASK:
566 * Used to mask off bits from byte 5 of the MAC address
567 * to determine the UNICAST_TO_ME bit for RX frames.
568 * The full mask is complemented by BSS_ID_MASK:
569 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
570 */
571 #define MAC_ADDR_DW1 0x100c
572 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
573 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
574 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
576 /*
577 * MAC_BSSID_DW0: BSSID register 0
578 */
579 #define MAC_BSSID_DW0 0x1010
580 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
581 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
582 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
583 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
585 /*
586 * MAC_BSSID_DW1: BSSID register 1
587 * BSS_ID_MASK:
588 * 0: 1-BSSID mode (BSS index = 0)
589 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
590 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
591 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
592 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
593 * BSSID. This will make sure that those bits will be ignored
594 * when determining the MY_BSS of RX frames.
595 */
596 #define MAC_BSSID_DW1 0x1014
597 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
598 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
599 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
600 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
602 /*
603 * MAX_LEN_CFG: Maximum frame length register.
604 * MAX_MPDU: rt2860b max 16k bytes
605 * MAX_PSDU: Maximum PSDU length
606 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
607 */
608 #define MAX_LEN_CFG 0x1018
609 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
610 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
611 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
612 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
614 /*
615 * BBP_CSR_CFG: BBP serial control register
616 * VALUE: Register value to program into BBP
617 * REG_NUM: Selected BBP register
618 * READ_CONTROL: 0 write BBP, 1 read BBP
619 * BUSY: ASIC is busy executing BBP commands
620 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
621 * BBP_RW_MODE: 0 serial, 1 parallel
622 */
623 #define BBP_CSR_CFG 0x101c
624 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
625 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
626 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
627 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
628 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
629 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
631 /*
632 * RF_CSR_CFG0: RF control register
633 * REGID_AND_VALUE: Register value to program into RF
634 * BITWIDTH: Selected RF register
635 * STANDBYMODE: 0 high when standby, 1 low when standby
636 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
637 * BUSY: ASIC is busy executing RF commands
638 */
639 #define RF_CSR_CFG0 0x1020
640 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
641 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
642 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
643 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
644 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
645 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
647 /*
648 * RF_CSR_CFG1: RF control register
649 * REGID_AND_VALUE: Register value to program into RF
650 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
651 * 0: 3 system clock cycle (37.5usec)
652 * 1: 5 system clock cycle (62.5usec)
653 */
654 #define RF_CSR_CFG1 0x1024
655 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
656 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
658 /*
659 * RF_CSR_CFG2: RF control register
660 * VALUE: Register value to program into RF
661 */
662 #define RF_CSR_CFG2 0x1028
663 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
665 /*
666 * LED_CFG: LED control
667 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
668 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
669 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
670 * color LED's:
671 * 0: off
672 * 1: blinking upon TX2
673 * 2: periodic slow blinking
674 * 3: always on
675 * LED polarity:
676 * 0: active low
677 * 1: active high
678 */
679 #define LED_CFG 0x102c
680 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
681 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
682 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
683 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
684 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
685 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
686 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
688 /*
689 * AMPDU_BA_WINSIZE: Force BlockAck window size
690 * FORCE_WINSIZE_ENABLE:
691 * 0: Disable forcing of BlockAck window size
692 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
693 * window size values in the TXWI
694 * FORCE_WINSIZE: BlockAck window size
695 */
696 #define AMPDU_BA_WINSIZE 0x1040
697 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
698 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
700 /*
701 * XIFS_TIME_CFG: MAC timing
702 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
703 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
704 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
705 * when MAC doesn't reference BBP signal BBRXEND
706 * EIFS: unit 1us
707 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
708 *
709 */
710 #define XIFS_TIME_CFG 0x1100
711 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
712 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
713 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
714 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
715 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
717 /*
718 * BKOFF_SLOT_CFG:
719 */
720 #define BKOFF_SLOT_CFG 0x1104
721 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
722 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
724 /*
725 * NAV_TIME_CFG:
726 */
727 #define NAV_TIME_CFG 0x1108
728 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
729 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
730 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
731 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
733 /*
734 * CH_TIME_CFG: count as channel busy
735 * EIFS_BUSY: Count EIFS as channel busy
736 * NAV_BUSY: Count NAS as channel busy
737 * RX_BUSY: Count RX as channel busy
738 * TX_BUSY: Count TX as channel busy
739 * TMR_EN: Enable channel statistics timer
740 */
741 #define CH_TIME_CFG 0x110c
742 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
743 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
744 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
745 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
746 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
748 /*
749 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
750 */
751 #define PBF_LIFE_TIMER 0x1110
753 /*
754 * BCN_TIME_CFG:
755 * BEACON_INTERVAL: in unit of 1/16 TU
756 * TSF_TICKING: Enable TSF auto counting
757 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
758 * BEACON_GEN: Enable beacon generator
759 */
760 #define BCN_TIME_CFG 0x1114
761 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
762 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
763 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
764 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
765 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
766 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
768 /*
769 * TBTT_SYNC_CFG:
770 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
771 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
772 */
773 #define TBTT_SYNC_CFG 0x1118
774 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
775 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
776 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
777 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
779 /*
780 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
781 */
782 #define TSF_TIMER_DW0 0x111c
783 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
785 /*
786 * TSF_TIMER_DW1: Local msb TSF timer, read-only
787 */
788 #define TSF_TIMER_DW1 0x1120
789 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
791 /*
792 * TBTT_TIMER: TImer remains till next TBTT, read-only
793 */
794 #define TBTT_TIMER 0x1124
796 /*
797 * INT_TIMER_CFG: timer configuration
798 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
799 * GP_TIMER: period of general purpose timer in units of 1/16 TU
800 */
801 #define INT_TIMER_CFG 0x1128
802 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
803 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
805 /*
806 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
807 */
808 #define INT_TIMER_EN 0x112c
809 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
810 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
812 /*
813 * CH_IDLE_STA: channel idle time (in us)
814 */
815 #define CH_IDLE_STA 0x1130
817 /*
818 * CH_BUSY_STA: channel busy time on primary channel (in us)
819 */
820 #define CH_BUSY_STA 0x1134
822 /*
823 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
824 */
825 #define CH_BUSY_STA_SEC 0x1138
827 /*
828 * MAC_STATUS_CFG:
829 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
830 * if 1 or higher one of the 2 registers is busy.
831 */
832 #define MAC_STATUS_CFG 0x1200
833 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
835 /*
836 * PWR_PIN_CFG:
837 */
838 #define PWR_PIN_CFG 0x1204
840 /*
841 * AUTOWAKEUP_CFG: Manual power control / status register
842 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
843 * AUTOWAKE: 0:sleep, 1:awake
844 */
845 #define AUTOWAKEUP_CFG 0x1208
846 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
847 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
848 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
850 /*
851 * EDCA_AC0_CFG:
852 */
853 #define EDCA_AC0_CFG 0x1300
854 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
855 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
856 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
857 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
859 /*
860 * EDCA_AC1_CFG:
861 */
862 #define EDCA_AC1_CFG 0x1304
863 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
864 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
865 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
866 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
868 /*
869 * EDCA_AC2_CFG:
870 */
871 #define EDCA_AC2_CFG 0x1308
872 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
873 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
874 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
875 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
877 /*
878 * EDCA_AC3_CFG:
879 */
880 #define EDCA_AC3_CFG 0x130c
881 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
882 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
883 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
884 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
886 /*
887 * EDCA_TID_AC_MAP:
888 */
889 #define EDCA_TID_AC_MAP 0x1310
891 /*
892 * TX_PWR_CFG:
893 */
894 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
895 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
896 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
897 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
898 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
899 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
900 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
901 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
903 /*
904 * TX_PWR_CFG_0:
905 */
906 #define TX_PWR_CFG_0 0x1314
907 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
908 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
909 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
910 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
911 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
912 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
913 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
914 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
916 /*
917 * TX_PWR_CFG_1:
918 */
919 #define TX_PWR_CFG_1 0x1318
920 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
921 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
922 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
923 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
924 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
925 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
926 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
927 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
929 /*
930 * TX_PWR_CFG_2:
931 */
932 #define TX_PWR_CFG_2 0x131c
933 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
934 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
935 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
936 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
937 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
938 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
939 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
940 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
942 /*
943 * TX_PWR_CFG_3:
944 */
945 #define TX_PWR_CFG_3 0x1320
946 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
947 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
948 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
949 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
950 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
951 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
952 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
953 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
955 /*
956 * TX_PWR_CFG_4:
957 */
958 #define TX_PWR_CFG_4 0x1324
959 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
960 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
961 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
962 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
964 /*
965 * TX_PIN_CFG:
966 */
967 #define TX_PIN_CFG 0x1328
968 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
969 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
970 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
971 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
972 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
973 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
974 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
975 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
976 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
977 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
978 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
979 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
980 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
981 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
982 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
983 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
984 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
985 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
986 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
987 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
989 /*
990 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
991 */
992 #define TX_BAND_CFG 0x132c
993 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
994 #define TX_BAND_CFG_A FIELD32(0x00000002)
995 #define TX_BAND_CFG_BG FIELD32(0x00000004)
997 /*
998 * TX_SW_CFG0:
999 */
1000 #define TX_SW_CFG0 0x1330
1002 /*
1003 * TX_SW_CFG1:
1004 */
1005 #define TX_SW_CFG1 0x1334
1007 /*
1008 * TX_SW_CFG2:
1009 */
1010 #define TX_SW_CFG2 0x1338
1012 /*
1013 * TXOP_THRES_CFG:
1014 */
1015 #define TXOP_THRES_CFG 0x133c
1017 /*
1018 * TXOP_CTRL_CFG:
1019 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1020 * AC_TRUN_EN: Enable/Disable truncation for AC change
1021 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1022 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1023 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1024 * RESERVED_TRUN_EN: Reserved
1025 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1026 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1027 * transmissions if extension CCA is clear).
1028 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1029 * EXT_CWMIN: CwMin for extension channel backoff
1030 * 0: Disabled
1031 *
1032 */
1033 #define TXOP_CTRL_CFG 0x1340
1034 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1035 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1036 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1037 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1038 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1039 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1040 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1041 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1042 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1043 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1045 /*
1046 * TX_RTS_CFG:
1047 * RTS_THRES: unit:byte
1048 * RTS_FBK_EN: enable rts rate fallback
1049 */
1050 #define TX_RTS_CFG 0x1344
1051 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1052 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1053 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1055 /*
1056 * TX_TIMEOUT_CFG:
1057 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1058 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1059 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1060 * it is recommended that:
1061 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1062 */
1063 #define TX_TIMEOUT_CFG 0x1348
1064 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1065 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1066 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1068 /*
1069 * TX_RTY_CFG:
1070 * SHORT_RTY_LIMIT: short retry limit
1071 * LONG_RTY_LIMIT: long retry limit
1072 * LONG_RTY_THRE: Long retry threshoold
1073 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1074 * 0:expired by retry limit, 1: expired by mpdu life timer
1075 * AGG_RTY_MODE: Aggregate MPDU retry mode
1076 * 0:expired by retry limit, 1: expired by mpdu life timer
1077 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1078 */
1079 #define TX_RTY_CFG 0x134c
1080 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1081 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1082 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1083 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1084 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1085 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1087 /*
1088 * TX_LINK_CFG:
1089 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1090 * MFB_ENABLE: TX apply remote MFB 1:enable
1091 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1092 * 0: not apply remote remote unsolicit (MFS=7)
1093 * TX_MRQ_EN: MCS request TX enable
1094 * TX_RDG_EN: RDG TX enable
1095 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1096 * REMOTE_MFB: remote MCS feedback
1097 * REMOTE_MFS: remote MCS feedback sequence number
1098 */
1099 #define TX_LINK_CFG 0x1350
1100 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1101 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1102 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1103 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1104 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1105 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1106 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1107 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1109 /*
1110 * HT_FBK_CFG0:
1111 */
1112 #define HT_FBK_CFG0 0x1354
1113 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1114 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1115 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1116 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1117 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1118 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1119 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1120 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1122 /*
1123 * HT_FBK_CFG1:
1124 */
1125 #define HT_FBK_CFG1 0x1358
1126 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1127 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1128 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1129 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1130 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1131 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1132 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1133 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1135 /*
1136 * LG_FBK_CFG0:
1137 */
1138 #define LG_FBK_CFG0 0x135c
1139 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1140 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1141 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1142 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1143 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1144 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1145 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1146 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1148 /*
1149 * LG_FBK_CFG1:
1150 */
1151 #define LG_FBK_CFG1 0x1360
1152 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1153 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1154 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1155 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1157 /*
1158 * CCK_PROT_CFG: CCK Protection
1159 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1160 * PROTECT_CTRL: Protection control frame type for CCK TX
1161 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1162 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1163 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1164 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1165 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1166 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1167 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1168 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1169 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1170 * RTS_TH_EN: RTS threshold enable on CCK TX
1171 */
1172 #define CCK_PROT_CFG 0x1364
1173 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1174 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1175 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1176 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1177 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1178 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1179 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1180 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1181 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1182 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1183 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1185 /*
1186 * OFDM_PROT_CFG: OFDM Protection
1187 */
1188 #define OFDM_PROT_CFG 0x1368
1189 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1190 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1191 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1192 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1193 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1194 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1195 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1196 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1197 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1198 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1199 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1201 /*
1202 * MM20_PROT_CFG: MM20 Protection
1203 */
1204 #define MM20_PROT_CFG 0x136c
1205 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1206 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1207 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1208 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1209 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1210 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1211 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1212 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1213 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1214 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1215 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1217 /*
1218 * MM40_PROT_CFG: MM40 Protection
1219 */
1220 #define MM40_PROT_CFG 0x1370
1221 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1222 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1223 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1224 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1225 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1226 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1227 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1228 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1229 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1230 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1231 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1233 /*
1234 * GF20_PROT_CFG: GF20 Protection
1235 */
1236 #define GF20_PROT_CFG 0x1374
1237 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1238 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1239 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1240 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1241 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1242 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1243 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1244 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1245 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1246 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1247 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1249 /*
1250 * GF40_PROT_CFG: GF40 Protection
1251 */
1252 #define GF40_PROT_CFG 0x1378
1253 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1254 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1255 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1256 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1257 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1258 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1259 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1260 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1261 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1262 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1263 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1265 /*
1266 * EXP_CTS_TIME:
1267 */
1268 #define EXP_CTS_TIME 0x137c
1270 /*
1271 * EXP_ACK_TIME:
1272 */
1273 #define EXP_ACK_TIME 0x1380
1275 /*
1276 * RX_FILTER_CFG: RX configuration register.
1277 */
1278 #define RX_FILTER_CFG 0x1400
1279 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1280 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1281 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1282 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1283 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1284 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1285 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1286 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1287 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1288 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1289 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1290 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1291 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1292 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1293 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1294 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1295 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1297 /*
1298 * AUTO_RSP_CFG:
1299 * AUTORESPONDER: 0: disable, 1: enable
1300 * BAC_ACK_POLICY: 0:long, 1:short preamble
1301 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1302 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1303 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1304 * DUAL_CTS_EN: Power bit value in control frame
1305 * ACK_CTS_PSM_BIT:Power bit value in control frame
1306 */
1307 #define AUTO_RSP_CFG 0x1404
1308 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1309 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1310 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1311 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1312 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1313 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1314 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1316 /*
1317 * LEGACY_BASIC_RATE:
1318 */
1319 #define LEGACY_BASIC_RATE 0x1408
1321 /*
1322 * HT_BASIC_RATE:
1323 */
1324 #define HT_BASIC_RATE 0x140c
1326 /*
1327 * HT_CTRL_CFG:
1328 */
1329 #define HT_CTRL_CFG 0x1410
1331 /*
1332 * SIFS_COST_CFG:
1333 */
1334 #define SIFS_COST_CFG 0x1414
1336 /*
1337 * RX_PARSER_CFG:
1338 * Set NAV for all received frames
1339 */
1340 #define RX_PARSER_CFG 0x1418
1342 /*
1343 * TX_SEC_CNT0:
1344 */
1345 #define TX_SEC_CNT0 0x1500
1347 /*
1348 * RX_SEC_CNT0:
1349 */
1350 #define RX_SEC_CNT0 0x1504
1352 /*
1353 * CCMP_FC_MUTE:
1354 */
1355 #define CCMP_FC_MUTE 0x1508
1357 /*
1358 * TXOP_HLDR_ADDR0:
1359 */
1360 #define TXOP_HLDR_ADDR0 0x1600
1362 /*
1363 * TXOP_HLDR_ADDR1:
1364 */
1365 #define TXOP_HLDR_ADDR1 0x1604
1367 /*
1368 * TXOP_HLDR_ET:
1369 */
1370 #define TXOP_HLDR_ET 0x1608
1372 /*
1373 * QOS_CFPOLL_RA_DW0:
1374 */
1375 #define QOS_CFPOLL_RA_DW0 0x160c
1377 /*
1378 * QOS_CFPOLL_RA_DW1:
1379 */
1380 #define QOS_CFPOLL_RA_DW1 0x1610
1382 /*
1383 * QOS_CFPOLL_QC:
1384 */
1385 #define QOS_CFPOLL_QC 0x1614
1387 /*
1388 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1389 */
1390 #define RX_STA_CNT0 0x1700
1391 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1392 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1394 /*
1395 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1396 */
1397 #define RX_STA_CNT1 0x1704
1398 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1399 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1401 /*
1402 * RX_STA_CNT2:
1403 */
1404 #define RX_STA_CNT2 0x1708
1405 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1406 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1408 /*
1409 * TX_STA_CNT0: TX Beacon count
1410 */
1411 #define TX_STA_CNT0 0x170c
1412 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1413 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1415 /*
1416 * TX_STA_CNT1: TX tx count
1417 */
1418 #define TX_STA_CNT1 0x1710
1419 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1420 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1422 /*
1423 * TX_STA_CNT2: TX tx count
1424 */
1425 #define TX_STA_CNT2 0x1714
1426 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1427 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1429 /*
1430 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1431 *
1432 * This register is implemented as FIFO with 16 entries in the HW. Each
1433 * register read fetches the next tx result. If the FIFO is full because
1434 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1435 * triggered, the hw seems to simply drop further tx results.
1436 *
1437 * VALID: 1: this tx result is valid
1438 * 0: no valid tx result -> driver should stop reading
1439 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1440 * to match a frame with its tx result (even though the PID is
1441 * only 4 bits wide).
1442 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1443 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1444 * This identification number is calculated by ((idx % 3) + 1).
1445 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1446 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1447 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1448 * WCID: The wireless client ID.
1449 * MCS: The tx rate used during the last transmission of this frame, be it
1450 * successful or not.
1451 * PHYMODE: The phymode used for the transmission.
1452 */
1453 #define TX_STA_FIFO 0x1718
1454 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1455 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1456 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1457 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1458 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1459 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1460 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1461 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1462 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1463 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1464 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1466 /*
1467 * TX_AGG_CNT: Debug counter
1468 */
1469 #define TX_AGG_CNT 0x171c
1470 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1471 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1473 /*
1474 * TX_AGG_CNT0:
1475 */
1476 #define TX_AGG_CNT0 0x1720
1477 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1478 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1480 /*
1481 * TX_AGG_CNT1:
1482 */
1483 #define TX_AGG_CNT1 0x1724
1484 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1485 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1487 /*
1488 * TX_AGG_CNT2:
1489 */
1490 #define TX_AGG_CNT2 0x1728
1491 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1492 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1494 /*
1495 * TX_AGG_CNT3:
1496 */
1497 #define TX_AGG_CNT3 0x172c
1498 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1499 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1501 /*
1502 * TX_AGG_CNT4:
1503 */
1504 #define TX_AGG_CNT4 0x1730
1505 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1506 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1508 /*
1509 * TX_AGG_CNT5:
1510 */
1511 #define TX_AGG_CNT5 0x1734
1512 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1513 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1515 /*
1516 * TX_AGG_CNT6:
1517 */
1518 #define TX_AGG_CNT6 0x1738
1519 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1520 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1522 /*
1523 * TX_AGG_CNT7:
1524 */
1525 #define TX_AGG_CNT7 0x173c
1526 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1527 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1529 /*
1530 * MPDU_DENSITY_CNT:
1531 * TX_ZERO_DEL: TX zero length delimiter count
1532 * RX_ZERO_DEL: RX zero length delimiter count
1533 */
1534 #define MPDU_DENSITY_CNT 0x1740
1535 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1536 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1538 /*
1539 * Security key table memory.
1540 *
1541 * The pairwise key table shares some memory with the beacon frame
1542 * buffers 6 and 7. That basically means that when beacon 6 & 7
1543 * are used we should only use the reduced pairwise key table which
1544 * has a maximum of 222 entries.
1545 *
1546 * ---------------------------------------------
1547 * |0x4000 | Pairwise Key | Reduced Pairwise |
1548 * | | Table | Key Table |
1549 * | | Size: 256 * 32 | Size: 222 * 32 |
1550 * |0x5BC0 | |-------------------
1551 * | | | Beacon 6 |
1552 * |0x5DC0 | |-------------------
1553 * | | | Beacon 7 |
1554 * |0x5FC0 | |-------------------
1555 * |0x5FFF | |
1556 * --------------------------
1557 *
1558 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1559 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1560 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1561 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1562 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1563 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1564 */
1565 #define MAC_WCID_BASE 0x1800
1566 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1567 #define MAC_IVEIV_TABLE_BASE 0x6000
1568 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1569 #define SHARED_KEY_TABLE_BASE 0x6c00
1570 #define SHARED_KEY_MODE_BASE 0x7000
1572 #define MAC_WCID_ENTRY(__idx) \
1573 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1574 #define PAIRWISE_KEY_ENTRY(__idx) \
1575 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1576 #define MAC_IVEIV_ENTRY(__idx) \
1577 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1578 #define MAC_WCID_ATTR_ENTRY(__idx) \
1579 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1580 #define SHARED_KEY_ENTRY(__idx) \
1581 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1582 #define SHARED_KEY_MODE_ENTRY(__idx) \
1583 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1600 /*
1601 * MAC_WCID_ATTRIBUTE:
1602 */
1603 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1604 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1605 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1606 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1607 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1608 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1609 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1610 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1612 /*
1613 * SHARED_KEY_MODE:
1614 */
1615 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1616 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1617 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1618 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1619 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1620 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1621 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1622 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1624 /*
1625 * HOST-MCU communication
1626 */
1628 /*
1629 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1630 */
1631 #define H2M_MAILBOX_CSR 0x7010
1632 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1633 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1634 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1635 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1637 /*
1638 * H2M_MAILBOX_CID:
1639 */
1640 #define H2M_MAILBOX_CID 0x7014
1641 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1642 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1643 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1644 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1646 /*
1647 * H2M_MAILBOX_STATUS:
1648 */
1649 #define H2M_MAILBOX_STATUS 0x701c
1651 /*
1652 * H2M_INT_SRC:
1653 */
1654 #define H2M_INT_SRC 0x7024
1656 /*
1657 * H2M_BBP_AGENT:
1658 */
1659 #define H2M_BBP_AGENT 0x7028
1661 /*
1662 * MCU_LEDCS: LED control for MCU Mailbox.
1663 */
1664 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1665 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1667 /*
1668 * HW_CS_CTS_BASE:
1669 * Carrier-sense CTS frame base address.
1670 * It's where mac stores carrier-sense frame for carrier-sense function.
1671 */
1672 #define HW_CS_CTS_BASE 0x7700
1674 /*
1675 * HW_DFS_CTS_BASE:
1676 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1677 */
1678 #define HW_DFS_CTS_BASE 0x7780
1680 /*
1681 * TXRX control registers - base address 0x3000
1682 */
1684 /*
1685 * TXRX_CSR1:
1686 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1687 */
1688 #define TXRX_CSR1 0x77d0
1690 /*
1691 * HW_DEBUG_SETTING_BASE:
1692 * since NULL frame won't be that long (256 byte)
1693 * We steal 16 tail bytes to save debugging settings
1694 */
1695 #define HW_DEBUG_SETTING_BASE 0x77f0
1696 #define HW_DEBUG_SETTING_BASE2 0x7770
1698 /*
1699 * HW_BEACON_BASE
1700 * In order to support maximum 8 MBSS and its maximum length
1701 * is 512 bytes for each beacon
1702 * Three section discontinue memory segments will be used.
1703 * 1. The original region for BCN 0~3
1704 * 2. Extract memory from FCE table for BCN 4~5
1705 * 3. Extract memory from Pair-wise key table for BCN 6~7
1706 * It occupied those memory of wcid 238~253 for BCN 6
1707 * and wcid 222~237 for BCN 7 (see Security key table memory
1708 * for more info).
1709 *
1710 * IMPORTANT NOTE: Not sure why legacy driver does this,
1711 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1712 */
1713 #define HW_BEACON_BASE0 0x7800
1714 #define HW_BEACON_BASE1 0x7a00
1715 #define HW_BEACON_BASE2 0x7c00
1716 #define HW_BEACON_BASE3 0x7e00
1717 #define HW_BEACON_BASE4 0x7200
1718 #define HW_BEACON_BASE5 0x7400
1719 #define HW_BEACON_BASE6 0x5dc0
1720 #define HW_BEACON_BASE7 0x5bc0
1722 #define HW_BEACON_OFFSET(__index) \
1723 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1724 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1725 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1727 /*
1728 * BBP registers.
1729 * The wordsize of the BBP is 8 bits.
1730 */
1732 /*
1733 * BBP 1: TX Antenna & Power Control
1734 * POWER_CTRL:
1735 * 0 - normal,
1736 * 1 - drop tx power by 6dBm,
1737 * 2 - drop tx power by 12dBm,
1738 * 3 - increase tx power by 6dBm
1739 */
1740 #define BBP1_TX_POWER_CTRL FIELD8(0x07)
1741 #define BBP1_TX_ANTENNA FIELD8(0x18)
1743 /*
1744 * BBP 3: RX Antenna
1745 */
1746 #define BBP3_RX_ADC FIELD8(0x03)
1747 #define BBP3_RX_ANTENNA FIELD8(0x18)
1748 #define BBP3_HT40_MINUS FIELD8(0x20)
1750 /*
1751 * BBP 4: Bandwidth
1752 */
1753 #define BBP4_TX_BF FIELD8(0x01)
1754 #define BBP4_BANDWIDTH FIELD8(0x18)
1755 #define BBP4_MAC_IF_CTRL FIELD8(0x40)
1757 /*
1758 * BBP 109
1759 */
1760 #define BBP109_TX0_POWER FIELD8(0x0f)
1761 #define BBP109_TX1_POWER FIELD8(0xf0)
1763 /*
1764 * BBP 138: Unknown
1765 */
1766 #define BBP138_RX_ADC1 FIELD8(0x02)
1767 #define BBP138_RX_ADC2 FIELD8(0x04)
1768 #define BBP138_TX_DAC1 FIELD8(0x20)
1769 #define BBP138_TX_DAC2 FIELD8(0x40)
1771 /*
1772 * BBP 152: Rx Ant
1773 */
1774 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1776 /*
1777 * RFCSR registers
1778 * The wordsize of the RFCSR is 8 bits.
1779 */
1781 /*
1782 * RFCSR 1:
1783 */
1784 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1785 #define RFCSR1_PLL_PD FIELD8(0x02)
1786 #define RFCSR1_RX0_PD FIELD8(0x04)
1787 #define RFCSR1_TX0_PD FIELD8(0x08)
1788 #define RFCSR1_RX1_PD FIELD8(0x10)
1789 #define RFCSR1_TX1_PD FIELD8(0x20)
1790 #define RFCSR1_RX2_PD FIELD8(0x40)
1791 #define RFCSR1_TX2_PD FIELD8(0x80)
1793 /*
1794 * RFCSR 2:
1795 */
1796 #define RFCSR2_RESCAL_EN FIELD8(0x80)
1798 /*
1799 * FRCSR 5:
1800 */
1801 #define RFCSR5_R1 FIELD8(0x0c)
1803 /*
1804 * RFCSR 6:
1805 */
1806 #define RFCSR6_R1 FIELD8(0x03)
1807 #define RFCSR6_R2 FIELD8(0x40)
1808 #define RFCSR6_TXDIV FIELD8(0x0c)
1810 /*
1811 * RFCSR 7:
1812 */
1813 #define RFCSR7_RF_TUNING FIELD8(0x01)
1814 #define RFCSR7_R02 FIELD8(0x07)
1815 #define RFCSR7_R3 FIELD8(0x08)
1816 #define RFCSR7_R45 FIELD8(0x30)
1817 #define RFCSR7_R67 FIELD8(0xc0)
1819 /*
1820 * RFCSR 11:
1821 */
1822 #define RFCSR11_R FIELD8(0x03)
1824 /*
1825 * RFCSR 12:
1826 */
1827 #define RFCSR12_TX_POWER FIELD8(0x1f)
1828 #define RFCSR12_DR0 FIELD8(0xe0)
1830 /*
1831 * RFCSR 13:
1832 */
1833 #define RFCSR13_TX_POWER FIELD8(0x1f)
1834 #define RFCSR13_DR0 FIELD8(0xe0)
1836 /*
1837 * RFCSR 15:
1838 */
1839 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
1841 /*
1842 * RFCSR 17:
1843 */
1844 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1845 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
1846 #define RFCSR17_R FIELD8(0x20)
1847 #define RFCSR17_CODE FIELD8(0x7f)
1849 /*
1850 * RFCSR 20:
1851 */
1852 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
1854 /*
1855 * RFCSR 21:
1856 */
1857 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
1859 /*
1860 * RFCSR 22:
1861 */
1862 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1864 /*
1865 * RFCSR 23:
1866 */
1867 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1869 /*
1870 * RFCSR 27:
1871 */
1872 #define RFCSR27_R1 FIELD8(0x03)
1873 #define RFCSR27_R2 FIELD8(0x04)
1874 #define RFCSR27_R3 FIELD8(0x30)
1875 #define RFCSR27_R4 FIELD8(0x40)
1877 /*
1878 * RFCSR 30:
1879 */
1880 #define RFCSR30_TX_H20M FIELD8(0x02)
1881 #define RFCSR30_RX_H20M FIELD8(0x04)
1882 #define RFCSR30_RX_VCM FIELD8(0x18)
1883 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1885 /*
1886 * RFCSR 31:
1887 */
1888 #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
1889 #define RFCSR31_RX_H20M FIELD8(0x20)
1891 /*
1892 * RFCSR 38:
1893 */
1894 #define RFCSR38_RX_LO1_EN FIELD8(0x20)
1896 /*
1897 * RFCSR 39:
1898 */
1899 #define RFCSR39_RX_LO2_EN FIELD8(0x80)
1901 /*
1902 * RFCSR 49:
1903 */
1904 #define RFCSR49_TX FIELD8(0x3f)
1906 /*
1907 * RF registers
1908 */
1910 /*
1911 * RF 2
1912 */
1913 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1914 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1915 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1917 /*
1918 * RF 3
1919 */
1920 #define RF3_TXPOWER_G FIELD32(0x00003e00)
1921 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1922 #define RF3_TXPOWER_A FIELD32(0x00003c00)
1924 /*
1925 * RF 4
1926 */
1927 #define RF4_TXPOWER_G FIELD32(0x000007c0)
1928 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1929 #define RF4_TXPOWER_A FIELD32(0x00000780)
1930 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1931 #define RF4_HT40 FIELD32(0x00200000)
1933 /*
1934 * EEPROM content.
1935 * The wordsize of the EEPROM is 16 bits.
1936 */
1938 /*
1939 * Chip ID
1940 */
1941 #define EEPROM_CHIP_ID 0x0000
1943 /*
1944 * EEPROM Version
1945 */
1946 #define EEPROM_VERSION 0x0001
1947 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
1948 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
1950 /*
1951 * HW MAC address.
1952 */
1953 #define EEPROM_MAC_ADDR_0 0x0002
1954 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1955 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1956 #define EEPROM_MAC_ADDR_1 0x0003
1957 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1958 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1959 #define EEPROM_MAC_ADDR_2 0x0004
1960 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1961 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1963 /*
1964 * EEPROM NIC Configuration 0
1965 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1966 * TXPATH: 1: 1T, 2: 2T, 3: 3T
1967 * RF_TYPE: RFIC type
1968 */
1969 #define EEPROM_NIC_CONF0 0x001a
1970 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
1971 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
1972 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
1974 /*
1975 * EEPROM NIC Configuration 1
1976 * HW_RADIO: 0: disable, 1: enable
1977 * EXTERNAL_TX_ALC: 0: disable, 1: enable
1978 * EXTERNAL_LNA_2G: 0: disable, 1: enable
1979 * EXTERNAL_LNA_5G: 0: disable, 1: enable
1980 * CARDBUS_ACCEL: 0: enable, 1: disable
1981 * BW40M_SB_2G: 0: disable, 1: enable
1982 * BW40M_SB_5G: 0: disable, 1: enable
1983 * WPS_PBC: 0: disable, 1: enable
1984 * BW40M_2G: 0: enable, 1: disable
1985 * BW40M_5G: 0: enable, 1: disable
1986 * BROADBAND_EXT_LNA: 0: disable, 1: enable
1987 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
1988 * 10: Main antenna, 11: Aux antenna
1989 * INTERNAL_TX_ALC: 0: disable, 1: enable
1990 * BT_COEXIST: 0: disable, 1: enable
1991 * DAC_TEST: 0: disable, 1: enable
1992 */
1993 #define EEPROM_NIC_CONF1 0x001b
1994 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
1995 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
1996 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
1997 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
1998 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
1999 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2000 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2001 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2002 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2003 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2004 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2005 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2006 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2007 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2008 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2010 /*
2011 * EEPROM frequency
2012 */
2013 #define EEPROM_FREQ 0x001d
2014 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2015 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2016 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2018 /*
2019 * EEPROM LED
2020 * POLARITY_RDY_G: Polarity RDY_G setting.
2021 * POLARITY_RDY_A: Polarity RDY_A setting.
2022 * POLARITY_ACT: Polarity ACT setting.
2023 * POLARITY_GPIO_0: Polarity GPIO0 setting.
2024 * POLARITY_GPIO_1: Polarity GPIO1 setting.
2025 * POLARITY_GPIO_2: Polarity GPIO2 setting.
2026 * POLARITY_GPIO_3: Polarity GPIO3 setting.
2027 * POLARITY_GPIO_4: Polarity GPIO4 setting.
2028 * LED_MODE: Led mode.
2029 */
2030 #define EEPROM_LED_AG_CONF 0x001e
2031 #define EEPROM_LED_ACT_CONF 0x001f
2032 #define EEPROM_LED_POLARITY 0x0020
2033 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2034 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2035 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2036 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2037 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2038 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2039 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2040 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2041 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2043 /*
2044 * EEPROM NIC Configuration 2
2045 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2046 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2047 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2048 */
2049 #define EEPROM_NIC_CONF2 0x0021
2050 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2051 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2052 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2054 /*
2055 * EEPROM LNA
2056 */
2057 #define EEPROM_LNA 0x0022
2058 #define EEPROM_LNA_BG FIELD16(0x00ff)
2059 #define EEPROM_LNA_A0 FIELD16(0xff00)
2061 /*
2062 * EEPROM RSSI BG offset
2063 */
2064 #define EEPROM_RSSI_BG 0x0023
2065 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2066 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2068 /*
2069 * EEPROM RSSI BG2 offset
2070 */
2071 #define EEPROM_RSSI_BG2 0x0024
2072 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2073 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2075 /*
2076 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2077 */
2078 #define EEPROM_TXMIXER_GAIN_BG 0x0024
2079 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2081 /*
2082 * EEPROM RSSI A offset
2083 */
2084 #define EEPROM_RSSI_A 0x0025
2085 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2086 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2088 /*
2089 * EEPROM RSSI A2 offset
2090 */
2091 #define EEPROM_RSSI_A2 0x0026
2092 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2093 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2095 /*
2096 * EEPROM EIRP Maximum TX power values(unit: dbm)
2097 */
2098 #define EEPROM_EIRP_MAX_TX_POWER 0x0027
2099 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2100 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2102 /*
2103 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2104 * This is delta in 40MHZ.
2105 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2106 * TYPE: 1: Plus the delta value, 0: minus the delta value
2107 * ENABLE: enable tx power compensation for 40BW
2108 */
2109 #define EEPROM_TXPOWER_DELTA 0x0028
2110 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2111 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2112 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2113 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2114 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2115 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2117 /*
2118 * EEPROM TXPOWER 802.11BG
2119 */
2120 #define EEPROM_TXPOWER_BG1 0x0029
2121 #define EEPROM_TXPOWER_BG2 0x0030
2122 #define EEPROM_TXPOWER_BG_SIZE 7
2123 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2124 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2126 /*
2127 * EEPROM temperature compensation boundaries 802.11BG
2128 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2129 * reduced by (agc_step * -4)
2130 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2131 * reduced by (agc_step * -3)
2132 */
2133 #define EEPROM_TSSI_BOUND_BG1 0x0037
2134 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2135 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2137 /*
2138 * EEPROM temperature compensation boundaries 802.11BG
2139 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2140 * reduced by (agc_step * -2)
2141 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2142 * reduced by (agc_step * -1)
2143 */
2144 #define EEPROM_TSSI_BOUND_BG2 0x0038
2145 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2146 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2148 /*
2149 * EEPROM temperature compensation boundaries 802.11BG
2150 * REF: Reference TSSI value, no tx power changes needed
2151 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2152 * increased by (agc_step * 1)
2153 */
2154 #define EEPROM_TSSI_BOUND_BG3 0x0039
2155 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2156 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2158 /*
2159 * EEPROM temperature compensation boundaries 802.11BG
2160 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2161 * increased by (agc_step * 2)
2162 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2163 * increased by (agc_step * 3)
2164 */
2165 #define EEPROM_TSSI_BOUND_BG4 0x003a
2166 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2167 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2169 /*
2170 * EEPROM temperature compensation boundaries 802.11BG
2171 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2172 * increased by (agc_step * 4)
2173 * AGC_STEP: Temperature compensation step.
2174 */
2175 #define EEPROM_TSSI_BOUND_BG5 0x003b
2176 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2177 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2179 /*
2180 * EEPROM TXPOWER 802.11A
2181 */
2182 #define EEPROM_TXPOWER_A1 0x003c
2183 #define EEPROM_TXPOWER_A2 0x0053
2184 #define EEPROM_TXPOWER_A_SIZE 6
2185 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2186 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2188 /*
2189 * EEPROM temperature compensation boundaries 802.11A
2190 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2191 * reduced by (agc_step * -4)
2192 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2193 * reduced by (agc_step * -3)
2194 */
2195 #define EEPROM_TSSI_BOUND_A1 0x006a
2196 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2197 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2199 /*
2200 * EEPROM temperature compensation boundaries 802.11A
2201 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2202 * reduced by (agc_step * -2)
2203 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2204 * reduced by (agc_step * -1)
2205 */
2206 #define EEPROM_TSSI_BOUND_A2 0x006b
2207 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2208 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2210 /*
2211 * EEPROM temperature compensation boundaries 802.11A
2212 * REF: Reference TSSI value, no tx power changes needed
2213 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2214 * increased by (agc_step * 1)
2215 */
2216 #define EEPROM_TSSI_BOUND_A3 0x006c
2217 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2218 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2220 /*
2221 * EEPROM temperature compensation boundaries 802.11A
2222 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2223 * increased by (agc_step * 2)
2224 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2225 * increased by (agc_step * 3)
2226 */
2227 #define EEPROM_TSSI_BOUND_A4 0x006d
2228 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2229 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2231 /*
2232 * EEPROM temperature compensation boundaries 802.11A
2233 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2234 * increased by (agc_step * 4)
2235 * AGC_STEP: Temperature compensation step.
2236 */
2237 #define EEPROM_TSSI_BOUND_A5 0x006e
2238 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2239 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2241 /*
2242 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2243 */
2244 #define EEPROM_TXPOWER_BYRATE 0x006f
2245 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2247 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2248 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2249 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2250 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2252 /*
2253 * EEPROM BBP.
2254 */
2255 #define EEPROM_BBP_START 0x0078
2256 #define EEPROM_BBP_SIZE 16
2257 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2258 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2260 /*
2261 * MCU mailbox commands.
2262 */
2263 #define MCU_SLEEP 0x30
2264 #define MCU_WAKEUP 0x31
2265 #define MCU_RADIO_OFF 0x35
2266 #define MCU_CURRENT 0x36
2267 #define MCU_LED 0x50
2268 #define MCU_LED_STRENGTH 0x51
2269 #define MCU_LED_AG_CONF 0x52
2270 #define MCU_LED_ACT_CONF 0x53
2271 #define MCU_LED_LED_POLARITY 0x54
2272 #define MCU_RADAR 0x60
2273 #define MCU_BOOT_SIGNAL 0x72
2274 #define MCU_ANT_SELECT 0X73
2275 #define MCU_BBP_SIGNAL 0x80
2276 #define MCU_POWER_SAVE 0x83
2277 #define MCU_BAND_SELECT 0x91
2279 /*
2280 * MCU mailbox tokens
2281 */
2282 #define TOKEN_WAKUP 3
2284 /*
2285 * DMA descriptor defines.
2286 */
2287 #define TXWI_DESC_SIZE (4 * sizeof(__le32))
2288 #define RXWI_DESC_SIZE (4 * sizeof(__le32))
2290 /*
2291 * TX WI structure
2292 */
2294 /*
2295 * Word0
2296 * FRAG: 1 To inform TKIP engine this is a fragment.
2297 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2298 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2299 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2300 * duplicate the frame to both channels).
2301 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2302 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2303 * aggregate consecutive frames with the same RA and QoS TID. If
2304 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2305 * directly after a frame B with AMPDU=1, frame A might still
2306 * get aggregated into the AMPDU started by frame B. So, setting
2307 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2308 * MPDU, it can still end up in an AMPDU if the previous frame
2309 * was tagged as AMPDU.
2310 */
2311 #define TXWI_W0_FRAG FIELD32(0x00000001)
2312 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2313 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2314 #define TXWI_W0_TS FIELD32(0x00000008)
2315 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2316 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2317 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2318 #define TXWI_W0_MCS FIELD32(0x007f0000)
2319 #define TXWI_W0_BW FIELD32(0x00800000)
2320 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2321 #define TXWI_W0_STBC FIELD32(0x06000000)
2322 #define TXWI_W0_IFS FIELD32(0x08000000)
2323 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2325 /*
2326 * Word1
2327 * ACK: 0: No Ack needed, 1: Ack needed
2328 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2329 * BW_WIN_SIZE: BA windows size of the recipient
2330 * WIRELESS_CLI_ID: Client ID for WCID table access
2331 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2332 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2333 * frame was processed. If multiple frames are aggregated together
2334 * (AMPDU==1) the reported tx status will always contain the packet
2335 * id of the first frame. 0: Don't report tx status for this frame.
2336 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2337 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2338 * This identification number is calculated by ((idx % 3) + 1).
2339 * The (+1) is required to prevent PACKETID to become 0.
2340 */
2341 #define TXWI_W1_ACK FIELD32(0x00000001)
2342 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2343 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2344 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2345 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2346 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2347 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2348 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2350 /*
2351 * Word2
2352 */
2353 #define TXWI_W2_IV FIELD32(0xffffffff)
2355 /*
2356 * Word3
2357 */
2358 #define TXWI_W3_EIV FIELD32(0xffffffff)
2360 /*
2361 * RX WI structure
2362 */
2364 /*
2365 * Word0
2366 */
2367 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2368 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2369 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2370 #define RXWI_W0_UDF FIELD32(0x0000e000)
2371 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2372 #define RXWI_W0_TID FIELD32(0xf0000000)
2374 /*
2375 * Word1
2376 */
2377 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2378 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2379 #define RXWI_W1_MCS FIELD32(0x007f0000)
2380 #define RXWI_W1_BW FIELD32(0x00800000)
2381 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2382 #define RXWI_W1_STBC FIELD32(0x06000000)
2383 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2385 /*
2386 * Word2
2387 */
2388 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2389 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2390 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2392 /*
2393 * Word3
2394 */
2395 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2396 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2398 /*
2399 * Macros for converting txpower from EEPROM to mac80211 value
2400 * and from mac80211 value to register value.
2401 */
2402 #define MIN_G_TXPOWER 0
2403 #define MIN_A_TXPOWER -7
2404 #define MAX_G_TXPOWER 31
2405 #define MAX_A_TXPOWER 15
2406 #define DEFAULT_TXPOWER 5
2408 #define TXPOWER_G_FROM_DEV(__txpower) \
2409 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2411 #define TXPOWER_G_TO_DEV(__txpower) \
2412 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2414 #define TXPOWER_A_FROM_DEV(__txpower) \
2415 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2417 #define TXPOWER_A_TO_DEV(__txpower) \
2418 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2420 /*
2421 * Board's maximun TX power limitation
2422 */
2423 #define EIRP_MAX_TX_POWER_LIMIT 0x50