Staging: pata_rdc: remove pointless comments
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / pata_rdc / pata_rdc.h
bloba833339886d9d031343c11f6e843f4f3eafe283f
1 #ifndef pata_rdc_H
2 #define pata_rdc_H
4 #ifndef TRUE
5 #define TRUE 1
6 #endif
8 #ifndef FALSE
9 #define FALSE 0
10 #endif
12 /* ATA Configuration Register ID offset address size */
13 #define ATAConfiguration_PCIOffset 0x40
14 #define ATAConfiguration_ID_PrimaryTiming 0x00
15 #define ATAConfiguration_ID_SecondaryTiming 0x02
16 #define ATAConfiguration_ID_Device1Timing 0x04
17 #define ATAConfiguration_ID_UDMAControl 0x08
18 #define ATAConfiguration_ID_UDMATiming 0x0A
19 #define ATAConfiguration_ID_IDEIOConfiguration 0x14
21 #define ATAConfiguration_ID_PrimaryTiming_Size 2
22 #define ATAConfiguration_ID_SecondaryTiming_Size 2
23 #define ATAConfiguration_ID_Device1Timing_Size 1
24 #define ATAConfiguration_ID_UDMAControl_Size 1
25 #define ATAConfiguration_ID_UDMATiming_Size 2
26 #define ATAConfiguration_ID_IDEIOConfiguration_Size 4
28 /* ATA Configuration Register bit define */
29 #define ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 0x0001
30 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 0x0002 /* PIO 3 or greater */
31 #define ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 0x0004 /* PIO 2 or greater */
32 #define ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 0x0008
33 #define ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 0x0010
34 #define ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 0x0020 /* PIO 3 or greater */
35 #define ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 0x0040 /* PIO 2 or greater */
36 #define ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 0x0080
37 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode 0x0300
38 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0 0x0000 /* PIO 0, PIO 2, MDMA 0 */
39 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1 0x0100 /* PIO 3, MDMA 1 */
40 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_2 0x0200 /* X */
41 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3 0x0300 /* PIO 4, MDMA 2 */
42 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 0x3000
43 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0 0x0000 /* PIO 0 */
44 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1 0x1000 /* PIO 2, MDMA 0 */
45 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2 0x2000 /* PIO 3, PIO 4, MDMA 1, MDMA 2 */
46 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_3 0x3000 /* X */
47 #define ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable 0x4000
48 #define ATAConfiguration_PrimaryTiming_IDEDecodeEnable 0x8000
50 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode 0x0003
51 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0 0x0000
52 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1 0x0001
53 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_2 0x0002
54 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3 0x0003
55 #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode 0x000C
56 #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0 0x0000
57 #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1 0x0004
58 #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2 0x0008
59 #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_3 0x000C
60 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode 0x0030
61 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0 0x0000
62 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1 0x0010
63 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_2 0x0020
64 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3 0x0030
65 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode 0x00C0
66 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0 0x0000
67 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1 0x0040
68 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2 0x0080
69 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_3 0x00C0
71 #define ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable 0x0001
72 #define ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable 0x0002
73 #define ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable 0x0004
74 #define ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable 0x0008
76 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime 0x0003
77 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0 0x0000 /* UDMA 0 */
78 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1 0x0001 /* UDMA 1, UDMA 3, UDMA 5 */
79 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2 0x0002 /* UDMA 2, UDMA 4 */
80 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_3 0x0003 /* X */
81 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime 0x0030
82 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0 0x0000 /* UDMA 0 */
83 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1 0x0010 /* UDMA 1, UDMA 3, UDMA 5 */
84 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2 0x0020 /* UDMA 2, UDMA 4 */
85 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_3 0x0030 /* X */
86 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime 0x0300
87 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0 0x0000 /* UDMA 0 */
88 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1 0x0100 /* UDMA 1, UDMA 3, UDMA 5 */
89 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2 0x0200 /* UDMA 2, UDMA 4 */
90 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_3 0x0300 /* X */
91 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime 0x3000
92 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0 0x0000 /* UDMA 0 */
93 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1 0x1000 /* UDMA 1, UDMA 3, UDMA 5 */
94 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2 0x2000 /* UDMA 2, UDMA 4 */
95 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_3 0x3000 /* X */
97 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable 0x00000001 /* UDMA 3, UDMA 4 */
98 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable 0x00000002
99 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable 0x00000004
100 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable 0x00000008
101 #define ATAConfiguration_IDEIOConfiguration_DeviceCable80Report 0x000000F0
102 #define ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report 0x00000030
103 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0Cable80Report 0x00000010 /* UDMA 3, UDMA 4, UDMA 5 */
104 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1Cable80Report 0x00000020
105 #define ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report 0x000000C0
106 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0Cable80Report 0x00000040
107 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1Cable80Report 0x00000080
108 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable 0x00001000 /* UDMA 5 */
109 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable 0x00002000
110 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable 0x00004000
111 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable 0x00008000
112 #define ATAConfiguration_IDEIOConfiguration_ATA100IsSupported 0x00F00000
114 enum _PIOTimingMode {
115 PIO0 = 0,
116 PIO1,
117 PIO2, /* MDMA 0 */
118 PIO3, /* MDMA 1 */
119 PIO4 /* MDMA 2 */
122 enum _DMATimingMode {
123 MDMA0 = 0,
124 MDMA1,
125 MDMA2
128 enum _UDMATimingMode {
129 UDMA0 = 0,
130 UDMA1,
131 UDMA2,
132 UDMA3,
133 UDMA4,
134 UDMA5
138 enum rdc_controller_ids {
139 /* controller IDs */
140 RDC_17F31011,
141 RDC_17F31012
144 #endif