1 #include <linux/kernel.h>
2 #include <linux/init.h>
3 #include <linux/module.h>
6 #include <linux/device.h>
8 #include <scsi/scsi_host.h>
9 #include <linux/libata.h>
13 static const struct pci_device_id rdc_pata_id_table
[] = {
14 { PCI_DEVICE(0x17F3, 0x1011), RDC_17F31011
},
15 { PCI_DEVICE(0x17F3, 0x1012), RDC_17F31012
},
16 { } /* terminate list */
18 MODULE_DEVICE_TABLE(pci
, rdc_pata_id_table
);
20 /* see ATA Host Adapters Standards. */
21 static struct pci_bits ATA_Decode_Enable_Bits
[] = {
22 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port (Channel) 0 */
23 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port (Channel) 1 */
26 static uint
PCIDeviceIO_ReadPCIConfiguration(struct pci_dev
*pdev
, uint Offset
, uint Length
, void *pBuffer
)
36 for (i
= 0; i
< Length
; i
++) {
37 pci_read_config_byte(pdev
, Offset
, pchar
);
50 static uint
PCIDeviceIO_WritePCIConfiguration(struct pci_dev
*pdev
, uint Offset
, uint Length
, void *pBuffer
)
60 for (i
= 0; i
< Length
; i
++) {
61 pci_write_config_byte(pdev
, Offset
, *pchar
);
74 static uint
ATAHostAdapter_SetPrimaryPIO(struct pci_dev
*pdev
, uint DeviceID
,
75 uint PIOTimingMode
, uint DMAEnable
,
76 uint PrefetchPostingEnable
)
80 uint ATATimingRegister
;
81 uint Device1TimingRegister
;
85 ATATimingRegister
= 0;
86 Device1TimingRegister
= 0;
88 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
89 ATAConfiguration_ID_PrimaryTiming
+ ATAConfiguration_PCIOffset
,
90 ATAConfiguration_ID_PrimaryTiming_Size
,
92 if (result
== FALSE
) {
97 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
98 ATAConfiguration_ID_Device1Timing
+ ATAConfiguration_PCIOffset
,
99 ATAConfiguration_ID_Device1Timing_Size
,
100 &Device1TimingRegister
);
101 if (result
== FALSE
) {
106 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable
;
111 ATATimingRegister
&= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable
|
112 ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable
|
113 ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
|
114 ATAConfiguration_PrimaryTiming_Device0DMATimingEnable
|
115 ATAConfiguration_PrimaryTiming_Device0RecoveryMode
|
116 ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode
);
118 if (PIOTimingMode
> PIO0
)
119 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable
;
121 if (PIOTimingMode
>= PIO3
)
122 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable
;
124 if (PIOTimingMode
>= PIO2
&& PrefetchPostingEnable
== TRUE
)
125 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
;
127 if (DMAEnable
== TRUE
&& PIOTimingMode
>= PIO2
)
128 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable
;
130 if (PIOTimingMode
<= PIO2
)
131 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0
;
132 else if (PIOTimingMode
== PIO3
)
133 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1
;
134 else if (PIOTimingMode
== PIO4
)
135 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3
;
137 if (PIOTimingMode
<= PIO1
)
138 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0
;
139 else if (PIOTimingMode
== PIO2
)
140 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1
;
141 else if (PIOTimingMode
<= PIO4
)
142 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2
;
145 ATATimingRegister
&= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable
|
146 ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable
|
147 ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable
|
148 ATAConfiguration_PrimaryTiming_Device1DMATimingEnable
);
150 if (PIOTimingMode
> PIO0
)
151 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable
;
153 if (PIOTimingMode
>= PIO3
)
154 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable
;
156 if (PIOTimingMode
>= PIO2
&& PrefetchPostingEnable
== TRUE
)
157 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable
;
159 if (DMAEnable
== TRUE
&& PIOTimingMode
>= PIO2
)
160 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable
;
162 Device1TimingRegister
&= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode
|
163 ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode
);
165 if (PIOTimingMode
<= PIO2
)
166 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0
;
167 else if (PIOTimingMode
== PIO3
)
168 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1
;
169 else if (PIOTimingMode
== PIO4
)
170 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3
;
172 if (PIOTimingMode
<= PIO1
)
173 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0
;
174 else if (PIOTimingMode
== PIO2
)
175 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1
;
176 else if (PIOTimingMode
<= PIO4
)
177 Device1TimingRegister
|= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2
;
185 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
186 ATAConfiguration_ID_PrimaryTiming
+ ATAConfiguration_PCIOffset
,
187 ATAConfiguration_ID_PrimaryTiming_Size
,
189 if (result
== FALSE
) {
194 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
195 ATAConfiguration_ID_Device1Timing
+ ATAConfiguration_PCIOffset
,
196 ATAConfiguration_ID_Device1Timing_Size
,
197 &Device1TimingRegister
);
198 if (result
== FALSE
) {
209 static uint
ATAHostAdapter_SetSecondaryPIO(struct pci_dev
*pdev
, uint DeviceID
,
210 uint PIOTimingMode
, uint DMAEnable
,
211 uint PrefetchPostingEnable
)
215 uint ATATimingRegister
;
216 uint Device1TimingRegister
;
220 ATATimingRegister
= 0;
221 Device1TimingRegister
= 0;
223 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
224 ATAConfiguration_ID_SecondaryTiming
+ ATAConfiguration_PCIOffset
,
225 ATAConfiguration_ID_SecondaryTiming_Size
,
227 if (result
== FALSE
) {
232 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
233 ATAConfiguration_ID_Device1Timing
+ ATAConfiguration_PCIOffset
,
234 ATAConfiguration_ID_Device1Timing_Size
,
235 &Device1TimingRegister
);
236 if (result
== FALSE
) {
241 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable
;
246 ATATimingRegister
&= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable
|
247 ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable
|
248 ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
|
249 ATAConfiguration_PrimaryTiming_Device0DMATimingEnable
|
250 ATAConfiguration_PrimaryTiming_Device0RecoveryMode
|
251 ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode
);
253 if (PIOTimingMode
> PIO0
)
254 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable
;
256 if (PIOTimingMode
>= PIO3
)
257 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable
;
259 if (PIOTimingMode
>= PIO2
&& PrefetchPostingEnable
== TRUE
)
260 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
;
262 if (DMAEnable
== TRUE
&& PIOTimingMode
>= PIO2
)
263 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable
;
265 if (PIOTimingMode
<= PIO2
)
266 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0
;
267 else if (PIOTimingMode
== PIO3
)
268 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1
;
269 else if (PIOTimingMode
== PIO4
)
270 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3
;
272 if (PIOTimingMode
<= PIO1
)
273 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0
;
274 else if (PIOTimingMode
== PIO2
)
275 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1
;
276 else if (PIOTimingMode
<= PIO4
)
277 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2
;
280 ATATimingRegister
&= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable
|
281 ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable
|
282 ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable
|
283 ATAConfiguration_PrimaryTiming_Device1DMATimingEnable
);
285 if (PIOTimingMode
> PIO0
)
286 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable
;
288 if (PIOTimingMode
>= PIO3
)
289 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable
;
291 if (PIOTimingMode
>= PIO2
&& PrefetchPostingEnable
== TRUE
)
292 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable
;
294 if (DMAEnable
== TRUE
&& PIOTimingMode
>= PIO2
)
295 ATATimingRegister
|= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable
;
297 Device1TimingRegister
&= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode
|
298 ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode
);
300 if (PIOTimingMode
<= PIO2
)
301 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0
;
302 else if (PIOTimingMode
== PIO3
)
303 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1
;
304 else if (PIOTimingMode
== PIO4
)
305 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3
;
307 if (PIOTimingMode
<= PIO1
)
308 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0
;
309 else if (PIOTimingMode
== PIO2
)
310 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1
;
311 else if (PIOTimingMode
<= PIO4
)
312 Device1TimingRegister
|= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2
;
320 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
321 ATAConfiguration_ID_SecondaryTiming
+ ATAConfiguration_PCIOffset
,
322 ATAConfiguration_ID_SecondaryTiming_Size
,
324 if (result
== FALSE
) {
329 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
330 ATAConfiguration_ID_Device1Timing
+ ATAConfiguration_PCIOffset
,
331 ATAConfiguration_ID_Device1Timing_Size
,
332 &Device1TimingRegister
);
333 if (result
== FALSE
) {
343 static uint
ATAHostAdapter_SetPrimaryUDMA(struct pci_dev
*pdev
, uint DeviceID
,
344 uint UDMAEnable
, uint UDMATimingMode
)
348 uint UDMAControlRegister
;
349 uint UDMATimingRegister
;
350 ulong IDEIOConfigurationRegister
;
353 UDMAControlRegister
= 0;
354 UDMATimingRegister
= 0;
355 IDEIOConfigurationRegister
= 0;
357 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
358 ATAConfiguration_ID_UDMAControl
+ ATAConfiguration_PCIOffset
,
359 ATAConfiguration_ID_UDMAControl_Size
,
360 &UDMAControlRegister
);
361 if (result
== FALSE
) {
366 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
367 ATAConfiguration_ID_UDMATiming
+ ATAConfiguration_PCIOffset
,
368 ATAConfiguration_ID_UDMATiming_Size
,
369 &UDMATimingRegister
);
370 if (result
== FALSE
) {
375 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
376 ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
,
377 ATAConfiguration_ID_IDEIOConfiguration_Size
,
378 &IDEIOConfigurationRegister
);
379 if (result
== FALSE
) {
384 /*Rom Code will determine the device cable type and ATA 100.*/
385 /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/
386 /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/
390 UDMAControlRegister
&= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable
);
391 if (UDMAEnable
== TRUE
)
392 UDMAControlRegister
|= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable
;
394 IDEIOConfigurationRegister
&= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable
|
395 ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable
);
397 if (UDMATimingMode
>= UDMA5
)
398 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable
;
399 else if (UDMATimingMode
>= UDMA3
)
400 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable
;
402 /* if 80 cable report */
403 UDMATimingRegister
&= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime
);
405 if (UDMATimingMode
== UDMA0
) {
406 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0
;
407 } else if (UDMATimingMode
== UDMA1
||
408 UDMATimingMode
== UDMA3
||
409 UDMATimingMode
== UDMA5
) {
410 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1
;
411 } else if (UDMATimingMode
== UDMA2
||
412 UDMATimingMode
== UDMA4
) {
413 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2
;
417 UDMAControlRegister
&= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable
);
418 if (UDMAEnable
== TRUE
)
419 UDMAControlRegister
|= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable
;
421 IDEIOConfigurationRegister
&= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable
|
422 ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable
);
424 if (UDMATimingMode
>= UDMA5
)
425 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable
;
426 else if (UDMATimingMode
>= UDMA3
)
427 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable
;
429 /* if 80 cable report */
430 UDMATimingRegister
&= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime
);
432 if (UDMATimingMode
== UDMA0
) {
433 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0
;
434 } else if (UDMATimingMode
== UDMA1
||
435 UDMATimingMode
== UDMA3
||
436 UDMATimingMode
== UDMA5
) {
437 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1
;
438 } else if (UDMATimingMode
== UDMA2
||
439 UDMATimingMode
== UDMA4
) {
440 UDMATimingRegister
|= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2
;
449 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
450 ATAConfiguration_ID_UDMAControl
+ ATAConfiguration_PCIOffset
,
451 ATAConfiguration_ID_UDMAControl_Size
,
452 &UDMAControlRegister
);
453 if (result
== FALSE
) {
458 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
459 ATAConfiguration_ID_UDMATiming
+ ATAConfiguration_PCIOffset
,
460 ATAConfiguration_ID_UDMATiming_Size
,
461 &UDMATimingRegister
);
462 if (result
== FALSE
) {
467 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
468 ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
,
469 ATAConfiguration_ID_IDEIOConfiguration_Size
,
470 &IDEIOConfigurationRegister
);
471 if (result
== FALSE
) {
481 static uint
ATAHostAdapter_SetSecondaryUDMA(struct pci_dev
*pdev
, uint DeviceID
,
482 uint UDMAEnable
, uint UDMATimingMode
)
486 uint UDMAControlRegister
;
487 uint UDMATimingRegister
;
488 ulong IDEIOConfigurationRegister
;
492 UDMAControlRegister
= 0;
493 UDMATimingRegister
= 0;
494 IDEIOConfigurationRegister
= 0;
496 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
497 ATAConfiguration_ID_UDMAControl
+ ATAConfiguration_PCIOffset
,
498 ATAConfiguration_ID_UDMAControl_Size
,
499 &UDMAControlRegister
);
500 if (result
== FALSE
) {
505 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
506 ATAConfiguration_ID_UDMATiming
+ ATAConfiguration_PCIOffset
,
507 ATAConfiguration_ID_UDMATiming_Size
,
508 &UDMATimingRegister
);
509 if (result
== FALSE
) {
514 result
= PCIDeviceIO_ReadPCIConfiguration(pdev
,
515 ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
,
516 ATAConfiguration_ID_IDEIOConfiguration_Size
,
517 &IDEIOConfigurationRegister
);
518 if (result
== FALSE
) {
523 /* Rom Code will determine the device cable type and ATA 100. */
524 /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */
525 /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */
529 UDMAControlRegister
&= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable
);
530 if (UDMAEnable
== TRUE
)
531 UDMAControlRegister
|= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable
;
533 IDEIOConfigurationRegister
&= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable
|
534 ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable
);
536 if (UDMATimingMode
>= UDMA5
)
537 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable
;
538 else if (UDMATimingMode
>= UDMA3
)
539 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable
;
541 /* if 80 cable report */
542 UDMATimingRegister
&= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime
);
544 if (UDMATimingMode
== UDMA0
) {
545 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0
;
546 } else if (UDMATimingMode
== UDMA1
||
547 UDMATimingMode
== UDMA3
||
548 UDMATimingMode
== UDMA5
) {
549 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1
;
550 } else if (UDMATimingMode
== UDMA2
||
551 UDMATimingMode
== UDMA4
) {
552 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2
;
556 UDMAControlRegister
&= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable
);
557 if (UDMAEnable
== TRUE
)
558 UDMAControlRegister
|= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable
;
560 IDEIOConfigurationRegister
&= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable
|
561 ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable
);
563 if (UDMATimingMode
>= UDMA5
)
564 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable
;
565 else if (UDMATimingMode
>= UDMA3
)
566 IDEIOConfigurationRegister
|= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable
;
568 /* if 80 cable report */
569 UDMATimingRegister
&= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime
);
571 if (UDMATimingMode
== UDMA0
) {
572 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0
;
573 } else if (UDMATimingMode
== UDMA1
||
574 UDMATimingMode
== UDMA3
||
575 UDMATimingMode
== UDMA5
) {
576 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1
;
577 } else if (UDMATimingMode
== UDMA2
||
578 UDMATimingMode
== UDMA4
) {
579 UDMATimingRegister
|= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2
;
588 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
589 ATAConfiguration_ID_UDMAControl
+ ATAConfiguration_PCIOffset
,
590 ATAConfiguration_ID_UDMAControl_Size
,
591 &UDMAControlRegister
);
592 if (result
== FALSE
) {
597 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
598 ATAConfiguration_ID_UDMATiming
+ ATAConfiguration_PCIOffset
,
599 ATAConfiguration_ID_UDMATiming_Size
,
600 &UDMATimingRegister
);
601 if (result
== FALSE
) {
606 result
= PCIDeviceIO_WritePCIConfiguration(pdev
,
607 ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
,
608 ATAConfiguration_ID_IDEIOConfiguration_Size
,
609 &IDEIOConfigurationRegister
);
610 if (result
== FALSE
) {
620 static int rdc_pata_port_start(struct ata_port
*ap
)
624 Channel
= ap
->port_no
;
625 dev_dbg(ap
->dev
, "%s: Channel: %u\n", __func__
, Channel
);
626 if (ap
->ioaddr
.bmdma_addr
) {
627 return ata_port_start(ap
);
629 dev_dbg(ap
->dev
, "%s: return 0!!!\n", __func__
);
634 static void rdc_pata_port_stop(struct ata_port
*ap
)
638 Channel
= ap
->port_no
;
640 dev_dbg(ap
->dev
, "%s Channel: %u\n", __func__
, Channel
);
643 static int rdc_pata_prereset(struct ata_link
*link
, unsigned long deadline
)
645 struct pci_dev
*pdev
;
649 dev_dbg(link
->ap
->dev
, "%s\n", __func__
);
652 pdev
= to_pci_dev(ap
->host
->dev
);
654 Channel
= ap
->port_no
;
656 /* test ATA Decode Enable Bits, should be enable. */
657 if (!pci_test_config_bits(pdev
, &ATA_Decode_Enable_Bits
[Channel
])) {
658 dev_dbg(link
->ap
->dev
, "%s: Channel: %u, Decode Disable\n",
662 dev_dbg(link
->ap
->dev
, "%s: Channel: %u, Decode Enable\n",
664 return ata_std_prereset(link
, deadline
);
668 static int rdc_pata_cable_detect(struct ata_port
*ap
)
670 struct pci_dev
*pdev
;
675 dev_dbg(ap
->dev
, "%s\n", __func__
);
677 pdev
= to_pci_dev(ap
->host
->dev
);
679 Channel
= ap
->port_no
;
682 Mask
= ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report
;
684 Mask
= ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report
;
686 /* check BIOS cable detect results */
687 pci_read_config_dword(pdev
, ATAConfiguration_ID_IDEIOConfiguration
+ ATAConfiguration_PCIOffset
, &u32Value
);
689 if ((u32Value
& Mask
) == 0) {
690 dev_dbg(ap
->dev
, "%s: Channel: %u, PATA40 \n",
692 return ATA_CBL_PATA40
;
694 dev_dbg(ap
->dev
, "%s: Channel: %u, PATA80 \n",
696 return ATA_CBL_PATA80
;
700 static void rdc_pata_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
702 struct pci_dev
*pdev
;
706 uint PrefetchPostingEnable
;
708 dev_dbg(ap
->dev
, "%s\n", __func__
);
710 pdev
= to_pci_dev(ap
->host
->dev
);
712 Channel
= ap
->port_no
;
713 DeviceID
= adev
->devno
;
715 * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
716 * XFER_PIO_2, XFER_PIO_3...
718 PIOTimingMode
= adev
->pio_mode
- XFER_PIO_0
;
720 if (adev
->class == ATA_DEV_ATA
) {
721 PrefetchPostingEnable
= TRUE
;
723 /* ATAPI, CD DVD Rom */
724 PrefetchPostingEnable
= FALSE
;
727 /* PIO configuration clears DTE unconditionally. It will be
728 * programmed in set_dmamode which is guaranteed to be called
729 * after set_piomode if any DMA mode is available.
732 /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
736 ATAHostAdapter_SetPrimaryPIO(
741 PrefetchPostingEnable
744 ATAHostAdapter_SetPrimaryUDMA(
751 ATAHostAdapter_SetSecondaryPIO(
756 PrefetchPostingEnable
759 ATAHostAdapter_SetSecondaryUDMA(
766 dev_dbg(ap
->dev
, "%s: Channel: %u, DeviceID: %u, PIO: %d\n",
767 __func__
, Channel
, DeviceID
, PIOTimingMode
);
770 static void rdc_pata_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
772 struct pci_dev
*pdev
;
776 uint PrefetchPostingEnable
;
780 dev_dbg(ap
->dev
, "%s\n", __func__
);
782 pdev
= to_pci_dev(ap
->host
->dev
);
784 Channel
= ap
->port_no
;
785 DeviceID
= adev
->devno
;
786 PIOTimingMode
= adev
->pio_mode
- XFER_PIO_0
; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
787 DMATimingMode
= adev
->dma_mode
; /* UDMA or MDMA */
789 if (adev
->class == ATA_DEV_ATA
) {
790 PrefetchPostingEnable
= TRUE
;
792 /* ATAPI, CD DVD Rom */
793 PrefetchPostingEnable
= FALSE
;
796 if (ap
->udma_mask
== 0) {
797 /* ata_port dont support udma. depend on hardware spec. */
804 if (DMATimingMode
>= XFER_UDMA_0
) {
806 ATAHostAdapter_SetPrimaryPIO(pdev
,
810 PrefetchPostingEnable
);
812 ATAHostAdapter_SetPrimaryUDMA(pdev
,
815 DMATimingMode
- XFER_UDMA_0
);
817 "%s: Channel: %u, DeviceID: %u, UDMA: %u\n",
818 __func__
, Channel
, DeviceID
,
819 (uint
)(DMATimingMode
- XFER_UDMA_0
));
822 ATAHostAdapter_SetPrimaryPIO(pdev
,
824 (DMATimingMode
- XFER_MW_DMA_0
) + PIO2
, /* MDMA0 = PIO2 */
826 PrefetchPostingEnable
);
828 ATAHostAdapter_SetPrimaryUDMA(pdev
,
833 "%s: Channel: %u, DeviceID: %u, MDMA: %u\n",
834 __func__
, Channel
, DeviceID
,
835 (uint
)(DMATimingMode
- XFER_MW_DMA_0
));
838 if (DMATimingMode
>= XFER_UDMA_0
) {
840 ATAHostAdapter_SetSecondaryPIO(pdev
,
844 PrefetchPostingEnable
);
846 ATAHostAdapter_SetSecondaryUDMA(pdev
,
849 DMATimingMode
- XFER_UDMA_0
);
851 "%s: Channel: %u, DeviceID: %u, UDMA: %u\n",
852 __func__
, Channel
, DeviceID
,
853 (uint
)(DMATimingMode
- XFER_UDMA_0
));
856 ATAHostAdapter_SetSecondaryPIO(pdev
,
858 (DMATimingMode
- XFER_MW_DMA_0
) + PIO2
, /* MDMA0 = PIO2 */
860 PrefetchPostingEnable
);
862 ATAHostAdapter_SetSecondaryUDMA(pdev
,
867 "%s: Channel: %u, DeviceID: %u, MDMA: %u \n",
868 __func__
, Channel
, DeviceID
,
869 (uint
)(DMATimingMode
- XFER_MW_DMA_0
));
874 static struct scsi_host_template rdc_pata_sht
= {
875 ATA_BMDMA_SHT(KBUILD_MODNAME
),
878 static struct ata_port_operations rdc_pata_ops
= {
879 .inherits
= &ata_bmdma_port_ops
,
881 .port_start
= rdc_pata_port_start
,
882 .port_stop
= rdc_pata_port_stop
,
883 .prereset
= rdc_pata_prereset
,
884 .cable_detect
= rdc_pata_cable_detect
,
885 .set_piomode
= rdc_pata_set_piomode
,
886 .set_dmamode
= rdc_pata_set_dmamode
,
889 static struct ata_port_info rdc_pata_port_info
[] = {
891 .flags
= ATA_FLAG_SLAVE_POSS
,
892 .pio_mask
= 0x1f, /* pio0-4 */
893 .mwdma_mask
= 0x07, /* mwdma0-2 */
894 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
895 .port_ops
= &rdc_pata_ops
,
899 .flags
= ATA_FLAG_SLAVE_POSS
,
900 .pio_mask
= 0x1f, /* pio0-4 */
901 .mwdma_mask
= 0x07, /* mwdma0-2 */
902 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
903 .port_ops
= &rdc_pata_ops
,
907 static int __devinit
rdc_init_one(struct pci_dev
*pdev
,
908 const struct pci_device_id
*ent
)
910 struct ata_port_info port_info
[2];
911 const struct ata_port_info
*ppinfo
[] = { &port_info
[0], &port_info
[1] };
915 dev_dbg(&pdev
->dev
, "%s\n", __func__
);
917 port_info
[0] = rdc_pata_port_info
[ent
->driver_data
];
918 port_info
[1] = rdc_pata_port_info
[ent
->driver_data
];
920 rc
= pci_enable_device(pdev
);
922 dev_dbg(&pdev
->dev
, "%s pci_enable_device failed\n", __func__
);
927 return ata_pci_sff_init_one(pdev
, ppinfo
, &rdc_pata_sht
, NULL
);
930 static struct pci_driver rdc_pata_driver
= {
931 .name
= KBUILD_MODNAME
,
932 .id_table
= rdc_pata_id_table
,
933 .probe
= rdc_init_one
,
934 .remove
= ata_pci_remove_one
,
936 .suspend
= ata_pci_device_suspend
,
937 .resume
= ata_pci_device_resume
,
941 static int __init
pata_rdc_init(void)
943 return pci_register_driver(&rdc_pata_driver
);
946 static void __exit
pata_rdc_exit(void)
948 pci_unregister_driver(&rdc_pata_driver
);
951 module_init(pata_rdc_init
);
952 module_exit(pata_rdc_exit
);
954 MODULE_LICENSE("GPL");
955 MODULE_DESCRIPTION("RDC PCI IDE Driver");