arch/arm/mach-iop32x/iq31244.c

   1 /*
   2  * arch/arm/mach-iop32x/iq31244.c
   3  *
   4  * Board support code for the Intel EP80219 and IQ31244 platforms.
   5  *
   6  * Author: Rory Bolt <rorybolt@pacbell.net>
   7  * Copyright (C) 2002 Rory Bolt
   8  * Copyright 2003 (c) MontaVista, Software, Inc.
   9  * Copyright (C) 2004 Intel Corp.
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License as published by the
  13  * Free Software Foundation; either version 2 of the License, or (at your
  14  * option) any later version.
  15  */
  16
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/pm.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/mtd/physmap.h>
  28 #include <linux/platform_device.h>
  29 #include <asm/hardware.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/pci.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/page.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/arch/time.h>
  40
  41 /*
  42  * The EP80219 and IQ31244 use the same machine ID.  To find out
  43  * which of the two we're running on, we look at the processor ID.
  44  */
  45 static int is_80219(void)
  46 {
  47         extern int processor_id;
  48         return !!((processor_id & 0xffffffe0) == 0x69052e20);
  49 }
  50
  51
  52 /*
  53  * EP80219/IQ31244 timer tick configuration.
  54  */
  55 static void __init iq31244_timer_init(void)
  56 {
  57         if (is_80219()) {
  58                 /* 33.333 MHz crystal.  */
  59                 iop_init_time(200000000);
  60         } else {
  61                 /* 33.000 MHz crystal.  */
  62                 iop_init_time(198000000);
  63         }
  64 }
  65
  66 static struct sys_timer iq31244_timer = {
  67         .init           = iq31244_timer_init,
  68         .offset         = iop_gettimeoffset,
  69 };
  70
  71
  72 /*
  73  * IQ31244 I/O.
  74  */
  75 static struct map_desc iq31244_io_desc[] __initdata = {
  76         {       /* on-board devices */
  77                 .virtual        = IQ31244_UART,
  78                 .pfn            = __phys_to_pfn(IQ31244_UART),
  79                 .length         = 0x00100000,
  80                 .type           = MT_DEVICE,
  81         },
  82 };
  83
  84 void __init iq31244_map_io(void)
  85 {
  86         iop3xx_map_io();
  87         iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
  88 }
  89
  90
  91 /*
  92  * EP80219/IQ31244 PCI.
  93  */
  94 static inline int __init
  95 ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  96 {
  97         int irq;
  98
  99         if (slot == 0) {
 100                 /* CFlash */
 101                 irq = IRQ_IOP32X_XINT1;
 102         } else if (slot == 1) {
 103                 /* 82551 Pro 100 */
 104                 irq = IRQ_IOP32X_XINT0;
 105         } else if (slot == 2) {
 106                 /* PCI-X Slot */
 107                 irq = IRQ_IOP32X_XINT3;
 108         } else if (slot == 3) {
 109                 /* SATA */
 110                 irq = IRQ_IOP32X_XINT2;
 111         } else {
 112                 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
 113                         "device PCI:%d:%d:%d\n", dev->bus->number,
 114                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
 115                 irq = -1;
 116         }
 117
 118         return irq;
 119 }
 120
 121 static struct hw_pci ep80219_pci __initdata = {
 122         .swizzle        = pci_std_swizzle,
 123         .nr_controllers = 1,
 124         .setup          = iop3xx_pci_setup,
 125         .preinit        = iop3xx_pci_preinit,
 126         .scan           = iop3xx_pci_scan_bus,
 127         .map_irq        = ep80219_pci_map_irq,
 128 };
 129
 130 static inline int __init
 131 iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 132 {
 133         int irq;
 134
 135         if (slot == 0) {
 136                 /* CFlash */
 137                 irq = IRQ_IOP32X_XINT1;
 138         } else if (slot == 1) {
 139                 /* SATA */
 140                 irq = IRQ_IOP32X_XINT2;
 141         } else if (slot == 2) {
 142                 /* PCI-X Slot */
 143                 irq = IRQ_IOP32X_XINT3;
 144         } else if (slot == 3) {
 145                 /* 82546 GigE */
 146                 irq = IRQ_IOP32X_XINT0;
 147         } else {
 148                 printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
 149                         "device PCI:%d:%d:%d\n", dev->bus->number,
 150                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
 151                 irq = -1;
 152         }
 153
 154         return irq;
 155 }
 156
 157 static struct hw_pci iq31244_pci __initdata = {
 158         .swizzle        = pci_std_swizzle,
 159         .nr_controllers = 1,
 160         .setup          = iop3xx_pci_setup,
 161         .preinit        = iop3xx_pci_preinit,
 162         .scan           = iop3xx_pci_scan_bus,
 163         .map_irq        = iq31244_pci_map_irq,
 164 };
 165
 166 static int __init iq31244_pci_init(void)
 167 {
 168         if (machine_is_iq31244()) {
 169                 if (is_80219()) {
 170                         pci_common_init(&ep80219_pci);
 171                 } else {
 172                         pci_common_init(&iq31244_pci);
 173                 }
 174         }
 175
 176         return 0;
 177 }
 178
 179 subsys_initcall(iq31244_pci_init);
 180
 181
 182 /*
 183  * IQ31244 machine initialisation.
 184  */
 185 static struct physmap_flash_data iq31244_flash_data = {
 186         .width          = 2,
 187 };
 188
 189 static struct resource iq31244_flash_resource = {
 190         .start          = 0xf0000000,
 191         .end            = 0xf07fffff,
 192         .flags          = IORESOURCE_MEM,
 193 };
 194
 195 static struct platform_device iq31244_flash_device = {
 196         .name           = "physmap-flash",
 197         .id             = 0,
 198         .dev            = {
 199                 .platform_data  = &iq31244_flash_data,
 200         },
 201         .num_resources  = 1,
 202         .resource       = &iq31244_flash_resource,
 203 };
 204
 205 static struct plat_serial8250_port iq31244_serial_port[] = {
 206         {
 207                 .mapbase        = IQ31244_UART,
 208                 .membase        = (char *)IQ31244_UART,
 209                 .irq            = IRQ_IOP32X_XINT1,
 210                 .flags          = UPF_SKIP_TEST,
 211                 .iotype         = UPIO_MEM,
 212                 .regshift       = 0,
 213                 .uartclk        = 1843200,
 214         },
 215         { },
 216 };
 217
 218 static struct resource iq31244_uart_resource = {
 219         .start          = IQ31244_UART,
 220         .end            = IQ31244_UART + 7,
 221         .flags          = IORESOURCE_MEM,
 222 };
 223
 224 static struct platform_device iq31244_serial_device = {
 225         .name           = "serial8250",
 226         .id             = PLAT8250_DEV_PLATFORM,
 227         .dev            = {
 228                 .platform_data          = iq31244_serial_port,
 229         },
 230         .num_resources  = 1,
 231         .resource       = &iq31244_uart_resource,
 232 };
 233
 234 /*
 235  * This function will send a SHUTDOWN_COMPLETE message to the PIC
 236  * controller over I2C.  We are not using the i2c subsystem since
 237  * we are going to power off and it may be removed
 238  */
 239 void ep80219_power_off(void)
 240 {
 241         /*
 242          * Send the Address byte w/ the start condition
 243          */
 244         *IOP3XX_IDBR1 = 0x60;
 245         *IOP3XX_ICR1 = 0xE9;
 246         mdelay(1);
 247
 248         /*
 249          * Send the START_MSG byte w/ no start or stop condition
 250          */
 251         *IOP3XX_IDBR1 = 0x0F;
 252         *IOP3XX_ICR1 = 0xE8;
 253         mdelay(1);
 254
 255         /*
 256          * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
 257          * stop condition
 258          */
 259         *IOP3XX_IDBR1 = 0x03;
 260         *IOP3XX_ICR1 = 0xE8;
 261         mdelay(1);
 262
 263         /*
 264          * Send an ignored byte w/ stop condition
 265          */
 266         *IOP3XX_IDBR1 = 0x00;
 267         *IOP3XX_ICR1 = 0xEA;
 268
 269         while (1)
 270                 ;
 271 }
 272
 273 static void __init iq31244_init_machine(void)
 274 {
 275         platform_device_register(&iop3xx_i2c0_device);
 276         platform_device_register(&iop3xx_i2c1_device);
 277         platform_device_register(&iq31244_flash_device);
 278         platform_device_register(&iq31244_serial_device);
 279
 280         if (is_80219())
 281                 pm_power_off = ep80219_power_off;
 282 }
 283
 284 MACHINE_START(IQ31244, "Intel IQ31244")
 285         /* Maintainer: Intel Corp. */
 286         .phys_io        = IQ31244_UART,
 287         .io_pg_offst    = ((IQ31244_UART) >> 18) & 0xfffc,
 288         .boot_params    = 0xa0000100,
 289         .map_io         = iq31244_map_io,
 290         .init_irq       = iop32x_init_irq,
 291         .timer          = &iq31244_timer,
 292         .init_machine   = iq31244_init_machine,
 293 MACHINE_END