2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/platform_device.h>
16 #include <asm/mach/map.h>
18 #include <mach/dm644x.h>
19 #include <mach/clock.h>
20 #include <mach/cputype.h>
21 #include <mach/edma.h>
22 #include <mach/irqs.h>
25 #include <mach/common.h>
31 * Device specific clocks
33 #define DM644X_REF_FREQ 27000000
35 static struct pll_data pll1_data
= {
37 .phys_base
= DAVINCI_PLL1_BASE
,
40 static struct pll_data pll2_data
= {
42 .phys_base
= DAVINCI_PLL2_BASE
,
45 static struct clk ref_clk
= {
47 .rate
= DM644X_REF_FREQ
,
50 static struct clk pll1_clk
= {
53 .pll_data
= &pll1_data
,
57 static struct clk pll1_sysclk1
= {
58 .name
= "pll1_sysclk1",
64 static struct clk pll1_sysclk2
= {
65 .name
= "pll1_sysclk2",
71 static struct clk pll1_sysclk3
= {
72 .name
= "pll1_sysclk3",
78 static struct clk pll1_sysclk5
= {
79 .name
= "pll1_sysclk5",
85 static struct clk pll1_aux_clk
= {
86 .name
= "pll1_aux_clk",
88 .flags
= CLK_PLL
| PRE_PLL
,
91 static struct clk pll1_sysclkbp
= {
92 .name
= "pll1_sysclkbp",
94 .flags
= CLK_PLL
| PRE_PLL
,
98 static struct clk pll2_clk
= {
101 .pll_data
= &pll2_data
,
105 static struct clk pll2_sysclk1
= {
106 .name
= "pll2_sysclk1",
112 static struct clk pll2_sysclk2
= {
113 .name
= "pll2_sysclk2",
119 static struct clk pll2_sysclkbp
= {
120 .name
= "pll2_sysclkbp",
122 .flags
= CLK_PLL
| PRE_PLL
,
126 static struct clk dsp_clk
= {
128 .parent
= &pll1_sysclk1
,
129 .lpsc
= DAVINCI_LPSC_GEM
,
131 .usecount
= 1, /* REVISIT how to disable? */
134 static struct clk arm_clk
= {
136 .parent
= &pll1_sysclk2
,
137 .lpsc
= DAVINCI_LPSC_ARM
,
138 .flags
= ALWAYS_ENABLED
,
141 static struct clk vicp_clk
= {
143 .parent
= &pll1_sysclk2
,
144 .lpsc
= DAVINCI_LPSC_IMCOP
,
146 .usecount
= 1, /* REVISIT how to disable? */
149 static struct clk vpss_master_clk
= {
150 .name
= "vpss_master",
151 .parent
= &pll1_sysclk3
,
152 .lpsc
= DAVINCI_LPSC_VPSSMSTR
,
156 static struct clk vpss_slave_clk
= {
157 .name
= "vpss_slave",
158 .parent
= &pll1_sysclk3
,
159 .lpsc
= DAVINCI_LPSC_VPSSSLV
,
162 static struct clk uart0_clk
= {
164 .parent
= &pll1_aux_clk
,
165 .lpsc
= DAVINCI_LPSC_UART0
,
168 static struct clk uart1_clk
= {
170 .parent
= &pll1_aux_clk
,
171 .lpsc
= DAVINCI_LPSC_UART1
,
174 static struct clk uart2_clk
= {
176 .parent
= &pll1_aux_clk
,
177 .lpsc
= DAVINCI_LPSC_UART2
,
180 static struct clk emac_clk
= {
182 .parent
= &pll1_sysclk5
,
183 .lpsc
= DAVINCI_LPSC_EMAC_WRAPPER
,
186 static struct clk i2c_clk
= {
188 .parent
= &pll1_aux_clk
,
189 .lpsc
= DAVINCI_LPSC_I2C
,
192 static struct clk ide_clk
= {
194 .parent
= &pll1_sysclk5
,
195 .lpsc
= DAVINCI_LPSC_ATA
,
198 static struct clk asp_clk
= {
200 .parent
= &pll1_sysclk5
,
201 .lpsc
= DAVINCI_LPSC_McBSP
,
204 static struct clk mmcsd_clk
= {
206 .parent
= &pll1_sysclk5
,
207 .lpsc
= DAVINCI_LPSC_MMC_SD
,
210 static struct clk spi_clk
= {
212 .parent
= &pll1_sysclk5
,
213 .lpsc
= DAVINCI_LPSC_SPI
,
216 static struct clk gpio_clk
= {
218 .parent
= &pll1_sysclk5
,
219 .lpsc
= DAVINCI_LPSC_GPIO
,
222 static struct clk usb_clk
= {
224 .parent
= &pll1_sysclk5
,
225 .lpsc
= DAVINCI_LPSC_USB
,
228 static struct clk vlynq_clk
= {
230 .parent
= &pll1_sysclk5
,
231 .lpsc
= DAVINCI_LPSC_VLYNQ
,
234 static struct clk aemif_clk
= {
236 .parent
= &pll1_sysclk5
,
237 .lpsc
= DAVINCI_LPSC_AEMIF
,
240 static struct clk pwm0_clk
= {
242 .parent
= &pll1_aux_clk
,
243 .lpsc
= DAVINCI_LPSC_PWM0
,
246 static struct clk pwm1_clk
= {
248 .parent
= &pll1_aux_clk
,
249 .lpsc
= DAVINCI_LPSC_PWM1
,
252 static struct clk pwm2_clk
= {
254 .parent
= &pll1_aux_clk
,
255 .lpsc
= DAVINCI_LPSC_PWM2
,
258 static struct clk timer0_clk
= {
260 .parent
= &pll1_aux_clk
,
261 .lpsc
= DAVINCI_LPSC_TIMER0
,
264 static struct clk timer1_clk
= {
266 .parent
= &pll1_aux_clk
,
267 .lpsc
= DAVINCI_LPSC_TIMER1
,
270 static struct clk timer2_clk
= {
272 .parent
= &pll1_aux_clk
,
273 .lpsc
= DAVINCI_LPSC_TIMER2
,
274 .usecount
= 1, /* REVISIT: why cant' this be disabled? */
277 struct davinci_clk dm644x_clks
[] = {
278 CLK(NULL
, "ref", &ref_clk
),
279 CLK(NULL
, "pll1", &pll1_clk
),
280 CLK(NULL
, "pll1_sysclk1", &pll1_sysclk1
),
281 CLK(NULL
, "pll1_sysclk2", &pll1_sysclk2
),
282 CLK(NULL
, "pll1_sysclk3", &pll1_sysclk3
),
283 CLK(NULL
, "pll1_sysclk5", &pll1_sysclk5
),
284 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
285 CLK(NULL
, "pll1_sysclkbp", &pll1_sysclkbp
),
286 CLK(NULL
, "pll2", &pll2_clk
),
287 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
288 CLK(NULL
, "pll2_sysclk2", &pll2_sysclk2
),
289 CLK(NULL
, "pll2_sysclkbp", &pll2_sysclkbp
),
290 CLK(NULL
, "dsp", &dsp_clk
),
291 CLK(NULL
, "arm", &arm_clk
),
292 CLK(NULL
, "vicp", &vicp_clk
),
293 CLK(NULL
, "vpss_master", &vpss_master_clk
),
294 CLK(NULL
, "vpss_slave", &vpss_slave_clk
),
295 CLK(NULL
, "arm", &arm_clk
),
296 CLK(NULL
, "uart0", &uart0_clk
),
297 CLK(NULL
, "uart1", &uart1_clk
),
298 CLK(NULL
, "uart2", &uart2_clk
),
299 CLK("davinci_emac.1", NULL
, &emac_clk
),
300 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
301 CLK("palm_bk3710", NULL
, &ide_clk
),
302 CLK("soc-audio.0", NULL
, &asp_clk
),
303 CLK("davinci_mmc.0", NULL
, &mmcsd_clk
),
304 CLK(NULL
, "spi", &spi_clk
),
305 CLK(NULL
, "gpio", &gpio_clk
),
306 CLK(NULL
, "usb", &usb_clk
),
307 CLK(NULL
, "vlynq", &vlynq_clk
),
308 CLK(NULL
, "aemif", &aemif_clk
),
309 CLK(NULL
, "pwm0", &pwm0_clk
),
310 CLK(NULL
, "pwm1", &pwm1_clk
),
311 CLK(NULL
, "pwm2", &pwm2_clk
),
312 CLK(NULL
, "timer0", &timer0_clk
),
313 CLK(NULL
, "timer1", &timer1_clk
),
314 CLK("watchdog", NULL
, &timer2_clk
),
315 CLK(NULL
, NULL
, NULL
),
318 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
320 static struct resource dm644x_emac_resources
[] = {
322 .start
= DM644X_EMAC_BASE
,
323 .end
= DM644X_EMAC_BASE
+ 0x47ff,
324 .flags
= IORESOURCE_MEM
,
327 .start
= IRQ_EMACINT
,
329 .flags
= IORESOURCE_IRQ
,
333 static struct platform_device dm644x_emac_device
= {
334 .name
= "davinci_emac",
336 .num_resources
= ARRAY_SIZE(dm644x_emac_resources
),
337 .resource
= dm644x_emac_resources
,
343 * Device specific mux setup
345 * soc description mux mode mode mux dbg
346 * reg offset mask mode
348 static const struct mux_config dm644x_pins
[] = {
349 #ifdef CONFIG_DAVINCI_MUX
350 MUX_CFG(DM644X
, HDIREN
, 0, 16, 1, 1, true)
351 MUX_CFG(DM644X
, ATAEN
, 0, 17, 1, 1, true)
352 MUX_CFG(DM644X
, ATAEN_DISABLE
, 0, 17, 1, 0, true)
354 MUX_CFG(DM644X
, HPIEN_DISABLE
, 0, 29, 1, 0, true)
356 MUX_CFG(DM644X
, AEAW
, 0, 0, 31, 31, true)
358 MUX_CFG(DM644X
, MSTK
, 1, 9, 1, 0, false)
360 MUX_CFG(DM644X
, I2C
, 1, 7, 1, 1, false)
362 MUX_CFG(DM644X
, MCBSP
, 1, 10, 1, 1, false)
364 MUX_CFG(DM644X
, UART1
, 1, 1, 1, 1, true)
365 MUX_CFG(DM644X
, UART2
, 1, 2, 1, 1, true)
367 MUX_CFG(DM644X
, PWM0
, 1, 4, 1, 1, false)
369 MUX_CFG(DM644X
, PWM1
, 1, 5, 1, 1, false)
371 MUX_CFG(DM644X
, PWM2
, 1, 6, 1, 1, false)
373 MUX_CFG(DM644X
, VLYNQEN
, 0, 15, 1, 1, false)
374 MUX_CFG(DM644X
, VLSCREN
, 0, 14, 1, 1, false)
375 MUX_CFG(DM644X
, VLYNQWD
, 0, 12, 3, 3, false)
377 MUX_CFG(DM644X
, EMACEN
, 0, 31, 1, 1, true)
379 MUX_CFG(DM644X
, GPIO3V
, 0, 31, 1, 0, true)
381 MUX_CFG(DM644X
, GPIO0
, 0, 24, 1, 0, true)
382 MUX_CFG(DM644X
, GPIO3
, 0, 25, 1, 0, false)
383 MUX_CFG(DM644X
, GPIO43_44
, 1, 7, 1, 0, false)
384 MUX_CFG(DM644X
, GPIO46_47
, 0, 22, 1, 0, true)
386 MUX_CFG(DM644X
, RGB666
, 0, 22, 1, 1, true)
388 MUX_CFG(DM644X
, LOEEN
, 0, 24, 1, 1, true)
389 MUX_CFG(DM644X
, LFLDEN
, 0, 25, 1, 1, false)
393 /*----------------------------------------------------------------------*/
395 static const s8 dma_chan_dm644x_no_event
[] = {
404 static struct edma_soc_info dm644x_edma_info
= {
409 .noevent
= dma_chan_dm644x_no_event
,
412 static struct resource edma_resources
[] = {
416 .end
= 0x01c00000 + SZ_64K
- 1,
417 .flags
= IORESOURCE_MEM
,
422 .end
= 0x01c10000 + SZ_1K
- 1,
423 .flags
= IORESOURCE_MEM
,
428 .end
= 0x01c10400 + SZ_1K
- 1,
429 .flags
= IORESOURCE_MEM
,
433 .flags
= IORESOURCE_IRQ
,
436 .start
= IRQ_CCERRINT
,
437 .flags
= IORESOURCE_IRQ
,
439 /* not using TC*_ERR */
442 static struct platform_device dm644x_edma_device
= {
445 .dev
.platform_data
= &dm644x_edma_info
,
446 .num_resources
= ARRAY_SIZE(edma_resources
),
447 .resource
= edma_resources
,
450 /*----------------------------------------------------------------------*/
451 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
453 void dm644x_init_emac(struct emac_platform_data
*pdata
)
455 pdata
->ctrl_reg_offset
= DM644X_EMAC_CNTRL_OFFSET
;
456 pdata
->ctrl_mod_reg_offset
= DM644X_EMAC_CNTRL_MOD_OFFSET
;
457 pdata
->ctrl_ram_offset
= DM644X_EMAC_CNTRL_RAM_OFFSET
;
458 pdata
->mdio_reg_offset
= DM644X_EMAC_MDIO_OFFSET
;
459 pdata
->ctrl_ram_size
= DM644X_EMAC_CNTRL_RAM_SIZE
;
460 pdata
->version
= EMAC_VERSION_1
;
461 dm644x_emac_device
.dev
.platform_data
= pdata
;
462 platform_device_register(&dm644x_emac_device
);
466 void dm644x_init_emac(struct emac_platform_data
*unused
) {}
470 static struct map_desc dm644x_io_desc
[] = {
473 .pfn
= __phys_to_pfn(IO_PHYS
),
479 /* Contents of JTAG ID register used to identify exact cpu type */
480 static struct davinci_id dm644x_ids
[] = {
484 .manufacturer
= 0x017,
485 .cpu_id
= DAVINCI_CPU_ID_DM6446
,
490 static void __iomem
*dm644x_psc_bases
[] = {
491 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE
),
494 static struct davinci_soc_info davinci_soc_info_dm644x
= {
495 .io_desc
= dm644x_io_desc
,
496 .io_desc_num
= ARRAY_SIZE(dm644x_io_desc
),
497 .jtag_id_base
= IO_ADDRESS(0x01c40028),
499 .ids_num
= ARRAY_SIZE(dm644x_ids
),
500 .cpu_clks
= dm644x_clks
,
501 .psc_bases
= dm644x_psc_bases
,
502 .psc_bases_num
= ARRAY_SIZE(dm644x_psc_bases
),
503 .pinmux_base
= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE
),
504 .pinmux_pins
= dm644x_pins
,
505 .pinmux_pins_num
= ARRAY_SIZE(dm644x_pins
),
508 void __init
dm644x_init(void)
510 davinci_common_init(&davinci_soc_info_dm644x
);
513 static int __init
dm644x_init_devices(void)
515 if (!cpu_is_davinci_dm644x())
518 platform_device_register(&dm644x_edma_device
);
521 postcore_initcall(dm644x_init_devices
);