2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
45 static void intel_update_watermarks(struct drm_device
*dev
);
46 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
47 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t
;
73 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
76 int, int, intel_clock_t
*);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
333 int target
, int refclk
, intel_clock_t
*best_clock
);
335 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
336 int target
, int refclk
, intel_clock_t
*best_clock
);
339 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
340 int target
, int refclk
, intel_clock_t
*best_clock
);
342 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
343 int target
, int refclk
, intel_clock_t
*best_clock
);
345 static const intel_limit_t intel_limits_i8xx_dvo
= {
346 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
347 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
348 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
349 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
350 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
351 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
352 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
353 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
354 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
355 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
356 .find_pll
= intel_find_best_PLL
,
359 static const intel_limit_t intel_limits_i8xx_lvds
= {
360 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
361 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
362 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
363 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
364 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
365 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
366 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
367 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
368 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
369 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
370 .find_pll
= intel_find_best_PLL
,
373 static const intel_limit_t intel_limits_i9xx_sdvo
= {
374 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
375 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
376 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
377 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
378 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
379 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
380 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
381 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
382 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
383 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
384 .find_pll
= intel_find_best_PLL
,
387 static const intel_limit_t intel_limits_i9xx_lvds
= {
388 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
389 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
390 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
391 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
392 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
393 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
394 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
395 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
399 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
400 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
401 .find_pll
= intel_find_best_PLL
,
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo
= {
406 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
407 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
408 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
409 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
410 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
411 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
412 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
413 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
414 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
415 .p2_slow
= G4X_P2_SDVO_SLOW
,
416 .p2_fast
= G4X_P2_SDVO_FAST
418 .find_pll
= intel_g4x_find_best_PLL
,
421 static const intel_limit_t intel_limits_g4x_hdmi
= {
422 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
423 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
424 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
425 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
426 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
427 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
428 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
429 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
430 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
431 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
432 .p2_fast
= G4X_P2_HDMI_DAC_FAST
434 .find_pll
= intel_g4x_find_best_PLL
,
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
438 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
439 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
440 .vco
= { .min
= G4X_VCO_MIN
,
441 .max
= G4X_VCO_MAX
},
442 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
443 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
444 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
445 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
446 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
447 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
448 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
449 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
450 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
451 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
452 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
453 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
454 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
455 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
456 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
458 .find_pll
= intel_g4x_find_best_PLL
,
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
462 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
463 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
464 .vco
= { .min
= G4X_VCO_MIN
,
465 .max
= G4X_VCO_MAX
},
466 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
467 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
468 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
469 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
470 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
471 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
472 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
473 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
474 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
475 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
476 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
477 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
478 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
479 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
480 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
482 .find_pll
= intel_g4x_find_best_PLL
,
485 static const intel_limit_t intel_limits_g4x_display_port
= {
486 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
487 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
488 .vco
= { .min
= G4X_VCO_MIN
,
490 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
491 .max
= G4X_N_DISPLAY_PORT_MAX
},
492 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
493 .max
= G4X_M_DISPLAY_PORT_MAX
},
494 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
495 .max
= G4X_M1_DISPLAY_PORT_MAX
},
496 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
497 .max
= G4X_M2_DISPLAY_PORT_MAX
},
498 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
499 .max
= G4X_P_DISPLAY_PORT_MAX
},
500 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
501 .max
= G4X_P1_DISPLAY_PORT_MAX
},
502 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
503 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
504 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
505 .find_pll
= intel_find_pll_g4x_dp
,
508 static const intel_limit_t intel_limits_pineview_sdvo
= {
509 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
510 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
511 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
512 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
513 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
514 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
515 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
516 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
517 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
518 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
519 .find_pll
= intel_find_best_PLL
,
522 static const intel_limit_t intel_limits_pineview_lvds
= {
523 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
524 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
525 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
526 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
527 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
528 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
529 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
530 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
531 /* Pineview only supports single-channel mode. */
532 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
533 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
534 .find_pll
= intel_find_best_PLL
,
537 static const intel_limit_t intel_limits_ironlake_dac
= {
538 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
539 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
540 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
541 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
542 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
543 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
544 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
545 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
546 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
547 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
548 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
549 .find_pll
= intel_g4x_find_best_PLL
,
552 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
553 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
554 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
555 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
556 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
557 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
558 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
559 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
560 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
561 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
562 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
563 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
564 .find_pll
= intel_g4x_find_best_PLL
,
567 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
568 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
569 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
570 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
571 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
572 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
573 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
574 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
575 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
576 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
577 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
578 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
579 .find_pll
= intel_g4x_find_best_PLL
,
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
583 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
584 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
585 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
586 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
587 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
588 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
589 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
590 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
591 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
592 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
593 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
594 .find_pll
= intel_g4x_find_best_PLL
,
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
598 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
599 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
600 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
601 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
602 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
603 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
604 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
605 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
606 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
607 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
608 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
609 .find_pll
= intel_g4x_find_best_PLL
,
612 static const intel_limit_t intel_limits_ironlake_display_port
= {
613 .dot
= { .min
= IRONLAKE_DOT_MIN
,
614 .max
= IRONLAKE_DOT_MAX
},
615 .vco
= { .min
= IRONLAKE_VCO_MIN
,
616 .max
= IRONLAKE_VCO_MAX
},
617 .n
= { .min
= IRONLAKE_DP_N_MIN
,
618 .max
= IRONLAKE_DP_N_MAX
},
619 .m
= { .min
= IRONLAKE_DP_M_MIN
,
620 .max
= IRONLAKE_DP_M_MAX
},
621 .m1
= { .min
= IRONLAKE_M1_MIN
,
622 .max
= IRONLAKE_M1_MAX
},
623 .m2
= { .min
= IRONLAKE_M2_MIN
,
624 .max
= IRONLAKE_M2_MAX
},
625 .p
= { .min
= IRONLAKE_DP_P_MIN
,
626 .max
= IRONLAKE_DP_P_MAX
},
627 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
628 .max
= IRONLAKE_DP_P1_MAX
},
629 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
630 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
631 .p2_fast
= IRONLAKE_DP_P2_FAST
},
632 .find_pll
= intel_find_pll_ironlake_dp
,
635 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
637 struct drm_device
*dev
= crtc
->dev
;
638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
639 const intel_limit_t
*limit
;
642 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
643 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
646 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
647 LVDS_CLKB_POWER_UP
) {
648 /* LVDS dual channel */
650 limit
= &intel_limits_ironlake_dual_lvds_100m
;
652 limit
= &intel_limits_ironlake_dual_lvds
;
655 limit
= &intel_limits_ironlake_single_lvds_100m
;
657 limit
= &intel_limits_ironlake_single_lvds
;
659 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
661 limit
= &intel_limits_ironlake_display_port
;
663 limit
= &intel_limits_ironlake_dac
;
668 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
670 struct drm_device
*dev
= crtc
->dev
;
671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
672 const intel_limit_t
*limit
;
674 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
675 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
677 /* LVDS with dual channel */
678 limit
= &intel_limits_g4x_dual_channel_lvds
;
680 /* LVDS with dual channel */
681 limit
= &intel_limits_g4x_single_channel_lvds
;
682 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
683 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
684 limit
= &intel_limits_g4x_hdmi
;
685 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
686 limit
= &intel_limits_g4x_sdvo
;
687 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
688 limit
= &intel_limits_g4x_display_port
;
689 } else /* The option is for other outputs */
690 limit
= &intel_limits_i9xx_sdvo
;
695 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
697 struct drm_device
*dev
= crtc
->dev
;
698 const intel_limit_t
*limit
;
700 if (HAS_PCH_SPLIT(dev
))
701 limit
= intel_ironlake_limit(crtc
);
702 else if (IS_G4X(dev
)) {
703 limit
= intel_g4x_limit(crtc
);
704 } else if (IS_I9XX(dev
) && !IS_PINEVIEW(dev
)) {
705 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
706 limit
= &intel_limits_i9xx_lvds
;
708 limit
= &intel_limits_i9xx_sdvo
;
709 } else if (IS_PINEVIEW(dev
)) {
710 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
711 limit
= &intel_limits_pineview_lvds
;
713 limit
= &intel_limits_pineview_sdvo
;
715 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
716 limit
= &intel_limits_i8xx_lvds
;
718 limit
= &intel_limits_i8xx_dvo
;
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
726 clock
->m
= clock
->m2
+ 2;
727 clock
->p
= clock
->p1
* clock
->p2
;
728 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
729 clock
->dot
= clock
->vco
/ clock
->p
;
732 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
734 if (IS_PINEVIEW(dev
)) {
735 pineview_clock(refclk
, clock
);
738 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
739 clock
->p
= clock
->p1
* clock
->p2
;
740 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
741 clock
->dot
= clock
->vco
/ clock
->p
;
745 * Returns whether any output on the specified pipe is of the specified type
747 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
749 struct drm_device
*dev
= crtc
->dev
;
750 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
751 struct intel_encoder
*encoder
;
753 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
754 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
760 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
762 * Returns whether the given set of divisors are valid for a given refclk with
763 * the given connectors.
766 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
768 const intel_limit_t
*limit
= intel_limit (crtc
);
769 struct drm_device
*dev
= crtc
->dev
;
771 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
772 INTELPllInvalid ("p1 out of range\n");
773 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
774 INTELPllInvalid ("p out of range\n");
775 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
776 INTELPllInvalid ("m2 out of range\n");
777 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
778 INTELPllInvalid ("m1 out of range\n");
779 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
780 INTELPllInvalid ("m1 <= m2\n");
781 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
782 INTELPllInvalid ("m out of range\n");
783 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
784 INTELPllInvalid ("n out of range\n");
785 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
786 INTELPllInvalid ("vco out of range\n");
787 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
788 * connector, etc., rather than just a single range.
790 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
791 INTELPllInvalid ("dot out of range\n");
797 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
798 int target
, int refclk
, intel_clock_t
*best_clock
)
801 struct drm_device
*dev
= crtc
->dev
;
802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
806 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
807 (I915_READ(LVDS
)) != 0) {
809 * For LVDS, if the panel is on, just rely on its current
810 * settings for dual-channel. We haven't figured out how to
811 * reliably set up different single/dual channel state, if we
814 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
816 clock
.p2
= limit
->p2
.p2_fast
;
818 clock
.p2
= limit
->p2
.p2_slow
;
820 if (target
< limit
->p2
.dot_limit
)
821 clock
.p2
= limit
->p2
.p2_slow
;
823 clock
.p2
= limit
->p2
.p2_fast
;
826 memset (best_clock
, 0, sizeof (*best_clock
));
828 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
830 for (clock
.m2
= limit
->m2
.min
;
831 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
832 /* m1 is always 0 in Pineview */
833 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
835 for (clock
.n
= limit
->n
.min
;
836 clock
.n
<= limit
->n
.max
; clock
.n
++) {
837 for (clock
.p1
= limit
->p1
.min
;
838 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
841 intel_clock(dev
, refclk
, &clock
);
843 if (!intel_PLL_is_valid(crtc
, &clock
))
846 this_err
= abs(clock
.dot
- target
);
847 if (this_err
< err
) {
856 return (err
!= target
);
860 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
861 int target
, int refclk
, intel_clock_t
*best_clock
)
863 struct drm_device
*dev
= crtc
->dev
;
864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
868 /* approximately equals target * 0.00585 */
869 int err_most
= (target
>> 8) + (target
>> 9);
872 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
875 if (HAS_PCH_SPLIT(dev
))
879 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
881 clock
.p2
= limit
->p2
.p2_fast
;
883 clock
.p2
= limit
->p2
.p2_slow
;
885 if (target
< limit
->p2
.dot_limit
)
886 clock
.p2
= limit
->p2
.p2_slow
;
888 clock
.p2
= limit
->p2
.p2_fast
;
891 memset(best_clock
, 0, sizeof(*best_clock
));
892 max_n
= limit
->n
.max
;
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
895 /* based on hardware requirement, prefere larger m1,m2 */
896 for (clock
.m1
= limit
->m1
.max
;
897 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
898 for (clock
.m2
= limit
->m2
.max
;
899 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
900 for (clock
.p1
= limit
->p1
.max
;
901 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
904 intel_clock(dev
, refclk
, &clock
);
905 if (!intel_PLL_is_valid(crtc
, &clock
))
907 this_err
= abs(clock
.dot
- target
) ;
908 if (this_err
< err_most
) {
922 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
923 int target
, int refclk
, intel_clock_t
*best_clock
)
925 struct drm_device
*dev
= crtc
->dev
;
928 /* return directly when it is eDP */
932 if (target
< 200000) {
945 intel_clock(dev
, refclk
, &clock
);
946 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
950 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
952 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
953 int target
, int refclk
, intel_clock_t
*best_clock
)
956 if (target
< 200000) {
969 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
970 clock
.p
= (clock
.p1
* clock
.p2
);
971 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
973 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
978 * intel_wait_for_vblank - wait for vblank on a given pipe
980 * @pipe: pipe to wait for
982 * Wait for vblank to occur on a given pipe. Needed for various bits of
985 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 int pipestat_reg
= (pipe
== 0 ? PIPEASTAT
: PIPEBSTAT
);
990 /* Clear existing vblank status. Note this will clear any other
991 * sticky status fields as well.
993 * This races with i915_driver_irq_handler() with the result
994 * that either function could miss a vblank event. Here it is not
995 * fatal, as we will either wait upon the next vblank interrupt or
996 * timeout. Generally speaking intel_wait_for_vblank() is only
997 * called during modeset at which time the GPU should be idle and
998 * should *not* be performing page flips and thus not waiting on
1000 * Currently, the result of us stealing a vblank from the irq
1001 * handler is that a single frame will be skipped during swapbuffers.
1003 I915_WRITE(pipestat_reg
,
1004 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
1006 /* Wait for vblank interrupt bit to set */
1007 if (wait_for(I915_READ(pipestat_reg
) &
1008 PIPE_VBLANK_INTERRUPT_STATUS
,
1010 DRM_DEBUG_KMS("vblank wait timed out\n");
1014 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1016 * @pipe: pipe to wait for
1018 * After disabling a pipe, we can't wait for vblank in the usual way,
1019 * spinning on the vblank interrupt status bit, since we won't actually
1020 * see an interrupt when the pipe is disabled.
1022 * So this function waits for the display line value to settle (it
1023 * usually ends up stopping at the start of the next frame).
1025 void intel_wait_for_vblank_off(struct drm_device
*dev
, int pipe
)
1027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1028 int pipedsl_reg
= (pipe
== 0 ? PIPEADSL
: PIPEBDSL
);
1029 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1032 /* Wait for the display line to settle */
1034 last_line
= I915_READ(pipedsl_reg
) & DSL_LINEMASK
;
1036 } while (((I915_READ(pipedsl_reg
) & DSL_LINEMASK
) != last_line
) &&
1037 time_after(timeout
, jiffies
));
1039 if (time_after(jiffies
, timeout
))
1040 DRM_DEBUG_KMS("vblank wait timed out\n");
1043 /* Parameters have changed, update FBC info */
1044 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1046 struct drm_device
*dev
= crtc
->dev
;
1047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1048 struct drm_framebuffer
*fb
= crtc
->fb
;
1049 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1050 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1051 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1053 u32 fbc_ctl
, fbc_ctl2
;
1055 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1057 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1058 dev_priv
->cfb_pitch
= fb
->pitch
;
1060 /* FBC_CTL wants 64B units */
1061 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1062 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1063 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1064 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1066 /* Clear old tags */
1067 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1068 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1071 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1072 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1073 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1074 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1075 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1078 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1080 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1081 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1082 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1083 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1084 fbc_ctl
|= dev_priv
->cfb_fence
;
1085 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1087 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1088 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1091 void i8xx_disable_fbc(struct drm_device
*dev
)
1093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1096 if (!I915_HAS_FBC(dev
))
1099 if (!(I915_READ(FBC_CONTROL
) & FBC_CTL_EN
))
1100 return; /* Already off, just return */
1102 /* Disable compression */
1103 fbc_ctl
= I915_READ(FBC_CONTROL
);
1104 fbc_ctl
&= ~FBC_CTL_EN
;
1105 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1107 /* Wait for compressing bit to clear */
1108 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
1109 DRM_DEBUG_KMS("FBC idle timed out\n");
1113 DRM_DEBUG_KMS("disabled FBC\n");
1116 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1120 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1123 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1125 struct drm_device
*dev
= crtc
->dev
;
1126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1127 struct drm_framebuffer
*fb
= crtc
->fb
;
1128 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1129 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1130 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1131 int plane
= (intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
:
1133 unsigned long stall_watermark
= 200;
1136 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1137 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1138 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1140 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1141 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1142 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1143 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1145 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1148 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1149 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1150 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1151 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1152 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1155 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1157 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1160 void g4x_disable_fbc(struct drm_device
*dev
)
1162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1165 /* Disable compression */
1166 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1167 dpfc_ctl
&= ~DPFC_CTL_EN
;
1168 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1170 DRM_DEBUG_KMS("disabled FBC\n");
1173 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1177 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1180 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1182 struct drm_device
*dev
= crtc
->dev
;
1183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1184 struct drm_framebuffer
*fb
= crtc
->fb
;
1185 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1186 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1188 int plane
= (intel_crtc
->plane
== 0) ? DPFC_CTL_PLANEA
:
1190 unsigned long stall_watermark
= 200;
1193 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1194 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1195 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1197 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1198 dpfc_ctl
&= DPFC_RESERVED
;
1199 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1200 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1201 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
);
1202 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1204 I915_WRITE(ILK_DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1207 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1208 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1209 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1210 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1211 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1212 I915_WRITE(ILK_FBC_RT_BASE
, obj_priv
->gtt_offset
| ILK_FBC_RT_VALID
);
1214 I915_WRITE(ILK_DPFC_CONTROL
, I915_READ(ILK_DPFC_CONTROL
) |
1217 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1220 void ironlake_disable_fbc(struct drm_device
*dev
)
1222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1225 /* Disable compression */
1226 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1227 dpfc_ctl
&= ~DPFC_CTL_EN
;
1228 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1230 DRM_DEBUG_KMS("disabled FBC\n");
1233 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1237 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1240 bool intel_fbc_enabled(struct drm_device
*dev
)
1242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1244 if (!dev_priv
->display
.fbc_enabled
)
1247 return dev_priv
->display
.fbc_enabled(dev
);
1250 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1252 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1254 if (!dev_priv
->display
.enable_fbc
)
1257 dev_priv
->display
.enable_fbc(crtc
, interval
);
1260 void intel_disable_fbc(struct drm_device
*dev
)
1262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1264 if (!dev_priv
->display
.disable_fbc
)
1267 dev_priv
->display
.disable_fbc(dev
);
1271 * intel_update_fbc - enable/disable FBC as needed
1272 * @crtc: CRTC to point the compressor at
1273 * @mode: mode in use
1275 * Set up the framebuffer compression hardware at mode set time. We
1276 * enable it if possible:
1277 * - plane A only (on pre-965)
1278 * - no pixel mulitply/line duplication
1279 * - no alpha buffer discard
1281 * - framebuffer <= 2048 in width, 1536 in height
1283 * We can't assume that any compression will take place (worst case),
1284 * so the compressed buffer has to be the same size as the uncompressed
1285 * one. It also must reside (along with the line length buffer) in
1288 * We need to enable/disable FBC on a global basis.
1290 static void intel_update_fbc(struct drm_crtc
*crtc
,
1291 struct drm_display_mode
*mode
)
1293 struct drm_device
*dev
= crtc
->dev
;
1294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1295 struct drm_framebuffer
*fb
= crtc
->fb
;
1296 struct intel_framebuffer
*intel_fb
;
1297 struct drm_i915_gem_object
*obj_priv
;
1298 struct drm_crtc
*tmp_crtc
;
1299 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1300 int plane
= intel_crtc
->plane
;
1301 int crtcs_enabled
= 0;
1303 DRM_DEBUG_KMS("\n");
1305 if (!i915_powersave
)
1308 if (!I915_HAS_FBC(dev
))
1314 intel_fb
= to_intel_framebuffer(fb
);
1315 obj_priv
= to_intel_bo(intel_fb
->obj
);
1318 * If FBC is already on, we just have to verify that we can
1319 * keep it that way...
1320 * Need to disable if:
1321 * - more than one pipe is active
1322 * - changing FBC params (stride, fence, mode)
1323 * - new fb is too large to fit in compressed buffer
1324 * - going to an unsupported config (interlace, pixel multiply, etc.)
1326 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1327 if (tmp_crtc
->enabled
)
1330 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled
);
1331 if (crtcs_enabled
> 1) {
1332 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1333 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
1336 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1337 DRM_DEBUG_KMS("framebuffer too large, disabling "
1339 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1342 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
1343 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1344 DRM_DEBUG_KMS("mode incompatible with compression, "
1346 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1349 if ((mode
->hdisplay
> 2048) ||
1350 (mode
->vdisplay
> 1536)) {
1351 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1352 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1355 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && plane
!= 0) {
1356 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1357 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1360 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1361 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1362 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1366 /* If the kernel debugger is active, always disable compression */
1367 if (in_dbg_master())
1370 if (intel_fbc_enabled(dev
)) {
1371 /* We can re-enable it in this case, but need to update pitch */
1372 if ((fb
->pitch
> dev_priv
->cfb_pitch
) ||
1373 (obj_priv
->fence_reg
!= dev_priv
->cfb_fence
) ||
1374 (plane
!= dev_priv
->cfb_plane
))
1375 intel_disable_fbc(dev
);
1378 /* Now try to turn it back on if possible */
1379 if (!intel_fbc_enabled(dev
))
1380 intel_enable_fbc(crtc
, 500);
1385 /* Multiple disables should be harmless */
1386 if (intel_fbc_enabled(dev
)) {
1387 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1388 intel_disable_fbc(dev
);
1393 intel_pin_and_fence_fb_obj(struct drm_device
*dev
, struct drm_gem_object
*obj
)
1395 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1399 switch (obj_priv
->tiling_mode
) {
1400 case I915_TILING_NONE
:
1401 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1402 alignment
= 128 * 1024;
1403 else if (IS_I965G(dev
))
1404 alignment
= 4 * 1024;
1406 alignment
= 64 * 1024;
1409 /* pin() will align the object as required by fence */
1413 /* FIXME: Is this true? */
1414 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1420 ret
= i915_gem_object_pin(obj
, alignment
);
1424 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1425 * fence, whereas 965+ only requires a fence if using
1426 * framebuffer compression. For simplicity, we always install
1427 * a fence as the cost is not that onerous.
1429 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1430 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1431 ret
= i915_gem_object_get_fence_reg(obj
);
1433 i915_gem_object_unpin(obj
);
1441 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1443 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1446 struct drm_device
*dev
= crtc
->dev
;
1447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1448 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1449 struct intel_framebuffer
*intel_fb
;
1450 struct drm_i915_gem_object
*obj_priv
;
1451 struct drm_gem_object
*obj
;
1452 int plane
= intel_crtc
->plane
;
1453 unsigned long Start
, Offset
;
1454 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1455 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1456 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1457 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1458 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1466 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1470 intel_fb
= to_intel_framebuffer(fb
);
1471 obj
= intel_fb
->obj
;
1472 obj_priv
= to_intel_bo(obj
);
1474 dspcntr
= I915_READ(dspcntr_reg
);
1475 /* Mask out pixel format bits in case we change it */
1476 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1477 switch (fb
->bits_per_pixel
) {
1479 dspcntr
|= DISPPLANE_8BPP
;
1482 if (fb
->depth
== 15)
1483 dspcntr
|= DISPPLANE_15_16BPP
;
1485 dspcntr
|= DISPPLANE_16BPP
;
1489 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1492 DRM_ERROR("Unknown color depth\n");
1495 if (IS_I965G(dev
)) {
1496 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1497 dspcntr
|= DISPPLANE_TILED
;
1499 dspcntr
&= ~DISPPLANE_TILED
;
1502 if (HAS_PCH_SPLIT(dev
))
1504 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1506 I915_WRITE(dspcntr_reg
, dspcntr
);
1508 Start
= obj_priv
->gtt_offset
;
1509 Offset
= y
* fb
->pitch
+ x
* (fb
->bits_per_pixel
/ 8);
1511 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1512 Start
, Offset
, x
, y
, fb
->pitch
);
1513 I915_WRITE(dspstride
, fb
->pitch
);
1514 if (IS_I965G(dev
)) {
1515 I915_WRITE(dspsurf
, Start
);
1516 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1517 I915_WRITE(dspbase
, Offset
);
1519 I915_WRITE(dspbase
, Start
+ Offset
);
1521 POSTING_READ(dspbase
);
1523 if (IS_I965G(dev
) || plane
== 0)
1524 intel_update_fbc(crtc
, &crtc
->mode
);
1526 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1527 intel_increase_pllclock(crtc
);
1533 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1534 struct drm_framebuffer
*old_fb
)
1536 struct drm_device
*dev
= crtc
->dev
;
1537 struct drm_i915_master_private
*master_priv
;
1538 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1539 struct intel_framebuffer
*intel_fb
;
1540 struct drm_i915_gem_object
*obj_priv
;
1541 struct drm_gem_object
*obj
;
1542 int pipe
= intel_crtc
->pipe
;
1543 int plane
= intel_crtc
->plane
;
1548 DRM_DEBUG_KMS("No FB bound\n");
1557 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1561 intel_fb
= to_intel_framebuffer(crtc
->fb
);
1562 obj
= intel_fb
->obj
;
1563 obj_priv
= to_intel_bo(obj
);
1565 mutex_lock(&dev
->struct_mutex
);
1566 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
1568 mutex_unlock(&dev
->struct_mutex
);
1572 ret
= i915_gem_object_set_to_display_plane(obj
);
1574 i915_gem_object_unpin(obj
);
1575 mutex_unlock(&dev
->struct_mutex
);
1579 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
);
1581 i915_gem_object_unpin(obj
);
1582 mutex_unlock(&dev
->struct_mutex
);
1587 intel_fb
= to_intel_framebuffer(old_fb
);
1588 obj_priv
= to_intel_bo(intel_fb
->obj
);
1589 i915_gem_object_unpin(intel_fb
->obj
);
1592 mutex_unlock(&dev
->struct_mutex
);
1594 if (!dev
->primary
->master
)
1597 master_priv
= dev
->primary
->master
->driver_priv
;
1598 if (!master_priv
->sarea_priv
)
1602 master_priv
->sarea_priv
->pipeB_x
= x
;
1603 master_priv
->sarea_priv
->pipeB_y
= y
;
1605 master_priv
->sarea_priv
->pipeA_x
= x
;
1606 master_priv
->sarea_priv
->pipeA_y
= y
;
1612 static void ironlake_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1614 struct drm_device
*dev
= crtc
->dev
;
1615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1618 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1619 dpa_ctl
= I915_READ(DP_A
);
1620 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1622 if (clock
< 200000) {
1624 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1625 /* workaround for 160Mhz:
1626 1) program 0x4600c bits 15:0 = 0x8124
1627 2) program 0x46010 bit 0 = 1
1628 3) program 0x46034 bit 24 = 1
1629 4) program 0x64000 bit 14 = 1
1631 temp
= I915_READ(0x4600c);
1633 I915_WRITE(0x4600c, temp
| 0x8124);
1635 temp
= I915_READ(0x46010);
1636 I915_WRITE(0x46010, temp
| 1);
1638 temp
= I915_READ(0x46034);
1639 I915_WRITE(0x46034, temp
| (1 << 24));
1641 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1643 I915_WRITE(DP_A
, dpa_ctl
);
1648 /* The FDI link training functions for ILK/Ibexpeak. */
1649 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
1651 struct drm_device
*dev
= crtc
->dev
;
1652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1654 int pipe
= intel_crtc
->pipe
;
1655 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1656 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1657 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1658 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1659 u32 temp
, tries
= 0;
1661 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1663 temp
= I915_READ(fdi_rx_imr_reg
);
1664 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1665 temp
&= ~FDI_RX_BIT_LOCK
;
1666 I915_WRITE(fdi_rx_imr_reg
, temp
);
1667 I915_READ(fdi_rx_imr_reg
);
1670 /* enable CPU FDI TX and PCH FDI RX */
1671 temp
= I915_READ(fdi_tx_reg
);
1672 temp
|= FDI_TX_ENABLE
;
1674 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1675 temp
&= ~FDI_LINK_TRAIN_NONE
;
1676 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1677 I915_WRITE(fdi_tx_reg
, temp
);
1678 I915_READ(fdi_tx_reg
);
1680 temp
= I915_READ(fdi_rx_reg
);
1681 temp
&= ~FDI_LINK_TRAIN_NONE
;
1682 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1683 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1684 I915_READ(fdi_rx_reg
);
1687 for (tries
= 0; tries
< 5; tries
++) {
1688 temp
= I915_READ(fdi_rx_iir_reg
);
1689 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1691 if ((temp
& FDI_RX_BIT_LOCK
)) {
1692 DRM_DEBUG_KMS("FDI train 1 done.\n");
1693 I915_WRITE(fdi_rx_iir_reg
,
1694 temp
| FDI_RX_BIT_LOCK
);
1699 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1702 temp
= I915_READ(fdi_tx_reg
);
1703 temp
&= ~FDI_LINK_TRAIN_NONE
;
1704 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1705 I915_WRITE(fdi_tx_reg
, temp
);
1707 temp
= I915_READ(fdi_rx_reg
);
1708 temp
&= ~FDI_LINK_TRAIN_NONE
;
1709 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1710 I915_WRITE(fdi_rx_reg
, temp
);
1715 for (tries
= 0; tries
< 5; tries
++) {
1716 temp
= I915_READ(fdi_rx_iir_reg
);
1717 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1719 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1720 I915_WRITE(fdi_rx_iir_reg
,
1721 temp
| FDI_RX_SYMBOL_LOCK
);
1722 DRM_DEBUG_KMS("FDI train 2 done.\n");
1727 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1729 DRM_DEBUG_KMS("FDI train done\n");
1732 static int snb_b_fdi_train_param
[] = {
1733 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
1734 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
1735 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
1736 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
1739 /* The FDI link training functions for SNB/Cougarpoint. */
1740 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
1742 struct drm_device
*dev
= crtc
->dev
;
1743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1744 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1745 int pipe
= intel_crtc
->pipe
;
1746 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1747 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1748 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1749 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1752 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1754 temp
= I915_READ(fdi_rx_imr_reg
);
1755 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1756 temp
&= ~FDI_RX_BIT_LOCK
;
1757 I915_WRITE(fdi_rx_imr_reg
, temp
);
1758 I915_READ(fdi_rx_imr_reg
);
1761 /* enable CPU FDI TX and PCH FDI RX */
1762 temp
= I915_READ(fdi_tx_reg
);
1763 temp
|= FDI_TX_ENABLE
;
1765 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1766 temp
&= ~FDI_LINK_TRAIN_NONE
;
1767 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1768 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1770 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1771 I915_WRITE(fdi_tx_reg
, temp
);
1772 I915_READ(fdi_tx_reg
);
1774 temp
= I915_READ(fdi_rx_reg
);
1775 if (HAS_PCH_CPT(dev
)) {
1776 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1777 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
1779 temp
&= ~FDI_LINK_TRAIN_NONE
;
1780 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1782 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1783 I915_READ(fdi_rx_reg
);
1786 for (i
= 0; i
< 4; i
++ ) {
1787 temp
= I915_READ(fdi_tx_reg
);
1788 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1789 temp
|= snb_b_fdi_train_param
[i
];
1790 I915_WRITE(fdi_tx_reg
, temp
);
1793 temp
= I915_READ(fdi_rx_iir_reg
);
1794 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1796 if (temp
& FDI_RX_BIT_LOCK
) {
1797 I915_WRITE(fdi_rx_iir_reg
,
1798 temp
| FDI_RX_BIT_LOCK
);
1799 DRM_DEBUG_KMS("FDI train 1 done.\n");
1804 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1807 temp
= I915_READ(fdi_tx_reg
);
1808 temp
&= ~FDI_LINK_TRAIN_NONE
;
1809 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1811 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1813 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1815 I915_WRITE(fdi_tx_reg
, temp
);
1817 temp
= I915_READ(fdi_rx_reg
);
1818 if (HAS_PCH_CPT(dev
)) {
1819 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1820 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
1822 temp
&= ~FDI_LINK_TRAIN_NONE
;
1823 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1825 I915_WRITE(fdi_rx_reg
, temp
);
1828 for (i
= 0; i
< 4; i
++ ) {
1829 temp
= I915_READ(fdi_tx_reg
);
1830 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1831 temp
|= snb_b_fdi_train_param
[i
];
1832 I915_WRITE(fdi_tx_reg
, temp
);
1835 temp
= I915_READ(fdi_rx_iir_reg
);
1836 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1838 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1839 I915_WRITE(fdi_rx_iir_reg
,
1840 temp
| FDI_RX_SYMBOL_LOCK
);
1841 DRM_DEBUG_KMS("FDI train 2 done.\n");
1846 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1848 DRM_DEBUG_KMS("FDI train done.\n");
1851 static void ironlake_fdi_enable(struct drm_crtc
*crtc
)
1853 struct drm_device
*dev
= crtc
->dev
;
1854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1856 int pipe
= intel_crtc
->pipe
;
1857 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1858 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1859 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1863 temp
= I915_READ(pipeconf_reg
);
1864 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1866 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1867 temp
= I915_READ(fdi_rx_reg
);
1869 * make the BPC in FDI Rx be consistent with that in
1872 temp
&= ~(0x7 << 16);
1873 temp
|= (pipe_bpc
<< 11);
1875 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1876 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
1877 I915_READ(fdi_rx_reg
);
1880 /* Switch from Rawclk to PCDclk */
1881 temp
= I915_READ(fdi_rx_reg
);
1882 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
1883 I915_READ(fdi_rx_reg
);
1886 /* Enable CPU FDI TX PLL, always on for Ironlake */
1887 temp
= I915_READ(fdi_tx_reg
);
1888 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1889 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1890 I915_READ(fdi_tx_reg
);
1895 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
1897 struct drm_device
*dev
= crtc
->dev
;
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1900 int pipe
= intel_crtc
->pipe
;
1901 int plane
= intel_crtc
->plane
;
1902 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1903 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1904 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1905 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1906 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1907 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1908 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1909 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1910 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1911 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1912 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1913 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1914 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1915 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1916 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1917 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1918 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1919 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1920 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1921 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
1925 temp
= I915_READ(pipeconf_reg
);
1926 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1928 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1929 temp
= I915_READ(PCH_LVDS
);
1930 if ((temp
& LVDS_PORT_EN
) == 0) {
1931 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1932 POSTING_READ(PCH_LVDS
);
1936 ironlake_fdi_enable(crtc
);
1938 /* Enable panel fitting for LVDS */
1939 if (dev_priv
->pch_pf_size
&&
1940 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)
1941 || HAS_eDP
|| intel_pch_has_edp(crtc
))) {
1942 /* Force use of hard-coded filter coefficients
1943 * as some pre-programmed values are broken,
1946 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
,
1947 PF_ENABLE
| PF_FILTER_MED_3x3
);
1948 I915_WRITE(pipe
? PFB_WIN_POS
: PFA_WIN_POS
,
1949 dev_priv
->pch_pf_pos
);
1950 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
,
1951 dev_priv
->pch_pf_size
);
1954 /* Enable CPU pipe */
1955 temp
= I915_READ(pipeconf_reg
);
1956 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1957 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1958 I915_READ(pipeconf_reg
);
1962 /* configure and enable CPU plane */
1963 temp
= I915_READ(dspcntr_reg
);
1964 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1965 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1966 /* Flush the plane changes */
1967 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1970 /* For PCH output, training FDI link */
1972 gen6_fdi_link_train(crtc
);
1974 ironlake_fdi_link_train(crtc
);
1976 /* enable PCH DPLL */
1977 temp
= I915_READ(pch_dpll_reg
);
1978 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1979 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1980 I915_READ(pch_dpll_reg
);
1984 if (HAS_PCH_CPT(dev
)) {
1985 /* Be sure PCH DPLL SEL is set */
1986 temp
= I915_READ(PCH_DPLL_SEL
);
1987 if (trans_dpll_sel
== 0 &&
1988 (temp
& TRANSA_DPLL_ENABLE
) == 0)
1989 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
1990 else if (trans_dpll_sel
== 1 &&
1991 (temp
& TRANSB_DPLL_ENABLE
) == 0)
1992 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
1993 I915_WRITE(PCH_DPLL_SEL
, temp
);
1994 I915_READ(PCH_DPLL_SEL
);
1996 /* set transcoder timing */
1997 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1998 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1999 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
2001 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
2002 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
2003 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
2005 /* enable normal train */
2006 temp
= I915_READ(fdi_tx_reg
);
2007 temp
&= ~FDI_LINK_TRAIN_NONE
;
2008 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
2009 FDI_TX_ENHANCE_FRAME_ENABLE
);
2010 I915_READ(fdi_tx_reg
);
2012 temp
= I915_READ(fdi_rx_reg
);
2013 if (HAS_PCH_CPT(dev
)) {
2014 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2015 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2017 temp
&= ~FDI_LINK_TRAIN_NONE
;
2018 temp
|= FDI_LINK_TRAIN_NONE
;
2020 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2021 I915_READ(fdi_rx_reg
);
2023 /* wait one idle pattern time */
2026 /* For PCH DP, enable TRANS_DP_CTL */
2027 if (HAS_PCH_CPT(dev
) &&
2028 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
2029 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2032 reg
= I915_READ(trans_dp_ctl
);
2033 reg
&= ~(TRANS_DP_PORT_SEL_MASK
|
2034 TRANS_DP_SYNC_MASK
);
2035 reg
|= (TRANS_DP_OUTPUT_ENABLE
|
2036 TRANS_DP_ENH_FRAMING
);
2038 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2039 reg
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2040 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2041 reg
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2043 switch (intel_trans_dp_port_sel(crtc
)) {
2045 reg
|= TRANS_DP_PORT_SEL_B
;
2048 reg
|= TRANS_DP_PORT_SEL_C
;
2051 reg
|= TRANS_DP_PORT_SEL_D
;
2054 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2055 reg
|= TRANS_DP_PORT_SEL_B
;
2059 I915_WRITE(trans_dp_ctl
, reg
);
2060 POSTING_READ(trans_dp_ctl
);
2063 /* enable PCH transcoder */
2064 temp
= I915_READ(transconf_reg
);
2066 * make the BPC in transcoder be consistent with
2067 * that in pipeconf reg.
2069 temp
&= ~PIPE_BPC_MASK
;
2071 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
2072 I915_READ(transconf_reg
);
2074 if (wait_for(I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
, 100))
2075 DRM_ERROR("failed to enable transcoder\n");
2077 intel_crtc_load_lut(crtc
);
2079 intel_update_fbc(crtc
, &crtc
->mode
);
2082 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
2084 struct drm_device
*dev
= crtc
->dev
;
2085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2087 int pipe
= intel_crtc
->pipe
;
2088 int plane
= intel_crtc
->plane
;
2089 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
2090 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2091 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2092 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
2093 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
2094 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
2095 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
2096 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
2100 temp
= I915_READ(pipeconf_reg
);
2101 pipe_bpc
= temp
& PIPE_BPC_MASK
;
2103 drm_vblank_off(dev
, pipe
);
2104 /* Disable display plane */
2105 temp
= I915_READ(dspcntr_reg
);
2106 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2107 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2108 /* Flush the plane changes */
2109 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2110 I915_READ(dspbase_reg
);
2113 if (dev_priv
->cfb_plane
== plane
&&
2114 dev_priv
->display
.disable_fbc
)
2115 dev_priv
->display
.disable_fbc(dev
);
2117 /* disable cpu pipe, disable after all planes disabled */
2118 temp
= I915_READ(pipeconf_reg
);
2119 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2120 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2122 /* wait for cpu pipe off, pipe state */
2123 if (wait_for((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) == 0, 50))
2124 DRM_ERROR("failed to turn off cpu pipe\n");
2126 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
2131 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
, 0);
2132 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
, 0);
2134 /* disable CPU FDI tx and PCH FDI rx */
2135 temp
= I915_READ(fdi_tx_reg
);
2136 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
2137 I915_READ(fdi_tx_reg
);
2139 temp
= I915_READ(fdi_rx_reg
);
2140 /* BPC in FDI rx is consistent with that in pipeconf */
2141 temp
&= ~(0x07 << 16);
2142 temp
|= (pipe_bpc
<< 11);
2143 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
2144 I915_READ(fdi_rx_reg
);
2148 /* still set train pattern 1 */
2149 temp
= I915_READ(fdi_tx_reg
);
2150 temp
&= ~FDI_LINK_TRAIN_NONE
;
2151 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2152 I915_WRITE(fdi_tx_reg
, temp
);
2153 POSTING_READ(fdi_tx_reg
);
2155 temp
= I915_READ(fdi_rx_reg
);
2156 if (HAS_PCH_CPT(dev
)) {
2157 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2158 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2160 temp
&= ~FDI_LINK_TRAIN_NONE
;
2161 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2163 I915_WRITE(fdi_rx_reg
, temp
);
2164 POSTING_READ(fdi_rx_reg
);
2168 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2169 temp
= I915_READ(PCH_LVDS
);
2170 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2171 I915_READ(PCH_LVDS
);
2175 /* disable PCH transcoder */
2176 temp
= I915_READ(transconf_reg
);
2177 if ((temp
& TRANS_ENABLE
) != 0) {
2178 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
2180 /* wait for PCH transcoder off, transcoder state */
2181 if (wait_for((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2182 DRM_ERROR("failed to disable transcoder\n");
2185 temp
= I915_READ(transconf_reg
);
2186 /* BPC in transcoder is consistent with that in pipeconf */
2187 temp
&= ~PIPE_BPC_MASK
;
2189 I915_WRITE(transconf_reg
, temp
);
2190 I915_READ(transconf_reg
);
2193 if (HAS_PCH_CPT(dev
)) {
2194 /* disable TRANS_DP_CTL */
2195 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2198 reg
= I915_READ(trans_dp_ctl
);
2199 reg
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2200 I915_WRITE(trans_dp_ctl
, reg
);
2201 POSTING_READ(trans_dp_ctl
);
2203 /* disable DPLL_SEL */
2204 temp
= I915_READ(PCH_DPLL_SEL
);
2205 if (trans_dpll_sel
== 0)
2206 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2208 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2209 I915_WRITE(PCH_DPLL_SEL
, temp
);
2210 I915_READ(PCH_DPLL_SEL
);
2214 /* disable PCH DPLL */
2215 temp
= I915_READ(pch_dpll_reg
);
2216 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2217 I915_READ(pch_dpll_reg
);
2219 /* Switch from PCDclk to Rawclk */
2220 temp
= I915_READ(fdi_rx_reg
);
2221 temp
&= ~FDI_SEL_PCDCLK
;
2222 I915_WRITE(fdi_rx_reg
, temp
);
2223 I915_READ(fdi_rx_reg
);
2225 /* Disable CPU FDI TX PLL */
2226 temp
= I915_READ(fdi_tx_reg
);
2227 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2228 I915_READ(fdi_tx_reg
);
2231 temp
= I915_READ(fdi_rx_reg
);
2232 temp
&= ~FDI_RX_PLL_ENABLE
;
2233 I915_WRITE(fdi_rx_reg
, temp
);
2234 I915_READ(fdi_rx_reg
);
2236 /* Wait for the clocks to turn off. */
2240 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2243 int pipe
= intel_crtc
->pipe
;
2244 int plane
= intel_crtc
->plane
;
2246 /* XXX: When our outputs are all unaware of DPMS modes other than off
2247 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2250 case DRM_MODE_DPMS_ON
:
2251 case DRM_MODE_DPMS_STANDBY
:
2252 case DRM_MODE_DPMS_SUSPEND
:
2253 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
2254 ironlake_crtc_enable(crtc
);
2257 case DRM_MODE_DPMS_OFF
:
2258 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
2259 ironlake_crtc_disable(crtc
);
2264 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2266 if (!enable
&& intel_crtc
->overlay
) {
2267 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2269 mutex_lock(&dev
->struct_mutex
);
2270 (void) intel_overlay_switch_off(intel_crtc
->overlay
, false);
2271 mutex_unlock(&dev
->struct_mutex
);
2274 /* Let userspace switch the overlay on again. In most cases userspace
2275 * has to recompute where to put it anyway.
2279 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
2281 struct drm_device
*dev
= crtc
->dev
;
2282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2283 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2284 int pipe
= intel_crtc
->pipe
;
2285 int plane
= intel_crtc
->plane
;
2286 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2287 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2288 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
2289 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2292 /* Enable the DPLL */
2293 temp
= I915_READ(dpll_reg
);
2294 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2295 I915_WRITE(dpll_reg
, temp
);
2296 I915_READ(dpll_reg
);
2297 /* Wait for the clocks to stabilize. */
2299 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2300 I915_READ(dpll_reg
);
2301 /* Wait for the clocks to stabilize. */
2303 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2304 I915_READ(dpll_reg
);
2305 /* Wait for the clocks to stabilize. */
2309 /* Enable the pipe */
2310 temp
= I915_READ(pipeconf_reg
);
2311 if ((temp
& PIPEACONF_ENABLE
) == 0)
2312 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
2314 /* Enable the plane */
2315 temp
= I915_READ(dspcntr_reg
);
2316 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2317 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
2318 /* Flush the plane changes */
2319 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2322 intel_crtc_load_lut(crtc
);
2324 if ((IS_I965G(dev
) || plane
== 0))
2325 intel_update_fbc(crtc
, &crtc
->mode
);
2327 /* Give the overlay scaler a chance to enable if it's on this pipe */
2328 intel_crtc_dpms_overlay(intel_crtc
, true);
2331 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
2333 struct drm_device
*dev
= crtc
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2336 int pipe
= intel_crtc
->pipe
;
2337 int plane
= intel_crtc
->plane
;
2338 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2339 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2340 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
2341 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2344 /* Give the overlay scaler a chance to disable if it's on this pipe */
2345 intel_crtc_dpms_overlay(intel_crtc
, false);
2346 drm_vblank_off(dev
, pipe
);
2348 if (dev_priv
->cfb_plane
== plane
&&
2349 dev_priv
->display
.disable_fbc
)
2350 dev_priv
->display
.disable_fbc(dev
);
2352 /* Disable display plane */
2353 temp
= I915_READ(dspcntr_reg
);
2354 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2355 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2356 /* Flush the plane changes */
2357 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2358 I915_READ(dspbase_reg
);
2361 if (!IS_I9XX(dev
)) {
2362 /* Wait for vblank for the disable to take effect */
2363 intel_wait_for_vblank_off(dev
, pipe
);
2366 /* Don't disable pipe A or pipe A PLLs if needed */
2367 if (pipeconf_reg
== PIPEACONF
&&
2368 (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2371 /* Next, disable display pipes */
2372 temp
= I915_READ(pipeconf_reg
);
2373 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2374 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2375 I915_READ(pipeconf_reg
);
2378 /* Wait for vblank for the disable to take effect. */
2379 intel_wait_for_vblank_off(dev
, pipe
);
2381 temp
= I915_READ(dpll_reg
);
2382 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
2383 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2384 I915_READ(dpll_reg
);
2387 /* Wait for the clocks to turn off. */
2391 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2393 /* XXX: When our outputs are all unaware of DPMS modes other than off
2394 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2397 case DRM_MODE_DPMS_ON
:
2398 case DRM_MODE_DPMS_STANDBY
:
2399 case DRM_MODE_DPMS_SUSPEND
:
2400 i9xx_crtc_enable(crtc
);
2402 case DRM_MODE_DPMS_OFF
:
2403 i9xx_crtc_disable(crtc
);
2409 * When we disable a pipe, we need to clear any pending scanline wait events
2410 * to avoid hanging the ring, which we assume we are waiting on.
2412 static void intel_clear_scanline_wait(struct drm_device
*dev
)
2414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2418 /* Can't break the hang on i8xx */
2421 tmp
= I915_READ(PRB0_CTL
);
2422 if (tmp
& RING_WAIT
) {
2423 I915_WRITE(PRB0_CTL
, tmp
);
2424 POSTING_READ(PRB0_CTL
);
2429 * Sets the power management mode of the pipe and plane.
2431 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2433 struct drm_device
*dev
= crtc
->dev
;
2434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 struct drm_i915_master_private
*master_priv
;
2436 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2437 int pipe
= intel_crtc
->pipe
;
2440 if (intel_crtc
->dpms_mode
== mode
)
2443 intel_crtc
->dpms_mode
= mode
;
2444 intel_crtc
->cursor_on
= mode
== DRM_MODE_DPMS_ON
;
2446 /* When switching on the display, ensure that SR is disabled
2447 * with multiple pipes prior to enabling to new pipe.
2449 * When switching off the display, make sure the cursor is
2450 * properly hidden and there are no pending waits prior to
2451 * disabling the pipe.
2453 if (mode
== DRM_MODE_DPMS_ON
)
2454 intel_update_watermarks(dev
);
2456 intel_crtc_update_cursor(crtc
);
2458 dev_priv
->display
.dpms(crtc
, mode
);
2460 if (mode
== DRM_MODE_DPMS_ON
)
2461 intel_crtc_update_cursor(crtc
);
2463 /* XXX Note that this is not a complete solution, but a hack
2464 * to avoid the most frequently hit hang.
2466 intel_clear_scanline_wait(dev
);
2468 intel_update_watermarks(dev
);
2471 if (!dev
->primary
->master
)
2474 master_priv
= dev
->primary
->master
->driver_priv
;
2475 if (!master_priv
->sarea_priv
)
2478 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2482 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2483 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2486 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2487 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2490 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2495 /* Prepare for a mode set.
2497 * Note we could be a lot smarter here. We need to figure out which outputs
2498 * will be enabled, which disabled (in short, how the config will changes)
2499 * and perform the minimum necessary steps to accomplish that, e.g. updating
2500 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2501 * panel fitting is in the proper state, etc.
2503 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
2505 struct drm_device
*dev
= crtc
->dev
;
2506 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2508 intel_crtc
->cursor_on
= false;
2509 intel_crtc_update_cursor(crtc
);
2511 i9xx_crtc_disable(crtc
);
2512 intel_clear_scanline_wait(dev
);
2515 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
2517 struct drm_device
*dev
= crtc
->dev
;
2518 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2520 intel_update_watermarks(dev
);
2521 i9xx_crtc_enable(crtc
);
2523 intel_crtc
->cursor_on
= true;
2524 intel_crtc_update_cursor(crtc
);
2527 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
2529 struct drm_device
*dev
= crtc
->dev
;
2530 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2532 intel_crtc
->cursor_on
= false;
2533 intel_crtc_update_cursor(crtc
);
2535 ironlake_crtc_disable(crtc
);
2536 intel_clear_scanline_wait(dev
);
2539 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
2541 struct drm_device
*dev
= crtc
->dev
;
2542 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2544 intel_update_watermarks(dev
);
2545 ironlake_crtc_enable(crtc
);
2547 intel_crtc
->cursor_on
= true;
2548 intel_crtc_update_cursor(crtc
);
2551 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2553 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2554 /* lvds has its own version of prepare see intel_lvds_prepare */
2555 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2558 void intel_encoder_commit (struct drm_encoder
*encoder
)
2560 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2561 /* lvds has its own version of commit see intel_lvds_commit */
2562 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2565 void intel_encoder_destroy(struct drm_encoder
*encoder
)
2567 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
2569 if (intel_encoder
->ddc_bus
)
2570 intel_i2c_destroy(intel_encoder
->ddc_bus
);
2572 if (intel_encoder
->i2c_bus
)
2573 intel_i2c_destroy(intel_encoder
->i2c_bus
);
2575 drm_encoder_cleanup(encoder
);
2576 kfree(intel_encoder
);
2579 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2580 struct drm_display_mode
*mode
,
2581 struct drm_display_mode
*adjusted_mode
)
2583 struct drm_device
*dev
= crtc
->dev
;
2584 if (HAS_PCH_SPLIT(dev
)) {
2585 /* FDI link clock is fixed at 2.7G */
2586 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
2592 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2597 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2602 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2607 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2611 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2613 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2616 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2617 case GC_DISPLAY_CLOCK_333_MHZ
:
2620 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2626 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2631 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2634 /* Assume that the hardware is in the high speed state. This
2635 * should be the default.
2637 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2638 case GC_CLOCK_133_200
:
2639 case GC_CLOCK_100_200
:
2641 case GC_CLOCK_166_250
:
2643 case GC_CLOCK_100_133
:
2647 /* Shouldn't happen */
2651 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2657 * Return the pipe currently connected to the panel fitter,
2658 * or -1 if the panel fitter is not present or not in use
2660 int intel_panel_fitter_pipe (struct drm_device
*dev
)
2662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2665 /* i830 doesn't have a panel fitter */
2669 pfit_control
= I915_READ(PFIT_CONTROL
);
2671 /* See if the panel fitter is in use */
2672 if ((pfit_control
& PFIT_ENABLE
) == 0)
2675 /* 965 can place panel fitter on either pipe */
2677 return (pfit_control
>> 29) & 0x3;
2679 /* older chips can only use pipe 1 */
2692 fdi_reduce_ratio(u32
*num
, u32
*den
)
2694 while (*num
> 0xffffff || *den
> 0xffffff) {
2700 #define DATA_N 0x800000
2701 #define LINK_N 0x80000
2704 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2705 int link_clock
, struct fdi_m_n
*m_n
)
2709 m_n
->tu
= 64; /* default size */
2711 temp
= (u64
) DATA_N
* pixel_clock
;
2712 temp
= div_u64(temp
, link_clock
);
2713 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2714 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2715 m_n
->gmch_n
= DATA_N
;
2716 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2718 temp
= (u64
) LINK_N
* pixel_clock
;
2719 m_n
->link_m
= div_u64(temp
, link_clock
);
2720 m_n
->link_n
= LINK_N
;
2721 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2725 struct intel_watermark_params
{
2726 unsigned long fifo_size
;
2727 unsigned long max_wm
;
2728 unsigned long default_wm
;
2729 unsigned long guard_size
;
2730 unsigned long cacheline_size
;
2733 /* Pineview has different values for various configs */
2734 static struct intel_watermark_params pineview_display_wm
= {
2735 PINEVIEW_DISPLAY_FIFO
,
2739 PINEVIEW_FIFO_LINE_SIZE
2741 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2742 PINEVIEW_DISPLAY_FIFO
,
2744 PINEVIEW_DFT_HPLLOFF_WM
,
2746 PINEVIEW_FIFO_LINE_SIZE
2748 static struct intel_watermark_params pineview_cursor_wm
= {
2749 PINEVIEW_CURSOR_FIFO
,
2750 PINEVIEW_CURSOR_MAX_WM
,
2751 PINEVIEW_CURSOR_DFT_WM
,
2752 PINEVIEW_CURSOR_GUARD_WM
,
2753 PINEVIEW_FIFO_LINE_SIZE
,
2755 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2756 PINEVIEW_CURSOR_FIFO
,
2757 PINEVIEW_CURSOR_MAX_WM
,
2758 PINEVIEW_CURSOR_DFT_WM
,
2759 PINEVIEW_CURSOR_GUARD_WM
,
2760 PINEVIEW_FIFO_LINE_SIZE
2762 static struct intel_watermark_params g4x_wm_info
= {
2769 static struct intel_watermark_params g4x_cursor_wm_info
= {
2776 static struct intel_watermark_params i965_cursor_wm_info
= {
2781 I915_FIFO_LINE_SIZE
,
2783 static struct intel_watermark_params i945_wm_info
= {
2790 static struct intel_watermark_params i915_wm_info
= {
2797 static struct intel_watermark_params i855_wm_info
= {
2804 static struct intel_watermark_params i830_wm_info
= {
2812 static struct intel_watermark_params ironlake_display_wm_info
= {
2820 static struct intel_watermark_params ironlake_cursor_wm_info
= {
2828 static struct intel_watermark_params ironlake_display_srwm_info
= {
2829 ILK_DISPLAY_SR_FIFO
,
2830 ILK_DISPLAY_MAX_SRWM
,
2831 ILK_DISPLAY_DFT_SRWM
,
2836 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
2838 ILK_CURSOR_MAX_SRWM
,
2839 ILK_CURSOR_DFT_SRWM
,
2845 * intel_calculate_wm - calculate watermark level
2846 * @clock_in_khz: pixel clock
2847 * @wm: chip FIFO params
2848 * @pixel_size: display pixel size
2849 * @latency_ns: memory latency for the platform
2851 * Calculate the watermark level (the level at which the display plane will
2852 * start fetching from memory again). Each chip has a different display
2853 * FIFO size and allocation, so the caller needs to figure that out and pass
2854 * in the correct intel_watermark_params structure.
2856 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2857 * on the pixel size. When it reaches the watermark level, it'll start
2858 * fetching FIFO line sized based chunks from memory until the FIFO fills
2859 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2860 * will occur, and a display engine hang could result.
2862 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2863 struct intel_watermark_params
*wm
,
2865 unsigned long latency_ns
)
2867 long entries_required
, wm_size
;
2870 * Note: we need to make sure we don't overflow for various clock &
2872 * clocks go from a few thousand to several hundred thousand.
2873 * latency is usually a few thousand
2875 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2877 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
2879 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2881 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2883 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2885 /* Don't promote wm_size to unsigned... */
2886 if (wm_size
> (long)wm
->max_wm
)
2887 wm_size
= wm
->max_wm
;
2889 wm_size
= wm
->default_wm
;
2893 struct cxsr_latency
{
2896 unsigned long fsb_freq
;
2897 unsigned long mem_freq
;
2898 unsigned long display_sr
;
2899 unsigned long display_hpll_disable
;
2900 unsigned long cursor_sr
;
2901 unsigned long cursor_hpll_disable
;
2904 static const struct cxsr_latency cxsr_latency_table
[] = {
2905 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2906 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2907 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2908 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2909 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2911 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2912 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2913 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2914 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2915 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2917 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2918 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2919 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2920 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2921 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2923 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2924 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2925 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2926 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2927 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2929 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2930 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2931 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2932 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2933 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2935 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2936 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2937 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2938 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2939 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2942 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
2947 const struct cxsr_latency
*latency
;
2950 if (fsb
== 0 || mem
== 0)
2953 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2954 latency
= &cxsr_latency_table
[i
];
2955 if (is_desktop
== latency
->is_desktop
&&
2956 is_ddr3
== latency
->is_ddr3
&&
2957 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2961 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2966 static void pineview_disable_cxsr(struct drm_device
*dev
)
2968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2970 /* deactivate cxsr */
2971 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
2975 * Latency for FIFO fetches is dependent on several factors:
2976 * - memory configuration (speed, channels)
2978 * - current MCH state
2979 * It can be fairly high in some situations, so here we assume a fairly
2980 * pessimal value. It's a tradeoff between extra memory fetches (if we
2981 * set this value too high, the FIFO will fetch frequently to stay full)
2982 * and power consumption (set it too low to save power and we might see
2983 * FIFO underruns and display "flicker").
2985 * A value of 5us seems to be a good balance; safe for very low end
2986 * platforms but not overly aggressive on lower latency configs.
2988 static const int latency_ns
= 5000;
2990 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2993 uint32_t dsparb
= I915_READ(DSPARB
);
2996 size
= dsparb
& 0x7f;
2998 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
3000 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3001 plane
? "B" : "A", size
);
3006 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
3008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3009 uint32_t dsparb
= I915_READ(DSPARB
);
3012 size
= dsparb
& 0x1ff;
3014 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
3015 size
>>= 1; /* Convert to cachelines */
3017 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3018 plane
? "B" : "A", size
);
3023 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
3025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3026 uint32_t dsparb
= I915_READ(DSPARB
);
3029 size
= dsparb
& 0x7f;
3030 size
>>= 2; /* Convert to cachelines */
3032 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3039 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
3041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3042 uint32_t dsparb
= I915_READ(DSPARB
);
3045 size
= dsparb
& 0x7f;
3046 size
>>= 1; /* Convert to cachelines */
3048 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3049 plane
? "B" : "A", size
);
3054 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
3055 int planeb_clock
, int sr_hdisplay
, int unused
,
3058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3059 const struct cxsr_latency
*latency
;
3064 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
3065 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3067 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3068 pineview_disable_cxsr(dev
);
3072 if (!planea_clock
|| !planeb_clock
) {
3073 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3076 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
3077 pixel_size
, latency
->display_sr
);
3078 reg
= I915_READ(DSPFW1
);
3079 reg
&= ~DSPFW_SR_MASK
;
3080 reg
|= wm
<< DSPFW_SR_SHIFT
;
3081 I915_WRITE(DSPFW1
, reg
);
3082 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
3085 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
3086 pixel_size
, latency
->cursor_sr
);
3087 reg
= I915_READ(DSPFW3
);
3088 reg
&= ~DSPFW_CURSOR_SR_MASK
;
3089 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
3090 I915_WRITE(DSPFW3
, reg
);
3092 /* Display HPLL off SR */
3093 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
3094 pixel_size
, latency
->display_hpll_disable
);
3095 reg
= I915_READ(DSPFW3
);
3096 reg
&= ~DSPFW_HPLL_SR_MASK
;
3097 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
3098 I915_WRITE(DSPFW3
, reg
);
3100 /* cursor HPLL off SR */
3101 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
3102 pixel_size
, latency
->cursor_hpll_disable
);
3103 reg
= I915_READ(DSPFW3
);
3104 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
3105 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
3106 I915_WRITE(DSPFW3
, reg
);
3107 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
3111 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
3112 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3114 pineview_disable_cxsr(dev
);
3115 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3119 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
3120 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3124 int total_size
, cacheline_size
;
3125 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
3126 struct intel_watermark_params planea_params
, planeb_params
;
3127 unsigned long line_time_us
;
3128 int sr_clock
, sr_entries
= 0, entries_required
;
3130 /* Create copies of the base settings for each pipe */
3131 planea_params
= planeb_params
= g4x_wm_info
;
3133 /* Grab a couple of global values before we overwrite them */
3134 total_size
= planea_params
.fifo_size
;
3135 cacheline_size
= planea_params
.cacheline_size
;
3138 * Note: we need to make sure we don't overflow for various clock &
3140 * clocks go from a few thousand to several hundred thousand.
3141 * latency is usually a few thousand
3143 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
3145 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3146 planea_wm
= entries_required
+ planea_params
.guard_size
;
3148 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
3150 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3151 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
3153 cursora_wm
= cursorb_wm
= 16;
3156 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3158 /* Calc sr entries for one plane configs */
3159 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3160 /* self-refresh has much higher latency */
3161 static const int sr_latency_ns
= 12000;
3163 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3164 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3166 /* Use ns/us then divide to preserve precision */
3167 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3168 pixel_size
* sr_hdisplay
;
3169 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3171 entries_required
= (((sr_latency_ns
/ line_time_us
) +
3172 1000) / 1000) * pixel_size
* 64;
3173 entries_required
= DIV_ROUND_UP(entries_required
,
3174 g4x_cursor_wm_info
.cacheline_size
);
3175 cursor_sr
= entries_required
+ g4x_cursor_wm_info
.guard_size
;
3177 if (cursor_sr
> g4x_cursor_wm_info
.max_wm
)
3178 cursor_sr
= g4x_cursor_wm_info
.max_wm
;
3179 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3180 "cursor %d\n", sr_entries
, cursor_sr
);
3182 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3184 /* Turn off self refresh if both pipes are enabled */
3185 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3189 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3190 planea_wm
, planeb_wm
, sr_entries
);
3195 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
3196 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
3197 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
3198 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
3199 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
3200 /* HPLL off in SR has some issues on G4x... disable it */
3201 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
3202 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3205 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
3206 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3210 unsigned long line_time_us
;
3211 int sr_clock
, sr_entries
, srwm
= 1;
3214 /* Calc sr entries for one plane configs */
3215 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3216 /* self-refresh has much higher latency */
3217 static const int sr_latency_ns
= 12000;
3219 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3220 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3222 /* Use ns/us then divide to preserve precision */
3223 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3224 pixel_size
* sr_hdisplay
;
3225 sr_entries
= DIV_ROUND_UP(sr_entries
, I915_FIFO_LINE_SIZE
);
3226 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
3227 srwm
= I965_FIFO_SIZE
- sr_entries
;
3232 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3234 sr_entries
= DIV_ROUND_UP(sr_entries
,
3235 i965_cursor_wm_info
.cacheline_size
);
3236 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
3237 (sr_entries
+ i965_cursor_wm_info
.guard_size
);
3239 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
3240 cursor_sr
= i965_cursor_wm_info
.max_wm
;
3242 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3243 "cursor %d\n", srwm
, cursor_sr
);
3246 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3248 /* Turn off self refresh if both pipes are enabled */
3250 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3254 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3257 /* 965 has limitations... */
3258 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
3260 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
3261 /* update cursor SR watermark */
3262 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3265 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
3266 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3272 int total_size
, cacheline_size
, cwm
, srwm
= 1;
3273 int planea_wm
, planeb_wm
;
3274 struct intel_watermark_params planea_params
, planeb_params
;
3275 unsigned long line_time_us
;
3276 int sr_clock
, sr_entries
= 0;
3278 /* Create copies of the base settings for each pipe */
3279 if (IS_I965GM(dev
) || IS_I945GM(dev
))
3280 planea_params
= planeb_params
= i945_wm_info
;
3281 else if (IS_I9XX(dev
))
3282 planea_params
= planeb_params
= i915_wm_info
;
3284 planea_params
= planeb_params
= i855_wm_info
;
3286 /* Grab a couple of global values before we overwrite them */
3287 total_size
= planea_params
.fifo_size
;
3288 cacheline_size
= planea_params
.cacheline_size
;
3290 /* Update per-plane FIFO sizes */
3291 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3292 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
3294 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
3295 pixel_size
, latency_ns
);
3296 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
3297 pixel_size
, latency_ns
);
3298 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3301 * Overlay gets an aggressive default since video jitter is bad.
3305 /* Calc sr entries for one plane configs */
3306 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
3307 (!planea_clock
|| !planeb_clock
)) {
3308 /* self-refresh has much higher latency */
3309 static const int sr_latency_ns
= 6000;
3311 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3312 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3314 /* Use ns/us then divide to preserve precision */
3315 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3316 pixel_size
* sr_hdisplay
;
3317 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3318 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
3319 srwm
= total_size
- sr_entries
;
3323 if (IS_I945G(dev
) || IS_I945GM(dev
))
3324 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3325 else if (IS_I915GM(dev
)) {
3326 /* 915M has a smaller SRWM field */
3327 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3328 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3331 /* Turn off self refresh if both pipes are enabled */
3332 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3333 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3335 } else if (IS_I915GM(dev
)) {
3336 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3340 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3341 planea_wm
, planeb_wm
, cwm
, srwm
);
3343 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3344 fwater_hi
= (cwm
& 0x1f);
3346 /* Set request length to 8 cachelines per fetch */
3347 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3348 fwater_hi
= fwater_hi
| (1 << 8);
3350 I915_WRITE(FW_BLC
, fwater_lo
);
3351 I915_WRITE(FW_BLC2
, fwater_hi
);
3354 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3355 int unused2
, int unused3
, int pixel_size
)
3357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3358 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3361 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3363 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3364 pixel_size
, latency_ns
);
3365 fwater_lo
|= (3<<8) | planea_wm
;
3367 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3369 I915_WRITE(FW_BLC
, fwater_lo
);
3372 #define ILK_LP0_PLANE_LATENCY 700
3373 #define ILK_LP0_CURSOR_LATENCY 1300
3375 static void ironlake_update_wm(struct drm_device
*dev
, int planea_clock
,
3376 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3380 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
3381 int sr_wm
, cursor_wm
;
3382 unsigned long line_time_us
;
3383 int sr_clock
, entries_required
;
3386 int planea_htotal
= 0, planeb_htotal
= 0;
3387 struct drm_crtc
*crtc
;
3389 /* Need htotal for all active display plane */
3390 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3391 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3392 if (intel_crtc
->dpms_mode
== DRM_MODE_DPMS_ON
) {
3393 if (intel_crtc
->plane
== 0)
3394 planea_htotal
= crtc
->mode
.htotal
;
3396 planeb_htotal
= crtc
->mode
.htotal
;
3400 /* Calculate and update the watermark for plane A */
3402 entries_required
= ((planea_clock
/ 1000) * pixel_size
*
3403 ILK_LP0_PLANE_LATENCY
) / 1000;
3404 entries_required
= DIV_ROUND_UP(entries_required
,
3405 ironlake_display_wm_info
.cacheline_size
);
3406 planea_wm
= entries_required
+
3407 ironlake_display_wm_info
.guard_size
;
3409 if (planea_wm
> (int)ironlake_display_wm_info
.max_wm
)
3410 planea_wm
= ironlake_display_wm_info
.max_wm
;
3412 /* Use the large buffer method to calculate cursor watermark */
3413 line_time_us
= (planea_htotal
* 1000) / planea_clock
;
3415 /* Use ns/us then divide to preserve precision */
3416 line_count
= (ILK_LP0_CURSOR_LATENCY
/ line_time_us
+ 1000) / 1000;
3418 /* calculate the cursor watermark for cursor A */
3419 entries_required
= line_count
* 64 * pixel_size
;
3420 entries_required
= DIV_ROUND_UP(entries_required
,
3421 ironlake_cursor_wm_info
.cacheline_size
);
3422 cursora_wm
= entries_required
+ ironlake_cursor_wm_info
.guard_size
;
3423 if (cursora_wm
> ironlake_cursor_wm_info
.max_wm
)
3424 cursora_wm
= ironlake_cursor_wm_info
.max_wm
;
3426 reg_value
= I915_READ(WM0_PIPEA_ILK
);
3427 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3428 reg_value
|= (planea_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3429 (cursora_wm
& WM0_PIPE_CURSOR_MASK
);
3430 I915_WRITE(WM0_PIPEA_ILK
, reg_value
);
3431 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3432 "cursor: %d\n", planea_wm
, cursora_wm
);
3434 /* Calculate and update the watermark for plane B */
3436 entries_required
= ((planeb_clock
/ 1000) * pixel_size
*
3437 ILK_LP0_PLANE_LATENCY
) / 1000;
3438 entries_required
= DIV_ROUND_UP(entries_required
,
3439 ironlake_display_wm_info
.cacheline_size
);
3440 planeb_wm
= entries_required
+
3441 ironlake_display_wm_info
.guard_size
;
3443 if (planeb_wm
> (int)ironlake_display_wm_info
.max_wm
)
3444 planeb_wm
= ironlake_display_wm_info
.max_wm
;
3446 /* Use the large buffer method to calculate cursor watermark */
3447 line_time_us
= (planeb_htotal
* 1000) / planeb_clock
;
3449 /* Use ns/us then divide to preserve precision */
3450 line_count
= (ILK_LP0_CURSOR_LATENCY
/ line_time_us
+ 1000) / 1000;
3452 /* calculate the cursor watermark for cursor B */
3453 entries_required
= line_count
* 64 * pixel_size
;
3454 entries_required
= DIV_ROUND_UP(entries_required
,
3455 ironlake_cursor_wm_info
.cacheline_size
);
3456 cursorb_wm
= entries_required
+ ironlake_cursor_wm_info
.guard_size
;
3457 if (cursorb_wm
> ironlake_cursor_wm_info
.max_wm
)
3458 cursorb_wm
= ironlake_cursor_wm_info
.max_wm
;
3460 reg_value
= I915_READ(WM0_PIPEB_ILK
);
3461 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3462 reg_value
|= (planeb_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3463 (cursorb_wm
& WM0_PIPE_CURSOR_MASK
);
3464 I915_WRITE(WM0_PIPEB_ILK
, reg_value
);
3465 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3466 "cursor: %d\n", planeb_wm
, cursorb_wm
);
3470 * Calculate and update the self-refresh watermark only when one
3471 * display plane is used.
3473 if (!planea_clock
|| !planeb_clock
) {
3475 /* Read the self-refresh latency. The unit is 0.5us */
3476 int ilk_sr_latency
= I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
;
3478 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3479 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3481 /* Use ns/us then divide to preserve precision */
3482 line_count
= ((ilk_sr_latency
* 500) / line_time_us
+ 1000)
3485 /* calculate the self-refresh watermark for display plane */
3486 entries_required
= line_count
* sr_hdisplay
* pixel_size
;
3487 entries_required
= DIV_ROUND_UP(entries_required
,
3488 ironlake_display_srwm_info
.cacheline_size
);
3489 sr_wm
= entries_required
+
3490 ironlake_display_srwm_info
.guard_size
;
3492 /* calculate the self-refresh watermark for display cursor */
3493 entries_required
= line_count
* pixel_size
* 64;
3494 entries_required
= DIV_ROUND_UP(entries_required
,
3495 ironlake_cursor_srwm_info
.cacheline_size
);
3496 cursor_wm
= entries_required
+
3497 ironlake_cursor_srwm_info
.guard_size
;
3499 /* configure watermark and enable self-refresh */
3500 reg_value
= I915_READ(WM1_LP_ILK
);
3501 reg_value
&= ~(WM1_LP_LATENCY_MASK
| WM1_LP_SR_MASK
|
3502 WM1_LP_CURSOR_MASK
);
3503 reg_value
|= WM1_LP_SR_EN
|
3504 (ilk_sr_latency
<< WM1_LP_LATENCY_SHIFT
) |
3505 (sr_wm
<< WM1_LP_SR_SHIFT
) | cursor_wm
;
3507 I915_WRITE(WM1_LP_ILK
, reg_value
);
3508 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3509 "cursor %d\n", sr_wm
, cursor_wm
);
3512 /* Turn off self refresh if both pipes are enabled */
3513 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
3517 * intel_update_watermarks - update FIFO watermark values based on current modes
3519 * Calculate watermark values for the various WM regs based on current mode
3520 * and plane configuration.
3522 * There are several cases to deal with here:
3523 * - normal (i.e. non-self-refresh)
3524 * - self-refresh (SR) mode
3525 * - lines are large relative to FIFO size (buffer can hold up to 2)
3526 * - lines are small relative to FIFO size (buffer can hold more than 2
3527 * lines), so need to account for TLB latency
3529 * The normal calculation is:
3530 * watermark = dotclock * bytes per pixel * latency
3531 * where latency is platform & configuration dependent (we assume pessimal
3534 * The SR calculation is:
3535 * watermark = (trunc(latency/line time)+1) * surface width *
3538 * line time = htotal / dotclock
3539 * surface width = hdisplay for normal plane and 64 for cursor
3540 * and latency is assumed to be high, as above.
3542 * The final value programmed to the register should always be rounded up,
3543 * and include an extra 2 entries to account for clock crossings.
3545 * We don't use the sprite, so we can ignore that. And on Crestline we have
3546 * to set the non-SR watermarks to 8.
3548 static void intel_update_watermarks(struct drm_device
*dev
)
3550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3551 struct drm_crtc
*crtc
;
3552 int sr_hdisplay
= 0;
3553 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
3554 int enabled
= 0, pixel_size
= 0;
3557 if (!dev_priv
->display
.update_wm
)
3560 /* Get the clock config from both planes */
3561 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3562 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3563 if (intel_crtc
->dpms_mode
== DRM_MODE_DPMS_ON
) {
3565 if (intel_crtc
->plane
== 0) {
3566 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3567 intel_crtc
->pipe
, crtc
->mode
.clock
);
3568 planea_clock
= crtc
->mode
.clock
;
3570 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3571 intel_crtc
->pipe
, crtc
->mode
.clock
);
3572 planeb_clock
= crtc
->mode
.clock
;
3574 sr_hdisplay
= crtc
->mode
.hdisplay
;
3575 sr_clock
= crtc
->mode
.clock
;
3576 sr_htotal
= crtc
->mode
.htotal
;
3578 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3580 pixel_size
= 4; /* by default */
3587 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
3588 sr_hdisplay
, sr_htotal
, pixel_size
);
3591 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
3592 struct drm_display_mode
*mode
,
3593 struct drm_display_mode
*adjusted_mode
,
3595 struct drm_framebuffer
*old_fb
)
3597 struct drm_device
*dev
= crtc
->dev
;
3598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3599 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3600 int pipe
= intel_crtc
->pipe
;
3601 int plane
= intel_crtc
->plane
;
3602 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
3603 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3604 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
3605 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
3606 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
3607 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
3608 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
3609 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
3610 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
3611 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
3612 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
3613 int dspsize_reg
= (plane
== 0) ? DSPASIZE
: DSPBSIZE
;
3614 int dsppos_reg
= (plane
== 0) ? DSPAPOS
: DSPBPOS
;
3615 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
3616 int refclk
, num_connectors
= 0;
3617 intel_clock_t clock
, reduced_clock
;
3618 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
3619 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
3620 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
3621 struct intel_encoder
*has_edp_encoder
= NULL
;
3622 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3623 struct drm_encoder
*encoder
;
3624 const intel_limit_t
*limit
;
3626 struct fdi_m_n m_n
= {0};
3627 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
3628 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
3629 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
3630 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
3631 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
3632 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
3633 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
3634 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
3635 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
3636 int lvds_reg
= LVDS
;
3640 drm_vblank_pre_modeset(dev
, pipe
);
3642 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
3643 struct intel_encoder
*intel_encoder
;
3645 if (encoder
->crtc
!= crtc
)
3648 intel_encoder
= to_intel_encoder(encoder
);
3649 switch (intel_encoder
->type
) {
3650 case INTEL_OUTPUT_LVDS
:
3653 case INTEL_OUTPUT_SDVO
:
3654 case INTEL_OUTPUT_HDMI
:
3656 if (intel_encoder
->needs_tv_clock
)
3659 case INTEL_OUTPUT_DVO
:
3662 case INTEL_OUTPUT_TVOUT
:
3665 case INTEL_OUTPUT_ANALOG
:
3668 case INTEL_OUTPUT_DISPLAYPORT
:
3671 case INTEL_OUTPUT_EDP
:
3672 has_edp_encoder
= intel_encoder
;
3679 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2) {
3680 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3681 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3683 } else if (IS_I9XX(dev
)) {
3685 if (HAS_PCH_SPLIT(dev
))
3686 refclk
= 120000; /* 120Mhz refclk */
3693 * Returns a set of divisors for the desired target clock with the given
3694 * refclk, or FALSE. The returned values represent the clock equation:
3695 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3697 limit
= intel_limit(crtc
);
3698 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
3700 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3701 drm_vblank_post_modeset(dev
, pipe
);
3705 /* Ensure that the cursor is valid for the new mode before changing... */
3706 intel_crtc_update_cursor(crtc
);
3708 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
3709 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
3710 dev_priv
->lvds_downclock
,
3713 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
3715 * If the different P is found, it means that we can't
3716 * switch the display clock by using the FP0/FP1.
3717 * In such case we will disable the LVDS downclock
3720 DRM_DEBUG_KMS("Different P is found for "
3721 "LVDS clock/downclock\n");
3722 has_reduced_clock
= 0;
3725 /* SDVO TV has fixed PLL values depend on its clock range,
3726 this mirrors vbios setting. */
3727 if (is_sdvo
&& is_tv
) {
3728 if (adjusted_mode
->clock
>= 100000
3729 && adjusted_mode
->clock
< 140500) {
3735 } else if (adjusted_mode
->clock
>= 140500
3736 && adjusted_mode
->clock
<= 200000) {
3746 if (HAS_PCH_SPLIT(dev
)) {
3747 int lane
= 0, link_bw
, bpp
;
3748 /* eDP doesn't require FDI link, so just set DP M/N
3749 according to current link config */
3750 if (has_edp_encoder
) {
3751 target_clock
= mode
->clock
;
3752 intel_edp_link_config(has_edp_encoder
,
3755 /* DP over FDI requires target mode clock
3756 instead of link clock */
3758 target_clock
= mode
->clock
;
3760 target_clock
= adjusted_mode
->clock
;
3764 /* determine panel color depth */
3765 temp
= I915_READ(pipeconf_reg
);
3766 temp
&= ~PIPE_BPC_MASK
;
3768 int lvds_reg
= I915_READ(PCH_LVDS
);
3769 /* the BPC will be 6 if it is 18-bit LVDS panel */
3770 if ((lvds_reg
& LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3774 } else if (has_edp_encoder
|| (is_dp
&& intel_pch_has_edp(crtc
))) {
3775 switch (dev_priv
->edp_bpp
/3) {
3791 I915_WRITE(pipeconf_reg
, temp
);
3792 I915_READ(pipeconf_reg
);
3794 switch (temp
& PIPE_BPC_MASK
) {
3808 DRM_ERROR("unknown pipe bpc value\n");
3814 * Account for spread spectrum to avoid
3815 * oversubscribing the link. Max center spread
3816 * is 2.5%; use 5% for safety's sake.
3818 u32 bps
= target_clock
* bpp
* 21 / 20;
3819 lane
= bps
/ (link_bw
* 8) + 1;
3822 intel_crtc
->fdi_lanes
= lane
;
3824 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3827 /* Ironlake: try to setup display ref clock before DPLL
3828 * enabling. This is only under driver's control after
3829 * PCH B stepping, previous chipset stepping should be
3830 * ignoring this setting.
3832 if (HAS_PCH_SPLIT(dev
)) {
3833 temp
= I915_READ(PCH_DREF_CONTROL
);
3834 /* Always enable nonspread source */
3835 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3836 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3837 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3838 POSTING_READ(PCH_DREF_CONTROL
);
3840 temp
&= ~DREF_SSC_SOURCE_MASK
;
3841 temp
|= DREF_SSC_SOURCE_ENABLE
;
3842 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3843 POSTING_READ(PCH_DREF_CONTROL
);
3847 if (has_edp_encoder
) {
3848 if (dev_priv
->lvds_use_ssc
) {
3849 temp
|= DREF_SSC1_ENABLE
;
3850 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3851 POSTING_READ(PCH_DREF_CONTROL
);
3855 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3856 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3857 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3858 POSTING_READ(PCH_DREF_CONTROL
);
3860 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3861 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3862 POSTING_READ(PCH_DREF_CONTROL
);
3867 if (IS_PINEVIEW(dev
)) {
3868 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3869 if (has_reduced_clock
)
3870 fp2
= (1 << reduced_clock
.n
) << 16 |
3871 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3873 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3874 if (has_reduced_clock
)
3875 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3879 if (!HAS_PCH_SPLIT(dev
))
3880 dpll
= DPLL_VGA_MODE_DIS
;
3884 dpll
|= DPLLB_MODE_LVDS
;
3886 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3888 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
3889 if (pixel_multiplier
> 1) {
3890 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3891 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3892 else if (HAS_PCH_SPLIT(dev
))
3893 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3895 dpll
|= DPLL_DVO_HIGH_SPEED
;
3898 dpll
|= DPLL_DVO_HIGH_SPEED
;
3900 /* compute bitmask from p1 value */
3901 if (IS_PINEVIEW(dev
))
3902 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3904 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3906 if (HAS_PCH_SPLIT(dev
))
3907 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3908 if (IS_G4X(dev
) && has_reduced_clock
)
3909 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3913 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3916 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3919 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3922 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3925 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
))
3926 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3929 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3932 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3934 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3936 dpll
|= PLL_P2_DIVIDE_BY_4
;
3940 if (is_sdvo
&& is_tv
)
3941 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3943 /* XXX: just matching BIOS for now */
3944 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3946 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2)
3947 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3949 dpll
|= PLL_REF_INPUT_DREFCLK
;
3951 /* setup pipeconf */
3952 pipeconf
= I915_READ(pipeconf_reg
);
3954 /* Set up the display plane register */
3955 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3957 /* Ironlake's plane is forced to pipe, bit 24 is to
3958 enable color space conversion */
3959 if (!HAS_PCH_SPLIT(dev
)) {
3961 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3963 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3966 if (pipe
== 0 && !IS_I965G(dev
)) {
3967 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3970 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3974 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3975 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
3977 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
3980 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3981 pipeconf
|= PIPEACONF_ENABLE
;
3982 dpll
|= DPLL_VCO_ENABLE
;
3985 /* Disable the panel fitter if it was on our pipe */
3986 if (!HAS_PCH_SPLIT(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
3987 I915_WRITE(PFIT_CONTROL
, 0);
3989 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3990 drm_mode_debug_printmodeline(mode
);
3992 /* assign to Ironlake registers */
3993 if (HAS_PCH_SPLIT(dev
)) {
3994 fp_reg
= pch_fp_reg
;
3995 dpll_reg
= pch_dpll_reg
;
3998 if (!has_edp_encoder
) {
3999 I915_WRITE(fp_reg
, fp
);
4000 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
4001 I915_READ(dpll_reg
);
4005 /* enable transcoder DPLL */
4006 if (HAS_PCH_CPT(dev
)) {
4007 temp
= I915_READ(PCH_DPLL_SEL
);
4008 if (trans_dpll_sel
== 0)
4009 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
4011 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
4012 I915_WRITE(PCH_DPLL_SEL
, temp
);
4013 I915_READ(PCH_DPLL_SEL
);
4017 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4018 * This is an exception to the general rule that mode_set doesn't turn
4024 if (HAS_PCH_SPLIT(dev
))
4025 lvds_reg
= PCH_LVDS
;
4027 lvds
= I915_READ(lvds_reg
);
4028 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4030 if (HAS_PCH_CPT(dev
))
4031 lvds
|= PORT_TRANS_B_SEL_CPT
;
4033 lvds
|= LVDS_PIPEB_SELECT
;
4035 if (HAS_PCH_CPT(dev
))
4036 lvds
&= ~PORT_TRANS_SEL_MASK
;
4038 lvds
&= ~LVDS_PIPEB_SELECT
;
4040 /* set the corresponsding LVDS_BORDER bit */
4041 lvds
|= dev_priv
->lvds_border_bits
;
4042 /* Set the B0-B3 data pairs corresponding to whether we're going to
4043 * set the DPLLs for dual-channel mode or not.
4046 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4048 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4050 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4051 * appropriately here, but we need to look more thoroughly into how
4052 * panels behave in the two modes.
4054 /* set the dithering flag on non-PCH LVDS as needed */
4055 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
)) {
4056 if (dev_priv
->lvds_dither
)
4057 lvds
|= LVDS_ENABLE_DITHER
;
4059 lvds
&= ~LVDS_ENABLE_DITHER
;
4061 I915_WRITE(lvds_reg
, lvds
);
4062 I915_READ(lvds_reg
);
4065 /* set the dithering flag and clear for anything other than a panel. */
4066 if (HAS_PCH_SPLIT(dev
)) {
4067 pipeconf
&= ~PIPECONF_DITHER_EN
;
4068 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
4069 if (dev_priv
->lvds_dither
&& (is_lvds
|| has_edp_encoder
)) {
4070 pipeconf
|= PIPECONF_DITHER_EN
;
4071 pipeconf
|= PIPECONF_DITHER_TYPE_ST1
;
4076 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4077 else if (HAS_PCH_SPLIT(dev
)) {
4078 /* For non-DP output, clear any trans DP clock recovery setting.*/
4080 I915_WRITE(TRANSA_DATA_M1
, 0);
4081 I915_WRITE(TRANSA_DATA_N1
, 0);
4082 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
4083 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
4085 I915_WRITE(TRANSB_DATA_M1
, 0);
4086 I915_WRITE(TRANSB_DATA_N1
, 0);
4087 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
4088 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
4092 if (!has_edp_encoder
) {
4093 I915_WRITE(fp_reg
, fp
);
4094 I915_WRITE(dpll_reg
, dpll
);
4095 I915_READ(dpll_reg
);
4096 /* Wait for the clocks to stabilize. */
4099 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
)) {
4101 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4102 if (pixel_multiplier
> 1)
4103 pixel_multiplier
= (pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4105 pixel_multiplier
= 0;
4107 I915_WRITE(dpll_md_reg
,
4108 (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
4111 I915_WRITE(dpll_md_reg
, 0);
4113 /* write it again -- the BIOS does, after all */
4114 I915_WRITE(dpll_reg
, dpll
);
4116 I915_READ(dpll_reg
);
4117 /* Wait for the clocks to stabilize. */
4121 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4122 I915_WRITE(fp_reg
+ 4, fp2
);
4123 intel_crtc
->lowfreq_avail
= true;
4124 if (HAS_PIPE_CXSR(dev
)) {
4125 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4126 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4129 I915_WRITE(fp_reg
+ 4, fp
);
4130 intel_crtc
->lowfreq_avail
= false;
4131 if (HAS_PIPE_CXSR(dev
)) {
4132 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4133 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4137 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4138 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4139 /* the chip adds 2 halflines automatically */
4140 adjusted_mode
->crtc_vdisplay
-= 1;
4141 adjusted_mode
->crtc_vtotal
-= 1;
4142 adjusted_mode
->crtc_vblank_start
-= 1;
4143 adjusted_mode
->crtc_vblank_end
-= 1;
4144 adjusted_mode
->crtc_vsync_end
-= 1;
4145 adjusted_mode
->crtc_vsync_start
-= 1;
4147 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
4149 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
4150 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4151 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
4152 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4153 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
4154 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4155 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
4156 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4157 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
4158 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4159 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
4160 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4161 /* pipesrc and dspsize control the size that is scaled from, which should
4162 * always be the user's requested size.
4164 if (!HAS_PCH_SPLIT(dev
)) {
4165 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
4166 (mode
->hdisplay
- 1));
4167 I915_WRITE(dsppos_reg
, 0);
4169 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4171 if (HAS_PCH_SPLIT(dev
)) {
4172 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4173 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
4174 I915_WRITE(link_m1_reg
, m_n
.link_m
);
4175 I915_WRITE(link_n1_reg
, m_n
.link_n
);
4177 if (has_edp_encoder
) {
4178 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4180 /* enable FDI RX PLL too */
4181 temp
= I915_READ(fdi_rx_reg
);
4182 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
4183 I915_READ(fdi_rx_reg
);
4186 /* enable FDI TX PLL too */
4187 temp
= I915_READ(fdi_tx_reg
);
4188 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
4189 I915_READ(fdi_tx_reg
);
4191 /* enable FDI RX PCDCLK */
4192 temp
= I915_READ(fdi_rx_reg
);
4193 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
4194 I915_READ(fdi_rx_reg
);
4199 I915_WRITE(pipeconf_reg
, pipeconf
);
4200 I915_READ(pipeconf_reg
);
4202 intel_wait_for_vblank(dev
, pipe
);
4204 if (IS_IRONLAKE(dev
)) {
4205 /* enable address swizzle for tiling buffer */
4206 temp
= I915_READ(DISP_ARB_CTL
);
4207 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
4210 I915_WRITE(dspcntr_reg
, dspcntr
);
4212 /* Flush the plane changes */
4213 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4215 intel_update_watermarks(dev
);
4217 drm_vblank_post_modeset(dev
, pipe
);
4222 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4223 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4225 struct drm_device
*dev
= crtc
->dev
;
4226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4227 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4228 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
4231 /* The clocks have to be on to load the palette. */
4235 /* use legacy palette for Ironlake */
4236 if (HAS_PCH_SPLIT(dev
))
4237 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
4240 for (i
= 0; i
< 256; i
++) {
4241 I915_WRITE(palreg
+ 4 * i
,
4242 (intel_crtc
->lut_r
[i
] << 16) |
4243 (intel_crtc
->lut_g
[i
] << 8) |
4244 intel_crtc
->lut_b
[i
]);
4248 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4250 struct drm_device
*dev
= crtc
->dev
;
4251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4252 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4253 bool visible
= base
!= 0;
4256 if (intel_crtc
->cursor_visible
== visible
)
4259 cntl
= I915_READ(CURACNTR
);
4261 /* On these chipsets we can only modify the base whilst
4262 * the cursor is disabled.
4264 I915_WRITE(CURABASE
, base
);
4266 cntl
&= ~(CURSOR_FORMAT_MASK
);
4267 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4268 cntl
|= CURSOR_ENABLE
|
4269 CURSOR_GAMMA_ENABLE
|
4272 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
4273 I915_WRITE(CURACNTR
, cntl
);
4275 intel_crtc
->cursor_visible
= visible
;
4278 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4280 struct drm_device
*dev
= crtc
->dev
;
4281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4282 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4283 int pipe
= intel_crtc
->pipe
;
4284 bool visible
= base
!= 0;
4286 if (intel_crtc
->cursor_visible
!= visible
) {
4287 uint32_t cntl
= I915_READ(pipe
== 0 ? CURACNTR
: CURBCNTR
);
4289 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
4290 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
4291 cntl
|= pipe
<< 28; /* Connect to correct pipe */
4293 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
4294 cntl
|= CURSOR_MODE_DISABLE
;
4296 I915_WRITE(pipe
== 0 ? CURACNTR
: CURBCNTR
, cntl
);
4298 intel_crtc
->cursor_visible
= visible
;
4300 /* and commit changes on next vblank */
4301 I915_WRITE(pipe
== 0 ? CURABASE
: CURBBASE
, base
);
4304 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4305 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
)
4307 struct drm_device
*dev
= crtc
->dev
;
4308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4309 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4310 int pipe
= intel_crtc
->pipe
;
4311 int x
= intel_crtc
->cursor_x
;
4312 int y
= intel_crtc
->cursor_y
;
4318 if (intel_crtc
->cursor_on
&& crtc
->fb
) {
4319 base
= intel_crtc
->cursor_addr
;
4320 if (x
> (int) crtc
->fb
->width
)
4323 if (y
> (int) crtc
->fb
->height
)
4329 if (x
+ intel_crtc
->cursor_width
< 0)
4332 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
4335 pos
|= x
<< CURSOR_X_SHIFT
;
4338 if (y
+ intel_crtc
->cursor_height
< 0)
4341 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
4344 pos
|= y
<< CURSOR_Y_SHIFT
;
4346 visible
= base
!= 0;
4347 if (!visible
&& !intel_crtc
->cursor_visible
)
4350 I915_WRITE(pipe
== 0 ? CURAPOS
: CURBPOS
, pos
);
4351 if (IS_845G(dev
) || IS_I865G(dev
))
4352 i845_update_cursor(crtc
, base
);
4354 i9xx_update_cursor(crtc
, base
);
4357 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
4360 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
4361 struct drm_file
*file_priv
,
4363 uint32_t width
, uint32_t height
)
4365 struct drm_device
*dev
= crtc
->dev
;
4366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4368 struct drm_gem_object
*bo
;
4369 struct drm_i915_gem_object
*obj_priv
;
4373 DRM_DEBUG_KMS("\n");
4375 /* if we want to turn off the cursor ignore width and height */
4377 DRM_DEBUG_KMS("cursor off\n");
4380 mutex_lock(&dev
->struct_mutex
);
4384 /* Currently we only support 64x64 cursors */
4385 if (width
!= 64 || height
!= 64) {
4386 DRM_ERROR("we currently only support 64x64 cursors\n");
4390 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
4394 obj_priv
= to_intel_bo(bo
);
4396 if (bo
->size
< width
* height
* 4) {
4397 DRM_ERROR("buffer is to small\n");
4402 /* we only need to pin inside GTT if cursor is non-phy */
4403 mutex_lock(&dev
->struct_mutex
);
4404 if (!dev_priv
->info
->cursor_needs_physical
) {
4405 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
4407 DRM_ERROR("failed to pin cursor bo\n");
4411 ret
= i915_gem_object_set_to_gtt_domain(bo
, 0);
4413 DRM_ERROR("failed to move cursor bo into the GTT\n");
4417 addr
= obj_priv
->gtt_offset
;
4419 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
4420 ret
= i915_gem_attach_phys_object(dev
, bo
,
4421 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
4424 DRM_ERROR("failed to attach phys object\n");
4427 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
4431 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
4434 if (intel_crtc
->cursor_bo
) {
4435 if (dev_priv
->info
->cursor_needs_physical
) {
4436 if (intel_crtc
->cursor_bo
!= bo
)
4437 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
4439 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
4440 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
4443 mutex_unlock(&dev
->struct_mutex
);
4445 intel_crtc
->cursor_addr
= addr
;
4446 intel_crtc
->cursor_bo
= bo
;
4447 intel_crtc
->cursor_width
= width
;
4448 intel_crtc
->cursor_height
= height
;
4450 intel_crtc_update_cursor(crtc
);
4454 i915_gem_object_unpin(bo
);
4456 mutex_unlock(&dev
->struct_mutex
);
4458 drm_gem_object_unreference_unlocked(bo
);
4462 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
4464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4466 intel_crtc
->cursor_x
= x
;
4467 intel_crtc
->cursor_y
= y
;
4469 intel_crtc_update_cursor(crtc
);
4474 /** Sets the color ramps on behalf of RandR */
4475 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
4476 u16 blue
, int regno
)
4478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4480 intel_crtc
->lut_r
[regno
] = red
>> 8;
4481 intel_crtc
->lut_g
[regno
] = green
>> 8;
4482 intel_crtc
->lut_b
[regno
] = blue
>> 8;
4485 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4486 u16
*blue
, int regno
)
4488 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4490 *red
= intel_crtc
->lut_r
[regno
] << 8;
4491 *green
= intel_crtc
->lut_g
[regno
] << 8;
4492 *blue
= intel_crtc
->lut_b
[regno
] << 8;
4495 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4496 u16
*blue
, uint32_t start
, uint32_t size
)
4498 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
4499 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4501 for (i
= start
; i
< end
; i
++) {
4502 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
4503 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
4504 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
4507 intel_crtc_load_lut(crtc
);
4511 * Get a pipe with a simple mode set on it for doing load-based monitor
4514 * It will be up to the load-detect code to adjust the pipe as appropriate for
4515 * its requirements. The pipe will be connected to no other encoders.
4517 * Currently this code will only succeed if there is a pipe with no encoders
4518 * configured for it. In the future, it could choose to temporarily disable
4519 * some outputs to free up a pipe for its use.
4521 * \return crtc, or NULL if no pipes are available.
4524 /* VESA 640x480x72Hz mode to set on the pipe */
4525 static struct drm_display_mode load_detect_mode
= {
4526 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
4527 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
4530 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4531 struct drm_connector
*connector
,
4532 struct drm_display_mode
*mode
,
4535 struct intel_crtc
*intel_crtc
;
4536 struct drm_crtc
*possible_crtc
;
4537 struct drm_crtc
*supported_crtc
=NULL
;
4538 struct drm_encoder
*encoder
= &intel_encoder
->base
;
4539 struct drm_crtc
*crtc
= NULL
;
4540 struct drm_device
*dev
= encoder
->dev
;
4541 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4542 struct drm_crtc_helper_funcs
*crtc_funcs
;
4546 * Algorithm gets a little messy:
4547 * - if the connector already has an assigned crtc, use it (but make
4548 * sure it's on first)
4549 * - try to find the first unused crtc that can drive this connector,
4550 * and use that if we find one
4551 * - if there are no unused crtcs available, try to use the first
4552 * one we found that supports the connector
4555 /* See if we already have a CRTC for this connector */
4556 if (encoder
->crtc
) {
4557 crtc
= encoder
->crtc
;
4558 /* Make sure the crtc and connector are running */
4559 intel_crtc
= to_intel_crtc(crtc
);
4560 *dpms_mode
= intel_crtc
->dpms_mode
;
4561 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4562 crtc_funcs
= crtc
->helper_private
;
4563 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4564 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4569 /* Find an unused one (if possible) */
4570 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
4572 if (!(encoder
->possible_crtcs
& (1 << i
)))
4574 if (!possible_crtc
->enabled
) {
4575 crtc
= possible_crtc
;
4578 if (!supported_crtc
)
4579 supported_crtc
= possible_crtc
;
4583 * If we didn't find an unused CRTC, don't use any.
4589 encoder
->crtc
= crtc
;
4590 connector
->encoder
= encoder
;
4591 intel_encoder
->load_detect_temp
= true;
4593 intel_crtc
= to_intel_crtc(crtc
);
4594 *dpms_mode
= intel_crtc
->dpms_mode
;
4596 if (!crtc
->enabled
) {
4598 mode
= &load_detect_mode
;
4599 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
4601 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4602 crtc_funcs
= crtc
->helper_private
;
4603 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4606 /* Add this connector to the crtc */
4607 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
4608 encoder_funcs
->commit(encoder
);
4610 /* let the connector get through one full cycle before testing */
4611 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4616 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4617 struct drm_connector
*connector
, int dpms_mode
)
4619 struct drm_encoder
*encoder
= &intel_encoder
->base
;
4620 struct drm_device
*dev
= encoder
->dev
;
4621 struct drm_crtc
*crtc
= encoder
->crtc
;
4622 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4623 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
4625 if (intel_encoder
->load_detect_temp
) {
4626 encoder
->crtc
= NULL
;
4627 connector
->encoder
= NULL
;
4628 intel_encoder
->load_detect_temp
= false;
4629 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
4630 drm_helper_disable_unused_functions(dev
);
4633 /* Switch crtc and encoder back off if necessary */
4634 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
4635 if (encoder
->crtc
== crtc
)
4636 encoder_funcs
->dpms(encoder
, dpms_mode
);
4637 crtc_funcs
->dpms(crtc
, dpms_mode
);
4641 /* Returns the clock of the currently programmed mode of the given pipe. */
4642 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
4644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4645 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4646 int pipe
= intel_crtc
->pipe
;
4647 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
4649 intel_clock_t clock
;
4651 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
4652 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
4654 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
4656 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
4657 if (IS_PINEVIEW(dev
)) {
4658 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
4659 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4661 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
4662 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4666 if (IS_PINEVIEW(dev
))
4667 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
4668 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
4670 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
4671 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4673 switch (dpll
& DPLL_MODE_MASK
) {
4674 case DPLLB_MODE_DAC_SERIAL
:
4675 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
4678 case DPLLB_MODE_LVDS
:
4679 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
4683 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4684 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
4688 /* XXX: Handle the 100Mhz refclk */
4689 intel_clock(dev
, 96000, &clock
);
4691 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
4694 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
4695 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4698 if ((dpll
& PLL_REF_INPUT_MASK
) ==
4699 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
4700 /* XXX: might not be 66MHz */
4701 intel_clock(dev
, 66000, &clock
);
4703 intel_clock(dev
, 48000, &clock
);
4705 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
4708 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
4709 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
4711 if (dpll
& PLL_P2_DIVIDE_BY_4
)
4716 intel_clock(dev
, 48000, &clock
);
4720 /* XXX: It would be nice to validate the clocks, but we can't reuse
4721 * i830PllIsValid() because it relies on the xf86_config connector
4722 * configuration being accurate, which it isn't necessarily.
4728 /** Returns the currently programmed mode of the given pipe. */
4729 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
4730 struct drm_crtc
*crtc
)
4732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4734 int pipe
= intel_crtc
->pipe
;
4735 struct drm_display_mode
*mode
;
4736 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
4737 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
4738 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
4739 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
4741 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
4745 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
4746 mode
->hdisplay
= (htot
& 0xffff) + 1;
4747 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
4748 mode
->hsync_start
= (hsync
& 0xffff) + 1;
4749 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
4750 mode
->vdisplay
= (vtot
& 0xffff) + 1;
4751 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
4752 mode
->vsync_start
= (vsync
& 0xffff) + 1;
4753 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
4755 drm_mode_set_name(mode
);
4756 drm_mode_set_crtcinfo(mode
, 0);
4761 #define GPU_IDLE_TIMEOUT 500 /* ms */
4763 /* When this timer fires, we've been idle for awhile */
4764 static void intel_gpu_idle_timer(unsigned long arg
)
4766 struct drm_device
*dev
= (struct drm_device
*)arg
;
4767 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4769 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4771 dev_priv
->busy
= false;
4773 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4776 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4778 static void intel_crtc_idle_timer(unsigned long arg
)
4780 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
4781 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4782 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
4784 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4786 intel_crtc
->busy
= false;
4788 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4791 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
4793 struct drm_device
*dev
= crtc
->dev
;
4794 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4795 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4796 int pipe
= intel_crtc
->pipe
;
4797 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4798 int dpll
= I915_READ(dpll_reg
);
4800 if (HAS_PCH_SPLIT(dev
))
4803 if (!dev_priv
->lvds_downclock_avail
)
4806 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
4807 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4809 /* Unlock panel regs */
4810 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4813 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
4814 I915_WRITE(dpll_reg
, dpll
);
4815 dpll
= I915_READ(dpll_reg
);
4816 intel_wait_for_vblank(dev
, pipe
);
4817 dpll
= I915_READ(dpll_reg
);
4818 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
4819 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4821 /* ...and lock them again */
4822 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4825 /* Schedule downclock */
4826 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4827 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4830 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
4832 struct drm_device
*dev
= crtc
->dev
;
4833 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4834 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4835 int pipe
= intel_crtc
->pipe
;
4836 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4837 int dpll
= I915_READ(dpll_reg
);
4839 if (HAS_PCH_SPLIT(dev
))
4842 if (!dev_priv
->lvds_downclock_avail
)
4846 * Since this is called by a timer, we should never get here in
4849 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
4850 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4852 /* Unlock panel regs */
4853 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4856 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
4857 I915_WRITE(dpll_reg
, dpll
);
4858 dpll
= I915_READ(dpll_reg
);
4859 intel_wait_for_vblank(dev
, pipe
);
4860 dpll
= I915_READ(dpll_reg
);
4861 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
4862 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4864 /* ...and lock them again */
4865 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4871 * intel_idle_update - adjust clocks for idleness
4872 * @work: work struct
4874 * Either the GPU or display (or both) went idle. Check the busy status
4875 * here and adjust the CRTC and GPU clocks as necessary.
4877 static void intel_idle_update(struct work_struct
*work
)
4879 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4881 struct drm_device
*dev
= dev_priv
->dev
;
4882 struct drm_crtc
*crtc
;
4883 struct intel_crtc
*intel_crtc
;
4886 if (!i915_powersave
)
4889 mutex_lock(&dev
->struct_mutex
);
4891 i915_update_gfx_val(dev_priv
);
4893 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4894 /* Skip inactive CRTCs */
4899 intel_crtc
= to_intel_crtc(crtc
);
4900 if (!intel_crtc
->busy
)
4901 intel_decrease_pllclock(crtc
);
4904 if ((enabled
== 1) && (IS_I945G(dev
) || IS_I945GM(dev
))) {
4905 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4906 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4909 mutex_unlock(&dev
->struct_mutex
);
4913 * intel_mark_busy - mark the GPU and possibly the display busy
4915 * @obj: object we're operating on
4917 * Callers can use this function to indicate that the GPU is busy processing
4918 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4919 * buffer), we'll also mark the display as busy, so we know to increase its
4922 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4924 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4925 struct drm_crtc
*crtc
= NULL
;
4926 struct intel_framebuffer
*intel_fb
;
4927 struct intel_crtc
*intel_crtc
;
4929 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4932 if (!dev_priv
->busy
) {
4933 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4936 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4937 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4938 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4939 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4941 dev_priv
->busy
= true;
4943 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4944 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4946 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4950 intel_crtc
= to_intel_crtc(crtc
);
4951 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4952 if (intel_fb
->obj
== obj
) {
4953 if (!intel_crtc
->busy
) {
4954 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4957 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4958 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4959 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4960 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4962 /* Non-busy -> busy, upclock */
4963 intel_increase_pllclock(crtc
);
4964 intel_crtc
->busy
= true;
4966 /* Busy -> busy, put off timer */
4967 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4968 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4974 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4976 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4977 struct drm_device
*dev
= crtc
->dev
;
4978 struct intel_unpin_work
*work
;
4979 unsigned long flags
;
4981 spin_lock_irqsave(&dev
->event_lock
, flags
);
4982 work
= intel_crtc
->unpin_work
;
4983 intel_crtc
->unpin_work
= NULL
;
4984 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4987 cancel_work_sync(&work
->work
);
4991 drm_crtc_cleanup(crtc
);
4996 static void intel_unpin_work_fn(struct work_struct
*__work
)
4998 struct intel_unpin_work
*work
=
4999 container_of(__work
, struct intel_unpin_work
, work
);
5001 mutex_lock(&work
->dev
->struct_mutex
);
5002 i915_gem_object_unpin(work
->old_fb_obj
);
5003 drm_gem_object_unreference(work
->pending_flip_obj
);
5004 drm_gem_object_unreference(work
->old_fb_obj
);
5005 mutex_unlock(&work
->dev
->struct_mutex
);
5009 static void do_intel_finish_page_flip(struct drm_device
*dev
,
5010 struct drm_crtc
*crtc
)
5012 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5013 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5014 struct intel_unpin_work
*work
;
5015 struct drm_i915_gem_object
*obj_priv
;
5016 struct drm_pending_vblank_event
*e
;
5018 unsigned long flags
;
5020 /* Ignore early vblank irqs */
5021 if (intel_crtc
== NULL
)
5024 spin_lock_irqsave(&dev
->event_lock
, flags
);
5025 work
= intel_crtc
->unpin_work
;
5026 if (work
== NULL
|| !work
->pending
) {
5027 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5031 intel_crtc
->unpin_work
= NULL
;
5032 drm_vblank_put(dev
, intel_crtc
->pipe
);
5036 do_gettimeofday(&now
);
5037 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
5038 e
->event
.tv_sec
= now
.tv_sec
;
5039 e
->event
.tv_usec
= now
.tv_usec
;
5040 list_add_tail(&e
->base
.link
,
5041 &e
->base
.file_priv
->event_list
);
5042 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
5045 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5047 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
5049 /* Initial scanout buffer will have a 0 pending flip count */
5050 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
5051 atomic_dec_and_test(&obj_priv
->pending_flip
))
5052 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
5053 schedule_work(&work
->work
);
5055 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
5058 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
5060 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5061 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
5063 do_intel_finish_page_flip(dev
, crtc
);
5066 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
5068 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5069 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
5071 do_intel_finish_page_flip(dev
, crtc
);
5074 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
5076 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5077 struct intel_crtc
*intel_crtc
=
5078 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
5079 unsigned long flags
;
5081 spin_lock_irqsave(&dev
->event_lock
, flags
);
5082 if (intel_crtc
->unpin_work
) {
5083 if ((++intel_crtc
->unpin_work
->pending
) > 1)
5084 DRM_ERROR("Prepared flip multiple times\n");
5086 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5088 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5091 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
5092 struct drm_framebuffer
*fb
,
5093 struct drm_pending_vblank_event
*event
)
5095 struct drm_device
*dev
= crtc
->dev
;
5096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5097 struct intel_framebuffer
*intel_fb
;
5098 struct drm_i915_gem_object
*obj_priv
;
5099 struct drm_gem_object
*obj
;
5100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5101 struct intel_unpin_work
*work
;
5102 unsigned long flags
, offset
;
5103 int pipe
= intel_crtc
->pipe
;
5107 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
5111 work
->event
= event
;
5112 work
->dev
= crtc
->dev
;
5113 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5114 work
->old_fb_obj
= intel_fb
->obj
;
5115 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
5117 /* We borrow the event spin lock for protecting unpin_work */
5118 spin_lock_irqsave(&dev
->event_lock
, flags
);
5119 if (intel_crtc
->unpin_work
) {
5120 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5123 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5126 intel_crtc
->unpin_work
= work
;
5127 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5129 intel_fb
= to_intel_framebuffer(fb
);
5130 obj
= intel_fb
->obj
;
5132 mutex_lock(&dev
->struct_mutex
);
5133 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
5137 /* Reference the objects for the scheduled work. */
5138 drm_gem_object_reference(work
->old_fb_obj
);
5139 drm_gem_object_reference(obj
);
5142 ret
= i915_gem_object_flush_write_domain(obj
);
5146 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
5150 obj_priv
= to_intel_bo(obj
);
5151 atomic_inc(&obj_priv
->pending_flip
);
5152 work
->pending_flip_obj
= obj
;
5154 if (IS_GEN3(dev
) || IS_GEN2(dev
)) {
5157 if (intel_crtc
->plane
)
5158 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
5160 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
5163 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
5168 work
->enable_stall_check
= true;
5170 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5171 offset
= crtc
->y
* fb
->pitch
+ crtc
->x
* fb
->bits_per_pixel
/8;
5174 switch(INTEL_INFO(dev
)->gen
) {
5176 OUT_RING(MI_DISPLAY_FLIP
|
5177 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5178 OUT_RING(fb
->pitch
);
5179 OUT_RING(obj_priv
->gtt_offset
+ offset
);
5184 OUT_RING(MI_DISPLAY_FLIP_I915
|
5185 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5186 OUT_RING(fb
->pitch
);
5187 OUT_RING(obj_priv
->gtt_offset
+ offset
);
5193 /* i965+ uses the linear or tiled offsets from the
5194 * Display Registers (which do not change across a page-flip)
5195 * so we need only reprogram the base address.
5197 OUT_RING(MI_DISPLAY_FLIP
|
5198 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5199 OUT_RING(fb
->pitch
);
5200 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
5202 /* XXX Enabling the panel-fitter across page-flip is so far
5203 * untested on non-native modes, so ignore it for now.
5204 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5207 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5208 OUT_RING(pf
| pipesrc
);
5212 OUT_RING(MI_DISPLAY_FLIP
|
5213 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5214 OUT_RING(fb
->pitch
| obj_priv
->tiling_mode
);
5215 OUT_RING(obj_priv
->gtt_offset
);
5217 pf
= I915_READ(pipe
== 0 ? PFA_CTL_1
: PFB_CTL_1
) & PF_ENABLE
;
5218 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5219 OUT_RING(pf
| pipesrc
);
5224 mutex_unlock(&dev
->struct_mutex
);
5226 trace_i915_flip_request(intel_crtc
->plane
, obj
);
5231 drm_gem_object_unreference(work
->old_fb_obj
);
5232 drm_gem_object_unreference(obj
);
5234 mutex_unlock(&dev
->struct_mutex
);
5236 spin_lock_irqsave(&dev
->event_lock
, flags
);
5237 intel_crtc
->unpin_work
= NULL
;
5238 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5245 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
5246 .dpms
= intel_crtc_dpms
,
5247 .mode_fixup
= intel_crtc_mode_fixup
,
5248 .mode_set
= intel_crtc_mode_set
,
5249 .mode_set_base
= intel_pipe_set_base
,
5250 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
5251 .load_lut
= intel_crtc_load_lut
,
5254 static const struct drm_crtc_funcs intel_crtc_funcs
= {
5255 .cursor_set
= intel_crtc_cursor_set
,
5256 .cursor_move
= intel_crtc_cursor_move
,
5257 .gamma_set
= intel_crtc_gamma_set
,
5258 .set_config
= drm_crtc_helper_set_config
,
5259 .destroy
= intel_crtc_destroy
,
5260 .page_flip
= intel_crtc_page_flip
,
5264 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
5266 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5267 struct intel_crtc
*intel_crtc
;
5270 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
5271 if (intel_crtc
== NULL
)
5274 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
5276 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
5277 intel_crtc
->pipe
= pipe
;
5278 intel_crtc
->plane
= pipe
;
5279 for (i
= 0; i
< 256; i
++) {
5280 intel_crtc
->lut_r
[i
] = i
;
5281 intel_crtc
->lut_g
[i
] = i
;
5282 intel_crtc
->lut_b
[i
] = i
;
5285 /* Swap pipes & planes for FBC on pre-965 */
5286 intel_crtc
->pipe
= pipe
;
5287 intel_crtc
->plane
= pipe
;
5288 if (IS_MOBILE(dev
) && (IS_I9XX(dev
) && !IS_I965G(dev
))) {
5289 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5290 intel_crtc
->plane
= ((pipe
== 0) ? 1 : 0);
5293 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
5294 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
5295 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
5296 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
5298 intel_crtc
->cursor_addr
= 0;
5299 intel_crtc
->dpms_mode
= -1;
5301 if (HAS_PCH_SPLIT(dev
)) {
5302 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
5303 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
5305 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
5306 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
5309 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
5311 intel_crtc
->busy
= false;
5313 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
5314 (unsigned long)intel_crtc
);
5317 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
5318 struct drm_file
*file_priv
)
5320 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5321 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
5322 struct drm_mode_object
*drmmode_obj
;
5323 struct intel_crtc
*crtc
;
5326 DRM_ERROR("called with no initialization\n");
5330 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
5331 DRM_MODE_OBJECT_CRTC
);
5334 DRM_ERROR("no such CRTC id\n");
5338 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
5339 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
5344 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
5346 struct intel_encoder
*encoder
;
5350 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
5351 if (type_mask
& encoder
->clone_mask
)
5352 index_mask
|= (1 << entry
);
5359 static void intel_setup_outputs(struct drm_device
*dev
)
5361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5362 struct intel_encoder
*encoder
;
5363 bool dpd_is_edp
= false;
5365 if (IS_MOBILE(dev
) && !IS_I830(dev
))
5366 intel_lvds_init(dev
);
5368 if (HAS_PCH_SPLIT(dev
)) {
5369 dpd_is_edp
= intel_dpd_is_edp(dev
);
5371 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
5372 intel_dp_init(dev
, DP_A
);
5374 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5375 intel_dp_init(dev
, PCH_DP_D
);
5378 intel_crt_init(dev
);
5380 if (HAS_PCH_SPLIT(dev
)) {
5383 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
5384 /* PCH SDVOB multiplex with HDMIB */
5385 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
5387 intel_hdmi_init(dev
, HDMIB
);
5388 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
5389 intel_dp_init(dev
, PCH_DP_B
);
5392 if (I915_READ(HDMIC
) & PORT_DETECTED
)
5393 intel_hdmi_init(dev
, HDMIC
);
5395 if (I915_READ(HDMID
) & PORT_DETECTED
)
5396 intel_hdmi_init(dev
, HDMID
);
5398 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
5399 intel_dp_init(dev
, PCH_DP_C
);
5401 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5402 intel_dp_init(dev
, PCH_DP_D
);
5404 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
5407 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5408 DRM_DEBUG_KMS("probing SDVOB\n");
5409 found
= intel_sdvo_init(dev
, SDVOB
);
5410 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
5411 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5412 intel_hdmi_init(dev
, SDVOB
);
5415 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
5416 DRM_DEBUG_KMS("probing DP_B\n");
5417 intel_dp_init(dev
, DP_B
);
5421 /* Before G4X SDVOC doesn't have its own detect register */
5423 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5424 DRM_DEBUG_KMS("probing SDVOC\n");
5425 found
= intel_sdvo_init(dev
, SDVOC
);
5428 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
5430 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
5431 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5432 intel_hdmi_init(dev
, SDVOC
);
5434 if (SUPPORTS_INTEGRATED_DP(dev
)) {
5435 DRM_DEBUG_KMS("probing DP_C\n");
5436 intel_dp_init(dev
, DP_C
);
5440 if (SUPPORTS_INTEGRATED_DP(dev
) &&
5441 (I915_READ(DP_D
) & DP_DETECTED
)) {
5442 DRM_DEBUG_KMS("probing DP_D\n");
5443 intel_dp_init(dev
, DP_D
);
5445 } else if (IS_GEN2(dev
))
5446 intel_dvo_init(dev
);
5448 if (SUPPORTS_TV(dev
))
5451 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
5452 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
5453 encoder
->base
.possible_clones
=
5454 intel_encoder_clones(dev
, encoder
->clone_mask
);
5458 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
5460 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5462 drm_framebuffer_cleanup(fb
);
5463 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
5468 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
5469 struct drm_file
*file_priv
,
5470 unsigned int *handle
)
5472 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5473 struct drm_gem_object
*object
= intel_fb
->obj
;
5475 return drm_gem_handle_create(file_priv
, object
, handle
);
5478 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
5479 .destroy
= intel_user_framebuffer_destroy
,
5480 .create_handle
= intel_user_framebuffer_create_handle
,
5483 int intel_framebuffer_init(struct drm_device
*dev
,
5484 struct intel_framebuffer
*intel_fb
,
5485 struct drm_mode_fb_cmd
*mode_cmd
,
5486 struct drm_gem_object
*obj
)
5488 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5491 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
5494 if (mode_cmd
->pitch
& 63)
5497 switch (mode_cmd
->bpp
) {
5507 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
5509 DRM_ERROR("framebuffer init failed %d\n", ret
);
5513 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
5514 intel_fb
->obj
= obj
;
5518 static struct drm_framebuffer
*
5519 intel_user_framebuffer_create(struct drm_device
*dev
,
5520 struct drm_file
*filp
,
5521 struct drm_mode_fb_cmd
*mode_cmd
)
5523 struct drm_gem_object
*obj
;
5524 struct intel_framebuffer
*intel_fb
;
5527 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
5529 return ERR_PTR(-ENOENT
);
5531 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5533 return ERR_PTR(-ENOMEM
);
5535 ret
= intel_framebuffer_init(dev
, intel_fb
,
5538 drm_gem_object_unreference_unlocked(obj
);
5540 return ERR_PTR(ret
);
5543 return &intel_fb
->base
;
5546 static const struct drm_mode_config_funcs intel_mode_funcs
= {
5547 .fb_create
= intel_user_framebuffer_create
,
5548 .output_poll_changed
= intel_fb_output_poll_changed
,
5551 static struct drm_gem_object
*
5552 intel_alloc_context_page(struct drm_device
*dev
)
5554 struct drm_gem_object
*ctx
;
5557 ctx
= i915_gem_alloc_object(dev
, 4096);
5559 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5563 mutex_lock(&dev
->struct_mutex
);
5564 ret
= i915_gem_object_pin(ctx
, 4096);
5566 DRM_ERROR("failed to pin power context: %d\n", ret
);
5570 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
5572 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
5575 mutex_unlock(&dev
->struct_mutex
);
5580 i915_gem_object_unpin(ctx
);
5582 drm_gem_object_unreference(ctx
);
5583 mutex_unlock(&dev
->struct_mutex
);
5587 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
5589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5592 rgvswctl
= I915_READ16(MEMSWCTL
);
5593 if (rgvswctl
& MEMCTL_CMD_STS
) {
5594 DRM_DEBUG("gpu busy, RCS change rejected\n");
5595 return false; /* still busy with another command */
5598 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5599 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5600 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5601 POSTING_READ16(MEMSWCTL
);
5603 rgvswctl
|= MEMCTL_CMD_STS
;
5604 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5609 void ironlake_enable_drps(struct drm_device
*dev
)
5611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5612 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
5613 u8 fmax
, fmin
, fstart
, vstart
;
5615 /* 100ms RC evaluation intervals */
5616 I915_WRITE(RCUPEI
, 100000);
5617 I915_WRITE(RCDNEI
, 100000);
5619 /* Set max/min thresholds to 90ms and 80ms respectively */
5620 I915_WRITE(RCBMAXAVG
, 90000);
5621 I915_WRITE(RCBMINAVG
, 80000);
5623 I915_WRITE(MEMIHYST
, 1);
5625 /* Set up min, max, and cur for interrupt handling */
5626 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5627 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5628 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5629 MEMMODE_FSTART_SHIFT
;
5632 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
5635 dev_priv
->fmax
= fstart
; /* IPS callback will increase this */
5636 dev_priv
->fstart
= fstart
;
5638 dev_priv
->max_delay
= fmax
;
5639 dev_priv
->min_delay
= fmin
;
5640 dev_priv
->cur_delay
= fstart
;
5642 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax
, fmin
,
5645 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5648 * Interrupts will be enabled in ironlake_irq_postinstall
5651 I915_WRITE(VIDSTART
, vstart
);
5652 POSTING_READ(VIDSTART
);
5654 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5655 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5657 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
5658 DRM_ERROR("stuck trying to change perf mode\n");
5661 ironlake_set_drps(dev
, fstart
);
5663 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
5665 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
5666 dev_priv
->last_count2
= I915_READ(0x112f4);
5667 getrawmonotonic(&dev_priv
->last_time2
);
5670 void ironlake_disable_drps(struct drm_device
*dev
)
5672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5673 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
5675 /* Ack interrupts, disable EFC interrupt */
5676 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5677 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5678 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5679 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5680 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5682 /* Go back to the starting frequency */
5683 ironlake_set_drps(dev
, dev_priv
->fstart
);
5685 rgvswctl
|= MEMCTL_CMD_STS
;
5686 I915_WRITE(MEMSWCTL
, rgvswctl
);
5691 static unsigned long intel_pxfreq(u32 vidfreq
)
5694 int div
= (vidfreq
& 0x3f0000) >> 16;
5695 int post
= (vidfreq
& 0x3000) >> 12;
5696 int pre
= (vidfreq
& 0x7);
5701 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5706 void intel_init_emon(struct drm_device
*dev
)
5708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5713 /* Disable to program */
5717 /* Program energy weights for various events */
5718 I915_WRITE(SDEW
, 0x15040d00);
5719 I915_WRITE(CSIEW0
, 0x007f0000);
5720 I915_WRITE(CSIEW1
, 0x1e220004);
5721 I915_WRITE(CSIEW2
, 0x04000004);
5723 for (i
= 0; i
< 5; i
++)
5724 I915_WRITE(PEW
+ (i
* 4), 0);
5725 for (i
= 0; i
< 3; i
++)
5726 I915_WRITE(DEW
+ (i
* 4), 0);
5728 /* Program P-state weights to account for frequency power adjustment */
5729 for (i
= 0; i
< 16; i
++) {
5730 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5731 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5732 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5737 val
*= (freq
/ 1000);
5739 val
/= (127*127*900);
5741 DRM_ERROR("bad pxval: %ld\n", val
);
5744 /* Render standby states get 0 weight */
5748 for (i
= 0; i
< 4; i
++) {
5749 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5750 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5751 I915_WRITE(PXW
+ (i
* 4), val
);
5754 /* Adjust magic regs to magic values (more experimental results) */
5755 I915_WRITE(OGW0
, 0);
5756 I915_WRITE(OGW1
, 0);
5757 I915_WRITE(EG0
, 0x00007f00);
5758 I915_WRITE(EG1
, 0x0000000e);
5759 I915_WRITE(EG2
, 0x000e0000);
5760 I915_WRITE(EG3
, 0x68000300);
5761 I915_WRITE(EG4
, 0x42000000);
5762 I915_WRITE(EG5
, 0x00140031);
5766 for (i
= 0; i
< 8; i
++)
5767 I915_WRITE(PXWL
+ (i
* 4), 0);
5769 /* Enable PMON + select events */
5770 I915_WRITE(ECR
, 0x80000019);
5772 lcfuse
= I915_READ(LCFUSE02
);
5774 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5777 void intel_init_clock_gating(struct drm_device
*dev
)
5779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5782 * Disable clock gating reported to work incorrectly according to the
5783 * specs, but enable as much else as we can.
5785 if (HAS_PCH_SPLIT(dev
)) {
5786 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
5788 if (IS_IRONLAKE(dev
)) {
5789 /* Required for FBC */
5790 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
5791 /* Required for CxSR */
5792 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
5794 I915_WRITE(PCH_3DCGDIS0
,
5795 MARIUNIT_CLOCK_GATE_DISABLE
|
5796 SVSMUNIT_CLOCK_GATE_DISABLE
);
5799 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
5802 * According to the spec the following bits should be set in
5803 * order to enable memory self-refresh
5804 * The bit 22/21 of 0x42004
5805 * The bit 5 of 0x42020
5806 * The bit 15 of 0x45000
5808 if (IS_IRONLAKE(dev
)) {
5809 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5810 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5811 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5812 I915_WRITE(ILK_DSPCLK_GATE
,
5813 (I915_READ(ILK_DSPCLK_GATE
) |
5814 ILK_DPARB_CLK_GATE
));
5815 I915_WRITE(DISP_ARB_CTL
,
5816 (I915_READ(DISP_ARB_CTL
) |
5820 * Based on the document from hardware guys the following bits
5821 * should be set unconditionally in order to enable FBC.
5822 * The bit 22 of 0x42000
5823 * The bit 22 of 0x42004
5824 * The bit 7,8,9 of 0x42020.
5826 if (IS_IRONLAKE_M(dev
)) {
5827 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5828 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5830 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5831 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5833 I915_WRITE(ILK_DSPCLK_GATE
,
5834 I915_READ(ILK_DSPCLK_GATE
) |
5840 } else if (IS_G4X(dev
)) {
5841 uint32_t dspclk_gate
;
5842 I915_WRITE(RENCLK_GATE_D1
, 0);
5843 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5844 GS_UNIT_CLOCK_GATE_DISABLE
|
5845 CL_UNIT_CLOCK_GATE_DISABLE
);
5846 I915_WRITE(RAMCLK_GATE_D
, 0);
5847 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5848 OVRUNIT_CLOCK_GATE_DISABLE
|
5849 OVCUNIT_CLOCK_GATE_DISABLE
;
5851 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5852 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5853 } else if (IS_I965GM(dev
)) {
5854 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5855 I915_WRITE(RENCLK_GATE_D2
, 0);
5856 I915_WRITE(DSPCLK_GATE_D
, 0);
5857 I915_WRITE(RAMCLK_GATE_D
, 0);
5858 I915_WRITE16(DEUC
, 0);
5859 } else if (IS_I965G(dev
)) {
5860 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5861 I965_RCC_CLOCK_GATE_DISABLE
|
5862 I965_RCPB_CLOCK_GATE_DISABLE
|
5863 I965_ISC_CLOCK_GATE_DISABLE
|
5864 I965_FBC_CLOCK_GATE_DISABLE
);
5865 I915_WRITE(RENCLK_GATE_D2
, 0);
5866 } else if (IS_I9XX(dev
)) {
5867 u32 dstate
= I915_READ(D_STATE
);
5869 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5870 DSTATE_DOT_CLOCK_GATING
;
5871 I915_WRITE(D_STATE
, dstate
);
5872 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
5873 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5874 } else if (IS_I830(dev
)) {
5875 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5879 * GPU can automatically power down the render unit if given a page
5882 if (IS_IRONLAKE_M(dev
)) {
5883 if (dev_priv
->renderctx
== NULL
)
5884 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
5885 if (dev_priv
->renderctx
) {
5886 struct drm_i915_gem_object
*obj_priv
;
5887 obj_priv
= to_intel_bo(dev_priv
->renderctx
);
5890 OUT_RING(MI_SET_CONTEXT
);
5891 OUT_RING(obj_priv
->gtt_offset
|
5893 MI_SAVE_EXT_STATE_EN
|
5894 MI_RESTORE_EXT_STATE_EN
|
5895 MI_RESTORE_INHIBIT
);
5901 DRM_DEBUG_KMS("Failed to allocate render context."
5905 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
5906 struct drm_i915_gem_object
*obj_priv
= NULL
;
5908 if (dev_priv
->pwrctx
) {
5909 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5911 struct drm_gem_object
*pwrctx
;
5913 pwrctx
= intel_alloc_context_page(dev
);
5915 dev_priv
->pwrctx
= pwrctx
;
5916 obj_priv
= to_intel_bo(pwrctx
);
5921 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
5922 I915_WRITE(MCHBAR_RENDER_STANDBY
,
5923 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
5928 /* Set up chip specific display functions */
5929 static void intel_init_display(struct drm_device
*dev
)
5931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5933 /* We always want a DPMS function */
5934 if (HAS_PCH_SPLIT(dev
))
5935 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
5937 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
5939 if (I915_HAS_FBC(dev
)) {
5940 if (IS_IRONLAKE_M(dev
)) {
5941 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5942 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
5943 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5944 } else if (IS_GM45(dev
)) {
5945 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5946 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5947 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5948 } else if (IS_I965GM(dev
)) {
5949 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5950 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5951 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5953 /* 855GM needs testing */
5956 /* Returns the core display clock speed */
5957 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
5958 dev_priv
->display
.get_display_clock_speed
=
5959 i945_get_display_clock_speed
;
5960 else if (IS_I915G(dev
))
5961 dev_priv
->display
.get_display_clock_speed
=
5962 i915_get_display_clock_speed
;
5963 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
5964 dev_priv
->display
.get_display_clock_speed
=
5965 i9xx_misc_get_display_clock_speed
;
5966 else if (IS_I915GM(dev
))
5967 dev_priv
->display
.get_display_clock_speed
=
5968 i915gm_get_display_clock_speed
;
5969 else if (IS_I865G(dev
))
5970 dev_priv
->display
.get_display_clock_speed
=
5971 i865_get_display_clock_speed
;
5972 else if (IS_I85X(dev
))
5973 dev_priv
->display
.get_display_clock_speed
=
5974 i855_get_display_clock_speed
;
5976 dev_priv
->display
.get_display_clock_speed
=
5977 i830_get_display_clock_speed
;
5979 /* For FIFO watermark updates */
5980 if (HAS_PCH_SPLIT(dev
)) {
5981 if (IS_IRONLAKE(dev
)) {
5982 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5983 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5985 DRM_DEBUG_KMS("Failed to get proper latency. "
5987 dev_priv
->display
.update_wm
= NULL
;
5990 dev_priv
->display
.update_wm
= NULL
;
5991 } else if (IS_PINEVIEW(dev
)) {
5992 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5995 dev_priv
->mem_freq
)) {
5996 DRM_INFO("failed to find known CxSR latency "
5997 "(found ddr%s fsb freq %d, mem freq %d), "
5999 (dev_priv
->is_ddr3
== 1) ? "3": "2",
6000 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
6001 /* Disable CxSR and never update its watermark again */
6002 pineview_disable_cxsr(dev
);
6003 dev_priv
->display
.update_wm
= NULL
;
6005 dev_priv
->display
.update_wm
= pineview_update_wm
;
6006 } else if (IS_G4X(dev
))
6007 dev_priv
->display
.update_wm
= g4x_update_wm
;
6008 else if (IS_I965G(dev
))
6009 dev_priv
->display
.update_wm
= i965_update_wm
;
6010 else if (IS_I9XX(dev
)) {
6011 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6012 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6013 } else if (IS_I85X(dev
)) {
6014 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6015 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
6017 dev_priv
->display
.update_wm
= i830_update_wm
;
6019 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6021 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6026 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6027 * resume, or other times. This quirk makes sure that's the case for
6030 static void quirk_pipea_force (struct drm_device
*dev
)
6032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6034 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
6035 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6038 struct intel_quirk
{
6040 int subsystem_vendor
;
6041 int subsystem_device
;
6042 void (*hook
)(struct drm_device
*dev
);
6045 struct intel_quirk intel_quirks
[] = {
6046 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6047 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force
},
6048 /* HP Mini needs pipe A force quirk (LP: #322104) */
6049 { 0x27ae,0x103c, 0x361a, quirk_pipea_force
},
6051 /* Thinkpad R31 needs pipe A force quirk */
6052 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
6053 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6054 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
6056 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6057 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
6058 /* ThinkPad X40 needs pipe A force quirk */
6060 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6061 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
6063 /* 855 & before need to leave pipe A & dpll A up */
6064 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
6065 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
6068 static void intel_init_quirks(struct drm_device
*dev
)
6070 struct pci_dev
*d
= dev
->pdev
;
6073 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
6074 struct intel_quirk
*q
= &intel_quirks
[i
];
6076 if (d
->device
== q
->device
&&
6077 (d
->subsystem_vendor
== q
->subsystem_vendor
||
6078 q
->subsystem_vendor
== PCI_ANY_ID
) &&
6079 (d
->subsystem_device
== q
->subsystem_device
||
6080 q
->subsystem_device
== PCI_ANY_ID
))
6085 /* Disable the VGA plane that we never use */
6086 static void i915_disable_vga(struct drm_device
*dev
)
6088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6092 if (HAS_PCH_SPLIT(dev
))
6093 vga_reg
= CPU_VGACNTRL
;
6097 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6098 outb(1, VGA_SR_INDEX
);
6099 sr1
= inb(VGA_SR_DATA
);
6100 outb(sr1
| 1<<5, VGA_SR_DATA
);
6101 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6104 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
6105 POSTING_READ(vga_reg
);
6108 void intel_modeset_init(struct drm_device
*dev
)
6110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6113 drm_mode_config_init(dev
);
6115 dev
->mode_config
.min_width
= 0;
6116 dev
->mode_config
.min_height
= 0;
6118 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
6120 intel_init_quirks(dev
);
6122 intel_init_display(dev
);
6124 if (IS_I965G(dev
)) {
6125 dev
->mode_config
.max_width
= 8192;
6126 dev
->mode_config
.max_height
= 8192;
6127 } else if (IS_I9XX(dev
)) {
6128 dev
->mode_config
.max_width
= 4096;
6129 dev
->mode_config
.max_height
= 4096;
6131 dev
->mode_config
.max_width
= 2048;
6132 dev
->mode_config
.max_height
= 2048;
6135 /* set memory base */
6137 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
6139 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
6141 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
6142 dev_priv
->num_pipe
= 2;
6144 dev_priv
->num_pipe
= 1;
6145 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6146 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
6148 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
6149 intel_crtc_init(dev
, i
);
6152 intel_setup_outputs(dev
);
6154 intel_init_clock_gating(dev
);
6156 /* Just disable it once at startup */
6157 i915_disable_vga(dev
);
6159 if (IS_IRONLAKE_M(dev
)) {
6160 ironlake_enable_drps(dev
);
6161 intel_init_emon(dev
);
6164 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
6165 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
6166 (unsigned long)dev
);
6168 intel_setup_overlay(dev
);
6171 void intel_modeset_cleanup(struct drm_device
*dev
)
6173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6174 struct drm_crtc
*crtc
;
6175 struct intel_crtc
*intel_crtc
;
6177 mutex_lock(&dev
->struct_mutex
);
6179 drm_kms_helper_poll_fini(dev
);
6180 intel_fbdev_fini(dev
);
6182 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6183 /* Skip inactive CRTCs */
6187 intel_crtc
= to_intel_crtc(crtc
);
6188 intel_increase_pllclock(crtc
);
6191 if (dev_priv
->display
.disable_fbc
)
6192 dev_priv
->display
.disable_fbc(dev
);
6194 if (dev_priv
->renderctx
) {
6195 struct drm_i915_gem_object
*obj_priv
;
6197 obj_priv
= to_intel_bo(dev_priv
->renderctx
);
6198 I915_WRITE(CCID
, obj_priv
->gtt_offset
&~ CCID_EN
);
6200 i915_gem_object_unpin(dev_priv
->renderctx
);
6201 drm_gem_object_unreference(dev_priv
->renderctx
);
6204 if (dev_priv
->pwrctx
) {
6205 struct drm_i915_gem_object
*obj_priv
;
6207 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
6208 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
6210 i915_gem_object_unpin(dev_priv
->pwrctx
);
6211 drm_gem_object_unreference(dev_priv
->pwrctx
);
6214 if (IS_IRONLAKE_M(dev
))
6215 ironlake_disable_drps(dev
);
6217 mutex_unlock(&dev
->struct_mutex
);
6219 /* Disable the irq before mode object teardown, for the irq might
6220 * enqueue unpin/hotplug work. */
6221 drm_irq_uninstall(dev
);
6222 cancel_work_sync(&dev_priv
->hotplug_work
);
6224 /* Shut off idle work before the crtcs get freed. */
6225 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6226 intel_crtc
= to_intel_crtc(crtc
);
6227 del_timer_sync(&intel_crtc
->idle_timer
);
6229 del_timer_sync(&dev_priv
->idle_timer
);
6230 cancel_work_sync(&dev_priv
->idle_work
);
6232 drm_mode_config_cleanup(dev
);
6236 * Return which encoder is currently attached for connector.
6238 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
6240 return &intel_attached_encoder(connector
)->base
;
6243 void intel_connector_attach_encoder(struct intel_connector
*connector
,
6244 struct intel_encoder
*encoder
)
6246 connector
->encoder
= encoder
;
6247 drm_mode_connector_attach_encoder(&connector
->base
,
6252 * set vga decode state - true == enable VGA decode
6254 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
6256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6259 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
6261 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
6263 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
6264 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);