Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / dma / amba-pl08x.c
blobe6d7228b1479a6d462b1e19c323541fe5a767a7f
1 /*
2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
23 * called COPYING.
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
29 * channel.
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
41 * Until no data left
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
44 * Clear burst request
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
62 * are ignored.
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
74 * Global TODO:
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/delay.h>
83 #include <linux/dmapool.h>
84 #include <linux/dmaengine.h>
85 #include <linux/amba/bus.h>
86 #include <linux/amba/pl08x.h>
87 #include <linux/debugfs.h>
88 #include <linux/seq_file.h>
90 #include <asm/hardware/pl080.h>
92 #define DRIVER_NAME "pl08xdmac"
94 /**
95 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters or not.
99 struct vendor_data {
100 u8 channels;
101 bool dualmaster;
105 * PL08X private data structures
106 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
107 * start & end do not - their bus bit info is in cctl. Also note that these
108 * are fixed 32-bit quantities.
110 struct pl08x_lli {
111 u32 src;
112 u32 dst;
113 u32 lli;
114 u32 cctl;
118 * struct pl08x_driver_data - the local state holder for the PL08x
119 * @slave: slave engine for this instance
120 * @memcpy: memcpy engine for this instance
121 * @base: virtual memory base (remapped) for the PL08x
122 * @adev: the corresponding AMBA (PrimeCell) bus entry
123 * @vd: vendor data for this PL08x variant
124 * @pd: platform data passed in from the platform/machine
125 * @phy_chans: array of data for the physical channels
126 * @pool: a pool for the LLI descriptors
127 * @pool_ctr: counter of LLIs in the pool
128 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
129 * @mem_buses: set to indicate memory transfers on AHB2.
130 * @lock: a spinlock for this struct
132 struct pl08x_driver_data {
133 struct dma_device slave;
134 struct dma_device memcpy;
135 void __iomem *base;
136 struct amba_device *adev;
137 const struct vendor_data *vd;
138 struct pl08x_platform_data *pd;
139 struct pl08x_phy_chan *phy_chans;
140 struct dma_pool *pool;
141 int pool_ctr;
142 u8 lli_buses;
143 u8 mem_buses;
144 spinlock_t lock;
148 * PL08X specific defines
152 * Memory boundaries: the manual for PL08x says that the controller
153 * cannot read past a 1KiB boundary, so these defines are used to
154 * create transfer LLIs that do not cross such boundaries.
156 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
157 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
159 /* Minimum period between work queue runs */
160 #define PL08X_WQ_PERIODMIN 20
162 /* Size (bytes) of each LLI buffer allocated for one transfer */
163 # define PL08X_LLI_TSFR_SIZE 0x2000
165 /* Maximum times we call dma_pool_alloc on this pool without freeing */
166 #define PL08X_MAX_ALLOCS 0x40
167 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
168 #define PL08X_ALIGN 8
170 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
172 return container_of(chan, struct pl08x_dma_chan, chan);
175 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
177 return container_of(tx, struct pl08x_txd, tx);
181 * Physical channel handling
184 /* Whether a certain channel is busy or not */
185 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
187 unsigned int val;
189 val = readl(ch->base + PL080_CH_CONFIG);
190 return val & PL080_CONFIG_ACTIVE;
194 * Set the initial DMA register values i.e. those for the first LLI
195 * The next LLI pointer and the configuration interrupt bit have
196 * been set when the LLIs were constructed. Poke them into the hardware
197 * and start the transfer.
199 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
200 struct pl08x_txd *txd)
202 struct pl08x_driver_data *pl08x = plchan->host;
203 struct pl08x_phy_chan *phychan = plchan->phychan;
204 struct pl08x_lli *lli = &txd->llis_va[0];
205 u32 val;
207 plchan->at = txd;
209 /* Wait for channel inactive */
210 while (pl08x_phy_channel_busy(phychan))
211 cpu_relax();
213 dev_vdbg(&pl08x->adev->dev,
214 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
215 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
216 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
217 txd->ccfg);
219 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
220 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
221 writel(lli->lli, phychan->base + PL080_CH_LLI);
222 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
223 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
225 /* Enable the DMA channel */
226 /* Do not access config register until channel shows as disabled */
227 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
228 cpu_relax();
230 /* Do not access config register until channel shows as inactive */
231 val = readl(phychan->base + PL080_CH_CONFIG);
232 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
233 val = readl(phychan->base + PL080_CH_CONFIG);
235 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
239 * Pause the channel by setting the HALT bit.
241 * For M->P transfers, pause the DMAC first and then stop the peripheral -
242 * the FIFO can only drain if the peripheral is still requesting data.
243 * (note: this can still timeout if the DMAC FIFO never drains of data.)
245 * For P->M transfers, disable the peripheral first to stop it filling
246 * the DMAC FIFO, and then pause the DMAC.
248 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
250 u32 val;
251 int timeout;
253 /* Set the HALT bit and wait for the FIFO to drain */
254 val = readl(ch->base + PL080_CH_CONFIG);
255 val |= PL080_CONFIG_HALT;
256 writel(val, ch->base + PL080_CH_CONFIG);
258 /* Wait for channel inactive */
259 for (timeout = 1000; timeout; timeout--) {
260 if (!pl08x_phy_channel_busy(ch))
261 break;
262 udelay(1);
264 if (pl08x_phy_channel_busy(ch))
265 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
268 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
270 u32 val;
272 /* Clear the HALT bit */
273 val = readl(ch->base + PL080_CH_CONFIG);
274 val &= ~PL080_CONFIG_HALT;
275 writel(val, ch->base + PL080_CH_CONFIG);
280 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
281 * clears any pending interrupt status. This should not be used for
282 * an on-going transfer, but as a method of shutting down a channel
283 * (eg, when it's no longer used) or terminating a transfer.
285 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
286 struct pl08x_phy_chan *ch)
288 u32 val = readl(ch->base + PL080_CH_CONFIG);
290 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
291 PL080_CONFIG_TC_IRQ_MASK);
293 writel(val, ch->base + PL080_CH_CONFIG);
295 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
296 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
299 static inline u32 get_bytes_in_cctl(u32 cctl)
301 /* The source width defines the number of bytes */
302 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
304 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
305 case PL080_WIDTH_8BIT:
306 break;
307 case PL080_WIDTH_16BIT:
308 bytes *= 2;
309 break;
310 case PL080_WIDTH_32BIT:
311 bytes *= 4;
312 break;
314 return bytes;
317 /* The channel should be paused when calling this */
318 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
320 struct pl08x_phy_chan *ch;
321 struct pl08x_txd *txd;
322 unsigned long flags;
323 size_t bytes = 0;
325 spin_lock_irqsave(&plchan->lock, flags);
326 ch = plchan->phychan;
327 txd = plchan->at;
330 * Follow the LLIs to get the number of remaining
331 * bytes in the currently active transaction.
333 if (ch && txd) {
334 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
336 /* First get the remaining bytes in the active transfer */
337 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
339 if (clli) {
340 struct pl08x_lli *llis_va = txd->llis_va;
341 dma_addr_t llis_bus = txd->llis_bus;
342 int index;
344 BUG_ON(clli < llis_bus || clli >= llis_bus +
345 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
348 * Locate the next LLI - as this is an array,
349 * it's simple maths to find.
351 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
353 for (; index < MAX_NUM_TSFR_LLIS; index++) {
354 bytes += get_bytes_in_cctl(llis_va[index].cctl);
357 * A LLI pointer of 0 terminates the LLI list
359 if (!llis_va[index].lli)
360 break;
365 /* Sum up all queued transactions */
366 if (!list_empty(&plchan->pend_list)) {
367 struct pl08x_txd *txdi;
368 list_for_each_entry(txdi, &plchan->pend_list, node) {
369 bytes += txdi->len;
373 spin_unlock_irqrestore(&plchan->lock, flags);
375 return bytes;
379 * Allocate a physical channel for a virtual channel
381 * Try to locate a physical channel to be used for this transfer. If all
382 * are taken return NULL and the requester will have to cope by using
383 * some fallback PIO mode or retrying later.
385 static struct pl08x_phy_chan *
386 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
387 struct pl08x_dma_chan *virt_chan)
389 struct pl08x_phy_chan *ch = NULL;
390 unsigned long flags;
391 int i;
393 for (i = 0; i < pl08x->vd->channels; i++) {
394 ch = &pl08x->phy_chans[i];
396 spin_lock_irqsave(&ch->lock, flags);
398 if (!ch->serving) {
399 ch->serving = virt_chan;
400 ch->signal = -1;
401 spin_unlock_irqrestore(&ch->lock, flags);
402 break;
405 spin_unlock_irqrestore(&ch->lock, flags);
408 if (i == pl08x->vd->channels) {
409 /* No physical channel available, cope with it */
410 return NULL;
413 return ch;
416 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
417 struct pl08x_phy_chan *ch)
419 unsigned long flags;
421 spin_lock_irqsave(&ch->lock, flags);
423 /* Stop the channel and clear its interrupts */
424 pl08x_terminate_phy_chan(pl08x, ch);
426 /* Mark it as free */
427 ch->serving = NULL;
428 spin_unlock_irqrestore(&ch->lock, flags);
432 * LLI handling
435 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
437 switch (coded) {
438 case PL080_WIDTH_8BIT:
439 return 1;
440 case PL080_WIDTH_16BIT:
441 return 2;
442 case PL080_WIDTH_32BIT:
443 return 4;
444 default:
445 break;
447 BUG();
448 return 0;
451 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
452 size_t tsize)
454 u32 retbits = cctl;
456 /* Remove all src, dst and transfer size bits */
457 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
458 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
459 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
461 /* Then set the bits according to the parameters */
462 switch (srcwidth) {
463 case 1:
464 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
465 break;
466 case 2:
467 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
468 break;
469 case 4:
470 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
471 break;
472 default:
473 BUG();
474 break;
477 switch (dstwidth) {
478 case 1:
479 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
480 break;
481 case 2:
482 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
483 break;
484 case 4:
485 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
486 break;
487 default:
488 BUG();
489 break;
492 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
493 return retbits;
496 struct pl08x_lli_build_data {
497 struct pl08x_txd *txd;
498 struct pl08x_driver_data *pl08x;
499 struct pl08x_bus_data srcbus;
500 struct pl08x_bus_data dstbus;
501 size_t remainder;
505 * Autoselect a master bus to use for the transfer this prefers the
506 * destination bus if both available if fixed address on one bus the
507 * other will be chosen
509 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
510 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
512 if (!(cctl & PL080_CONTROL_DST_INCR)) {
513 *mbus = &bd->srcbus;
514 *sbus = &bd->dstbus;
515 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
516 *mbus = &bd->dstbus;
517 *sbus = &bd->srcbus;
518 } else {
519 if (bd->dstbus.buswidth == 4) {
520 *mbus = &bd->dstbus;
521 *sbus = &bd->srcbus;
522 } else if (bd->srcbus.buswidth == 4) {
523 *mbus = &bd->srcbus;
524 *sbus = &bd->dstbus;
525 } else if (bd->dstbus.buswidth == 2) {
526 *mbus = &bd->dstbus;
527 *sbus = &bd->srcbus;
528 } else if (bd->srcbus.buswidth == 2) {
529 *mbus = &bd->srcbus;
530 *sbus = &bd->dstbus;
531 } else {
532 /* bd->srcbus.buswidth == 1 */
533 *mbus = &bd->dstbus;
534 *sbus = &bd->srcbus;
540 * Fills in one LLI for a certain transfer descriptor and advance the counter
542 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
543 int num_llis, int len, u32 cctl)
545 struct pl08x_lli *llis_va = bd->txd->llis_va;
546 dma_addr_t llis_bus = bd->txd->llis_bus;
548 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
550 llis_va[num_llis].cctl = cctl;
551 llis_va[num_llis].src = bd->srcbus.addr;
552 llis_va[num_llis].dst = bd->dstbus.addr;
553 llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
554 if (bd->pl08x->lli_buses & PL08X_AHB2)
555 llis_va[num_llis].lli |= PL080_LLI_LM_AHB2;
557 if (cctl & PL080_CONTROL_SRC_INCR)
558 bd->srcbus.addr += len;
559 if (cctl & PL080_CONTROL_DST_INCR)
560 bd->dstbus.addr += len;
562 BUG_ON(bd->remainder < len);
564 bd->remainder -= len;
568 * Return number of bytes to fill to boundary, or len.
569 * This calculation works for any value of addr.
571 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
573 size_t boundary_len = PL08X_BOUNDARY_SIZE -
574 (addr & (PL08X_BOUNDARY_SIZE - 1));
576 return min(boundary_len, len);
580 * This fills in the table of LLIs for the transfer descriptor
581 * Note that we assume we never have to change the burst sizes
582 * Return 0 for error
584 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
585 struct pl08x_txd *txd)
587 struct pl08x_bus_data *mbus, *sbus;
588 struct pl08x_lli_build_data bd;
589 int num_llis = 0;
590 u32 cctl;
591 size_t max_bytes_per_lli;
592 size_t total_bytes = 0;
593 struct pl08x_lli *llis_va;
595 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
596 &txd->llis_bus);
597 if (!txd->llis_va) {
598 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
599 return 0;
602 pl08x->pool_ctr++;
604 /* Get the default CCTL */
605 cctl = txd->cctl;
607 bd.txd = txd;
608 bd.pl08x = pl08x;
609 bd.srcbus.addr = txd->src_addr;
610 bd.dstbus.addr = txd->dst_addr;
612 /* Find maximum width of the source bus */
613 bd.srcbus.maxwidth =
614 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
615 PL080_CONTROL_SWIDTH_SHIFT);
617 /* Find maximum width of the destination bus */
618 bd.dstbus.maxwidth =
619 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
620 PL080_CONTROL_DWIDTH_SHIFT);
622 /* Set up the bus widths to the maximum */
623 bd.srcbus.buswidth = bd.srcbus.maxwidth;
624 bd.dstbus.buswidth = bd.dstbus.maxwidth;
625 dev_vdbg(&pl08x->adev->dev,
626 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
627 __func__, bd.srcbus.buswidth, bd.dstbus.buswidth);
631 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
633 max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
634 PL080_CONTROL_TRANSFER_SIZE_MASK;
635 dev_vdbg(&pl08x->adev->dev,
636 "%s max bytes per lli = %zu\n",
637 __func__, max_bytes_per_lli);
639 /* We need to count this down to zero */
640 bd.remainder = txd->len;
641 dev_vdbg(&pl08x->adev->dev,
642 "%s remainder = %zu\n",
643 __func__, bd.remainder);
646 * Choose bus to align to
647 * - prefers destination bus if both available
648 * - if fixed address on one bus chooses other
650 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
652 if (txd->len < mbus->buswidth) {
653 /* Less than a bus width available - send as single bytes */
654 while (bd.remainder) {
655 dev_vdbg(&pl08x->adev->dev,
656 "%s single byte LLIs for a transfer of "
657 "less than a bus width (remain 0x%08x)\n",
658 __func__, bd.remainder);
659 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
660 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
661 total_bytes++;
663 } else {
664 /* Make one byte LLIs until master bus is aligned */
665 while ((mbus->addr) % (mbus->buswidth)) {
666 dev_vdbg(&pl08x->adev->dev,
667 "%s adjustment lli for less than bus width "
668 "(remain 0x%08x)\n",
669 __func__, bd.remainder);
670 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
671 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
672 total_bytes++;
676 * Master now aligned
677 * - if slave is not then we must set its width down
679 if (sbus->addr % sbus->buswidth) {
680 dev_dbg(&pl08x->adev->dev,
681 "%s set down bus width to one byte\n",
682 __func__);
684 sbus->buswidth = 1;
688 * Make largest possible LLIs until less than one bus
689 * width left
691 while (bd.remainder > (mbus->buswidth - 1)) {
692 size_t lli_len, target_len, tsize, odd_bytes;
695 * If enough left try to send max possible,
696 * otherwise try to send the remainder
698 target_len = min(bd.remainder, max_bytes_per_lli);
701 * Set bus lengths for incrementing buses to the
702 * number of bytes which fill to next memory boundary,
703 * limiting on the target length calculated above.
705 if (cctl & PL080_CONTROL_SRC_INCR)
706 bd.srcbus.fill_bytes =
707 pl08x_pre_boundary(bd.srcbus.addr,
708 target_len);
709 else
710 bd.srcbus.fill_bytes = target_len;
712 if (cctl & PL080_CONTROL_DST_INCR)
713 bd.dstbus.fill_bytes =
714 pl08x_pre_boundary(bd.dstbus.addr,
715 target_len);
716 else
717 bd.dstbus.fill_bytes = target_len;
719 /* Find the nearest */
720 lli_len = min(bd.srcbus.fill_bytes,
721 bd.dstbus.fill_bytes);
723 BUG_ON(lli_len > bd.remainder);
725 if (lli_len <= 0) {
726 dev_err(&pl08x->adev->dev,
727 "%s lli_len is %zu, <= 0\n",
728 __func__, lli_len);
729 return 0;
732 if (lli_len == target_len) {
734 * Can send what we wanted.
735 * Maintain alignment
737 lli_len = (lli_len/mbus->buswidth) *
738 mbus->buswidth;
739 odd_bytes = 0;
740 } else {
742 * So now we know how many bytes to transfer
743 * to get to the nearest boundary. The next
744 * LLI will past the boundary. However, we
745 * may be working to a boundary on the slave
746 * bus. We need to ensure the master stays
747 * aligned, and that we are working in
748 * multiples of the bus widths.
750 odd_bytes = lli_len % mbus->buswidth;
751 lli_len -= odd_bytes;
755 if (lli_len) {
757 * Check against minimum bus alignment:
758 * Calculate actual transfer size in relation
759 * to bus width an get a maximum remainder of
760 * the smallest bus width - 1
762 /* FIXME: use round_down()? */
763 tsize = lli_len / min(mbus->buswidth,
764 sbus->buswidth);
765 lli_len = tsize * min(mbus->buswidth,
766 sbus->buswidth);
768 if (target_len != lli_len) {
769 dev_vdbg(&pl08x->adev->dev,
770 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
771 __func__, target_len, lli_len, txd->len);
774 cctl = pl08x_cctl_bits(cctl,
775 bd.srcbus.buswidth,
776 bd.dstbus.buswidth,
777 tsize);
779 dev_vdbg(&pl08x->adev->dev,
780 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
781 __func__, lli_len, bd.remainder);
782 pl08x_fill_lli_for_desc(&bd, num_llis++,
783 lli_len, cctl);
784 total_bytes += lli_len;
788 if (odd_bytes) {
790 * Creep past the boundary, maintaining
791 * master alignment
793 int j;
794 for (j = 0; (j < mbus->buswidth)
795 && (bd.remainder); j++) {
796 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
797 dev_vdbg(&pl08x->adev->dev,
798 "%s align with boundary, single byte (remain 0x%08zx)\n",
799 __func__, bd.remainder);
800 pl08x_fill_lli_for_desc(&bd,
801 num_llis++, 1, cctl);
802 total_bytes++;
808 * Send any odd bytes
810 while (bd.remainder) {
811 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
812 dev_vdbg(&pl08x->adev->dev,
813 "%s align with boundary, single odd byte (remain %zu)\n",
814 __func__, bd.remainder);
815 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
816 total_bytes++;
819 if (total_bytes != txd->len) {
820 dev_err(&pl08x->adev->dev,
821 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
822 __func__, total_bytes, txd->len);
823 return 0;
826 if (num_llis >= MAX_NUM_TSFR_LLIS) {
827 dev_err(&pl08x->adev->dev,
828 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
829 __func__, (u32) MAX_NUM_TSFR_LLIS);
830 return 0;
833 llis_va = txd->llis_va;
834 /* The final LLI terminates the LLI. */
835 llis_va[num_llis - 1].lli = 0;
836 /* The final LLI element shall also fire an interrupt. */
837 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
839 #ifdef VERBOSE_DEBUG
841 int i;
843 for (i = 0; i < num_llis; i++) {
844 dev_vdbg(&pl08x->adev->dev,
845 "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
847 &llis_va[i],
848 llis_va[i].src,
849 llis_va[i].dst,
850 llis_va[i].cctl,
851 llis_va[i].lli
855 #endif
857 return num_llis;
860 /* You should call this with the struct pl08x lock held */
861 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
862 struct pl08x_txd *txd)
864 /* Free the LLI */
865 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
867 pl08x->pool_ctr--;
869 kfree(txd);
872 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
873 struct pl08x_dma_chan *plchan)
875 struct pl08x_txd *txdi = NULL;
876 struct pl08x_txd *next;
878 if (!list_empty(&plchan->pend_list)) {
879 list_for_each_entry_safe(txdi,
880 next, &plchan->pend_list, node) {
881 list_del(&txdi->node);
882 pl08x_free_txd(pl08x, txdi);
888 * The DMA ENGINE API
890 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
892 return 0;
895 static void pl08x_free_chan_resources(struct dma_chan *chan)
900 * This should be called with the channel plchan->lock held
902 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
903 struct pl08x_txd *txd)
905 struct pl08x_driver_data *pl08x = plchan->host;
906 struct pl08x_phy_chan *ch;
907 int ret;
909 /* Check if we already have a channel */
910 if (plchan->phychan)
911 return 0;
913 ch = pl08x_get_phy_channel(pl08x, plchan);
914 if (!ch) {
915 /* No physical channel available, cope with it */
916 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
917 return -EBUSY;
921 * OK we have a physical channel: for memcpy() this is all we
922 * need, but for slaves the physical signals may be muxed!
923 * Can the platform allow us to use this channel?
925 if (plchan->slave &&
926 ch->signal < 0 &&
927 pl08x->pd->get_signal) {
928 ret = pl08x->pd->get_signal(plchan);
929 if (ret < 0) {
930 dev_dbg(&pl08x->adev->dev,
931 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
932 ch->id, plchan->name);
933 /* Release physical channel & return */
934 pl08x_put_phy_channel(pl08x, ch);
935 return -EBUSY;
937 ch->signal = ret;
939 /* Assign the flow control signal to this channel */
940 if (txd->direction == DMA_TO_DEVICE)
941 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
942 else if (txd->direction == DMA_FROM_DEVICE)
943 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
946 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
947 ch->id,
948 ch->signal,
949 plchan->name);
951 plchan->phychan_hold++;
952 plchan->phychan = ch;
954 return 0;
957 static void release_phy_channel(struct pl08x_dma_chan *plchan)
959 struct pl08x_driver_data *pl08x = plchan->host;
961 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
962 pl08x->pd->put_signal(plchan);
963 plchan->phychan->signal = -1;
965 pl08x_put_phy_channel(pl08x, plchan->phychan);
966 plchan->phychan = NULL;
969 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
971 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
972 struct pl08x_txd *txd = to_pl08x_txd(tx);
973 unsigned long flags;
975 spin_lock_irqsave(&plchan->lock, flags);
977 plchan->chan.cookie += 1;
978 if (plchan->chan.cookie < 0)
979 plchan->chan.cookie = 1;
980 tx->cookie = plchan->chan.cookie;
982 /* Put this onto the pending list */
983 list_add_tail(&txd->node, &plchan->pend_list);
986 * If there was no physical channel available for this memcpy,
987 * stack the request up and indicate that the channel is waiting
988 * for a free physical channel.
990 if (!plchan->slave && !plchan->phychan) {
991 /* Do this memcpy whenever there is a channel ready */
992 plchan->state = PL08X_CHAN_WAITING;
993 plchan->waiting = txd;
994 } else {
995 plchan->phychan_hold--;
998 spin_unlock_irqrestore(&plchan->lock, flags);
1000 return tx->cookie;
1003 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1004 struct dma_chan *chan, unsigned long flags)
1006 struct dma_async_tx_descriptor *retval = NULL;
1008 return retval;
1012 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1013 * If slaves are relying on interrupts to signal completion this function
1014 * must not be called with interrupts disabled.
1016 static enum dma_status
1017 pl08x_dma_tx_status(struct dma_chan *chan,
1018 dma_cookie_t cookie,
1019 struct dma_tx_state *txstate)
1021 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1022 dma_cookie_t last_used;
1023 dma_cookie_t last_complete;
1024 enum dma_status ret;
1025 u32 bytesleft = 0;
1027 last_used = plchan->chan.cookie;
1028 last_complete = plchan->lc;
1030 ret = dma_async_is_complete(cookie, last_complete, last_used);
1031 if (ret == DMA_SUCCESS) {
1032 dma_set_tx_state(txstate, last_complete, last_used, 0);
1033 return ret;
1037 * This cookie not complete yet
1039 last_used = plchan->chan.cookie;
1040 last_complete = plchan->lc;
1042 /* Get number of bytes left in the active transactions and queue */
1043 bytesleft = pl08x_getbytes_chan(plchan);
1045 dma_set_tx_state(txstate, last_complete, last_used,
1046 bytesleft);
1048 if (plchan->state == PL08X_CHAN_PAUSED)
1049 return DMA_PAUSED;
1051 /* Whether waiting or running, we're in progress */
1052 return DMA_IN_PROGRESS;
1055 /* PrimeCell DMA extension */
1056 struct burst_table {
1057 int burstwords;
1058 u32 reg;
1061 static const struct burst_table burst_sizes[] = {
1063 .burstwords = 256,
1064 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1065 (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1068 .burstwords = 128,
1069 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1070 (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1073 .burstwords = 64,
1074 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1075 (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1078 .burstwords = 32,
1079 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1080 (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1083 .burstwords = 16,
1084 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1085 (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1088 .burstwords = 8,
1089 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1090 (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1093 .burstwords = 4,
1094 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1095 (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1098 .burstwords = 1,
1099 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1100 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1104 static int dma_set_runtime_config(struct dma_chan *chan,
1105 struct dma_slave_config *config)
1107 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1108 struct pl08x_driver_data *pl08x = plchan->host;
1109 struct pl08x_channel_data *cd = plchan->cd;
1110 enum dma_slave_buswidth addr_width;
1111 dma_addr_t addr;
1112 u32 maxburst;
1113 u32 cctl = 0;
1114 int i;
1116 if (!plchan->slave)
1117 return -EINVAL;
1119 /* Transfer direction */
1120 plchan->runtime_direction = config->direction;
1121 if (config->direction == DMA_TO_DEVICE) {
1122 addr = config->dst_addr;
1123 addr_width = config->dst_addr_width;
1124 maxburst = config->dst_maxburst;
1125 } else if (config->direction == DMA_FROM_DEVICE) {
1126 addr = config->src_addr;
1127 addr_width = config->src_addr_width;
1128 maxburst = config->src_maxburst;
1129 } else {
1130 dev_err(&pl08x->adev->dev,
1131 "bad runtime_config: alien transfer direction\n");
1132 return -EINVAL;
1135 switch (addr_width) {
1136 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1137 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1138 (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1139 break;
1140 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1141 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1142 (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1143 break;
1144 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1145 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1146 (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1147 break;
1148 default:
1149 dev_err(&pl08x->adev->dev,
1150 "bad runtime_config: alien address width\n");
1151 return -EINVAL;
1155 * Now decide on a maxburst:
1156 * If this channel will only request single transfers, set this
1157 * down to ONE element. Also select one element if no maxburst
1158 * is specified.
1160 if (plchan->cd->single || maxburst == 0) {
1161 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1162 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1163 } else {
1164 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1165 if (burst_sizes[i].burstwords <= maxburst)
1166 break;
1167 cctl |= burst_sizes[i].reg;
1170 plchan->runtime_addr = addr;
1172 /* Modify the default channel data to fit PrimeCell request */
1173 cd->cctl = cctl;
1175 dev_dbg(&pl08x->adev->dev,
1176 "configured channel %s (%s) for %s, data width %d, "
1177 "maxburst %d words, LE, CCTL=0x%08x\n",
1178 dma_chan_name(chan), plchan->name,
1179 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1180 addr_width,
1181 maxburst,
1182 cctl);
1184 return 0;
1188 * Slave transactions callback to the slave device to allow
1189 * synchronization of slave DMA signals with the DMAC enable
1191 static void pl08x_issue_pending(struct dma_chan *chan)
1193 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1194 unsigned long flags;
1196 spin_lock_irqsave(&plchan->lock, flags);
1197 /* Something is already active, or we're waiting for a channel... */
1198 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1199 spin_unlock_irqrestore(&plchan->lock, flags);
1200 return;
1203 /* Take the first element in the queue and execute it */
1204 if (!list_empty(&plchan->pend_list)) {
1205 struct pl08x_txd *next;
1207 next = list_first_entry(&plchan->pend_list,
1208 struct pl08x_txd,
1209 node);
1210 list_del(&next->node);
1211 plchan->state = PL08X_CHAN_RUNNING;
1213 pl08x_start_txd(plchan, next);
1216 spin_unlock_irqrestore(&plchan->lock, flags);
1219 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1220 struct pl08x_txd *txd)
1222 struct pl08x_driver_data *pl08x = plchan->host;
1223 unsigned long flags;
1224 int num_llis, ret;
1226 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1227 if (!num_llis) {
1228 kfree(txd);
1229 return -EINVAL;
1232 spin_lock_irqsave(&plchan->lock, flags);
1235 * See if we already have a physical channel allocated,
1236 * else this is the time to try to get one.
1238 ret = prep_phy_channel(plchan, txd);
1239 if (ret) {
1241 * No physical channel was available.
1243 * memcpy transfers can be sorted out at submission time.
1245 * Slave transfers may have been denied due to platform
1246 * channel muxing restrictions. Since there is no guarantee
1247 * that this will ever be resolved, and the signal must be
1248 * acquired AFTER acquiring the physical channel, we will let
1249 * them be NACK:ed with -EBUSY here. The drivers can retry
1250 * the prep() call if they are eager on doing this using DMA.
1252 if (plchan->slave) {
1253 pl08x_free_txd_list(pl08x, plchan);
1254 pl08x_free_txd(pl08x, txd);
1255 spin_unlock_irqrestore(&plchan->lock, flags);
1256 return -EBUSY;
1258 } else
1260 * Else we're all set, paused and ready to roll, status
1261 * will switch to PL08X_CHAN_RUNNING when we call
1262 * issue_pending(). If there is something running on the
1263 * channel already we don't change its state.
1265 if (plchan->state == PL08X_CHAN_IDLE)
1266 plchan->state = PL08X_CHAN_PAUSED;
1268 spin_unlock_irqrestore(&plchan->lock, flags);
1270 return 0;
1274 * Given the source and destination available bus masks, select which
1275 * will be routed to each port. We try to have source and destination
1276 * on separate ports, but always respect the allowable settings.
1278 static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst)
1280 u32 cctl = 0;
1282 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1283 cctl |= PL080_CONTROL_DST_AHB2;
1284 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1285 cctl |= PL080_CONTROL_SRC_AHB2;
1287 return cctl;
1290 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1291 unsigned long flags)
1293 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1295 if (txd) {
1296 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1297 txd->tx.flags = flags;
1298 txd->tx.tx_submit = pl08x_tx_submit;
1299 INIT_LIST_HEAD(&txd->node);
1301 /* Always enable error and terminal interrupts */
1302 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1303 PL080_CONFIG_TC_IRQ_MASK;
1305 return txd;
1309 * Initialize a descriptor to be used by memcpy submit
1311 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1312 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1313 size_t len, unsigned long flags)
1315 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1316 struct pl08x_driver_data *pl08x = plchan->host;
1317 struct pl08x_txd *txd;
1318 int ret;
1320 txd = pl08x_get_txd(plchan, flags);
1321 if (!txd) {
1322 dev_err(&pl08x->adev->dev,
1323 "%s no memory for descriptor\n", __func__);
1324 return NULL;
1327 txd->direction = DMA_NONE;
1328 txd->src_addr = src;
1329 txd->dst_addr = dest;
1330 txd->len = len;
1332 /* Set platform data for m2m */
1333 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1334 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1335 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1337 /* Both to be incremented or the code will break */
1338 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1340 if (pl08x->vd->dualmaster)
1341 txd->cctl |= pl08x_select_bus(pl08x,
1342 pl08x->mem_buses, pl08x->mem_buses);
1344 ret = pl08x_prep_channel_resources(plchan, txd);
1345 if (ret)
1346 return NULL;
1348 return &txd->tx;
1351 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1352 struct dma_chan *chan, struct scatterlist *sgl,
1353 unsigned int sg_len, enum dma_data_direction direction,
1354 unsigned long flags)
1356 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1357 struct pl08x_driver_data *pl08x = plchan->host;
1358 struct pl08x_txd *txd;
1359 u8 src_buses, dst_buses;
1360 int ret;
1363 * Current implementation ASSUMES only one sg
1365 if (sg_len != 1) {
1366 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1367 __func__);
1368 BUG();
1371 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1372 __func__, sgl->length, plchan->name);
1374 txd = pl08x_get_txd(plchan, flags);
1375 if (!txd) {
1376 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1377 return NULL;
1380 if (direction != plchan->runtime_direction)
1381 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1382 "the direction configured for the PrimeCell\n",
1383 __func__);
1386 * Set up addresses, the PrimeCell configured address
1387 * will take precedence since this may configure the
1388 * channel target address dynamically at runtime.
1390 txd->direction = direction;
1391 txd->len = sgl->length;
1393 txd->cctl = plchan->cd->cctl &
1394 ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1395 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1396 PL080_CONTROL_PROT_MASK);
1398 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1399 txd->cctl |= PL080_CONTROL_PROT_SYS;
1401 if (direction == DMA_TO_DEVICE) {
1402 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1403 txd->cctl |= PL080_CONTROL_SRC_INCR;
1404 txd->src_addr = sgl->dma_address;
1405 if (plchan->runtime_addr)
1406 txd->dst_addr = plchan->runtime_addr;
1407 else
1408 txd->dst_addr = plchan->cd->addr;
1409 src_buses = pl08x->mem_buses;
1410 dst_buses = plchan->cd->periph_buses;
1411 } else if (direction == DMA_FROM_DEVICE) {
1412 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1413 txd->cctl |= PL080_CONTROL_DST_INCR;
1414 if (plchan->runtime_addr)
1415 txd->src_addr = plchan->runtime_addr;
1416 else
1417 txd->src_addr = plchan->cd->addr;
1418 txd->dst_addr = sgl->dma_address;
1419 src_buses = plchan->cd->periph_buses;
1420 dst_buses = pl08x->mem_buses;
1421 } else {
1422 dev_err(&pl08x->adev->dev,
1423 "%s direction unsupported\n", __func__);
1424 return NULL;
1427 txd->cctl |= pl08x_select_bus(pl08x, src_buses, dst_buses);
1429 ret = pl08x_prep_channel_resources(plchan, txd);
1430 if (ret)
1431 return NULL;
1433 return &txd->tx;
1436 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1437 unsigned long arg)
1439 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1440 struct pl08x_driver_data *pl08x = plchan->host;
1441 unsigned long flags;
1442 int ret = 0;
1444 /* Controls applicable to inactive channels */
1445 if (cmd == DMA_SLAVE_CONFIG) {
1446 return dma_set_runtime_config(chan,
1447 (struct dma_slave_config *)arg);
1451 * Anything succeeds on channels with no physical allocation and
1452 * no queued transfers.
1454 spin_lock_irqsave(&plchan->lock, flags);
1455 if (!plchan->phychan && !plchan->at) {
1456 spin_unlock_irqrestore(&plchan->lock, flags);
1457 return 0;
1460 switch (cmd) {
1461 case DMA_TERMINATE_ALL:
1462 plchan->state = PL08X_CHAN_IDLE;
1464 if (plchan->phychan) {
1465 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1468 * Mark physical channel as free and free any slave
1469 * signal
1471 release_phy_channel(plchan);
1473 /* Dequeue jobs and free LLIs */
1474 if (plchan->at) {
1475 pl08x_free_txd(pl08x, plchan->at);
1476 plchan->at = NULL;
1478 /* Dequeue jobs not yet fired as well */
1479 pl08x_free_txd_list(pl08x, plchan);
1480 break;
1481 case DMA_PAUSE:
1482 pl08x_pause_phy_chan(plchan->phychan);
1483 plchan->state = PL08X_CHAN_PAUSED;
1484 break;
1485 case DMA_RESUME:
1486 pl08x_resume_phy_chan(plchan->phychan);
1487 plchan->state = PL08X_CHAN_RUNNING;
1488 break;
1489 default:
1490 /* Unknown command */
1491 ret = -ENXIO;
1492 break;
1495 spin_unlock_irqrestore(&plchan->lock, flags);
1497 return ret;
1500 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1502 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1503 char *name = chan_id;
1505 /* Check that the channel is not taken! */
1506 if (!strcmp(plchan->name, name))
1507 return true;
1509 return false;
1513 * Just check that the device is there and active
1514 * TODO: turn this bit on/off depending on the number of physical channels
1515 * actually used, if it is zero... well shut it off. That will save some
1516 * power. Cut the clock at the same time.
1518 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1520 u32 val;
1522 val = readl(pl08x->base + PL080_CONFIG);
1523 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1524 /* We implicitly clear bit 1 and that means little-endian mode */
1525 val |= PL080_CONFIG_ENABLE;
1526 writel(val, pl08x->base + PL080_CONFIG);
1529 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1531 struct device *dev = txd->tx.chan->device->dev;
1533 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1534 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1535 dma_unmap_single(dev, txd->src_addr, txd->len,
1536 DMA_TO_DEVICE);
1537 else
1538 dma_unmap_page(dev, txd->src_addr, txd->len,
1539 DMA_TO_DEVICE);
1541 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1542 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1543 dma_unmap_single(dev, txd->dst_addr, txd->len,
1544 DMA_FROM_DEVICE);
1545 else
1546 dma_unmap_page(dev, txd->dst_addr, txd->len,
1547 DMA_FROM_DEVICE);
1551 static void pl08x_tasklet(unsigned long data)
1553 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1554 struct pl08x_driver_data *pl08x = plchan->host;
1555 struct pl08x_txd *txd;
1556 unsigned long flags;
1558 spin_lock_irqsave(&plchan->lock, flags);
1560 txd = plchan->at;
1561 plchan->at = NULL;
1563 if (txd) {
1564 /* Update last completed */
1565 plchan->lc = txd->tx.cookie;
1568 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1569 if (!list_empty(&plchan->pend_list)) {
1570 struct pl08x_txd *next;
1572 next = list_first_entry(&plchan->pend_list,
1573 struct pl08x_txd,
1574 node);
1575 list_del(&next->node);
1577 pl08x_start_txd(plchan, next);
1578 } else if (plchan->phychan_hold) {
1580 * This channel is still in use - we have a new txd being
1581 * prepared and will soon be queued. Don't give up the
1582 * physical channel.
1584 } else {
1585 struct pl08x_dma_chan *waiting = NULL;
1588 * No more jobs, so free up the physical channel
1589 * Free any allocated signal on slave transfers too
1591 release_phy_channel(plchan);
1592 plchan->state = PL08X_CHAN_IDLE;
1595 * And NOW before anyone else can grab that free:d up
1596 * physical channel, see if there is some memcpy pending
1597 * that seriously needs to start because of being stacked
1598 * up while we were choking the physical channels with data.
1600 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1601 chan.device_node) {
1602 if (waiting->state == PL08X_CHAN_WAITING &&
1603 waiting->waiting != NULL) {
1604 int ret;
1606 /* This should REALLY not fail now */
1607 ret = prep_phy_channel(waiting,
1608 waiting->waiting);
1609 BUG_ON(ret);
1610 waiting->phychan_hold--;
1611 waiting->state = PL08X_CHAN_RUNNING;
1612 waiting->waiting = NULL;
1613 pl08x_issue_pending(&waiting->chan);
1614 break;
1619 spin_unlock_irqrestore(&plchan->lock, flags);
1621 if (txd) {
1622 dma_async_tx_callback callback = txd->tx.callback;
1623 void *callback_param = txd->tx.callback_param;
1625 /* Don't try to unmap buffers on slave channels */
1626 if (!plchan->slave)
1627 pl08x_unmap_buffers(txd);
1629 /* Free the descriptor */
1630 spin_lock_irqsave(&plchan->lock, flags);
1631 pl08x_free_txd(pl08x, txd);
1632 spin_unlock_irqrestore(&plchan->lock, flags);
1634 /* Callback to signal completion */
1635 if (callback)
1636 callback(callback_param);
1640 static irqreturn_t pl08x_irq(int irq, void *dev)
1642 struct pl08x_driver_data *pl08x = dev;
1643 u32 mask = 0;
1644 u32 val;
1645 int i;
1647 val = readl(pl08x->base + PL080_ERR_STATUS);
1648 if (val) {
1649 /* An error interrupt (on one or more channels) */
1650 dev_err(&pl08x->adev->dev,
1651 "%s error interrupt, register value 0x%08x\n",
1652 __func__, val);
1654 * Simply clear ALL PL08X error interrupts,
1655 * regardless of channel and cause
1656 * FIXME: should be 0x00000003 on PL081 really.
1658 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1660 val = readl(pl08x->base + PL080_INT_STATUS);
1661 for (i = 0; i < pl08x->vd->channels; i++) {
1662 if ((1 << i) & val) {
1663 /* Locate physical channel */
1664 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1665 struct pl08x_dma_chan *plchan = phychan->serving;
1667 /* Schedule tasklet on this channel */
1668 tasklet_schedule(&plchan->tasklet);
1670 mask |= (1 << i);
1673 /* Clear only the terminal interrupts on channels we processed */
1674 writel(mask, pl08x->base + PL080_TC_CLEAR);
1676 return mask ? IRQ_HANDLED : IRQ_NONE;
1680 * Initialise the DMAC memcpy/slave channels.
1681 * Make a local wrapper to hold required data
1683 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1684 struct dma_device *dmadev,
1685 unsigned int channels,
1686 bool slave)
1688 struct pl08x_dma_chan *chan;
1689 int i;
1691 INIT_LIST_HEAD(&dmadev->channels);
1694 * Register as many many memcpy as we have physical channels,
1695 * we won't always be able to use all but the code will have
1696 * to cope with that situation.
1698 for (i = 0; i < channels; i++) {
1699 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1700 if (!chan) {
1701 dev_err(&pl08x->adev->dev,
1702 "%s no memory for channel\n", __func__);
1703 return -ENOMEM;
1706 chan->host = pl08x;
1707 chan->state = PL08X_CHAN_IDLE;
1709 if (slave) {
1710 chan->slave = true;
1711 chan->name = pl08x->pd->slave_channels[i].bus_id;
1712 chan->cd = &pl08x->pd->slave_channels[i];
1713 } else {
1714 chan->cd = &pl08x->pd->memcpy_channel;
1715 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1716 if (!chan->name) {
1717 kfree(chan);
1718 return -ENOMEM;
1721 if (chan->cd->circular_buffer) {
1722 dev_err(&pl08x->adev->dev,
1723 "channel %s: circular buffers not supported\n",
1724 chan->name);
1725 kfree(chan);
1726 continue;
1728 dev_info(&pl08x->adev->dev,
1729 "initialize virtual channel \"%s\"\n",
1730 chan->name);
1732 chan->chan.device = dmadev;
1733 chan->chan.cookie = 0;
1734 chan->lc = 0;
1736 spin_lock_init(&chan->lock);
1737 INIT_LIST_HEAD(&chan->pend_list);
1738 tasklet_init(&chan->tasklet, pl08x_tasklet,
1739 (unsigned long) chan);
1741 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1743 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1744 i, slave ? "slave" : "memcpy");
1745 return i;
1748 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1750 struct pl08x_dma_chan *chan = NULL;
1751 struct pl08x_dma_chan *next;
1753 list_for_each_entry_safe(chan,
1754 next, &dmadev->channels, chan.device_node) {
1755 list_del(&chan->chan.device_node);
1756 kfree(chan);
1760 #ifdef CONFIG_DEBUG_FS
1761 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1763 switch (state) {
1764 case PL08X_CHAN_IDLE:
1765 return "idle";
1766 case PL08X_CHAN_RUNNING:
1767 return "running";
1768 case PL08X_CHAN_PAUSED:
1769 return "paused";
1770 case PL08X_CHAN_WAITING:
1771 return "waiting";
1772 default:
1773 break;
1775 return "UNKNOWN STATE";
1778 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1780 struct pl08x_driver_data *pl08x = s->private;
1781 struct pl08x_dma_chan *chan;
1782 struct pl08x_phy_chan *ch;
1783 unsigned long flags;
1784 int i;
1786 seq_printf(s, "PL08x physical channels:\n");
1787 seq_printf(s, "CHANNEL:\tUSER:\n");
1788 seq_printf(s, "--------\t-----\n");
1789 for (i = 0; i < pl08x->vd->channels; i++) {
1790 struct pl08x_dma_chan *virt_chan;
1792 ch = &pl08x->phy_chans[i];
1794 spin_lock_irqsave(&ch->lock, flags);
1795 virt_chan = ch->serving;
1797 seq_printf(s, "%d\t\t%s\n",
1798 ch->id, virt_chan ? virt_chan->name : "(none)");
1800 spin_unlock_irqrestore(&ch->lock, flags);
1803 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1804 seq_printf(s, "CHANNEL:\tSTATE:\n");
1805 seq_printf(s, "--------\t------\n");
1806 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1807 seq_printf(s, "%s\t\t%s\n", chan->name,
1808 pl08x_state_str(chan->state));
1811 seq_printf(s, "\nPL08x virtual slave channels:\n");
1812 seq_printf(s, "CHANNEL:\tSTATE:\n");
1813 seq_printf(s, "--------\t------\n");
1814 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1815 seq_printf(s, "%s\t\t%s\n", chan->name,
1816 pl08x_state_str(chan->state));
1819 return 0;
1822 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1824 return single_open(file, pl08x_debugfs_show, inode->i_private);
1827 static const struct file_operations pl08x_debugfs_operations = {
1828 .open = pl08x_debugfs_open,
1829 .read = seq_read,
1830 .llseek = seq_lseek,
1831 .release = single_release,
1834 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1836 /* Expose a simple debugfs interface to view all clocks */
1837 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1838 NULL, pl08x,
1839 &pl08x_debugfs_operations);
1842 #else
1843 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1846 #endif
1848 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1850 struct pl08x_driver_data *pl08x;
1851 const struct vendor_data *vd = id->data;
1852 int ret = 0;
1853 int i;
1855 ret = amba_request_regions(adev, NULL);
1856 if (ret)
1857 return ret;
1859 /* Create the driver state holder */
1860 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1861 if (!pl08x) {
1862 ret = -ENOMEM;
1863 goto out_no_pl08x;
1866 /* Initialize memcpy engine */
1867 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1868 pl08x->memcpy.dev = &adev->dev;
1869 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1870 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1871 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1872 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1873 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1874 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1875 pl08x->memcpy.device_control = pl08x_control;
1877 /* Initialize slave engine */
1878 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1879 pl08x->slave.dev = &adev->dev;
1880 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1881 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1882 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1883 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1884 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1885 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1886 pl08x->slave.device_control = pl08x_control;
1888 /* Get the platform data */
1889 pl08x->pd = dev_get_platdata(&adev->dev);
1890 if (!pl08x->pd) {
1891 dev_err(&adev->dev, "no platform data supplied\n");
1892 goto out_no_platdata;
1895 /* Assign useful pointers to the driver state */
1896 pl08x->adev = adev;
1897 pl08x->vd = vd;
1899 /* By default, AHB1 only. If dualmaster, from platform */
1900 pl08x->lli_buses = PL08X_AHB1;
1901 pl08x->mem_buses = PL08X_AHB1;
1902 if (pl08x->vd->dualmaster) {
1903 pl08x->lli_buses = pl08x->pd->lli_buses;
1904 pl08x->mem_buses = pl08x->pd->mem_buses;
1907 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1908 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1909 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1910 if (!pl08x->pool) {
1911 ret = -ENOMEM;
1912 goto out_no_lli_pool;
1915 spin_lock_init(&pl08x->lock);
1917 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1918 if (!pl08x->base) {
1919 ret = -ENOMEM;
1920 goto out_no_ioremap;
1923 /* Turn on the PL08x */
1924 pl08x_ensure_on(pl08x);
1926 /* Attach the interrupt handler */
1927 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1928 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1930 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1931 DRIVER_NAME, pl08x);
1932 if (ret) {
1933 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1934 __func__, adev->irq[0]);
1935 goto out_no_irq;
1938 /* Initialize physical channels */
1939 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1940 GFP_KERNEL);
1941 if (!pl08x->phy_chans) {
1942 dev_err(&adev->dev, "%s failed to allocate "
1943 "physical channel holders\n",
1944 __func__);
1945 goto out_no_phychans;
1948 for (i = 0; i < vd->channels; i++) {
1949 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1951 ch->id = i;
1952 ch->base = pl08x->base + PL080_Cx_BASE(i);
1953 spin_lock_init(&ch->lock);
1954 ch->serving = NULL;
1955 ch->signal = -1;
1956 dev_info(&adev->dev,
1957 "physical channel %d is %s\n", i,
1958 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1961 /* Register as many memcpy channels as there are physical channels */
1962 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1963 pl08x->vd->channels, false);
1964 if (ret <= 0) {
1965 dev_warn(&pl08x->adev->dev,
1966 "%s failed to enumerate memcpy channels - %d\n",
1967 __func__, ret);
1968 goto out_no_memcpy;
1970 pl08x->memcpy.chancnt = ret;
1972 /* Register slave channels */
1973 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1974 pl08x->pd->num_slave_channels,
1975 true);
1976 if (ret <= 0) {
1977 dev_warn(&pl08x->adev->dev,
1978 "%s failed to enumerate slave channels - %d\n",
1979 __func__, ret);
1980 goto out_no_slave;
1982 pl08x->slave.chancnt = ret;
1984 ret = dma_async_device_register(&pl08x->memcpy);
1985 if (ret) {
1986 dev_warn(&pl08x->adev->dev,
1987 "%s failed to register memcpy as an async device - %d\n",
1988 __func__, ret);
1989 goto out_no_memcpy_reg;
1992 ret = dma_async_device_register(&pl08x->slave);
1993 if (ret) {
1994 dev_warn(&pl08x->adev->dev,
1995 "%s failed to register slave as an async device - %d\n",
1996 __func__, ret);
1997 goto out_no_slave_reg;
2000 amba_set_drvdata(adev, pl08x);
2001 init_pl08x_debugfs(pl08x);
2002 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2003 amba_part(adev), amba_rev(adev),
2004 (unsigned long long)adev->res.start, adev->irq[0]);
2005 return 0;
2007 out_no_slave_reg:
2008 dma_async_device_unregister(&pl08x->memcpy);
2009 out_no_memcpy_reg:
2010 pl08x_free_virtual_channels(&pl08x->slave);
2011 out_no_slave:
2012 pl08x_free_virtual_channels(&pl08x->memcpy);
2013 out_no_memcpy:
2014 kfree(pl08x->phy_chans);
2015 out_no_phychans:
2016 free_irq(adev->irq[0], pl08x);
2017 out_no_irq:
2018 iounmap(pl08x->base);
2019 out_no_ioremap:
2020 dma_pool_destroy(pl08x->pool);
2021 out_no_lli_pool:
2022 out_no_platdata:
2023 kfree(pl08x);
2024 out_no_pl08x:
2025 amba_release_regions(adev);
2026 return ret;
2029 /* PL080 has 8 channels and the PL080 have just 2 */
2030 static struct vendor_data vendor_pl080 = {
2031 .channels = 8,
2032 .dualmaster = true,
2035 static struct vendor_data vendor_pl081 = {
2036 .channels = 2,
2037 .dualmaster = false,
2040 static struct amba_id pl08x_ids[] = {
2041 /* PL080 */
2043 .id = 0x00041080,
2044 .mask = 0x000fffff,
2045 .data = &vendor_pl080,
2047 /* PL081 */
2049 .id = 0x00041081,
2050 .mask = 0x000fffff,
2051 .data = &vendor_pl081,
2053 /* Nomadik 8815 PL080 variant */
2055 .id = 0x00280880,
2056 .mask = 0x00ffffff,
2057 .data = &vendor_pl080,
2059 { 0, 0 },
2062 static struct amba_driver pl08x_amba_driver = {
2063 .drv.name = DRIVER_NAME,
2064 .id_table = pl08x_ids,
2065 .probe = pl08x_probe,
2068 static int __init pl08x_init(void)
2070 int retval;
2071 retval = amba_driver_register(&pl08x_amba_driver);
2072 if (retval)
2073 printk(KERN_WARNING DRIVER_NAME
2074 "failed to register as an AMBA device (%d)\n",
2075 retval);
2076 return retval;
2078 subsys_initcall(pl08x_init);