4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <linux/seq_file.h>
35 #include "intel_drv.h"
37 /* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41 #define IMAGE_MAX_WIDTH 2048
42 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43 /* on 830 and 845 these large limits result in the card hanging */
44 #define IMAGE_MAX_WIDTH_LEGACY 1024
45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
47 /* overlay register definitions */
49 #define OCMD_TILED_SURFACE (0x1<<19)
50 #define OCMD_MIRROR_MASK (0x3<<17)
51 #define OCMD_MIRROR_MODE (0x3<<17)
52 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53 #define OCMD_MIRROR_VERTICAL (0x2<<17)
54 #define OCMD_MIRROR_BOTH (0x3<<17)
55 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_422_PACKED (0x8<<10)
64 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_420_PLANAR (0xc<<10)
66 #define OCMD_YUV_422_PLANAR (0xd<<10)
67 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
70 #define OCMD_BUF_TYPE_MASK (0x1<<5)
71 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
72 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
73 #define OCMD_TEST_MODE (0x1<<4)
74 #define OCMD_BUFFER_SELECT (0x3<<2)
75 #define OCMD_BUFFER0 (0x0<<2)
76 #define OCMD_BUFFER1 (0x1<<2)
77 #define OCMD_FIELD_SELECT (0x1<<2)
78 #define OCMD_FIELD0 (0x0<<1)
79 #define OCMD_FIELD1 (0x1<<1)
80 #define OCMD_ENABLE (0x1<<0)
82 /* OCONFIG register */
83 #define OCONF_PIPE_MASK (0x1<<18)
84 #define OCONF_PIPE_A (0x0<<18)
85 #define OCONF_PIPE_B (0x1<<18)
86 #define OCONF_GAMMA2_ENABLE (0x1<<16)
87 #define OCONF_CSC_MODE_BT601 (0x0<<5)
88 #define OCONF_CSC_MODE_BT709 (0x1<<5)
89 #define OCONF_CSC_BYPASS (0x1<<4)
90 #define OCONF_CC_OUT_8BIT (0x1<<3)
91 #define OCONF_TEST_MODE (0x1<<2)
92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
93 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
95 /* DCLRKM (dst-key) register */
96 #define DST_KEY_ENABLE (0x1<<31)
97 #define CLK_RGB24_MASK 0x0
98 #define CLK_RGB16_MASK 0x070307
99 #define CLK_RGB15_MASK 0x070707
100 #define CLK_RGB8I_MASK 0xffffff
102 #define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104 #define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
107 /* overlay flip addr flag */
108 #define OFC_UPDATE 0x1
110 /* polyphase filter coefficients */
111 #define N_HORIZ_Y_TAPS 5
112 #define N_VERT_Y_TAPS 3
113 #define N_HORIZ_UV_TAPS 3
114 #define N_VERT_UV_TAPS 3
118 /* memory bufferd overlay registers */
119 struct overlay_registers
{
147 u32 RESERVED1
; /* 0x6C */
160 u32 FASTHSCALE
; /* 0xA0 */
161 u32 UVSCALEV
; /* 0xA4 */
162 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
164 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
165 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
166 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
167 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
168 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
169 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
170 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
173 /* overlay flip addr flag */
174 #define OFC_UPDATE 0x1
176 #define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
177 #define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
179 static struct overlay_registers
*intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
)
181 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
182 struct overlay_registers
*regs
;
184 /* no recursive mappings */
185 BUG_ON(overlay
->virt_addr
);
187 if (OVERLAY_NONPHYSICAL(overlay
->dev
)) {
188 regs
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
189 overlay
->reg_bo
->gtt_offset
,
193 DRM_ERROR("failed to map overlay regs in GTT\n");
197 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
199 return overlay
->virt_addr
= regs
;
202 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
)
204 if (OVERLAY_NONPHYSICAL(overlay
->dev
))
205 io_mapping_unmap_atomic(overlay
->virt_addr
, KM_USER0
);
207 overlay
->virt_addr
= NULL
;
212 /* overlay needs to be disable in OCMD reg */
213 static int intel_overlay_on(struct intel_overlay
*overlay
)
215 struct drm_device
*dev
= overlay
->dev
;
217 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
219 BUG_ON(overlay
->active
);
222 overlay
->hw_wedged
= NEEDS_WAIT_FOR_FLIP
;
225 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
226 OUT_RING(overlay
->flip_addr
| OFC_UPDATE
);
227 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
231 overlay
->last_flip_req
=
232 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
233 if (overlay
->last_flip_req
== 0)
236 ret
= i915_do_wait_request(dev
,
237 overlay
->last_flip_req
, true,
238 &dev_priv
->render_ring
);
242 overlay
->hw_wedged
= 0;
243 overlay
->last_flip_req
= 0;
247 /* overlay needs to be enabled in OCMD reg */
248 static void intel_overlay_continue(struct intel_overlay
*overlay
,
249 bool load_polyphase_filter
)
251 struct drm_device
*dev
= overlay
->dev
;
252 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
253 u32 flip_addr
= overlay
->flip_addr
;
256 BUG_ON(!overlay
->active
);
258 if (load_polyphase_filter
)
259 flip_addr
|= OFC_UPDATE
;
261 /* check for underruns */
262 tmp
= I915_READ(DOVSTA
);
264 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
267 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
271 overlay
->last_flip_req
=
272 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
275 static int intel_overlay_wait_flip(struct intel_overlay
*overlay
)
277 struct drm_device
*dev
= overlay
->dev
;
278 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
282 if (overlay
->last_flip_req
!= 0) {
283 ret
= i915_do_wait_request(dev
,
284 overlay
->last_flip_req
, true,
285 &dev_priv
->render_ring
);
287 overlay
->last_flip_req
= 0;
289 tmp
= I915_READ(ISR
);
291 if (!(tmp
& I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
))
296 /* synchronous slowpath */
297 overlay
->hw_wedged
= RELEASE_OLD_VID
;
300 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
304 overlay
->last_flip_req
=
305 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
306 if (overlay
->last_flip_req
== 0)
309 ret
= i915_do_wait_request(dev
,
310 overlay
->last_flip_req
, true,
311 &dev_priv
->render_ring
);
315 overlay
->hw_wedged
= 0;
316 overlay
->last_flip_req
= 0;
320 /* overlay needs to be disabled in OCMD reg */
321 static int intel_overlay_off(struct intel_overlay
*overlay
)
323 u32 flip_addr
= overlay
->flip_addr
;
324 struct drm_device
*dev
= overlay
->dev
;
325 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
328 BUG_ON(!overlay
->active
);
330 /* According to intel docs the overlay hw may hang (when switching
331 * off) without loading the filter coeffs. It is however unclear whether
332 * this applies to the disabling of the overlay or to the switching off
333 * of the hw. Do it in both cases */
334 flip_addr
|= OFC_UPDATE
;
336 /* wait for overlay to go idle */
337 overlay
->hw_wedged
= SWITCH_OFF_STAGE_1
;
340 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
342 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
346 overlay
->last_flip_req
=
347 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
348 if (overlay
->last_flip_req
== 0)
351 ret
= i915_do_wait_request(dev
,
352 overlay
->last_flip_req
, true,
353 &dev_priv
->render_ring
);
357 /* turn overlay off */
358 overlay
->hw_wedged
= SWITCH_OFF_STAGE_2
;
361 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
363 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
367 overlay
->last_flip_req
=
368 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
369 if (overlay
->last_flip_req
== 0)
372 ret
= i915_do_wait_request(dev
,
373 overlay
->last_flip_req
, true,
374 &dev_priv
->render_ring
);
378 overlay
->hw_wedged
= 0;
379 overlay
->last_flip_req
= 0;
383 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
385 struct drm_gem_object
*obj
;
387 /* never have the overlay hw on without showing a frame */
388 BUG_ON(!overlay
->vid_bo
);
389 obj
= &overlay
->vid_bo
->base
;
391 i915_gem_object_unpin(obj
);
392 drm_gem_object_unreference(obj
);
393 overlay
->vid_bo
= NULL
;
395 overlay
->crtc
->overlay
= NULL
;
396 overlay
->crtc
= NULL
;
400 /* recover from an interruption due to a signal
401 * We have to be careful not to repeat work forever an make forward progess. */
402 int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
,
405 struct drm_device
*dev
= overlay
->dev
;
406 struct drm_gem_object
*obj
;
407 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
411 if (overlay
->hw_wedged
== HW_WEDGED
)
414 if (overlay
->last_flip_req
== 0) {
415 overlay
->last_flip_req
=
416 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
417 if (overlay
->last_flip_req
== 0)
421 ret
= i915_do_wait_request(dev
, overlay
->last_flip_req
,
422 interruptible
, &dev_priv
->render_ring
);
426 switch (overlay
->hw_wedged
) {
427 case RELEASE_OLD_VID
:
428 obj
= &overlay
->old_vid_bo
->base
;
429 i915_gem_object_unpin(obj
);
430 drm_gem_object_unreference(obj
);
431 overlay
->old_vid_bo
= NULL
;
433 case SWITCH_OFF_STAGE_1
:
434 flip_addr
= overlay
->flip_addr
;
435 flip_addr
|= OFC_UPDATE
;
437 overlay
->hw_wedged
= SWITCH_OFF_STAGE_2
;
440 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
442 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
446 overlay
->last_flip_req
=
447 i915_add_request(dev
, NULL
,
448 &dev_priv
->render_ring
);
449 if (overlay
->last_flip_req
== 0)
452 ret
= i915_do_wait_request(dev
, overlay
->last_flip_req
,
454 &dev_priv
->render_ring
);
458 case SWITCH_OFF_STAGE_2
:
459 intel_overlay_off_tail(overlay
);
462 BUG_ON(overlay
->hw_wedged
!= NEEDS_WAIT_FOR_FLIP
);
465 overlay
->hw_wedged
= 0;
466 overlay
->last_flip_req
= 0;
470 /* Wait for pending overlay flip and release old frame.
471 * Needs to be called before the overlay register are changed
472 * via intel_overlay_(un)map_regs_atomic */
473 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
476 struct drm_gem_object
*obj
;
478 /* only wait if there is actually an old frame to release to
479 * guarantee forward progress */
480 if (!overlay
->old_vid_bo
)
483 ret
= intel_overlay_wait_flip(overlay
);
487 obj
= &overlay
->old_vid_bo
->base
;
488 i915_gem_object_unpin(obj
);
489 drm_gem_object_unreference(obj
);
490 overlay
->old_vid_bo
= NULL
;
495 struct put_image_params
{
512 static int packed_depth_bytes(u32 format
)
514 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
515 case I915_OVERLAY_YUV422
:
517 case I915_OVERLAY_YUV411
:
518 /* return 6; not implemented */
524 static int packed_width_bytes(u32 format
, short width
)
526 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
527 case I915_OVERLAY_YUV422
:
534 static int uv_hsubsampling(u32 format
)
536 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
537 case I915_OVERLAY_YUV422
:
538 case I915_OVERLAY_YUV420
:
540 case I915_OVERLAY_YUV411
:
541 case I915_OVERLAY_YUV410
:
548 static int uv_vsubsampling(u32 format
)
550 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
551 case I915_OVERLAY_YUV420
:
552 case I915_OVERLAY_YUV410
:
554 case I915_OVERLAY_YUV422
:
555 case I915_OVERLAY_YUV411
:
562 static u32
calc_swidthsw(struct drm_device
*dev
, u32 offset
, u32 width
)
564 u32 mask
, shift
, ret
;
572 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
579 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
580 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
581 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
582 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
583 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
584 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
585 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
586 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
587 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
588 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
589 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
590 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
591 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
592 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
593 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
594 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
595 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
596 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
599 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
600 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
601 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
602 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
603 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
604 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
605 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
606 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
607 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
608 0x3000, 0x0800, 0x3000
611 static void update_polyphase_filter(struct overlay_registers
*regs
)
613 memcpy(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
614 memcpy(regs
->UV_HCOEFS
, uv_static_hcoeffs
, sizeof(uv_static_hcoeffs
));
617 static bool update_scaling_factors(struct intel_overlay
*overlay
,
618 struct overlay_registers
*regs
,
619 struct put_image_params
*params
)
621 /* fixed point with a 12 bit shift */
622 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
624 #define FRACT_MASK 0xfff
625 bool scale_changed
= false;
626 int uv_hscale
= uv_hsubsampling(params
->format
);
627 int uv_vscale
= uv_vsubsampling(params
->format
);
629 if (params
->dst_w
> 1)
630 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
633 xscale
= 1 << FP_SHIFT
;
635 if (params
->dst_h
> 1)
636 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
639 yscale
= 1 << FP_SHIFT
;
641 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
642 xscale_UV
= xscale
/uv_hscale
;
643 yscale_UV
= yscale
/uv_vscale
;
644 /* make the Y scale to UV scale ratio an exact multiply */
645 xscale
= xscale_UV
* uv_hscale
;
646 yscale
= yscale_UV
* uv_vscale
;
652 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
653 scale_changed
= true;
654 overlay
->old_xscale
= xscale
;
655 overlay
->old_yscale
= yscale
;
657 regs
->YRGBSCALE
= (((yscale
& FRACT_MASK
) << 20) |
658 ((xscale
>> FP_SHIFT
) << 16) |
659 ((xscale
& FRACT_MASK
) << 3));
661 regs
->UVSCALE
= (((yscale_UV
& FRACT_MASK
) << 20) |
662 ((xscale_UV
>> FP_SHIFT
) << 16) |
663 ((xscale_UV
& FRACT_MASK
) << 3));
665 regs
->UVSCALEV
= ((((yscale
>> FP_SHIFT
) << 16) |
666 ((yscale_UV
>> FP_SHIFT
) << 0)));
669 update_polyphase_filter(regs
);
671 return scale_changed
;
674 static void update_colorkey(struct intel_overlay
*overlay
,
675 struct overlay_registers
*regs
)
677 u32 key
= overlay
->color_key
;
679 switch (overlay
->crtc
->base
.fb
->bits_per_pixel
) {
682 regs
->DCLRKM
= CLK_RGB8I_MASK
| DST_KEY_ENABLE
;
686 if (overlay
->crtc
->base
.fb
->depth
== 15) {
687 regs
->DCLRKV
= RGB15_TO_COLORKEY(key
);
688 regs
->DCLRKM
= CLK_RGB15_MASK
| DST_KEY_ENABLE
;
690 regs
->DCLRKV
= RGB16_TO_COLORKEY(key
);
691 regs
->DCLRKM
= CLK_RGB16_MASK
| DST_KEY_ENABLE
;
698 regs
->DCLRKM
= CLK_RGB24_MASK
| DST_KEY_ENABLE
;
703 static u32
overlay_cmd_reg(struct put_image_params
*params
)
705 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
707 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
708 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
709 case I915_OVERLAY_YUV422
:
710 cmd
|= OCMD_YUV_422_PLANAR
;
712 case I915_OVERLAY_YUV420
:
713 cmd
|= OCMD_YUV_420_PLANAR
;
715 case I915_OVERLAY_YUV411
:
716 case I915_OVERLAY_YUV410
:
717 cmd
|= OCMD_YUV_410_PLANAR
;
720 } else { /* YUV packed */
721 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
722 case I915_OVERLAY_YUV422
:
723 cmd
|= OCMD_YUV_422_PACKED
;
725 case I915_OVERLAY_YUV411
:
726 cmd
|= OCMD_YUV_411_PACKED
;
730 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
731 case I915_OVERLAY_NO_SWAP
:
733 case I915_OVERLAY_UV_SWAP
:
736 case I915_OVERLAY_Y_SWAP
:
739 case I915_OVERLAY_Y_AND_UV_SWAP
:
740 cmd
|= OCMD_Y_AND_UV_SWAP
;
748 int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
749 struct drm_gem_object
*new_bo
,
750 struct put_image_params
*params
)
753 struct overlay_registers
*regs
;
754 bool scale_changed
= false;
755 struct drm_i915_gem_object
*bo_priv
= to_intel_bo(new_bo
);
756 struct drm_device
*dev
= overlay
->dev
;
758 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
759 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
762 ret
= intel_overlay_release_old_vid(overlay
);
766 ret
= i915_gem_object_pin(new_bo
, PAGE_SIZE
);
770 ret
= i915_gem_object_set_to_gtt_domain(new_bo
, 0);
774 if (!overlay
->active
) {
775 regs
= intel_overlay_map_regs_atomic(overlay
);
780 regs
->OCONFIG
= OCONF_CC_OUT_8BIT
;
781 if (IS_I965GM(overlay
->dev
))
782 regs
->OCONFIG
|= OCONF_CSC_MODE_BT709
;
783 regs
->OCONFIG
|= overlay
->crtc
->pipe
== 0 ?
784 OCONF_PIPE_A
: OCONF_PIPE_B
;
785 intel_overlay_unmap_regs_atomic(overlay
);
787 ret
= intel_overlay_on(overlay
);
792 regs
= intel_overlay_map_regs_atomic(overlay
);
798 regs
->DWINPOS
= (params
->dst_y
<< 16) | params
->dst_x
;
799 regs
->DWINSZ
= (params
->dst_h
<< 16) | params
->dst_w
;
801 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
802 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
804 tmp_width
= params
->src_w
;
806 regs
->SWIDTH
= params
->src_w
;
807 regs
->SWIDTHSW
= calc_swidthsw(overlay
->dev
,
808 params
->offset_Y
, tmp_width
);
809 regs
->SHEIGHT
= params
->src_h
;
810 regs
->OBUF_0Y
= bo_priv
->gtt_offset
+ params
-> offset_Y
;
811 regs
->OSTRIDE
= params
->stride_Y
;
813 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
814 int uv_hscale
= uv_hsubsampling(params
->format
);
815 int uv_vscale
= uv_vsubsampling(params
->format
);
817 regs
->SWIDTH
|= (params
->src_w
/uv_hscale
) << 16;
818 tmp_U
= calc_swidthsw(overlay
->dev
, params
->offset_U
,
819 params
->src_w
/uv_hscale
);
820 tmp_V
= calc_swidthsw(overlay
->dev
, params
->offset_V
,
821 params
->src_w
/uv_hscale
);
822 regs
->SWIDTHSW
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
823 regs
->SHEIGHT
|= (params
->src_h
/uv_vscale
) << 16;
824 regs
->OBUF_0U
= bo_priv
->gtt_offset
+ params
->offset_U
;
825 regs
->OBUF_0V
= bo_priv
->gtt_offset
+ params
->offset_V
;
826 regs
->OSTRIDE
|= params
->stride_UV
<< 16;
829 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
831 update_colorkey(overlay
, regs
);
833 regs
->OCMD
= overlay_cmd_reg(params
);
835 intel_overlay_unmap_regs_atomic(overlay
);
837 intel_overlay_continue(overlay
, scale_changed
);
839 overlay
->old_vid_bo
= overlay
->vid_bo
;
840 overlay
->vid_bo
= to_intel_bo(new_bo
);
845 i915_gem_object_unpin(new_bo
);
849 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
852 struct overlay_registers
*regs
;
853 struct drm_device
*dev
= overlay
->dev
;
855 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
856 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
858 if (overlay
->hw_wedged
) {
859 ret
= intel_overlay_recover_from_interrupt(overlay
, 1);
864 if (!overlay
->active
)
867 ret
= intel_overlay_release_old_vid(overlay
);
871 regs
= intel_overlay_map_regs_atomic(overlay
);
873 intel_overlay_unmap_regs_atomic(overlay
);
875 ret
= intel_overlay_off(overlay
);
879 intel_overlay_off_tail(overlay
);
884 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
885 struct intel_crtc
*crtc
)
887 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
889 int pipeconf_reg
= (crtc
->pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
891 if (!crtc
->base
.enabled
|| crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
)
894 pipeconf
= I915_READ(pipeconf_reg
);
896 /* can't use the overlay with double wide pipe */
897 if (!IS_I965G(overlay
->dev
) && pipeconf
& PIPEACONF_DOUBLE_WIDE
)
903 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
905 struct drm_device
*dev
= overlay
->dev
;
906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
908 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
910 /* XXX: This is not the same logic as in the xorg driver, but more in
911 * line with the intel documentation for the i965 */
912 if (!IS_I965G(dev
) && (pfit_control
& VERT_AUTO_SCALE
)) {
913 ratio
= I915_READ(PFIT_AUTO_RATIOS
) >> PFIT_VERT_SCALE_SHIFT
;
914 } else { /* on i965 use the PGM reg to read out the autoscaler values */
915 ratio
= I915_READ(PFIT_PGM_RATIOS
);
917 ratio
>>= PFIT_VERT_SCALE_SHIFT_965
;
919 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
922 overlay
->pfit_vscale_ratio
= ratio
;
925 static int check_overlay_dst(struct intel_overlay
*overlay
,
926 struct drm_intel_overlay_put_image
*rec
)
928 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
930 if (rec
->dst_x
< mode
->crtc_hdisplay
&&
931 rec
->dst_x
+ rec
->dst_width
<= mode
->crtc_hdisplay
&&
932 rec
->dst_y
< mode
->crtc_vdisplay
&&
933 rec
->dst_y
+ rec
->dst_height
<= mode
->crtc_vdisplay
)
939 static int check_overlay_scaling(struct put_image_params
*rec
)
943 /* downscaling limit is 8.0 */
944 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
947 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
954 static int check_overlay_src(struct drm_device
*dev
,
955 struct drm_intel_overlay_put_image
*rec
,
956 struct drm_gem_object
*new_bo
)
960 int uv_hscale
= uv_hsubsampling(rec
->flags
);
961 int uv_vscale
= uv_vsubsampling(rec
->flags
);
964 /* check src dimensions */
965 if (IS_845G(dev
) || IS_I830(dev
)) {
966 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
967 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
970 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
971 rec
->src_width
> IMAGE_MAX_WIDTH
)
974 /* better safe than sorry, use 4 as the maximal subsampling ratio */
975 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
976 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
979 /* check alignment constraints */
980 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
981 case I915_OVERLAY_RGB
:
982 /* not implemented */
984 case I915_OVERLAY_YUV_PACKED
:
985 depth
= packed_depth_bytes(rec
->flags
);
990 /* ignore UV planes */
994 /* check pixel alignment */
995 if (rec
->offset_Y
% depth
)
998 case I915_OVERLAY_YUV_PLANAR
:
999 if (uv_vscale
< 0 || uv_hscale
< 0)
1001 /* no offset restrictions for planar formats */
1007 if (rec
->src_width
% uv_hscale
)
1010 /* stride checking */
1011 if (IS_I830(dev
) || IS_845G(dev
))
1016 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1018 if (IS_I965G(dev
) && rec
->stride_Y
< 512)
1021 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1023 if (rec
->stride_Y
> tmp
*1024 || rec
->stride_UV
> 2*1024)
1026 /* check buffer dimensions */
1027 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1028 case I915_OVERLAY_RGB
:
1029 case I915_OVERLAY_YUV_PACKED
:
1030 /* always 4 Y values per depth pixels */
1031 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1034 tmp
= rec
->stride_Y
*rec
->src_height
;
1035 if (rec
->offset_Y
+ tmp
> new_bo
->size
)
1039 case I915_OVERLAY_YUV_PLANAR
:
1040 if (rec
->src_width
> rec
->stride_Y
)
1042 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1045 tmp
= rec
->stride_Y
*rec
->src_height
;
1046 if (rec
->offset_Y
+ tmp
> new_bo
->size
)
1048 tmp
= rec
->stride_UV
*rec
->src_height
;
1050 if (rec
->offset_U
+ tmp
> new_bo
->size
||
1051 rec
->offset_V
+ tmp
> new_bo
->size
)
1059 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1060 struct drm_file
*file_priv
)
1062 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1063 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1064 struct intel_overlay
*overlay
;
1065 struct drm_mode_object
*drmmode_obj
;
1066 struct intel_crtc
*crtc
;
1067 struct drm_gem_object
*new_bo
;
1068 struct put_image_params
*params
;
1072 DRM_ERROR("called with no initialization\n");
1076 overlay
= dev_priv
->overlay
;
1078 DRM_DEBUG("userspace bug: no overlay\n");
1082 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1083 mutex_lock(&dev
->mode_config
.mutex
);
1084 mutex_lock(&dev
->struct_mutex
);
1086 ret
= intel_overlay_switch_off(overlay
);
1088 mutex_unlock(&dev
->struct_mutex
);
1089 mutex_unlock(&dev
->mode_config
.mutex
);
1094 params
= kmalloc(sizeof(struct put_image_params
), GFP_KERNEL
);
1098 drmmode_obj
= drm_mode_object_find(dev
, put_image_rec
->crtc_id
,
1099 DRM_MODE_OBJECT_CRTC
);
1104 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
1106 new_bo
= drm_gem_object_lookup(dev
, file_priv
,
1107 put_image_rec
->bo_handle
);
1113 mutex_lock(&dev
->mode_config
.mutex
);
1114 mutex_lock(&dev
->struct_mutex
);
1116 if (overlay
->hw_wedged
) {
1117 ret
= intel_overlay_recover_from_interrupt(overlay
, 1);
1122 if (overlay
->crtc
!= crtc
) {
1123 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1124 ret
= intel_overlay_switch_off(overlay
);
1128 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1132 overlay
->crtc
= crtc
;
1133 crtc
->overlay
= overlay
;
1135 if (intel_panel_fitter_pipe(dev
) == crtc
->pipe
1136 /* and line to wide, i.e. one-line-mode */
1137 && mode
->hdisplay
> 1024) {
1138 overlay
->pfit_active
= 1;
1139 update_pfit_vscale_ratio(overlay
);
1141 overlay
->pfit_active
= 0;
1144 ret
= check_overlay_dst(overlay
, put_image_rec
);
1148 if (overlay
->pfit_active
) {
1149 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1150 overlay
->pfit_vscale_ratio
);
1151 /* shifting right rounds downwards, so add 1 */
1152 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1153 overlay
->pfit_vscale_ratio
) + 1;
1155 params
->dst_y
= put_image_rec
->dst_y
;
1156 params
->dst_h
= put_image_rec
->dst_height
;
1158 params
->dst_x
= put_image_rec
->dst_x
;
1159 params
->dst_w
= put_image_rec
->dst_width
;
1161 params
->src_w
= put_image_rec
->src_width
;
1162 params
->src_h
= put_image_rec
->src_height
;
1163 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1164 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1165 if (params
->src_scan_h
> params
->src_h
||
1166 params
->src_scan_w
> params
->src_w
) {
1171 ret
= check_overlay_src(dev
, put_image_rec
, new_bo
);
1174 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1175 params
->stride_Y
= put_image_rec
->stride_Y
;
1176 params
->stride_UV
= put_image_rec
->stride_UV
;
1177 params
->offset_Y
= put_image_rec
->offset_Y
;
1178 params
->offset_U
= put_image_rec
->offset_U
;
1179 params
->offset_V
= put_image_rec
->offset_V
;
1181 /* Check scaling after src size to prevent a divide-by-zero. */
1182 ret
= check_overlay_scaling(params
);
1186 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1190 mutex_unlock(&dev
->struct_mutex
);
1191 mutex_unlock(&dev
->mode_config
.mutex
);
1198 mutex_unlock(&dev
->struct_mutex
);
1199 mutex_unlock(&dev
->mode_config
.mutex
);
1200 drm_gem_object_unreference_unlocked(new_bo
);
1207 static void update_reg_attrs(struct intel_overlay
*overlay
,
1208 struct overlay_registers
*regs
)
1210 regs
->OCLRC0
= (overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff);
1211 regs
->OCLRC1
= overlay
->saturation
;
1214 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1218 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1221 for (i
= 0; i
< 3; i
++) {
1222 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1229 static bool check_gamma5_errata(u32 gamma5
)
1233 for (i
= 0; i
< 3; i
++) {
1234 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1241 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1243 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1244 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1245 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1246 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1247 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1248 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1249 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1252 if (!check_gamma5_errata(attrs
->gamma5
))
1258 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1259 struct drm_file
*file_priv
)
1261 struct drm_intel_overlay_attrs
*attrs
= data
;
1262 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1263 struct intel_overlay
*overlay
;
1264 struct overlay_registers
*regs
;
1268 DRM_ERROR("called with no initialization\n");
1272 overlay
= dev_priv
->overlay
;
1274 DRM_DEBUG("userspace bug: no overlay\n");
1278 mutex_lock(&dev
->mode_config
.mutex
);
1279 mutex_lock(&dev
->struct_mutex
);
1281 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1282 attrs
->color_key
= overlay
->color_key
;
1283 attrs
->brightness
= overlay
->brightness
;
1284 attrs
->contrast
= overlay
->contrast
;
1285 attrs
->saturation
= overlay
->saturation
;
1288 attrs
->gamma0
= I915_READ(OGAMC0
);
1289 attrs
->gamma1
= I915_READ(OGAMC1
);
1290 attrs
->gamma2
= I915_READ(OGAMC2
);
1291 attrs
->gamma3
= I915_READ(OGAMC3
);
1292 attrs
->gamma4
= I915_READ(OGAMC4
);
1293 attrs
->gamma5
= I915_READ(OGAMC5
);
1297 overlay
->color_key
= attrs
->color_key
;
1298 if (attrs
->brightness
>= -128 && attrs
->brightness
<= 127) {
1299 overlay
->brightness
= attrs
->brightness
;
1305 if (attrs
->contrast
<= 255) {
1306 overlay
->contrast
= attrs
->contrast
;
1312 if (attrs
->saturation
<= 1023) {
1313 overlay
->saturation
= attrs
->saturation
;
1319 regs
= intel_overlay_map_regs_atomic(overlay
);
1325 update_reg_attrs(overlay
, regs
);
1327 intel_overlay_unmap_regs_atomic(overlay
);
1329 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1330 if (!IS_I9XX(dev
)) {
1335 if (overlay
->active
) {
1340 ret
= check_gamma(attrs
);
1344 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1345 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1346 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1347 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1348 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1349 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1355 mutex_unlock(&dev
->struct_mutex
);
1356 mutex_unlock(&dev
->mode_config
.mutex
);
1361 void intel_setup_overlay(struct drm_device
*dev
)
1363 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1364 struct intel_overlay
*overlay
;
1365 struct drm_gem_object
*reg_bo
;
1366 struct overlay_registers
*regs
;
1369 if (!OVERLAY_EXISTS(dev
))
1372 overlay
= kzalloc(sizeof(struct intel_overlay
), GFP_KERNEL
);
1377 reg_bo
= i915_gem_alloc_object(dev
, PAGE_SIZE
);
1380 overlay
->reg_bo
= to_intel_bo(reg_bo
);
1382 if (OVERLAY_NONPHYSICAL(dev
)) {
1383 ret
= i915_gem_object_pin(reg_bo
, PAGE_SIZE
);
1385 DRM_ERROR("failed to pin overlay register bo\n");
1388 overlay
->flip_addr
= overlay
->reg_bo
->gtt_offset
;
1390 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1392 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1396 ret
= i915_gem_attach_phys_object(dev
, reg_bo
,
1397 I915_GEM_PHYS_OVERLAY_REGS
,
1400 DRM_ERROR("failed to attach phys overlay regs\n");
1403 overlay
->flip_addr
= overlay
->reg_bo
->phys_obj
->handle
->busaddr
;
1406 /* init all values */
1407 overlay
->color_key
= 0x0101fe;
1408 overlay
->brightness
= -19;
1409 overlay
->contrast
= 75;
1410 overlay
->saturation
= 146;
1412 regs
= intel_overlay_map_regs_atomic(overlay
);
1416 memset(regs
, 0, sizeof(struct overlay_registers
));
1417 update_polyphase_filter(regs
);
1419 update_reg_attrs(overlay
, regs
);
1421 intel_overlay_unmap_regs_atomic(overlay
);
1423 dev_priv
->overlay
= overlay
;
1424 DRM_INFO("initialized overlay support\n");
1428 i915_gem_object_unpin(reg_bo
);
1430 drm_gem_object_unreference(reg_bo
);
1436 void intel_cleanup_overlay(struct drm_device
*dev
)
1438 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1440 if (dev_priv
->overlay
) {
1441 /* The bo's should be free'd by the generic code already.
1442 * Furthermore modesetting teardown happens beforehand so the
1443 * hardware should be off already */
1444 BUG_ON(dev_priv
->overlay
->active
);
1446 kfree(dev_priv
->overlay
);
1450 struct intel_overlay_error_state
{
1451 struct overlay_registers regs
;
1457 struct intel_overlay_error_state
*
1458 intel_overlay_capture_error_state(struct drm_device
*dev
)
1460 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1461 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1462 struct intel_overlay_error_state
*error
;
1463 struct overlay_registers __iomem
*regs
;
1465 if (!overlay
|| !overlay
->active
)
1468 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1472 error
->dovsta
= I915_READ(DOVSTA
);
1473 error
->isr
= I915_READ(ISR
);
1474 if (OVERLAY_NONPHYSICAL(overlay
->dev
))
1475 error
->base
= (long) overlay
->reg_bo
->gtt_offset
;
1477 error
->base
= (long) overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1479 regs
= intel_overlay_map_regs_atomic(overlay
);
1483 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1484 intel_overlay_unmap_regs_atomic(overlay
);
1494 intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
)
1496 seq_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1497 error
->dovsta
, error
->isr
);
1498 seq_printf(m
, " Register file at 0x%08lx:\n",
1501 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)