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MIPS: Add Cavium OCTEON processor constants and CPU probe.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / mips / kernel / cpu-probe.c
blob6b3c63dd181867179d879720eb163ced08cf3329
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
18
19 #include <asm/bugs.h>
20 #include <asm/cpu.h>
21 #include <asm/fpu.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
24 #include <asm/watch.h>
25
26 /*
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
31 * the CPU very much.
32 */
33 void (*cpu_wait)(void) = NULL;
34
35 static void r3081_wait(void)
36 {
37 unsigned long cfg = read_c0_conf();
38 write_c0_conf(cfg | R30XX_CONF_HALT);
39 }
40
41 static void r39xx_wait(void)
42 {
43 local_irq_disable();
44 if (!need_resched())
45 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
46 local_irq_enable();
47 }
48
49 extern void r4k_wait(void);
50
51 /*
52 * This variant is preferable as it allows testing need_resched and going to
53 * sleep depending on the outcome atomically. Unfortunately the "It is
54 * implementation-dependent whether the pipeline restarts when a non-enabled
55 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
56 * using this version a gamble.
57 */
58 void r4k_wait_irqoff(void)
59 {
60 local_irq_disable();
61 if (!need_resched())
62 __asm__(" .set push \n"
63 " .set mips3 \n"
64 " wait \n"
65 " .set pop \n");
66 local_irq_enable();
67 __asm__(" .globl __pastwait \n"
68 "__pastwait: \n");
69 return;
70 }
71
72 /*
73 * The RM7000 variant has to handle erratum 38. The workaround is to not
74 * have any pending stores when the WAIT instruction is executed.
75 */
76 static void rm7k_wait_irqoff(void)
77 {
78 local_irq_disable();
79 if (!need_resched())
80 __asm__(
81 " .set push \n"
82 " .set mips3 \n"
83 " .set noat \n"
84 " mfc0 $1, $12 \n"
85 " sync \n"
86 " mtc0 $1, $12 # stalls until W stage \n"
87 " wait \n"
88 " mtc0 $1, $12 # stalls until W stage \n"
89 " .set pop \n");
90 local_irq_enable();
91 }
92
93 /* The Au1xxx wait is available only if using 32khz counter or
94 * external timer source, but specifically not CP0 Counter. */
95 int allow_au1k_wait;
96
97 static void au1k_wait(void)
98 {
99 /* using the wait instruction makes CP0 counter unusable */
100 __asm__(" .set mips3 \n"
101 " cache 0x14, 0(%0) \n"
102 " cache 0x14, 32(%0) \n"
103 " sync \n"
104 " nop \n"
105 " wait \n"
106 " nop \n"
107 " nop \n"
108 " nop \n"
109 " nop \n"
110 " .set mips0 \n"
111 : : "r" (au1k_wait));
112 }
113
114 static int __initdata nowait = 0;
115
116 static int __init wait_disable(char *s)
117 {
118 nowait = 1;
119
120 return 1;
121 }
122
123 __setup("nowait", wait_disable);
124
125 void __init check_wait(void)
126 {
127 struct cpuinfo_mips *c = &current_cpu_data;
128
129 if (nowait) {
130 printk("Wait instruction disabled.\n");
131 return;
132 }
133
134 switch (c->cputype) {
135 case CPU_R3081:
136 case CPU_R3081E:
137 cpu_wait = r3081_wait;
138 break;
139 case CPU_TX3927:
140 cpu_wait = r39xx_wait;
141 break;
142 case CPU_R4200:
143 /* case CPU_R4300: */
144 case CPU_R4600:
145 case CPU_R4640:
146 case CPU_R4650:
147 case CPU_R4700:
148 case CPU_R5000:
149 case CPU_NEVADA:
150 case CPU_4KC:
151 case CPU_4KEC:
152 case CPU_4KSC:
153 case CPU_5KC:
154 case CPU_25KF:
155 case CPU_PR4450:
156 case CPU_BCM3302:
157 case CPU_CAVIUM_OCTEON:
158 cpu_wait = r4k_wait;
159 break;
160
161 case CPU_RM7000:
162 cpu_wait = rm7k_wait_irqoff;
163 break;
164
165 case CPU_24K:
166 case CPU_34K:
167 case CPU_1004K:
168 cpu_wait = r4k_wait;
169 if (read_c0_config7() & MIPS_CONF7_WII)
170 cpu_wait = r4k_wait_irqoff;
171 break;
172
173 case CPU_74K:
174 cpu_wait = r4k_wait;
175 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
176 cpu_wait = r4k_wait_irqoff;
177 break;
178
179 case CPU_TX49XX:
180 cpu_wait = r4k_wait_irqoff;
181 break;
182 case CPU_AU1000:
183 case CPU_AU1100:
184 case CPU_AU1500:
185 case CPU_AU1550:
186 case CPU_AU1200:
187 case CPU_AU1210:
188 case CPU_AU1250:
189 if (allow_au1k_wait)
190 cpu_wait = au1k_wait;
191 break;
192 case CPU_20KC:
193 /*
194 * WAIT on Rev1.0 has E1, E2, E3 and E16.
195 * WAIT on Rev2.0 and Rev3.0 has E16.
196 * Rev3.1 WAIT is nop, why bother
197 */
198 if ((c->processor_id & 0xff) <= 0x64)
199 break;
200
201 /*
202 * Another rev is incremeting c0_count at a reduced clock
203 * rate while in WAIT mode. So we basically have the choice
204 * between using the cp0 timer as clocksource or avoiding
205 * the WAIT instruction. Until more details are known,
206 * disable the use of WAIT for 20Kc entirely.
207 cpu_wait = r4k_wait;
208 */
209 break;
210 case CPU_RM9000:
211 if ((c->processor_id & 0x00ff) >= 0x40)
212 cpu_wait = r4k_wait;
213 break;
214 default:
215 break;
216 }
217 }
218
219 static inline void check_errata(void)
220 {
221 struct cpuinfo_mips *c = &current_cpu_data;
222
223 switch (c->cputype) {
224 case CPU_34K:
225 /*
226 * Erratum "RPS May Cause Incorrect Instruction Execution"
227 * This code only handles VPE0, any SMP/SMTC/RTOS code
228 * making use of VPE1 will be responsable for that VPE.
229 */
230 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
231 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
232 break;
233 default:
234 break;
235 }
236 }
237
238 void __init check_bugs32(void)
239 {
240 check_errata();
241 }
242
243 /*
244 * Probe whether cpu has config register by trying to play with
245 * alternate cache bit and see whether it matters.
246 * It's used by cpu_probe to distinguish between R3000A and R3081.
247 */
248 static inline int cpu_has_confreg(void)
249 {
250 #ifdef CONFIG_CPU_R3000
251 extern unsigned long r3k_cache_size(unsigned long);
252 unsigned long size1, size2;
253 unsigned long cfg = read_c0_conf();
254
255 size1 = r3k_cache_size(ST0_ISC);
256 write_c0_conf(cfg ^ R30XX_CONF_AC);
257 size2 = r3k_cache_size(ST0_ISC);
258 write_c0_conf(cfg);
259 return size1 != size2;
260 #else
261 return 0;
262 #endif
263 }
264
265 /*
266 * Get the FPU Implementation/Revision.
267 */
268 static inline unsigned long cpu_get_fpu_id(void)
269 {
270 unsigned long tmp, fpu_id;
271
272 tmp = read_c0_status();
273 __enable_fpu();
274 fpu_id = read_32bit_cp1_register(CP1_REVISION);
275 write_c0_status(tmp);
276 return fpu_id;
277 }
278
279 /*
280 * Check the CPU has an FPU the official way.
281 */
282 static inline int __cpu_has_fpu(void)
283 {
284 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
285 }
286
287 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
288 | MIPS_CPU_COUNTER)
289
290 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
291 {
292 switch (c->processor_id & 0xff00) {
293 case PRID_IMP_R2000:
294 c->cputype = CPU_R2000;
295 __cpu_name[cpu] = "R2000";
296 c->isa_level = MIPS_CPU_ISA_I;
297 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
298 MIPS_CPU_NOFPUEX;
299 if (__cpu_has_fpu())
300 c->options |= MIPS_CPU_FPU;
301 c->tlbsize = 64;
302 break;
303 case PRID_IMP_R3000:
304 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
305 if (cpu_has_confreg()) {
306 c->cputype = CPU_R3081E;
307 __cpu_name[cpu] = "R3081";
308 } else {
309 c->cputype = CPU_R3000A;
310 __cpu_name[cpu] = "R3000A";
311 }
312 break;
313 } else {
314 c->cputype = CPU_R3000;
315 __cpu_name[cpu] = "R3000";
316 }
317 c->isa_level = MIPS_CPU_ISA_I;
318 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
319 MIPS_CPU_NOFPUEX;
320 if (__cpu_has_fpu())
321 c->options |= MIPS_CPU_FPU;
322 c->tlbsize = 64;
323 break;
324 case PRID_IMP_R4000:
325 if (read_c0_config() & CONF_SC) {
326 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
327 c->cputype = CPU_R4400PC;
328 __cpu_name[cpu] = "R4400PC";
329 } else {
330 c->cputype = CPU_R4000PC;
331 __cpu_name[cpu] = "R4000PC";
332 }
333 } else {
334 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
335 c->cputype = CPU_R4400SC;
336 __cpu_name[cpu] = "R4400SC";
337 } else {
338 c->cputype = CPU_R4000SC;
339 __cpu_name[cpu] = "R4000SC";
340 }
341 }
342
343 c->isa_level = MIPS_CPU_ISA_III;
344 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
345 MIPS_CPU_WATCH | MIPS_CPU_VCE |
346 MIPS_CPU_LLSC;
347 c->tlbsize = 48;
348 break;
349 case PRID_IMP_VR41XX:
350 switch (c->processor_id & 0xf0) {
351 case PRID_REV_VR4111:
352 c->cputype = CPU_VR4111;
353 __cpu_name[cpu] = "NEC VR4111";
354 break;
355 case PRID_REV_VR4121:
356 c->cputype = CPU_VR4121;
357 __cpu_name[cpu] = "NEC VR4121";
358 break;
359 case PRID_REV_VR4122:
360 if ((c->processor_id & 0xf) < 0x3) {
361 c->cputype = CPU_VR4122;
362 __cpu_name[cpu] = "NEC VR4122";
363 } else {
364 c->cputype = CPU_VR4181A;
365 __cpu_name[cpu] = "NEC VR4181A";
366 }
367 break;
368 case PRID_REV_VR4130:
369 if ((c->processor_id & 0xf) < 0x4) {
370 c->cputype = CPU_VR4131;
371 __cpu_name[cpu] = "NEC VR4131";
372 } else {
373 c->cputype = CPU_VR4133;
374 __cpu_name[cpu] = "NEC VR4133";
375 }
376 break;
377 default:
378 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
379 c->cputype = CPU_VR41XX;
380 __cpu_name[cpu] = "NEC Vr41xx";
381 break;
382 }
383 c->isa_level = MIPS_CPU_ISA_III;
384 c->options = R4K_OPTS;
385 c->tlbsize = 32;
386 break;
387 case PRID_IMP_R4300:
388 c->cputype = CPU_R4300;
389 __cpu_name[cpu] = "R4300";
390 c->isa_level = MIPS_CPU_ISA_III;
391 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
392 MIPS_CPU_LLSC;
393 c->tlbsize = 32;
394 break;
395 case PRID_IMP_R4600:
396 c->cputype = CPU_R4600;
397 __cpu_name[cpu] = "R4600";
398 c->isa_level = MIPS_CPU_ISA_III;
399 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
400 MIPS_CPU_LLSC;
401 c->tlbsize = 48;
402 break;
403 #if 0
404 case PRID_IMP_R4650:
405 /*
406 * This processor doesn't have an MMU, so it's not
407 * "real easy" to run Linux on it. It is left purely
408 * for documentation. Commented out because it shares
409 * it's c0_prid id number with the TX3900.
410 */
411 c->cputype = CPU_R4650;
412 __cpu_name[cpu] = "R4650";
413 c->isa_level = MIPS_CPU_ISA_III;
414 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
415 c->tlbsize = 48;
416 break;
417 #endif
418 case PRID_IMP_TX39:
419 c->isa_level = MIPS_CPU_ISA_I;
420 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
421
422 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
423 c->cputype = CPU_TX3927;
424 __cpu_name[cpu] = "TX3927";
425 c->tlbsize = 64;
426 } else {
427 switch (c->processor_id & 0xff) {
428 case PRID_REV_TX3912:
429 c->cputype = CPU_TX3912;
430 __cpu_name[cpu] = "TX3912";
431 c->tlbsize = 32;
432 break;
433 case PRID_REV_TX3922:
434 c->cputype = CPU_TX3922;
435 __cpu_name[cpu] = "TX3922";
436 c->tlbsize = 64;
437 break;
438 }
439 }
440 break;
441 case PRID_IMP_R4700:
442 c->cputype = CPU_R4700;
443 __cpu_name[cpu] = "R4700";
444 c->isa_level = MIPS_CPU_ISA_III;
445 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
446 MIPS_CPU_LLSC;
447 c->tlbsize = 48;
448 break;
449 case PRID_IMP_TX49:
450 c->cputype = CPU_TX49XX;
451 __cpu_name[cpu] = "R49XX";
452 c->isa_level = MIPS_CPU_ISA_III;
453 c->options = R4K_OPTS | MIPS_CPU_LLSC;
454 if (!(c->processor_id & 0x08))
455 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
456 c->tlbsize = 48;
457 break;
458 case PRID_IMP_R5000:
459 c->cputype = CPU_R5000;
460 __cpu_name[cpu] = "R5000";
461 c->isa_level = MIPS_CPU_ISA_IV;
462 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
463 MIPS_CPU_LLSC;
464 c->tlbsize = 48;
465 break;
466 case PRID_IMP_R5432:
467 c->cputype = CPU_R5432;
468 __cpu_name[cpu] = "R5432";
469 c->isa_level = MIPS_CPU_ISA_IV;
470 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
471 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
472 c->tlbsize = 48;
473 break;
474 case PRID_IMP_R5500:
475 c->cputype = CPU_R5500;
476 __cpu_name[cpu] = "R5500";
477 c->isa_level = MIPS_CPU_ISA_IV;
478 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
479 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
480 c->tlbsize = 48;
481 break;
482 case PRID_IMP_NEVADA:
483 c->cputype = CPU_NEVADA;
484 __cpu_name[cpu] = "Nevada";
485 c->isa_level = MIPS_CPU_ISA_IV;
486 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
487 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
488 c->tlbsize = 48;
489 break;
490 case PRID_IMP_R6000:
491 c->cputype = CPU_R6000;
492 __cpu_name[cpu] = "R6000";
493 c->isa_level = MIPS_CPU_ISA_II;
494 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
495 MIPS_CPU_LLSC;
496 c->tlbsize = 32;
497 break;
498 case PRID_IMP_R6000A:
499 c->cputype = CPU_R6000A;
500 __cpu_name[cpu] = "R6000A";
501 c->isa_level = MIPS_CPU_ISA_II;
502 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
503 MIPS_CPU_LLSC;
504 c->tlbsize = 32;
505 break;
506 case PRID_IMP_RM7000:
507 c->cputype = CPU_RM7000;
508 __cpu_name[cpu] = "RM7000";
509 c->isa_level = MIPS_CPU_ISA_IV;
510 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
511 MIPS_CPU_LLSC;
512 /*
513 * Undocumented RM7000: Bit 29 in the info register of
514 * the RM7000 v2.0 indicates if the TLB has 48 or 64
515 * entries.
516 *
517 * 29 1 => 64 entry JTLB
518 * 0 => 48 entry JTLB
519 */
520 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
521 break;
522 case PRID_IMP_RM9000:
523 c->cputype = CPU_RM9000;
524 __cpu_name[cpu] = "RM9000";
525 c->isa_level = MIPS_CPU_ISA_IV;
526 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
527 MIPS_CPU_LLSC;
528 /*
529 * Bit 29 in the info register of the RM9000
530 * indicates if the TLB has 48 or 64 entries.
531 *
532 * 29 1 => 64 entry JTLB
533 * 0 => 48 entry JTLB
534 */
535 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
536 break;
537 case PRID_IMP_R8000:
538 c->cputype = CPU_R8000;
539 __cpu_name[cpu] = "RM8000";
540 c->isa_level = MIPS_CPU_ISA_IV;
541 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
542 MIPS_CPU_FPU | MIPS_CPU_32FPR |
543 MIPS_CPU_LLSC;
544 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
545 break;
546 case PRID_IMP_R10000:
547 c->cputype = CPU_R10000;
548 __cpu_name[cpu] = "R10000";
549 c->isa_level = MIPS_CPU_ISA_IV;
550 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
551 MIPS_CPU_FPU | MIPS_CPU_32FPR |
552 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
553 MIPS_CPU_LLSC;
554 c->tlbsize = 64;
555 break;
556 case PRID_IMP_R12000:
557 c->cputype = CPU_R12000;
558 __cpu_name[cpu] = "R12000";
559 c->isa_level = MIPS_CPU_ISA_IV;
560 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
561 MIPS_CPU_FPU | MIPS_CPU_32FPR |
562 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
563 MIPS_CPU_LLSC;
564 c->tlbsize = 64;
565 break;
566 case PRID_IMP_R14000:
567 c->cputype = CPU_R14000;
568 __cpu_name[cpu] = "R14000";
569 c->isa_level = MIPS_CPU_ISA_IV;
570 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
571 MIPS_CPU_FPU | MIPS_CPU_32FPR |
572 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
573 MIPS_CPU_LLSC;
574 c->tlbsize = 64;
575 break;
576 case PRID_IMP_LOONGSON2:
577 c->cputype = CPU_LOONGSON2;
578 __cpu_name[cpu] = "ICT Loongson-2";
579 c->isa_level = MIPS_CPU_ISA_III;
580 c->options = R4K_OPTS |
581 MIPS_CPU_FPU | MIPS_CPU_LLSC |
582 MIPS_CPU_32FPR;
583 c->tlbsize = 64;
584 break;
585 }
586 }
587
588 static char unknown_isa[] __cpuinitdata = KERN_ERR \
589 "Unsupported ISA type, c0.config0: %d.";
590
591 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
592 {
593 unsigned int config0;
594 int isa;
595
596 config0 = read_c0_config();
597
598 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
599 c->options |= MIPS_CPU_TLB;
600 isa = (config0 & MIPS_CONF_AT) >> 13;
601 switch (isa) {
602 case 0:
603 switch ((config0 & MIPS_CONF_AR) >> 10) {
604 case 0:
605 c->isa_level = MIPS_CPU_ISA_M32R1;
606 break;
607 case 1:
608 c->isa_level = MIPS_CPU_ISA_M32R2;
609 break;
610 default:
611 goto unknown;
612 }
613 break;
614 case 2:
615 switch ((config0 & MIPS_CONF_AR) >> 10) {
616 case 0:
617 c->isa_level = MIPS_CPU_ISA_M64R1;
618 break;
619 case 1:
620 c->isa_level = MIPS_CPU_ISA_M64R2;
621 break;
622 default:
623 goto unknown;
624 }
625 break;
626 default:
627 goto unknown;
628 }
629
630 return config0 & MIPS_CONF_M;
631
632 unknown:
633 panic(unknown_isa, config0);
634 }
635
636 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
637 {
638 unsigned int config1;
639
640 config1 = read_c0_config1();
641
642 if (config1 & MIPS_CONF1_MD)
643 c->ases |= MIPS_ASE_MDMX;
644 if (config1 & MIPS_CONF1_WR)
645 c->options |= MIPS_CPU_WATCH;
646 if (config1 & MIPS_CONF1_CA)
647 c->ases |= MIPS_ASE_MIPS16;
648 if (config1 & MIPS_CONF1_EP)
649 c->options |= MIPS_CPU_EJTAG;
650 if (config1 & MIPS_CONF1_FP) {
651 c->options |= MIPS_CPU_FPU;
652 c->options |= MIPS_CPU_32FPR;
653 }
654 if (cpu_has_tlb)
655 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
656
657 return config1 & MIPS_CONF_M;
658 }
659
660 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
661 {
662 unsigned int config2;
663
664 config2 = read_c0_config2();
665
666 if (config2 & MIPS_CONF2_SL)
667 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
668
669 return config2 & MIPS_CONF_M;
670 }
671
672 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
673 {
674 unsigned int config3;
675
676 config3 = read_c0_config3();
677
678 if (config3 & MIPS_CONF3_SM)
679 c->ases |= MIPS_ASE_SMARTMIPS;
680 if (config3 & MIPS_CONF3_DSP)
681 c->ases |= MIPS_ASE_DSP;
682 if (config3 & MIPS_CONF3_VINT)
683 c->options |= MIPS_CPU_VINT;
684 if (config3 & MIPS_CONF3_VEIC)
685 c->options |= MIPS_CPU_VEIC;
686 if (config3 & MIPS_CONF3_MT)
687 c->ases |= MIPS_ASE_MIPSMT;
688 if (config3 & MIPS_CONF3_ULRI)
689 c->options |= MIPS_CPU_ULRI;
690
691 return config3 & MIPS_CONF_M;
692 }
693
694 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
695 {
696 int ok;
697
698 /* MIPS32 or MIPS64 compliant CPU. */
699 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
700 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
701
702 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
703
704 ok = decode_config0(c); /* Read Config registers. */
705 BUG_ON(!ok); /* Arch spec violation! */
706 if (ok)
707 ok = decode_config1(c);
708 if (ok)
709 ok = decode_config2(c);
710 if (ok)
711 ok = decode_config3(c);
712
713 mips_probe_watch_registers(c);
714 }
715
716 #ifdef CONFIG_CPU_MIPSR2
717 extern void spram_config(void);
718 #else
719 static inline void spram_config(void) {}
720 #endif
721
722 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
723 {
724 decode_configs(c);
725 switch (c->processor_id & 0xff00) {
726 case PRID_IMP_4KC:
727 c->cputype = CPU_4KC;
728 __cpu_name[cpu] = "MIPS 4Kc";
729 break;
730 case PRID_IMP_4KEC:
731 c->cputype = CPU_4KEC;
732 __cpu_name[cpu] = "MIPS 4KEc";
733 break;
734 case PRID_IMP_4KECR2:
735 c->cputype = CPU_4KEC;
736 __cpu_name[cpu] = "MIPS 4KEc";
737 break;
738 case PRID_IMP_4KSC:
739 case PRID_IMP_4KSD:
740 c->cputype = CPU_4KSC;
741 __cpu_name[cpu] = "MIPS 4KSc";
742 break;
743 case PRID_IMP_5KC:
744 c->cputype = CPU_5KC;
745 __cpu_name[cpu] = "MIPS 5Kc";
746 break;
747 case PRID_IMP_20KC:
748 c->cputype = CPU_20KC;
749 __cpu_name[cpu] = "MIPS 20Kc";
750 break;
751 case PRID_IMP_24K:
752 case PRID_IMP_24KE:
753 c->cputype = CPU_24K;
754 __cpu_name[cpu] = "MIPS 24Kc";
755 break;
756 case PRID_IMP_25KF:
757 c->cputype = CPU_25KF;
758 __cpu_name[cpu] = "MIPS 25Kc";
759 break;
760 case PRID_IMP_34K:
761 c->cputype = CPU_34K;
762 __cpu_name[cpu] = "MIPS 34Kc";
763 break;
764 case PRID_IMP_74K:
765 c->cputype = CPU_74K;
766 __cpu_name[cpu] = "MIPS 74Kc";
767 break;
768 case PRID_IMP_1004K:
769 c->cputype = CPU_1004K;
770 __cpu_name[cpu] = "MIPS 1004Kc";
771 break;
772 }
773
774 spram_config();
775 }
776
777 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
778 {
779 decode_configs(c);
780 switch (c->processor_id & 0xff00) {
781 case PRID_IMP_AU1_REV1:
782 case PRID_IMP_AU1_REV2:
783 switch ((c->processor_id >> 24) & 0xff) {
784 case 0:
785 c->cputype = CPU_AU1000;
786 __cpu_name[cpu] = "Au1000";
787 break;
788 case 1:
789 c->cputype = CPU_AU1500;
790 __cpu_name[cpu] = "Au1500";
791 break;
792 case 2:
793 c->cputype = CPU_AU1100;
794 __cpu_name[cpu] = "Au1100";
795 break;
796 case 3:
797 c->cputype = CPU_AU1550;
798 __cpu_name[cpu] = "Au1550";
799 break;
800 case 4:
801 c->cputype = CPU_AU1200;
802 __cpu_name[cpu] = "Au1200";
803 if ((c->processor_id & 0xff) == 2) {
804 c->cputype = CPU_AU1250;
805 __cpu_name[cpu] = "Au1250";
806 }
807 break;
808 case 5:
809 c->cputype = CPU_AU1210;
810 __cpu_name[cpu] = "Au1210";
811 break;
812 default:
813 panic("Unknown Au Core!");
814 break;
815 }
816 break;
817 }
818 }
819
820 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
821 {
822 decode_configs(c);
823
824 switch (c->processor_id & 0xff00) {
825 case PRID_IMP_SB1:
826 c->cputype = CPU_SB1;
827 __cpu_name[cpu] = "SiByte SB1";
828 /* FPU in pass1 is known to have issues. */
829 if ((c->processor_id & 0xff) < 0x02)
830 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
831 break;
832 case PRID_IMP_SB1A:
833 c->cputype = CPU_SB1A;
834 __cpu_name[cpu] = "SiByte SB1A";
835 break;
836 }
837 }
838
839 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
840 {
841 decode_configs(c);
842 switch (c->processor_id & 0xff00) {
843 case PRID_IMP_SR71000:
844 c->cputype = CPU_SR71000;
845 __cpu_name[cpu] = "Sandcraft SR71000";
846 c->scache.ways = 8;
847 c->tlbsize = 64;
848 break;
849 }
850 }
851
852 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
853 {
854 decode_configs(c);
855 switch (c->processor_id & 0xff00) {
856 case PRID_IMP_PR4450:
857 c->cputype = CPU_PR4450;
858 __cpu_name[cpu] = "Philips PR4450";
859 c->isa_level = MIPS_CPU_ISA_M32R1;
860 break;
861 }
862 }
863
864 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
865 {
866 decode_configs(c);
867 switch (c->processor_id & 0xff00) {
868 case PRID_IMP_BCM3302:
869 c->cputype = CPU_BCM3302;
870 __cpu_name[cpu] = "Broadcom BCM3302";
871 break;
872 case PRID_IMP_BCM4710:
873 c->cputype = CPU_BCM4710;
874 __cpu_name[cpu] = "Broadcom BCM4710";
875 break;
876 }
877 }
878
879 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
880 {
881 decode_configs(c);
882 switch (c->processor_id & 0xff00) {
883 case PRID_IMP_CAVIUM_CN38XX:
884 case PRID_IMP_CAVIUM_CN31XX:
885 case PRID_IMP_CAVIUM_CN30XX:
886 case PRID_IMP_CAVIUM_CN58XX:
887 case PRID_IMP_CAVIUM_CN56XX:
888 case PRID_IMP_CAVIUM_CN50XX:
889 case PRID_IMP_CAVIUM_CN52XX:
890 c->cputype = CPU_CAVIUM_OCTEON;
891 __cpu_name[cpu] = "Cavium Octeon";
892 break;
893 default:
894 printk(KERN_INFO "Unknown Octeon chip!\n");
895 c->cputype = CPU_UNKNOWN;
896 break;
897 }
898 }
899
900 const char *__cpu_name[NR_CPUS];
901
902 __cpuinit void cpu_probe(void)
903 {
904 struct cpuinfo_mips *c = &current_cpu_data;
905 unsigned int cpu = smp_processor_id();
906
907 c->processor_id = PRID_IMP_UNKNOWN;
908 c->fpu_id = FPIR_IMP_NONE;
909 c->cputype = CPU_UNKNOWN;
910
911 c->processor_id = read_c0_prid();
912 switch (c->processor_id & 0xff0000) {
913 case PRID_COMP_LEGACY:
914 cpu_probe_legacy(c, cpu);
915 break;
916 case PRID_COMP_MIPS:
917 cpu_probe_mips(c, cpu);
918 break;
919 case PRID_COMP_ALCHEMY:
920 cpu_probe_alchemy(c, cpu);
921 break;
922 case PRID_COMP_SIBYTE:
923 cpu_probe_sibyte(c, cpu);
924 break;
925 case PRID_COMP_BROADCOM:
926 cpu_probe_broadcom(c, cpu);
927 break;
928 case PRID_COMP_SANDCRAFT:
929 cpu_probe_sandcraft(c, cpu);
930 break;
931 case PRID_COMP_NXP:
932 cpu_probe_nxp(c, cpu);
933 break;
934 case PRID_COMP_CAVIUM:
935 cpu_probe_cavium(c, cpu);
936 break;
937 }
938
939 BUG_ON(!__cpu_name[cpu]);
940 BUG_ON(c->cputype == CPU_UNKNOWN);
941
942 /*
943 * Platform code can force the cpu type to optimize code
944 * generation. In that case be sure the cpu type is correctly
945 * manually setup otherwise it could trigger some nasty bugs.
946 */
947 BUG_ON(current_cpu_type() != c->cputype);
948
949 if (c->options & MIPS_CPU_FPU) {
950 c->fpu_id = cpu_get_fpu_id();
951
952 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
953 c->isa_level == MIPS_CPU_ISA_M32R2 ||
954 c->isa_level == MIPS_CPU_ISA_M64R1 ||
955 c->isa_level == MIPS_CPU_ISA_M64R2) {
956 if (c->fpu_id & MIPS_FPIR_3D)
957 c->ases |= MIPS_ASE_MIPS3D;
958 }
959 }
960
961 if (cpu_has_mips_r2)
962 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
963 else
964 c->srsets = 1;
965 }
966
967 __cpuinit void cpu_report(void)
968 {
969 struct cpuinfo_mips *c = &current_cpu_data;
970
971 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
972 c->processor_id, cpu_name_string());
973 if (c->options & MIPS_CPU_FPU)
974 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
975 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree