1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
17 /* compilation time flags */
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
23 #define DRV_MODULE_VERSION "1.60.00-4"
24 #define DRV_MODULE_RELDATE "2010/11/01"
25 #define BNX2X_BC_VER 0x040200
27 #define BNX2X_MULTI_QUEUE
29 #define BNX2X_NEW_NAPI
32 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
34 #include "../cnic_if.h"
38 #define BNX2X_MIN_MSIX_VEC_CNT 3
39 #define BNX2X_MSIX_VEC_FP_START 2
41 #define BNX2X_MIN_MSIX_VEC_CNT 2
42 #define BNX2X_MSIX_VEC_FP_START 1
45 #include <linux/mdio.h>
46 #include <linux/pci.h>
47 #include "bnx2x_reg.h"
48 #include "bnx2x_fw_defs.h"
49 #include "bnx2x_hsi.h"
50 #include "bnx2x_link.h"
51 #include "bnx2x_stats.h"
53 /* error/debug prints */
55 #define DRV_MODULE_NAME "bnx2x"
57 /* for messages that are currently off */
58 #define BNX2X_MSG_OFF 0
59 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
60 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
61 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
62 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
63 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
64 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
66 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
68 /* regular debug print */
69 #define DP(__mask, __fmt, __args...) \
71 if (bp->msg_enable & (__mask)) \
72 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
74 bp->dev ? (bp->dev->name) : "?", \
78 /* errors debug print */
79 #define BNX2X_DBG_ERR(__fmt, __args...) \
81 if (netif_msg_probe(bp)) \
82 pr_err("[%s:%d(%s)]" __fmt, \
84 bp->dev ? (bp->dev->name) : "?", \
88 /* for errors (never masked) */
89 #define BNX2X_ERR(__fmt, __args...) \
91 pr_err("[%s:%d(%s)]" __fmt, \
93 bp->dev ? (bp->dev->name) : "?", \
97 #define BNX2X_ERROR(__fmt, __args...) do { \
98 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
102 /* before we have a dev->name use dev_info() */
103 #define BNX2X_DEV_INFO(__fmt, __args...) \
105 if (netif_msg_probe(bp)) \
106 dev_info(&bp->pdev->dev, __fmt, ##__args); \
109 void bnx2x_panic_dump(struct bnx2x
*bp
);
111 #ifdef BNX2X_STOP_ON_ERROR
112 #define bnx2x_panic() do { \
114 BNX2X_ERR("driver assert\n"); \
115 bnx2x_int_disable(bp); \
116 bnx2x_panic_dump(bp); \
119 #define bnx2x_panic() do { \
121 BNX2X_ERR("driver assert\n"); \
122 bnx2x_panic_dump(bp); \
126 #define bnx2x_mc_addr(ha) ((ha)->addr)
128 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
129 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
130 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
133 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
135 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
136 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
137 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
139 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
140 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
141 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
143 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
144 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
146 #define REG_RD_DMAE(bp, offset, valp, len32) \
148 bnx2x_read_dmae(bp, offset, len32);\
149 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
152 #define REG_WR_DMAE(bp, offset, valp, len32) \
154 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
155 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
159 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
160 REG_WR_DMAE(bp, offset, valp, len32)
162 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
164 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
165 bnx2x_write_big_buf_wb(bp, addr, len32); \
168 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
169 offsetof(struct shmem_region, field))
170 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
171 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
173 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
174 offsetof(struct shmem2_region, field))
175 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
176 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
177 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
178 offsetof(struct mf_cfg, field))
179 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
180 offsetof(struct mf2_cfg, field))
182 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
183 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
184 MF_CFG_ADDR(bp, field), (val))
185 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
187 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
188 (SHMEM2_RD((bp), size) > \
189 offsetof(struct shmem2_region, field)))
191 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
192 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
196 /* General SP events - stats query, cfc delete, etc */
197 #define HC_SP_INDEX_ETH_DEF_CONS 3
200 #define HC_SP_INDEX_EQ_CONS 7
203 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
204 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
208 * CLIDs below is a CLID for func 0, then the CLID for other
209 * functions will be calculated by the formula:
211 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
215 #define BNX2X_ISCSI_ETH_CL_ID 17
216 #define BNX2X_ISCSI_ETH_CID 17
218 /** Additional rings budgeting */
220 #define CNIC_CONTEXT_USE 1
222 #define CNIC_CONTEXT_USE 0
223 #endif /* BCM_CNIC */
225 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
226 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
235 DEFINE_DMA_UNMAP_ADDR(mapping
);
242 /* Set on the first BD descriptor when there is a split BD */
243 #define BNX2X_TSO_SPLIT_BD (1<<0)
248 DEFINE_DMA_UNMAP_ADDR(mapping
);
252 struct doorbell_set_prod data
;
258 #define BCM_PAGE_SHIFT 12
259 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
260 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
261 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
263 #define PAGES_PER_SGE_SHIFT 0
264 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
265 #define SGE_PAGE_SIZE PAGE_SIZE
266 #define SGE_PAGE_SHIFT PAGE_SHIFT
267 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
269 /* SGE ring related macros */
270 #define NUM_RX_SGE_PAGES 2
271 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
272 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
273 /* RX_SGE_CNT is promised to be a power of 2 */
274 #define RX_SGE_MASK (RX_SGE_CNT - 1)
275 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
276 #define MAX_RX_SGE (NUM_RX_SGE - 1)
277 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
278 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
279 #define RX_SGE(x) ((x) & MAX_RX_SGE)
281 /* SGE producer mask related macros */
282 /* Number of bits in one sge_mask array element */
283 #define RX_SGE_MASK_ELEM_SZ 64
284 #define RX_SGE_MASK_ELEM_SHIFT 6
285 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
287 /* Creates a bitmask of all ones in less significant bits.
288 idx - index of the most significant bit in the created mask */
289 #define RX_SGE_ONES_MASK(idx) \
290 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
291 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
293 /* Number of u64 elements in SGE mask array */
294 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
296 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
297 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
299 union host_hc_status_block
{
300 /* pointer to fp status block e1x */
301 struct host_hc_status_block_e1x
*e1x_sb
;
302 /* pointer to fp status block e2 */
303 struct host_hc_status_block_e2
*e2_sb
;
306 struct bnx2x_fastpath
{
308 #define BNX2X_NAPI_WEIGHT 128
309 struct napi_struct napi
;
310 union host_hc_status_block status_blk
;
311 /* chip independed shortcuts into sb structure */
312 __le16
*sb_index_values
;
313 __le16
*sb_running_index
;
314 /* chip independed shortcut into rx_prods_offset memory */
315 u32 ustorm_rx_prods_offset
;
317 dma_addr_t status_blk_mapping
;
319 struct sw_tx_bd
*tx_buf_ring
;
321 union eth_tx_bd_types
*tx_desc_ring
;
322 dma_addr_t tx_desc_mapping
;
324 struct sw_rx_bd
*rx_buf_ring
; /* BDs mappings ring */
325 struct sw_rx_page
*rx_page_ring
; /* SGE pages mappings ring */
327 struct eth_rx_bd
*rx_desc_ring
;
328 dma_addr_t rx_desc_mapping
;
330 union eth_rx_cqe
*rx_comp_ring
;
331 dma_addr_t rx_comp_mapping
;
334 struct eth_rx_sge
*rx_sge_ring
;
335 dma_addr_t rx_sge_mapping
;
337 u64 sge_mask
[RX_SGE_MASK_LEN
];
340 #define BNX2X_FP_STATE_CLOSED 0
341 #define BNX2X_FP_STATE_IRQ 0x80000
342 #define BNX2X_FP_STATE_OPENING 0x90000
343 #define BNX2X_FP_STATE_OPEN 0xa0000
344 #define BNX2X_FP_STATE_HALTING 0xb0000
345 #define BNX2X_FP_STATE_HALTED 0xc0000
346 #define BNX2X_FP_STATE_TERMINATING 0xd0000
347 #define BNX2X_FP_STATE_TERMINATED 0xe0000
349 u8 index
; /* number in fp array */
350 u8 cl_id
; /* eth client id */
352 u8 fw_sb_id
; /* status block number in FW */
353 u8 igu_sb_id
; /* status block number in HW */
371 /* The last maximal completed SGE */
375 unsigned long tx_pkt
,
380 struct sw_rx_bd tpa_pool
[ETH_MAX_AGGREGATION_QUEUES_E1H
];
381 u8 tpa_state
[ETH_MAX_AGGREGATION_QUEUES_E1H
];
382 #define BNX2X_TPA_START 1
383 #define BNX2X_TPA_STOP 2
385 #ifdef BNX2X_STOP_ON_ERROR
389 struct tstorm_per_client_stats old_tclient
;
390 struct ustorm_per_client_stats old_uclient
;
391 struct xstorm_per_client_stats old_xclient
;
392 struct bnx2x_eth_q_stats eth_q_stats
;
394 /* The size is calculated using the following:
395 sizeof name field from netdev structure +
397 4 (for the digits and to make it DWORD aligned) */
398 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
399 char name
[FP_NAME_SIZE
];
400 struct bnx2x
*bp
; /* parent */
403 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
407 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
408 #define RX_COPY_THRESH 92
410 #define NUM_TX_RINGS 16
411 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
412 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
413 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
414 #define MAX_TX_BD (NUM_TX_BD - 1)
415 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
416 #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL
417 #define INIT_TX_RING_SIZE MAX_TX_AVAIL
418 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
419 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
420 #define TX_BD(x) ((x) & MAX_TX_BD)
421 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
423 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
424 #define NUM_RX_RINGS 8
425 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
426 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
427 #define RX_DESC_MASK (RX_DESC_CNT - 1)
428 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
429 #define MAX_RX_BD (NUM_RX_BD - 1)
430 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
431 #define MIN_RX_AVAIL 128
432 #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL
433 #define INIT_RX_RING_SIZE MAX_RX_AVAIL
434 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
435 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
436 #define RX_BD(x) ((x) & MAX_RX_BD)
438 /* As long as CQE is 4 times bigger than BD entry we have to allocate
439 4 times more pages for CQ ring in order to keep it balanced with
441 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
442 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
443 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
444 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
445 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
446 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
447 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
448 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
449 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
452 /* This is needed for determining of last_max */
453 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
455 #define __SGE_MASK_SET_BIT(el, bit) \
457 el = ((el) | ((u64)0x1 << (bit))); \
460 #define __SGE_MASK_CLEAR_BIT(el, bit) \
462 el = ((el) & (~((u64)0x1 << (bit)))); \
465 #define SGE_MASK_SET_BIT(fp, idx) \
466 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
467 ((idx) & RX_SGE_MASK_ELEM_MASK))
469 #define SGE_MASK_CLEAR_BIT(fp, idx) \
470 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
471 ((idx) & RX_SGE_MASK_ELEM_MASK))
474 /* used on a CID received from the HW */
475 #define SW_CID(x) (le32_to_cpu(x) & \
476 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
477 #define CQE_CMD(x) (le32_to_cpu(x) >> \
478 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
480 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
481 le32_to_cpu((bd)->addr_lo))
482 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
484 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
485 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
486 #define DPM_TRIGER_TYPE 0x40
487 #define DOORBELL(bp, cid, val) \
489 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
494 /* TX CSUM helpers */
495 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
497 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
500 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
503 #define XMIT_CSUM_V4 0x1
504 #define XMIT_CSUM_V6 0x2
505 #define XMIT_CSUM_TCP 0x4
506 #define XMIT_GSO_V4 0x8
507 #define XMIT_GSO_V6 0x10
509 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
510 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
513 /* stuff added to make the code fit 80Col */
515 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
517 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
518 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
519 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
520 (TPA_TYPE_START | TPA_TYPE_END))
522 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
524 #define BNX2X_IP_CSUM_ERR(cqe) \
525 (!((cqe)->fast_path_cqe.status_flags & \
526 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
527 ((cqe)->fast_path_cqe.type_error_flags & \
528 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
530 #define BNX2X_L4_CSUM_ERR(cqe) \
531 (!((cqe)->fast_path_cqe.status_flags & \
532 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
533 ((cqe)->fast_path_cqe.type_error_flags & \
534 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
536 #define BNX2X_RX_CSUM_OK(cqe) \
537 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
539 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
540 (((le16_to_cpu(flags) & \
541 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
542 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
543 == PRS_FLAG_OVERETH_IPV4)
544 #define BNX2X_RX_SUM_FIX(cqe) \
545 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
547 #define U_SB_ETH_RX_CQ_INDEX 1
548 #define U_SB_ETH_RX_BD_INDEX 2
549 #define C_SB_ETH_TX_CQ_INDEX 5
551 #define BNX2X_RX_SB_INDEX \
552 (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX])
554 #define BNX2X_TX_SB_INDEX \
555 (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
557 /* end of fast path */
561 struct bnx2x_common
{
564 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
565 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
567 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
568 #define CHIP_NUM_57710 0x164e
569 #define CHIP_NUM_57711 0x164f
570 #define CHIP_NUM_57711E 0x1650
571 #define CHIP_NUM_57712 0x1662
572 #define CHIP_NUM_57712E 0x1663
573 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
574 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
575 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
576 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
577 #define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E)
578 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
580 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
582 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
583 #define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp))
585 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
586 #define CHIP_REV_Ax 0x00000000
587 /* assume maximum 5 revisions */
588 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
589 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
590 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
591 !(CHIP_REV(bp) & 0x00001000))
592 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
593 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
594 (CHIP_REV(bp) & 0x00001000))
596 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
597 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
599 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
600 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
603 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
604 #define NVRAM_TIMEOUT_COUNT 30000
605 #define NVRAM_PAGE_SIZE 256
617 #define INT_BLOCK_HC 0
618 #define INT_BLOCK_IGU 1
619 #define INT_BLOCK_MODE_NORMAL 0
620 #define INT_BLOCK_MODE_BW_COMP 2
621 #define CHIP_INT_MODE_IS_NBC(bp) \
623 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
624 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
627 #define CHIP_4_PORT_MODE 0x0
628 #define CHIP_2_PORT_MODE 0x1
629 #define CHIP_PORT_MODE_NONE 0x2
630 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
631 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
634 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
635 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
636 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
645 u32 link_config
[LINK_CONFIG_SIZE
];
647 u32 supported
[LINK_CONFIG_SIZE
];
648 /* link settings - missing defines */
649 #define SUPPORTED_2500baseX_Full (1 << 15)
651 u32 advertising
[LINK_CONFIG_SIZE
];
652 /* link settings - missing defines */
653 #define ADVERTISED_2500baseX_Full (1 << 15)
657 /* used to synchronize phy accesses */
658 struct mutex phy_mutex
;
663 struct nig_stats old_nig_stats
;
668 /* e1h Classification CAM line allocations */
672 CAM_MAX_PF_LINE
= CAM_ISCSI_ETH_LINE
675 #define BNX2X_VF_ID_INVALID 0xFF
678 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
679 * control by the number of fast-path status blocks supported by the
680 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
681 * status block represents an independent interrupts context that can
682 * serve a regular L2 networking queue. However special L2 queues such
683 * as the FCoE queue do not require a FP-SB and other components like
684 * the CNIC may consume FP-SB reducing the number of possible L2 queues
686 * If the maximum number of FP-SB available is X then:
687 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
688 * regular L2 queues is Y=X-1
689 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
690 * c. If the FCoE L2 queue is supported the actual number of L2 queues
692 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
693 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
694 * FP interrupt context for the CNIC).
695 * e. The number of HW context (CID count) is always X or X+1 if FCoE
696 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
699 #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */
700 #define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */
703 * cid_cnt paramter below refers to the value returned by
704 * 'bnx2x_get_l2_cid_count()' routine
708 * The number of FP context allocated by the driver == max number of regular
709 * L2 queues + 1 for the FCoE L2 queue
711 #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE)
714 struct eth_context eth
;
718 /* CDU host DB constants */
719 #define CDU_ILT_PAGE_SZ_HW 3
720 #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */
721 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
724 #define CNIC_ISCSI_CID_MAX 256
725 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX)
726 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
729 #define QM_ILT_PAGE_SZ_HW 3
730 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */
731 #define QM_CID_ROUND 1024
734 /* TM (timers) host DB constants */
735 #define TM_ILT_PAGE_SZ_HW 2
736 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */
737 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
738 #define TM_CONN_NUM 1024
739 #define TM_ILT_SZ (8 * TM_CONN_NUM)
740 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
742 /* SRC (Searcher) host DB constants */
743 #define SRC_ILT_PAGE_SZ_HW 3
744 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */
745 #define SRC_HASH_BITS 10
746 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
747 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
748 #define SRC_T2_SZ SRC_ILT_SZ
749 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
754 /* DMA memory not used in fastpath */
755 struct bnx2x_slowpath
{
756 struct eth_stats_query fw_stats
;
757 struct mac_configuration_cmd mac_config
;
758 struct mac_configuration_cmd mcast_config
;
759 struct client_init_ramrod_data client_init_data
;
761 /* used by dmae command executer */
762 struct dmae_command dmae
[MAX_DMAE_C
];
765 union mac_stats mac_stats
;
766 struct nig_stats nig_stats
;
767 struct host_port_stats port_stats
;
768 struct host_func_stats func_stats
;
769 struct host_func_stats func_stats_base
;
775 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
776 #define bnx2x_sp_mapping(bp, var) \
777 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
780 /* attn group wiring */
781 #define MAX_DYNAMIC_ATTN_GRPS 8
796 union cdu_context
*vcxt
;
797 dma_addr_t cxt_mapping
;
808 } bnx2x_recovery_state_t
;
811 * Event queue (EQ or event ring) MC hsi
812 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
814 #define NUM_EQ_PAGES 1
815 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
816 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
817 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
818 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
819 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
821 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
822 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
823 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
825 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
826 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
828 #define BNX2X_EQ_INDEX \
829 (&bp->def_status_blk->sp_sb.\
830 index_values[HC_SP_INDEX_EQ_CONS])
833 /* Fields used in the tx and intr/napi performance paths
834 * are grouped together in the beginning of the structure
836 struct bnx2x_fastpath
*fp
;
837 void __iomem
*regview
;
838 void __iomem
*doorbells
;
841 struct net_device
*dev
;
842 struct pci_dev
*pdev
;
845 #define IRO (bp->iro_arr)
849 bnx2x_recovery_state_t recovery_state
;
851 struct msix_entry
*msix_table
;
852 #define INT_MODE_INTx 1
853 #define INT_MODE_MSI 2
859 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
860 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
861 #define ETH_MIN_PACKET_SIZE 60
862 #define ETH_MAX_PACKET_SIZE 1500
863 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
865 /* Max supported alignment is 256 (8 shift) */
866 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
868 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
869 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
871 struct host_sp_status_block
*def_status_blk
;
872 #define DEF_SB_IGU_ID 16
873 #define DEF_SB_ID HC_SP_SB_ID
877 struct attn_route attn_group
[MAX_DYNAMIC_ATTN_GRPS
];
881 dma_addr_t spq_mapping
;
883 struct eth_spe
*spq_prod_bd
;
884 struct eth_spe
*spq_last_bd
;
886 atomic_t spq_left
; /* serialize spq */
887 /* used to synchronize spq accesses */
891 union event_ring_elem
*eq_ring
;
892 dma_addr_t eq_mapping
;
897 /* Flags for marking that there is a STAT_QUERY or
898 SET_MAC ramrod pending */
902 /* End of fields used in the performance code paths */
909 #define PCI_32BIT_FLAG 2
910 #define ONE_PORT_FLAG 4
911 #define NO_WOL_FLAG 8
912 #define USING_DAC_FLAG 0x10
913 #define USING_MSIX_FLAG 0x20
914 #define USING_MSI_FLAG 0x40
916 #define TPA_ENABLE_FLAG 0x80
917 #define NO_MCP_FLAG 0x100
918 #define DISABLE_MSI_FLAG 0x200
919 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
920 #define MF_FUNC_DIS 0x1000
922 int pf_num
; /* absolute PF number */
923 int pfid
; /* per-path PF number */
925 #define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \
926 0 : (bp->pf_num & 1))
927 #define BP_PORT(bp) (bp->pfid & 1)
928 #define BP_FUNC(bp) (bp->pfid)
929 #define BP_ABS_FUNC(bp) (bp->pf_num)
930 #define BP_E1HVN(bp) (bp->pfid >> 1)
931 #define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \
933 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
934 #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\
935 BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1))
938 #define BCM_CNIC_CID_START 16
939 #define BCM_ISCSI_ETH_CL_ID 17
946 struct delayed_work sp_task
;
947 struct delayed_work reset_task
;
948 struct timer_list timer
;
949 int current_interval
;
952 u16 fw_drv_pulse_wr_seq
;
955 struct link_params link_params
;
956 struct link_vars link_vars
;
957 struct mdio_if_info mdio
;
959 struct bnx2x_common common
;
960 struct bnx2x_port port
;
962 struct cmng_struct_per_port cmng
;
965 u32 mf_config
[E1HVN_MAX
];
966 u32 mf2_config
[E2_FUNC_MAX
];
969 #define IS_MF(bp) (bp->mf_mode != 0)
975 u16 tx_quick_cons_trip_int
;
976 u16 tx_quick_cons_trip
;
980 u16 rx_quick_cons_trip_int
;
981 u16 rx_quick_cons_trip
;
984 /* Maximal coalescing timeout in us */
985 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
990 #define BNX2X_STATE_CLOSED 0
991 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
992 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
993 #define BNX2X_STATE_OPEN 0x3000
994 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
995 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
996 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
997 #define BNX2X_STATE_FUNC_STARTED 0x7000
998 #define BNX2X_STATE_DIAG 0xe000
999 #define BNX2X_STATE_ERROR 0xf000
1006 struct tstorm_eth_mac_filter_config mac_filters
;
1007 #define BNX2X_ACCEPT_NONE 0x0000
1008 #define BNX2X_ACCEPT_UNICAST 0x0001
1009 #define BNX2X_ACCEPT_MULTICAST 0x0002
1010 #define BNX2X_ACCEPT_ALL_UNICAST 0x0004
1011 #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008
1012 #define BNX2X_ACCEPT_BROADCAST 0x0010
1013 #define BNX2X_PROMISCUOUS_MODE 0x10000
1016 #define BNX2X_RX_MODE_NONE 0
1017 #define BNX2X_RX_MODE_NORMAL 1
1018 #define BNX2X_RX_MODE_ALLMULTI 2
1019 #define BNX2X_RX_MODE_PROMISC 3
1020 #define BNX2X_MAX_MULTICAST 64
1021 #define BNX2X_MAX_EMUL_MULTI 16
1026 dma_addr_t def_status_blk_mapping
;
1028 struct bnx2x_slowpath
*slowpath
;
1029 dma_addr_t slowpath_mapping
;
1030 struct hw_context context
;
1032 struct bnx2x_ilt
*ilt
;
1033 #define BP_ILT(bp) ((bp)->ilt)
1034 #define ILT_MAX_LINES 128
1037 #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \
1039 #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT))
1047 #define BNX2X_CNIC_FLAG_MAC_SET 1
1049 dma_addr_t t2_mapping
;
1050 struct cnic_ops
*cnic_ops
;
1053 struct cnic_eth_dev cnic_eth_dev
;
1054 union host_hc_status_block cnic_sb
;
1055 dma_addr_t cnic_sb_mapping
;
1056 #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp))
1057 #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb)
1058 struct eth_spe
*cnic_kwq
;
1059 struct eth_spe
*cnic_kwq_prod
;
1060 struct eth_spe
*cnic_kwq_cons
;
1061 struct eth_spe
*cnic_kwq_last
;
1062 u16 cnic_kwq_pending
;
1063 u16 cnic_spq_pending
;
1064 struct mutex cnic_mutex
;
1069 /* used to synchronize dmae accesses */
1070 struct mutex dmae_mutex
;
1072 /* used to protect the FW mail box */
1073 struct mutex fw_mb_mutex
;
1075 /* used to synchronize stats collecting */
1078 /* used for synchronization of concurrent threads statistics handling */
1079 spinlock_t stats_lock
;
1081 /* used by dmae command loader */
1082 struct dmae_command stats_dmae
;
1086 struct bnx2x_eth_stats eth_stats
;
1088 struct z_stream_s
*strm
;
1090 dma_addr_t gunzip_mapping
;
1092 #define FW_BUF_SIZE 0x8000
1093 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1094 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1095 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1097 struct raw_op
*init_ops
;
1098 /* Init blocks offsets inside init_ops */
1099 u16
*init_ops_offsets
;
1100 /* Data blob - has 32 bit granularity */
1102 /* Zipped PRAM blobs - raw data */
1103 const u8
*tsem_int_table_data
;
1104 const u8
*tsem_pram_data
;
1105 const u8
*usem_int_table_data
;
1106 const u8
*usem_pram_data
;
1107 const u8
*xsem_int_table_data
;
1108 const u8
*xsem_pram_data
;
1109 const u8
*csem_int_table_data
;
1110 const u8
*csem_pram_data
;
1111 #define INIT_OPS(bp) (bp->init_ops)
1112 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1113 #define INIT_DATA(bp) (bp->init_data)
1114 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1115 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1116 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1117 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1118 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1119 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1120 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1121 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1124 const struct firmware
*firmware
;
1128 * Init queue/func interface
1130 /* queue init flags */
1131 #define QUEUE_FLG_TPA 0x0001
1132 #define QUEUE_FLG_CACHE_ALIGN 0x0002
1133 #define QUEUE_FLG_STATS 0x0004
1134 #define QUEUE_FLG_OV 0x0008
1135 #define QUEUE_FLG_VLAN 0x0010
1136 #define QUEUE_FLG_COS 0x0020
1137 #define QUEUE_FLG_HC 0x0040
1138 #define QUEUE_FLG_DHC 0x0080
1139 #define QUEUE_FLG_OOO 0x0100
1141 #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR
1142 #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR
1143 #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0
1144 #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR
1148 /* rss capabilities */
1149 #define RSS_IPV4_CAP 0x0001
1150 #define RSS_IPV4_TCP_CAP 0x0002
1151 #define RSS_IPV6_CAP 0x0004
1152 #define RSS_IPV6_TCP_CAP 0x0008
1154 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1155 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1157 #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
1158 #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1)
1160 #define RSS_IPV4_CAP_MASK \
1161 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1163 #define RSS_IPV4_TCP_CAP_MASK \
1164 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1166 #define RSS_IPV6_CAP_MASK \
1167 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1169 #define RSS_IPV6_TCP_CAP_MASK \
1170 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1172 /* func init flags */
1173 #define FUNC_FLG_STATS 0x0001
1174 #define FUNC_FLG_TPA 0x0002
1175 #define FUNC_FLG_SPQ 0x0004
1176 #define FUNC_FLG_LEADING 0x0008 /* PF only */
1178 struct rxq_pause_params
{
1183 u16 sge_th_lo
; /* valid iff QUEUE_FLG_TPA */
1184 u16 sge_th_hi
; /* valid iff QUEUE_FLG_TPA */
1188 struct bnx2x_rxq_init_params
{
1190 struct eth_context
*cxt
;
1193 dma_addr_t dscr_map
;
1196 dma_addr_t rcq_np_map
;
1207 /* valid iff QUEUE_FLG_STATS */
1210 /* valid iff QUEUE_FLG_TPA */
1215 /* valid iff QUEUE_FLG_CACHE_ALIGN */
1221 /* desired interrupts per sec. valid iff QUEUE_FLG_HC */
1225 struct bnx2x_txq_init_params
{
1227 struct eth_context
*cxt
;
1230 dma_addr_t dscr_map
;
1235 u8 cos
; /* valid iff QUEUE_FLG_COS */
1236 u16 stat_id
; /* valid iff QUEUE_FLG_STATS */
1239 u16 hc_rate
; /* desired interrupts per sec.*/
1240 /* valid iff QUEUE_FLG_HC */
1244 struct bnx2x_client_ramrod_params
{
1251 #define CLIENT_IS_LEADING_RSS 0x02
1255 struct bnx2x_client_init_params
{
1256 struct rxq_pause_params pause
;
1257 struct bnx2x_rxq_init_params rxq_params
;
1258 struct bnx2x_txq_init_params txq_params
;
1259 struct bnx2x_client_ramrod_params ramrod_params
;
1262 struct bnx2x_rss_params
{
1268 struct bnx2x_func_init_params
{
1271 struct bnx2x_rss_params
*rss
; /* valid iff FUNC_FLG_RSS */
1274 dma_addr_t fw_stat_map
; /* valid iff FUNC_FLG_STATS */
1275 dma_addr_t spq_map
; /* valid iff FUNC_FLG_SPQ */
1278 u16 func_id
; /* abs fid */
1280 u16 spq_prod
; /* valid iff FUNC_FLG_SPQ */
1283 #define for_each_queue(bp, var) \
1284 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1285 #define for_each_nondefault_queue(bp, var) \
1286 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
1289 #define WAIT_RAMROD_POLL 0x01
1290 #define WAIT_RAMROD_COMMON 0x02
1293 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
);
1294 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
1296 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
);
1297 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
);
1298 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
);
1299 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
1300 bool with_comp
, u8 comp_type
);
1302 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
);
1303 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
);
1304 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
);
1305 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
);
1307 void bnx2x_calc_fc_adv(struct bnx2x
*bp
);
1308 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
1309 u32 data_hi
, u32 data_lo
, int common
);
1310 void bnx2x_update_coalesce(struct bnx2x
*bp
);
1311 int bnx2x_get_link_cfg_idx(struct bnx2x
*bp
);
1313 static inline u32
reg_poll(struct bnx2x
*bp
, u32 reg
, u32 expected
, int ms
,
1319 val
= REG_RD(bp
, reg
);
1320 if (val
== expected
)
1330 #define BNX2X_ILT_ZALLOC(x, y, size) \
1332 x = pci_alloc_consistent(bp->pdev, size, y); \
1334 memset(x, 0, size); \
1337 #define BNX2X_ILT_FREE(x, y, size) \
1340 pci_free_consistent(bp->pdev, size, x, y); \
1346 #define ILOG2(x) (ilog2((x)))
1348 #define ILT_NUM_PAGE_ENTRIES (3072)
1349 /* In 57710/11 we use whole table since we have 8 func
1350 * In 57712 we have only 4 func, but use same size per func, then only half of
1353 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1355 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1357 * the phys address is shifted right 12 bits and has an added
1358 * 1=valid bit added to the 53rd bit
1359 * then since this is a wide register(TM)
1360 * we split it into two 32 bit writes
1362 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1363 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1365 /* load/unload mode */
1366 #define LOAD_NORMAL 0
1369 #define UNLOAD_NORMAL 0
1370 #define UNLOAD_CLOSE 1
1371 #define UNLOAD_RECOVERY 2
1374 /* DMAE command defines */
1375 #define DMAE_TIMEOUT -1
1376 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1377 #define DMAE_NOT_RDY -3
1378 #define DMAE_PCI_ERR_FLAG 0x80000000
1380 #define DMAE_SRC_PCI 0
1381 #define DMAE_SRC_GRC 1
1383 #define DMAE_DST_NONE 0
1384 #define DMAE_DST_PCI 1
1385 #define DMAE_DST_GRC 2
1387 #define DMAE_COMP_PCI 0
1388 #define DMAE_COMP_GRC 1
1390 /* E2 and onward - PCI error handling in the completion */
1392 #define DMAE_COMP_REGULAR 0
1393 #define DMAE_COM_SET_ERR 1
1395 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1396 DMAE_COMMAND_SRC_SHIFT)
1397 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1398 DMAE_COMMAND_SRC_SHIFT)
1400 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1401 DMAE_COMMAND_DST_SHIFT)
1402 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1403 DMAE_COMMAND_DST_SHIFT)
1405 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1406 DMAE_COMMAND_C_DST_SHIFT)
1407 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1408 DMAE_COMMAND_C_DST_SHIFT)
1410 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1412 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1413 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1414 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1415 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1417 #define DMAE_CMD_PORT_0 0
1418 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1420 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1421 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1422 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1424 #define DMAE_SRC_PF 0
1425 #define DMAE_SRC_VF 1
1427 #define DMAE_DST_PF 0
1428 #define DMAE_DST_VF 1
1430 #define DMAE_C_SRC 0
1431 #define DMAE_C_DST 1
1433 #define DMAE_LEN32_RD_MAX 0x80
1434 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1436 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1439 #define MAX_DMAE_C_PER_PORT 8
1440 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1442 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1445 /* PCIE link and speed */
1446 #define PCICFG_LINK_WIDTH 0x1f00000
1447 #define PCICFG_LINK_WIDTH_SHIFT 20
1448 #define PCICFG_LINK_SPEED 0xf0000
1449 #define PCICFG_LINK_SPEED_SHIFT 16
1452 #define BNX2X_NUM_TESTS 7
1454 #define BNX2X_PHY_LOOPBACK 0
1455 #define BNX2X_MAC_LOOPBACK 1
1456 #define BNX2X_PHY_LOOPBACK_FAILED 1
1457 #define BNX2X_MAC_LOOPBACK_FAILED 2
1458 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1459 BNX2X_PHY_LOOPBACK_FAILED)
1462 #define STROM_ASSERT_ARRAY_SIZE 50
1465 /* must be used on a CID before placing it on a HW ring */
1466 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1467 (BP_E1HVN(bp) << 17) | (x))
1469 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1470 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1474 #define MAX_SPQ_PENDING 8
1478 derived from lab experiments, and not from system spec calculations !!! */
1479 #define DEF_MIN_RATE 100
1480 /* resolution of the rate shaping timer - 100 usec */
1481 #define RS_PERIODIC_TIMEOUT_USEC 100
1482 /* resolution of fairness algorithm in usecs -
1483 coefficient for calculating the actual t fair */
1484 #define T_FAIR_COEF 10000000
1485 /* number of bytes in single QM arbitration cycle -
1486 coefficient for calculating the fairness timer */
1487 #define QM_ARB_BYTES 40000
1491 #define ATTN_NIG_FOR_FUNC (1L << 8)
1492 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1493 #define GPIO_2_FUNC (1L << 10)
1494 #define GPIO_3_FUNC (1L << 11)
1495 #define GPIO_4_FUNC (1L << 12)
1496 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1497 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1498 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1499 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1500 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1501 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1503 #define ATTN_HARD_WIRED_MASK 0xff00
1504 #define ATTENTION_ID 4
1507 /* stuff added to make the code fit 80Col */
1509 #define BNX2X_PMF_LINK_ASSERT \
1510 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1512 #define BNX2X_MC_ASSERT_BITS \
1513 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1514 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1515 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1516 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1518 #define BNX2X_MCP_ASSERT \
1519 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1521 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1522 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1523 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1524 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1525 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1526 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1527 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1529 #define HW_INTERRUT_ASSERT_SET_0 \
1530 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1531 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1532 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1533 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1534 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1535 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1536 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1537 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1538 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1539 #define HW_INTERRUT_ASSERT_SET_1 \
1540 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1541 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1542 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1543 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1544 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1545 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1546 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1547 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1548 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1549 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1550 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1551 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1552 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1553 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1554 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1555 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1556 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1557 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1558 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1559 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1560 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1561 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1562 #define HW_INTERRUT_ASSERT_SET_2 \
1563 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1564 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1565 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1566 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1567 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1568 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1569 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1570 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1571 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1572 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1573 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1574 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1576 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1577 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1578 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1579 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1581 #define RSS_FLAGS(bp) \
1582 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1583 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1584 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1585 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1586 (bp->multi_mode << \
1587 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1588 #define MULTI_MASK 0x7f
1590 #define BNX2X_SP_DSB_INDEX \
1591 (&bp->def_status_blk->sp_sb.\
1592 index_values[HC_SP_INDEX_ETH_DEF_CONS])
1594 #define SET_FLAG(value, mask, flag) \
1596 (value) &= ~(mask);\
1597 (value) |= ((flag) << (mask##_SHIFT));\
1600 #define GET_FLAG(value, mask) \
1601 (((value) &= (mask)) >> (mask##_SHIFT))
1603 #define GET_FIELD(value, fname) \
1604 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
1606 #define CAM_IS_INVALID(x) \
1607 (GET_FLAG(x.flags, \
1608 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
1609 (T_ETH_MAC_COMMAND_INVALIDATE))
1611 #define CAM_INVALIDATE(x) \
1612 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1615 /* Number of u32 elements in MC hash array */
1616 #define MC_HASH_SIZE 8
1617 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1618 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1621 #ifndef PXP2_REG_PXP2_INT_STS
1622 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1625 #ifndef ETH_MAX_RX_CLIENTS_E2
1626 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
1629 #define BNX2X_VPD_LEN 128
1630 #define VENDOR_ID_LEN 4
1632 /* Congestion management fairness mode */
1633 #define CMNG_FNS_NONE 0
1634 #define CMNG_FNS_MINMAX 1
1636 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
1637 #define HC_SEG_ACCESS_ATTN 4
1638 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
1641 #define BNX2X_EXTERN
1643 #define BNX2X_EXTERN extern
1646 BNX2X_EXTERN
int load_count
[2][3]; /* per path: 0-common, 1-port0, 2-port1 */
1648 extern void bnx2x_set_ethtool_ops(struct net_device
*netdev
);
1650 #endif /* bnx2x.h */