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ath9k: fix double calls to ath_radio_enable
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
blob7b1eab4d85cbddc6cccab608319f22f6eb4ec985
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19 #include "btcoex.h"
20
21 static char *dev_info = "ath9k";
22
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
27
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
32 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33 module_param_named(debug, ath9k_debug, uint, 0);
34 MODULE_PARM_DESC(debug, "Debugging mask");
35
36 /* We use the hw_value as an index into our private channel structure */
37
38 #define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
41 .max_power = 20, \
42 }
43
44 #define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
47 .hw_value = (_idx), \
48 .max_power = 20, \
49 }
50
51 /* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
54 * this static */
55 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
70 };
71
72 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
75 * this static */
76 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
105 };
106
107 /* Atheros hardware rate code addition for short premble */
108 #define SHPCHECK(__hw_rate, __flags) \
109 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
110
111 #define RATE(_bitrate, _hw_rate, _flags) { \
112 .bitrate = (_bitrate), \
113 .flags = (_flags), \
114 .hw_value = (_hw_rate), \
115 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
116 }
117
118 static struct ieee80211_rate ath9k_legacy_rates[] = {
119 RATE(10, 0x1b, 0),
120 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
122 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATE(60, 0x0b, 0),
124 RATE(90, 0x0f, 0),
125 RATE(120, 0x0a, 0),
126 RATE(180, 0x0e, 0),
127 RATE(240, 0x09, 0),
128 RATE(360, 0x0d, 0),
129 RATE(480, 0x08, 0),
130 RATE(540, 0x0c, 0),
131 };
132
133 static void ath_cache_conf_rate(struct ath_softc *sc,
134 struct ieee80211_conf *conf)
135 {
136 switch (conf->channel->band) {
137 case IEEE80211_BAND_2GHZ:
138 if (conf_is_ht20(conf))
139 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
140 else if (conf_is_ht40_minus(conf))
141 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
142 else if (conf_is_ht40_plus(conf))
143 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
144 else
145 sc->cur_rate_mode = ATH9K_MODE_11G;
146 break;
147 case IEEE80211_BAND_5GHZ:
148 if (conf_is_ht20(conf))
149 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
150 else if (conf_is_ht40_minus(conf))
151 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
152 else if (conf_is_ht40_plus(conf))
153 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
154 else
155 sc->cur_rate_mode = ATH9K_MODE_11A;
156 break;
157 default:
158 BUG_ON(1);
159 break;
160 }
161 }
162
163 static void ath_update_txpow(struct ath_softc *sc)
164 {
165 struct ath_hw *ah = sc->sc_ah;
166 u32 txpow;
167
168 if (sc->curtxpow != sc->config.txpowlimit) {
169 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
170 /* read back in case value is clamped */
171 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
172 sc->curtxpow = txpow;
173 }
174 }
175
176 static u8 parse_mpdudensity(u8 mpdudensity)
177 {
178 /*
179 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
180 * 0 for no restriction
181 * 1 for 1/4 us
182 * 2 for 1/2 us
183 * 3 for 1 us
184 * 4 for 2 us
185 * 5 for 4 us
186 * 6 for 8 us
187 * 7 for 16 us
188 */
189 switch (mpdudensity) {
190 case 0:
191 return 0;
192 case 1:
193 case 2:
194 case 3:
195 /* Our lower layer calculations limit our precision to
196 1 microsecond */
197 return 1;
198 case 4:
199 return 2;
200 case 5:
201 return 4;
202 case 6:
203 return 8;
204 case 7:
205 return 16;
206 default:
207 return 0;
208 }
209 }
210
211 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
212 struct ieee80211_hw *hw)
213 {
214 struct ieee80211_channel *curchan = hw->conf.channel;
215 struct ath9k_channel *channel;
216 u8 chan_idx;
217
218 chan_idx = curchan->hw_value;
219 channel = &sc->sc_ah->channels[chan_idx];
220 ath9k_update_ichannel(sc, hw, channel);
221 return channel;
222 }
223
224 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
225 {
226 unsigned long flags;
227 bool ret;
228
229 spin_lock_irqsave(&sc->sc_pm_lock, flags);
230 ret = ath9k_hw_setpower(sc->sc_ah, mode);
231 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
232
233 return ret;
234 }
235
236 void ath9k_ps_wakeup(struct ath_softc *sc)
237 {
238 unsigned long flags;
239
240 spin_lock_irqsave(&sc->sc_pm_lock, flags);
241 if (++sc->ps_usecount != 1)
242 goto unlock;
243
244 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
245
246 unlock:
247 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
248 }
249
250 void ath9k_ps_restore(struct ath_softc *sc)
251 {
252 unsigned long flags;
253
254 spin_lock_irqsave(&sc->sc_pm_lock, flags);
255 if (--sc->ps_usecount != 0)
256 goto unlock;
257
258 if (sc->ps_enabled &&
259 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
260 SC_OP_WAIT_FOR_CAB |
261 SC_OP_WAIT_FOR_PSPOLL_DATA |
262 SC_OP_WAIT_FOR_TX_ACK)))
263 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
264
265 unlock:
266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267 }
268
269 /*
270 * Set/change channels. If the channel is really being changed, it's done
271 * by reseting the chip. To accomplish this we must first cleanup any pending
272 * DMA, then restart stuff.
273 */
274 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
275 struct ath9k_channel *hchan)
276 {
277 struct ath_hw *ah = sc->sc_ah;
278 struct ath_common *common = ath9k_hw_common(ah);
279 struct ieee80211_conf *conf = &common->hw->conf;
280 bool fastcc = true, stopped;
281 struct ieee80211_channel *channel = hw->conf.channel;
282 int r;
283
284 if (sc->sc_flags & SC_OP_INVALID)
285 return -EIO;
286
287 ath9k_ps_wakeup(sc);
288
289 /*
290 * This is only performed if the channel settings have
291 * actually changed.
292 *
293 * To switch channels clear any pending DMA operations;
294 * wait long enough for the RX fifo to drain, reset the
295 * hardware at the new frequency, and then re-enable
296 * the relevant bits of the h/w.
297 */
298 ath9k_hw_set_interrupts(ah, 0);
299 ath_drain_all_txq(sc, false);
300 stopped = ath_stoprecv(sc);
301
302 /* XXX: do not flush receive queue here. We don't want
303 * to flush data frames already in queue because of
304 * changing channel. */
305
306 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
307 fastcc = false;
308
309 ath_print(common, ATH_DBG_CONFIG,
310 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
311 sc->sc_ah->curchan->channel,
312 channel->center_freq, conf_is_ht40(conf));
313
314 spin_lock_bh(&sc->sc_resetlock);
315
316 r = ath9k_hw_reset(ah, hchan, fastcc);
317 if (r) {
318 ath_print(common, ATH_DBG_FATAL,
319 "Unable to reset channel (%u Mhz) "
320 "reset status %d\n",
321 channel->center_freq, r);
322 spin_unlock_bh(&sc->sc_resetlock);
323 goto ps_restore;
324 }
325 spin_unlock_bh(&sc->sc_resetlock);
326
327 sc->sc_flags &= ~SC_OP_FULL_RESET;
328
329 if (ath_startrecv(sc) != 0) {
330 ath_print(common, ATH_DBG_FATAL,
331 "Unable to restart recv logic\n");
332 r = -EIO;
333 goto ps_restore;
334 }
335
336 ath_cache_conf_rate(sc, &hw->conf);
337 ath_update_txpow(sc);
338 ath9k_hw_set_interrupts(ah, sc->imask);
339
340 ps_restore:
341 ath9k_ps_restore(sc);
342 return r;
343 }
344
345 /*
346 * This routine performs the periodic noise floor calibration function
347 * that is used to adjust and optimize the chip performance. This
348 * takes environmental changes (location, temperature) into account.
349 * When the task is complete, it reschedules itself depending on the
350 * appropriate interval that was calculated.
351 */
352 static void ath_ani_calibrate(unsigned long data)
353 {
354 struct ath_softc *sc = (struct ath_softc *)data;
355 struct ath_hw *ah = sc->sc_ah;
356 struct ath_common *common = ath9k_hw_common(ah);
357 bool longcal = false;
358 bool shortcal = false;
359 bool aniflag = false;
360 unsigned int timestamp = jiffies_to_msecs(jiffies);
361 u32 cal_interval, short_cal_interval;
362
363 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
364 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
365
366 /*
367 * don't calibrate when we're scanning.
368 * we are most likely not on our home channel.
369 */
370 spin_lock(&sc->ani_lock);
371 if (sc->sc_flags & SC_OP_SCANNING)
372 goto set_timer;
373
374 /* Only calibrate if awake */
375 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
376 goto set_timer;
377
378 ath9k_ps_wakeup(sc);
379
380 /* Long calibration runs independently of short calibration. */
381 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
382 longcal = true;
383 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
384 common->ani.longcal_timer = timestamp;
385 }
386
387 /* Short calibration applies only while caldone is false */
388 if (!common->ani.caldone) {
389 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
390 shortcal = true;
391 ath_print(common, ATH_DBG_ANI,
392 "shortcal @%lu\n", jiffies);
393 common->ani.shortcal_timer = timestamp;
394 common->ani.resetcal_timer = timestamp;
395 }
396 } else {
397 if ((timestamp - common->ani.resetcal_timer) >=
398 ATH_RESTART_CALINTERVAL) {
399 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
400 if (common->ani.caldone)
401 common->ani.resetcal_timer = timestamp;
402 }
403 }
404
405 /* Verify whether we must check ANI */
406 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
407 aniflag = true;
408 common->ani.checkani_timer = timestamp;
409 }
410
411 /* Skip all processing if there's nothing to do. */
412 if (longcal || shortcal || aniflag) {
413 /* Call ANI routine if necessary */
414 if (aniflag)
415 ath9k_hw_ani_monitor(ah, ah->curchan);
416
417 /* Perform calibration if necessary */
418 if (longcal || shortcal) {
419 common->ani.caldone =
420 ath9k_hw_calibrate(ah,
421 ah->curchan,
422 common->rx_chainmask,
423 longcal);
424
425 if (longcal)
426 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
427 ah->curchan);
428
429 ath_print(common, ATH_DBG_ANI,
430 " calibrate chan %u/%x nf: %d\n",
431 ah->curchan->channel,
432 ah->curchan->channelFlags,
433 common->ani.noise_floor);
434 }
435 }
436
437 ath9k_ps_restore(sc);
438
439 set_timer:
440 spin_unlock(&sc->ani_lock);
441 /*
442 * Set timer interval based on previous results.
443 * The interval must be the shortest necessary to satisfy ANI,
444 * short calibration and long calibration.
445 */
446 cal_interval = ATH_LONG_CALINTERVAL;
447 if (sc->sc_ah->config.enable_ani)
448 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
449 if (!common->ani.caldone)
450 cal_interval = min(cal_interval, (u32)short_cal_interval);
451
452 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
453 }
454
455 static void ath_start_ani(struct ath_common *common)
456 {
457 unsigned long timestamp = jiffies_to_msecs(jiffies);
458
459 common->ani.longcal_timer = timestamp;
460 common->ani.shortcal_timer = timestamp;
461 common->ani.checkani_timer = timestamp;
462
463 mod_timer(&common->ani.timer,
464 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
465 }
466
467 /*
468 * Update tx/rx chainmask. For legacy association,
469 * hard code chainmask to 1x1, for 11n association, use
470 * the chainmask configuration, for bt coexistence, use
471 * the chainmask configuration even in legacy mode.
472 */
473 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
474 {
475 struct ath_hw *ah = sc->sc_ah;
476 struct ath_common *common = ath9k_hw_common(ah);
477
478 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
479 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
480 common->tx_chainmask = ah->caps.tx_chainmask;
481 common->rx_chainmask = ah->caps.rx_chainmask;
482 } else {
483 common->tx_chainmask = 1;
484 common->rx_chainmask = 1;
485 }
486
487 ath_print(common, ATH_DBG_CONFIG,
488 "tx chmask: %d, rx chmask: %d\n",
489 common->tx_chainmask,
490 common->rx_chainmask);
491 }
492
493 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
494 {
495 struct ath_node *an;
496
497 an = (struct ath_node *)sta->drv_priv;
498
499 if (sc->sc_flags & SC_OP_TXAGGR) {
500 ath_tx_node_init(sc, an);
501 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
502 sta->ht_cap.ampdu_factor);
503 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
504 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
505 }
506 }
507
508 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
509 {
510 struct ath_node *an = (struct ath_node *)sta->drv_priv;
511
512 if (sc->sc_flags & SC_OP_TXAGGR)
513 ath_tx_node_cleanup(sc, an);
514 }
515
516 static void ath9k_tasklet(unsigned long data)
517 {
518 struct ath_softc *sc = (struct ath_softc *)data;
519 struct ath_hw *ah = sc->sc_ah;
520 struct ath_common *common = ath9k_hw_common(ah);
521
522 u32 status = sc->intrstatus;
523
524 ath9k_ps_wakeup(sc);
525
526 if (status & ATH9K_INT_FATAL) {
527 ath_reset(sc, false);
528 ath9k_ps_restore(sc);
529 return;
530 }
531
532 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
533 spin_lock_bh(&sc->rx.rxflushlock);
534 ath_rx_tasklet(sc, 0);
535 spin_unlock_bh(&sc->rx.rxflushlock);
536 }
537
538 if (status & ATH9K_INT_TX)
539 ath_tx_tasklet(sc);
540
541 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
542 /*
543 * TSF sync does not look correct; remain awake to sync with
544 * the next Beacon.
545 */
546 ath_print(common, ATH_DBG_PS,
547 "TSFOOR - Sync with next Beacon\n");
548 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
549 }
550
551 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
552 if (status & ATH9K_INT_GENTIMER)
553 ath_gen_timer_isr(sc->sc_ah);
554
555 /* re-enable hardware interrupt */
556 ath9k_hw_set_interrupts(ah, sc->imask);
557 ath9k_ps_restore(sc);
558 }
559
560 irqreturn_t ath_isr(int irq, void *dev)
561 {
562 #define SCHED_INTR ( \
563 ATH9K_INT_FATAL | \
564 ATH9K_INT_RXORN | \
565 ATH9K_INT_RXEOL | \
566 ATH9K_INT_RX | \
567 ATH9K_INT_TX | \
568 ATH9K_INT_BMISS | \
569 ATH9K_INT_CST | \
570 ATH9K_INT_TSFOOR | \
571 ATH9K_INT_GENTIMER)
572
573 struct ath_softc *sc = dev;
574 struct ath_hw *ah = sc->sc_ah;
575 enum ath9k_int status;
576 bool sched = false;
577
578 /*
579 * The hardware is not ready/present, don't
580 * touch anything. Note this can happen early
581 * on if the IRQ is shared.
582 */
583 if (sc->sc_flags & SC_OP_INVALID)
584 return IRQ_NONE;
585
586
587 /* shared irq, not for us */
588
589 if (!ath9k_hw_intrpend(ah))
590 return IRQ_NONE;
591
592 /*
593 * Figure out the reason(s) for the interrupt. Note
594 * that the hal returns a pseudo-ISR that may include
595 * bits we haven't explicitly enabled so we mask the
596 * value to insure we only process bits we requested.
597 */
598 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
599 status &= sc->imask; /* discard unasked-for bits */
600
601 /*
602 * If there are no status bits set, then this interrupt was not
603 * for me (should have been caught above).
604 */
605 if (!status)
606 return IRQ_NONE;
607
608 /* Cache the status */
609 sc->intrstatus = status;
610
611 if (status & SCHED_INTR)
612 sched = true;
613
614 /*
615 * If a FATAL or RXORN interrupt is received, we have to reset the
616 * chip immediately.
617 */
618 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
619 goto chip_reset;
620
621 if (status & ATH9K_INT_SWBA)
622 tasklet_schedule(&sc->bcon_tasklet);
623
624 if (status & ATH9K_INT_TXURN)
625 ath9k_hw_updatetxtriglevel(ah, true);
626
627 if (status & ATH9K_INT_MIB) {
628 /*
629 * Disable interrupts until we service the MIB
630 * interrupt; otherwise it will continue to
631 * fire.
632 */
633 ath9k_hw_set_interrupts(ah, 0);
634 /*
635 * Let the hal handle the event. We assume
636 * it will clear whatever condition caused
637 * the interrupt.
638 */
639 ath9k_hw_procmibevent(ah);
640 ath9k_hw_set_interrupts(ah, sc->imask);
641 }
642
643 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
644 if (status & ATH9K_INT_TIM_TIMER) {
645 /* Clear RxAbort bit so that we can
646 * receive frames */
647 ath9k_setpower(sc, ATH9K_PM_AWAKE);
648 ath9k_hw_setrxabort(sc->sc_ah, 0);
649 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
650 }
651
652 chip_reset:
653
654 ath_debug_stat_interrupt(sc, status);
655
656 if (sched) {
657 /* turn off every interrupt except SWBA */
658 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
659 tasklet_schedule(&sc->intr_tq);
660 }
661
662 return IRQ_HANDLED;
663
664 #undef SCHED_INTR
665 }
666
667 static u32 ath_get_extchanmode(struct ath_softc *sc,
668 struct ieee80211_channel *chan,
669 enum nl80211_channel_type channel_type)
670 {
671 u32 chanmode = 0;
672
673 switch (chan->band) {
674 case IEEE80211_BAND_2GHZ:
675 switch(channel_type) {
676 case NL80211_CHAN_NO_HT:
677 case NL80211_CHAN_HT20:
678 chanmode = CHANNEL_G_HT20;
679 break;
680 case NL80211_CHAN_HT40PLUS:
681 chanmode = CHANNEL_G_HT40PLUS;
682 break;
683 case NL80211_CHAN_HT40MINUS:
684 chanmode = CHANNEL_G_HT40MINUS;
685 break;
686 }
687 break;
688 case IEEE80211_BAND_5GHZ:
689 switch(channel_type) {
690 case NL80211_CHAN_NO_HT:
691 case NL80211_CHAN_HT20:
692 chanmode = CHANNEL_A_HT20;
693 break;
694 case NL80211_CHAN_HT40PLUS:
695 chanmode = CHANNEL_A_HT40PLUS;
696 break;
697 case NL80211_CHAN_HT40MINUS:
698 chanmode = CHANNEL_A_HT40MINUS;
699 break;
700 }
701 break;
702 default:
703 break;
704 }
705
706 return chanmode;
707 }
708
709 static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
710 struct ath9k_keyval *hk, const u8 *addr,
711 bool authenticator)
712 {
713 struct ath_hw *ah = common->ah;
714 const u8 *key_rxmic;
715 const u8 *key_txmic;
716
717 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
718 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
719
720 if (addr == NULL) {
721 /*
722 * Group key installation - only two key cache entries are used
723 * regardless of splitmic capability since group key is only
724 * used either for TX or RX.
725 */
726 if (authenticator) {
727 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
728 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
729 } else {
730 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
731 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
732 }
733 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
734 }
735 if (!common->splitmic) {
736 /* TX and RX keys share the same key cache entry. */
737 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
738 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
739 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
740 }
741
742 /* Separate key cache entries for TX and RX */
743
744 /* TX key goes at first index, RX key at +32. */
745 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
746 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
747 /* TX MIC entry failed. No need to proceed further */
748 ath_print(common, ATH_DBG_FATAL,
749 "Setting TX MIC Key Failed\n");
750 return 0;
751 }
752
753 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
754 /* XXX delete tx key on failure? */
755 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
756 }
757
758 static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
759 {
760 int i;
761
762 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
763 if (test_bit(i, common->keymap) ||
764 test_bit(i + 64, common->keymap))
765 continue; /* At least one part of TKIP key allocated */
766 if (common->splitmic &&
767 (test_bit(i + 32, common->keymap) ||
768 test_bit(i + 64 + 32, common->keymap)))
769 continue; /* At least one part of TKIP key allocated */
770
771 /* Found a free slot for a TKIP key */
772 return i;
773 }
774 return -1;
775 }
776
777 static int ath_reserve_key_cache_slot(struct ath_common *common)
778 {
779 int i;
780
781 /* First, try to find slots that would not be available for TKIP. */
782 if (common->splitmic) {
783 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
784 if (!test_bit(i, common->keymap) &&
785 (test_bit(i + 32, common->keymap) ||
786 test_bit(i + 64, common->keymap) ||
787 test_bit(i + 64 + 32, common->keymap)))
788 return i;
789 if (!test_bit(i + 32, common->keymap) &&
790 (test_bit(i, common->keymap) ||
791 test_bit(i + 64, common->keymap) ||
792 test_bit(i + 64 + 32, common->keymap)))
793 return i + 32;
794 if (!test_bit(i + 64, common->keymap) &&
795 (test_bit(i , common->keymap) ||
796 test_bit(i + 32, common->keymap) ||
797 test_bit(i + 64 + 32, common->keymap)))
798 return i + 64;
799 if (!test_bit(i + 64 + 32, common->keymap) &&
800 (test_bit(i, common->keymap) ||
801 test_bit(i + 32, common->keymap) ||
802 test_bit(i + 64, common->keymap)))
803 return i + 64 + 32;
804 }
805 } else {
806 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
807 if (!test_bit(i, common->keymap) &&
808 test_bit(i + 64, common->keymap))
809 return i;
810 if (test_bit(i, common->keymap) &&
811 !test_bit(i + 64, common->keymap))
812 return i + 64;
813 }
814 }
815
816 /* No partially used TKIP slots, pick any available slot */
817 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
818 /* Do not allow slots that could be needed for TKIP group keys
819 * to be used. This limitation could be removed if we know that
820 * TKIP will not be used. */
821 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
822 continue;
823 if (common->splitmic) {
824 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
825 continue;
826 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
827 continue;
828 }
829
830 if (!test_bit(i, common->keymap))
831 return i; /* Found a free slot for a key */
832 }
833
834 /* No free slot found */
835 return -1;
836 }
837
838 static int ath_key_config(struct ath_common *common,
839 struct ieee80211_vif *vif,
840 struct ieee80211_sta *sta,
841 struct ieee80211_key_conf *key)
842 {
843 struct ath_hw *ah = common->ah;
844 struct ath9k_keyval hk;
845 const u8 *mac = NULL;
846 int ret = 0;
847 int idx;
848
849 memset(&hk, 0, sizeof(hk));
850
851 switch (key->alg) {
852 case ALG_WEP:
853 hk.kv_type = ATH9K_CIPHER_WEP;
854 break;
855 case ALG_TKIP:
856 hk.kv_type = ATH9K_CIPHER_TKIP;
857 break;
858 case ALG_CCMP:
859 hk.kv_type = ATH9K_CIPHER_AES_CCM;
860 break;
861 default:
862 return -EOPNOTSUPP;
863 }
864
865 hk.kv_len = key->keylen;
866 memcpy(hk.kv_val, key->key, key->keylen);
867
868 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
869 /* For now, use the default keys for broadcast keys. This may
870 * need to change with virtual interfaces. */
871 idx = key->keyidx;
872 } else if (key->keyidx) {
873 if (WARN_ON(!sta))
874 return -EOPNOTSUPP;
875 mac = sta->addr;
876
877 if (vif->type != NL80211_IFTYPE_AP) {
878 /* Only keyidx 0 should be used with unicast key, but
879 * allow this for client mode for now. */
880 idx = key->keyidx;
881 } else
882 return -EIO;
883 } else {
884 if (WARN_ON(!sta))
885 return -EOPNOTSUPP;
886 mac = sta->addr;
887
888 if (key->alg == ALG_TKIP)
889 idx = ath_reserve_key_cache_slot_tkip(common);
890 else
891 idx = ath_reserve_key_cache_slot(common);
892 if (idx < 0)
893 return -ENOSPC; /* no free key cache entries */
894 }
895
896 if (key->alg == ALG_TKIP)
897 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
898 vif->type == NL80211_IFTYPE_AP);
899 else
900 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
901
902 if (!ret)
903 return -EIO;
904
905 set_bit(idx, common->keymap);
906 if (key->alg == ALG_TKIP) {
907 set_bit(idx + 64, common->keymap);
908 if (common->splitmic) {
909 set_bit(idx + 32, common->keymap);
910 set_bit(idx + 64 + 32, common->keymap);
911 }
912 }
913
914 return idx;
915 }
916
917 static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
918 {
919 struct ath_hw *ah = common->ah;
920
921 ath9k_hw_keyreset(ah, key->hw_key_idx);
922 if (key->hw_key_idx < IEEE80211_WEP_NKID)
923 return;
924
925 clear_bit(key->hw_key_idx, common->keymap);
926 if (key->alg != ALG_TKIP)
927 return;
928
929 clear_bit(key->hw_key_idx + 64, common->keymap);
930 if (common->splitmic) {
931 ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
932 clear_bit(key->hw_key_idx + 32, common->keymap);
933 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
934 }
935 }
936
937 static void setup_ht_cap(struct ath_softc *sc,
938 struct ieee80211_sta_ht_cap *ht_info)
939 {
940 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
941 u8 tx_streams, rx_streams;
942
943 ht_info->ht_supported = true;
944 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
945 IEEE80211_HT_CAP_SM_PS |
946 IEEE80211_HT_CAP_SGI_40 |
947 IEEE80211_HT_CAP_DSSSCCK40;
948
949 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
950 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
951
952 /* set up supported mcs set */
953 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
954 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
955 1 : 2;
956 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
957 1 : 2;
958
959 if (tx_streams != rx_streams) {
960 ath_print(common, ATH_DBG_CONFIG,
961 "TX streams %d, RX streams: %d\n",
962 tx_streams, rx_streams);
963 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
964 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
965 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
966 }
967
968 ht_info->mcs.rx_mask[0] = 0xff;
969 if (rx_streams >= 2)
970 ht_info->mcs.rx_mask[1] = 0xff;
971
972 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
973 }
974
975 static void ath9k_bss_assoc_info(struct ath_softc *sc,
976 struct ieee80211_vif *vif,
977 struct ieee80211_bss_conf *bss_conf)
978 {
979 struct ath_hw *ah = sc->sc_ah;
980 struct ath_common *common = ath9k_hw_common(ah);
981
982 if (bss_conf->assoc) {
983 ath_print(common, ATH_DBG_CONFIG,
984 "Bss Info ASSOC %d, bssid: %pM\n",
985 bss_conf->aid, common->curbssid);
986
987 /* New association, store aid */
988 common->curaid = bss_conf->aid;
989 ath9k_hw_write_associd(ah);
990
991 /*
992 * Request a re-configuration of Beacon related timers
993 * on the receipt of the first Beacon frame (i.e.,
994 * after time sync with the AP).
995 */
996 sc->sc_flags |= SC_OP_BEACON_SYNC;
997
998 /* Configure the beacon */
999 ath_beacon_config(sc, vif);
1000
1001 /* Reset rssi stats */
1002 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1003
1004 ath_start_ani(common);
1005 } else {
1006 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1007 common->curaid = 0;
1008 /* Stop ANI */
1009 del_timer_sync(&common->ani.timer);
1010 }
1011 }
1012
1013 /********************************/
1014 /* LED functions */
1015 /********************************/
1016
1017 static void ath_led_blink_work(struct work_struct *work)
1018 {
1019 struct ath_softc *sc = container_of(work, struct ath_softc,
1020 ath_led_blink_work.work);
1021
1022 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1023 return;
1024
1025 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1026 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1027 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1028 else
1029 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1030 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1031
1032 ieee80211_queue_delayed_work(sc->hw,
1033 &sc->ath_led_blink_work,
1034 (sc->sc_flags & SC_OP_LED_ON) ?
1035 msecs_to_jiffies(sc->led_off_duration) :
1036 msecs_to_jiffies(sc->led_on_duration));
1037
1038 sc->led_on_duration = sc->led_on_cnt ?
1039 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1040 ATH_LED_ON_DURATION_IDLE;
1041 sc->led_off_duration = sc->led_off_cnt ?
1042 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1043 ATH_LED_OFF_DURATION_IDLE;
1044 sc->led_on_cnt = sc->led_off_cnt = 0;
1045 if (sc->sc_flags & SC_OP_LED_ON)
1046 sc->sc_flags &= ~SC_OP_LED_ON;
1047 else
1048 sc->sc_flags |= SC_OP_LED_ON;
1049 }
1050
1051 static void ath_led_brightness(struct led_classdev *led_cdev,
1052 enum led_brightness brightness)
1053 {
1054 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1055 struct ath_softc *sc = led->sc;
1056
1057 switch (brightness) {
1058 case LED_OFF:
1059 if (led->led_type == ATH_LED_ASSOC ||
1060 led->led_type == ATH_LED_RADIO) {
1061 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1062 (led->led_type == ATH_LED_RADIO));
1063 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1064 if (led->led_type == ATH_LED_RADIO)
1065 sc->sc_flags &= ~SC_OP_LED_ON;
1066 } else {
1067 sc->led_off_cnt++;
1068 }
1069 break;
1070 case LED_FULL:
1071 if (led->led_type == ATH_LED_ASSOC) {
1072 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1073 ieee80211_queue_delayed_work(sc->hw,
1074 &sc->ath_led_blink_work, 0);
1075 } else if (led->led_type == ATH_LED_RADIO) {
1076 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1077 sc->sc_flags |= SC_OP_LED_ON;
1078 } else {
1079 sc->led_on_cnt++;
1080 }
1081 break;
1082 default:
1083 break;
1084 }
1085 }
1086
1087 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1088 char *trigger)
1089 {
1090 int ret;
1091
1092 led->sc = sc;
1093 led->led_cdev.name = led->name;
1094 led->led_cdev.default_trigger = trigger;
1095 led->led_cdev.brightness_set = ath_led_brightness;
1096
1097 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1098 if (ret)
1099 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1100 "Failed to register led:%s", led->name);
1101 else
1102 led->registered = 1;
1103 return ret;
1104 }
1105
1106 static void ath_unregister_led(struct ath_led *led)
1107 {
1108 if (led->registered) {
1109 led_classdev_unregister(&led->led_cdev);
1110 led->registered = 0;
1111 }
1112 }
1113
1114 static void ath_deinit_leds(struct ath_softc *sc)
1115 {
1116 ath_unregister_led(&sc->assoc_led);
1117 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1118 ath_unregister_led(&sc->tx_led);
1119 ath_unregister_led(&sc->rx_led);
1120 ath_unregister_led(&sc->radio_led);
1121 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1122 }
1123
1124 static void ath_init_leds(struct ath_softc *sc)
1125 {
1126 char *trigger;
1127 int ret;
1128
1129 if (AR_SREV_9287(sc->sc_ah))
1130 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1131 else
1132 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1133
1134 /* Configure gpio 1 for output */
1135 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1136 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1137 /* LED off, active low */
1138 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1139
1140 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1141
1142 trigger = ieee80211_get_radio_led_name(sc->hw);
1143 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1144 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1145 ret = ath_register_led(sc, &sc->radio_led, trigger);
1146 sc->radio_led.led_type = ATH_LED_RADIO;
1147 if (ret)
1148 goto fail;
1149
1150 trigger = ieee80211_get_assoc_led_name(sc->hw);
1151 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1152 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1153 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1154 sc->assoc_led.led_type = ATH_LED_ASSOC;
1155 if (ret)
1156 goto fail;
1157
1158 trigger = ieee80211_get_tx_led_name(sc->hw);
1159 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1160 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1161 ret = ath_register_led(sc, &sc->tx_led, trigger);
1162 sc->tx_led.led_type = ATH_LED_TX;
1163 if (ret)
1164 goto fail;
1165
1166 trigger = ieee80211_get_rx_led_name(sc->hw);
1167 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1168 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1169 ret = ath_register_led(sc, &sc->rx_led, trigger);
1170 sc->rx_led.led_type = ATH_LED_RX;
1171 if (ret)
1172 goto fail;
1173
1174 return;
1175
1176 fail:
1177 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1178 ath_deinit_leds(sc);
1179 }
1180
1181 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
1182 {
1183 struct ath_hw *ah = sc->sc_ah;
1184 struct ath_common *common = ath9k_hw_common(ah);
1185 struct ieee80211_channel *channel = hw->conf.channel;
1186 int r;
1187
1188 ath9k_ps_wakeup(sc);
1189 ath9k_hw_configpcipowersave(ah, 0, 0);
1190
1191 if (!ah->curchan)
1192 ah->curchan = ath_get_curchannel(sc, sc->hw);
1193
1194 spin_lock_bh(&sc->sc_resetlock);
1195 r = ath9k_hw_reset(ah, ah->curchan, false);
1196 if (r) {
1197 ath_print(common, ATH_DBG_FATAL,
1198 "Unable to reset channel %u (%uMhz) ",
1199 "reset status %d\n",
1200 channel->center_freq, r);
1201 }
1202 spin_unlock_bh(&sc->sc_resetlock);
1203
1204 ath_update_txpow(sc);
1205 if (ath_startrecv(sc) != 0) {
1206 ath_print(common, ATH_DBG_FATAL,
1207 "Unable to restart recv logic\n");
1208 return;
1209 }
1210
1211 if (sc->sc_flags & SC_OP_BEACONS)
1212 ath_beacon_config(sc, NULL); /* restart beacons */
1213
1214 /* Re-Enable interrupts */
1215 ath9k_hw_set_interrupts(ah, sc->imask);
1216
1217 /* Enable LED */
1218 ath9k_hw_cfg_output(ah, ah->led_pin,
1219 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1220 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1221
1222 ieee80211_wake_queues(hw);
1223 ath9k_ps_restore(sc);
1224 }
1225
1226 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
1227 {
1228 struct ath_hw *ah = sc->sc_ah;
1229 struct ieee80211_channel *channel = hw->conf.channel;
1230 int r;
1231
1232 ath9k_ps_wakeup(sc);
1233 ieee80211_stop_queues(hw);
1234
1235 /* Disable LED */
1236 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1237 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1238
1239 /* Disable interrupts */
1240 ath9k_hw_set_interrupts(ah, 0);
1241
1242 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1243 ath_stoprecv(sc); /* turn off frame recv */
1244 ath_flushrecv(sc); /* flush recv queue */
1245
1246 if (!ah->curchan)
1247 ah->curchan = ath_get_curchannel(sc, hw);
1248
1249 spin_lock_bh(&sc->sc_resetlock);
1250 r = ath9k_hw_reset(ah, ah->curchan, false);
1251 if (r) {
1252 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1253 "Unable to reset channel %u (%uMhz) "
1254 "reset status %d\n",
1255 channel->center_freq, r);
1256 }
1257 spin_unlock_bh(&sc->sc_resetlock);
1258
1259 ath9k_hw_phy_disable(ah);
1260 ath9k_hw_configpcipowersave(ah, 1, 1);
1261 ath9k_ps_restore(sc);
1262 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1263 }
1264
1265 /*******************/
1266 /* Rfkill */
1267 /*******************/
1268
1269 static bool ath_is_rfkill_set(struct ath_softc *sc)
1270 {
1271 struct ath_hw *ah = sc->sc_ah;
1272
1273 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1274 ah->rfkill_polarity;
1275 }
1276
1277 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1278 {
1279 struct ath_wiphy *aphy = hw->priv;
1280 struct ath_softc *sc = aphy->sc;
1281 bool blocked = !!ath_is_rfkill_set(sc);
1282
1283 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1284 }
1285
1286 static void ath_start_rfkill_poll(struct ath_softc *sc)
1287 {
1288 struct ath_hw *ah = sc->sc_ah;
1289
1290 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1291 wiphy_rfkill_start_polling(sc->hw->wiphy);
1292 }
1293
1294 static void ath9k_uninit_hw(struct ath_softc *sc)
1295 {
1296 struct ath_hw *ah = sc->sc_ah;
1297
1298 BUG_ON(!ah);
1299
1300 ath9k_exit_debug(ah);
1301 ath9k_hw_detach(ah);
1302 sc->sc_ah = NULL;
1303 }
1304
1305 static void ath_clean_core(struct ath_softc *sc)
1306 {
1307 struct ieee80211_hw *hw = sc->hw;
1308 struct ath_hw *ah = sc->sc_ah;
1309 int i = 0;
1310
1311 ath9k_ps_wakeup(sc);
1312
1313 dev_dbg(sc->dev, "Detach ATH hw\n");
1314
1315 ath_deinit_leds(sc);
1316 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1317
1318 for (i = 0; i < sc->num_sec_wiphy; i++) {
1319 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1320 if (aphy == NULL)
1321 continue;
1322 sc->sec_wiphy[i] = NULL;
1323 ieee80211_unregister_hw(aphy->hw);
1324 ieee80211_free_hw(aphy->hw);
1325 }
1326 ieee80211_unregister_hw(hw);
1327 ath_rx_cleanup(sc);
1328 ath_tx_cleanup(sc);
1329
1330 tasklet_kill(&sc->intr_tq);
1331 tasklet_kill(&sc->bcon_tasklet);
1332
1333 if (!(sc->sc_flags & SC_OP_INVALID))
1334 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1335
1336 /* cleanup tx queues */
1337 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1338 if (ATH_TXQ_SETUP(sc, i))
1339 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1340
1341 if ((sc->btcoex.no_stomp_timer) &&
1342 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1343 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1344 }
1345
1346 void ath_detach(struct ath_softc *sc)
1347 {
1348 ath_clean_core(sc);
1349 ath9k_uninit_hw(sc);
1350 }
1351
1352 void ath_cleanup(struct ath_softc *sc)
1353 {
1354 struct ath_hw *ah = sc->sc_ah;
1355 struct ath_common *common = ath9k_hw_common(ah);
1356
1357 ath_clean_core(sc);
1358 free_irq(sc->irq, sc);
1359 ath_bus_cleanup(common);
1360 kfree(sc->sec_wiphy);
1361 ieee80211_free_hw(sc->hw);
1362
1363 ath9k_uninit_hw(sc);
1364 }
1365
1366 static int ath9k_reg_notifier(struct wiphy *wiphy,
1367 struct regulatory_request *request)
1368 {
1369 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1370 struct ath_wiphy *aphy = hw->priv;
1371 struct ath_softc *sc = aphy->sc;
1372 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1373
1374 return ath_reg_notifier_apply(wiphy, request, reg);
1375 }
1376
1377 /*
1378 * Detects if there is any priority bt traffic
1379 */
1380 static void ath_detect_bt_priority(struct ath_softc *sc)
1381 {
1382 struct ath_btcoex *btcoex = &sc->btcoex;
1383 struct ath_hw *ah = sc->sc_ah;
1384
1385 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1386 btcoex->bt_priority_cnt++;
1387
1388 if (time_after(jiffies, btcoex->bt_priority_time +
1389 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1390 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1391 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1392 "BT priority traffic detected");
1393 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1394 } else {
1395 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1396 }
1397
1398 btcoex->bt_priority_cnt = 0;
1399 btcoex->bt_priority_time = jiffies;
1400 }
1401 }
1402
1403 /*
1404 * Configures appropriate weight based on stomp type.
1405 */
1406 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1407 enum ath_stomp_type stomp_type)
1408 {
1409 struct ath_hw *ah = sc->sc_ah;
1410
1411 switch (stomp_type) {
1412 case ATH_BTCOEX_STOMP_ALL:
1413 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1414 AR_STOMP_ALL_WLAN_WGHT);
1415 break;
1416 case ATH_BTCOEX_STOMP_LOW:
1417 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1418 AR_STOMP_LOW_WLAN_WGHT);
1419 break;
1420 case ATH_BTCOEX_STOMP_NONE:
1421 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1422 AR_STOMP_NONE_WLAN_WGHT);
1423 break;
1424 default:
1425 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1426 "Invalid Stomptype\n");
1427 break;
1428 }
1429
1430 ath9k_hw_btcoex_enable(ah);
1431 }
1432
1433 static void ath9k_gen_timer_start(struct ath_hw *ah,
1434 struct ath_gen_timer *timer,
1435 u32 timer_next,
1436 u32 timer_period)
1437 {
1438 struct ath_common *common = ath9k_hw_common(ah);
1439 struct ath_softc *sc = (struct ath_softc *) common->priv;
1440
1441 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1442
1443 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
1444 ath9k_hw_set_interrupts(ah, 0);
1445 sc->imask |= ATH9K_INT_GENTIMER;
1446 ath9k_hw_set_interrupts(ah, sc->imask);
1447 }
1448 }
1449
1450 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1451 {
1452 struct ath_common *common = ath9k_hw_common(ah);
1453 struct ath_softc *sc = (struct ath_softc *) common->priv;
1454 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1455
1456 ath9k_hw_gen_timer_stop(ah, timer);
1457
1458 /* if no timer is enabled, turn off interrupt mask */
1459 if (timer_table->timer_mask.val == 0) {
1460 ath9k_hw_set_interrupts(ah, 0);
1461 sc->imask &= ~ATH9K_INT_GENTIMER;
1462 ath9k_hw_set_interrupts(ah, sc->imask);
1463 }
1464 }
1465
1466 /*
1467 * This is the master bt coex timer which runs for every
1468 * 45ms, bt traffic will be given priority during 55% of this
1469 * period while wlan gets remaining 45%
1470 */
1471 static void ath_btcoex_period_timer(unsigned long data)
1472 {
1473 struct ath_softc *sc = (struct ath_softc *) data;
1474 struct ath_hw *ah = sc->sc_ah;
1475 struct ath_btcoex *btcoex = &sc->btcoex;
1476
1477 ath_detect_bt_priority(sc);
1478
1479 spin_lock_bh(&btcoex->btcoex_lock);
1480
1481 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1482
1483 spin_unlock_bh(&btcoex->btcoex_lock);
1484
1485 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1486 if (btcoex->hw_timer_enabled)
1487 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1488
1489 ath9k_gen_timer_start(ah,
1490 btcoex->no_stomp_timer,
1491 (ath9k_hw_gettsf32(ah) +
1492 btcoex->btcoex_no_stomp),
1493 btcoex->btcoex_no_stomp * 10);
1494 btcoex->hw_timer_enabled = true;
1495 }
1496
1497 mod_timer(&btcoex->period_timer, jiffies +
1498 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1499 }
1500
1501 /*
1502 * Generic tsf based hw timer which configures weight
1503 * registers to time slice between wlan and bt traffic
1504 */
1505 static void ath_btcoex_no_stomp_timer(void *arg)
1506 {
1507 struct ath_softc *sc = (struct ath_softc *)arg;
1508 struct ath_hw *ah = sc->sc_ah;
1509 struct ath_btcoex *btcoex = &sc->btcoex;
1510
1511 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1512 "no stomp timer running \n");
1513
1514 spin_lock_bh(&btcoex->btcoex_lock);
1515
1516 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1517 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1518 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1519 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1520
1521 spin_unlock_bh(&btcoex->btcoex_lock);
1522 }
1523
1524 static int ath_init_btcoex_timer(struct ath_softc *sc)
1525 {
1526 struct ath_btcoex *btcoex = &sc->btcoex;
1527
1528 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1529 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1530 btcoex->btcoex_period / 100;
1531
1532 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1533 (unsigned long) sc);
1534
1535 spin_lock_init(&btcoex->btcoex_lock);
1536
1537 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1538 ath_btcoex_no_stomp_timer,
1539 ath_btcoex_no_stomp_timer,
1540 (void *) sc, AR_FIRST_NDP_TIMER);
1541
1542 if (!btcoex->no_stomp_timer)
1543 return -ENOMEM;
1544
1545 return 0;
1546 }
1547
1548 /*
1549 * Read and write, they both share the same lock. We do this to serialize
1550 * reads and writes on Atheros 802.11n PCI devices only. This is required
1551 * as the FIFO on these devices can only accept sanely 2 requests. After
1552 * that the device goes bananas. Serializing the reads/writes prevents this
1553 * from happening.
1554 */
1555
1556 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1557 {
1558 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1559 struct ath_common *common = ath9k_hw_common(ah);
1560 struct ath_softc *sc = (struct ath_softc *) common->priv;
1561
1562 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1563 unsigned long flags;
1564 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1565 iowrite32(val, sc->mem + reg_offset);
1566 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1567 } else
1568 iowrite32(val, sc->mem + reg_offset);
1569 }
1570
1571 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1572 {
1573 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1574 struct ath_common *common = ath9k_hw_common(ah);
1575 struct ath_softc *sc = (struct ath_softc *) common->priv;
1576 u32 val;
1577
1578 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1579 unsigned long flags;
1580 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1581 val = ioread32(sc->mem + reg_offset);
1582 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1583 } else
1584 val = ioread32(sc->mem + reg_offset);
1585 return val;
1586 }
1587
1588 static const struct ath_ops ath9k_common_ops = {
1589 .read = ath9k_ioread32,
1590 .write = ath9k_iowrite32,
1591 };
1592
1593 /*
1594 * Initialize and fill ath_softc, ath_sofct is the
1595 * "Software Carrier" struct. Historically it has existed
1596 * to allow the separation between hardware specific
1597 * variables (now in ath_hw) and driver specific variables.
1598 */
1599 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1600 const struct ath_bus_ops *bus_ops)
1601 {
1602 struct ath_hw *ah = NULL;
1603 struct ath_common *common;
1604 int r = 0, i;
1605 int csz = 0;
1606 int qnum;
1607
1608 /* XXX: hardware will not be ready until ath_open() being called */
1609 sc->sc_flags |= SC_OP_INVALID;
1610
1611 spin_lock_init(&sc->wiphy_lock);
1612 spin_lock_init(&sc->sc_resetlock);
1613 spin_lock_init(&sc->sc_serial_rw);
1614 spin_lock_init(&sc->ani_lock);
1615 spin_lock_init(&sc->sc_pm_lock);
1616 mutex_init(&sc->mutex);
1617 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1618 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1619 (unsigned long)sc);
1620
1621 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1622 if (!ah)
1623 return -ENOMEM;
1624
1625 ah->hw_version.devid = devid;
1626 ah->hw_version.subsysid = subsysid;
1627 sc->sc_ah = ah;
1628
1629 common = ath9k_hw_common(ah);
1630 common->ops = &ath9k_common_ops;
1631 common->bus_ops = bus_ops;
1632 common->ah = ah;
1633 common->hw = sc->hw;
1634 common->priv = sc;
1635 common->debug_mask = ath9k_debug;
1636
1637 /*
1638 * Cache line size is used to size and align various
1639 * structures used to communicate with the hardware.
1640 */
1641 ath_read_cachesize(common, &csz);
1642 /* XXX assert csz is non-zero */
1643 common->cachelsz = csz << 2; /* convert to bytes */
1644
1645 r = ath9k_hw_init(ah);
1646 if (r) {
1647 ath_print(common, ATH_DBG_FATAL,
1648 "Unable to initialize hardware; "
1649 "initialization status: %d\n", r);
1650 goto bad_free_hw;
1651 }
1652
1653 if (ath9k_init_debug(ah) < 0) {
1654 ath_print(common, ATH_DBG_FATAL,
1655 "Unable to create debugfs files\n");
1656 goto bad_free_hw;
1657 }
1658
1659 /* Get the hardware key cache size. */
1660 common->keymax = ah->caps.keycache_size;
1661 if (common->keymax > ATH_KEYMAX) {
1662 ath_print(common, ATH_DBG_ANY,
1663 "Warning, using only %u entries in %u key cache\n",
1664 ATH_KEYMAX, common->keymax);
1665 common->keymax = ATH_KEYMAX;
1666 }
1667
1668 /*
1669 * Reset the key cache since some parts do not
1670 * reset the contents on initial power up.
1671 */
1672 for (i = 0; i < common->keymax; i++)
1673 ath9k_hw_keyreset(ah, (u16) i);
1674
1675 /* default to MONITOR mode */
1676 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1677
1678 /*
1679 * Allocate hardware transmit queues: one queue for
1680 * beacon frames and one data queue for each QoS
1681 * priority. Note that the hal handles reseting
1682 * these queues at the needed time.
1683 */
1684 sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
1685 if (sc->beacon.beaconq == -1) {
1686 ath_print(common, ATH_DBG_FATAL,
1687 "Unable to setup a beacon xmit queue\n");
1688 r = -EIO;
1689 goto bad2;
1690 }
1691 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1692 if (sc->beacon.cabq == NULL) {
1693 ath_print(common, ATH_DBG_FATAL,
1694 "Unable to setup CAB xmit queue\n");
1695 r = -EIO;
1696 goto bad2;
1697 }
1698
1699 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1700 ath_cabq_update(sc);
1701
1702 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1703 sc->tx.hwq_map[i] = -1;
1704
1705 /* Setup data queues */
1706 /* NB: ensure BK queue is the lowest priority h/w queue */
1707 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1708 ath_print(common, ATH_DBG_FATAL,
1709 "Unable to setup xmit queue for BK traffic\n");
1710 r = -EIO;
1711 goto bad2;
1712 }
1713
1714 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1715 ath_print(common, ATH_DBG_FATAL,
1716 "Unable to setup xmit queue for BE traffic\n");
1717 r = -EIO;
1718 goto bad2;
1719 }
1720 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1721 ath_print(common, ATH_DBG_FATAL,
1722 "Unable to setup xmit queue for VI traffic\n");
1723 r = -EIO;
1724 goto bad2;
1725 }
1726 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1727 ath_print(common, ATH_DBG_FATAL,
1728 "Unable to setup xmit queue for VO traffic\n");
1729 r = -EIO;
1730 goto bad2;
1731 }
1732
1733 /* Initializes the noise floor to a reasonable default value.
1734 * Later on this will be updated during ANI processing. */
1735
1736 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1737 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1738
1739 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1740 ATH9K_CIPHER_TKIP, NULL)) {
1741 /*
1742 * Whether we should enable h/w TKIP MIC.
1743 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1744 * report WMM capable, so it's always safe to turn on
1745 * TKIP MIC in this case.
1746 */
1747 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1748 0, 1, NULL);
1749 }
1750
1751 /*
1752 * Check whether the separate key cache entries
1753 * are required to handle both tx+rx MIC keys.
1754 * With split mic keys the number of stations is limited
1755 * to 27 otherwise 59.
1756 */
1757 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1758 ATH9K_CIPHER_TKIP, NULL)
1759 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1760 ATH9K_CIPHER_MIC, NULL)
1761 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1762 0, NULL))
1763 common->splitmic = 1;
1764
1765 /* turn on mcast key search if possible */
1766 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1767 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1768 1, NULL);
1769
1770 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1771
1772 /* 11n Capabilities */
1773 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1774 sc->sc_flags |= SC_OP_TXAGGR;
1775 sc->sc_flags |= SC_OP_RXAGGR;
1776 }
1777
1778 common->tx_chainmask = ah->caps.tx_chainmask;
1779 common->rx_chainmask = ah->caps.rx_chainmask;
1780
1781 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1782 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1783
1784 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1785 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1786
1787 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1788
1789 /* initialize beacon slots */
1790 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1791 sc->beacon.bslot[i] = NULL;
1792 sc->beacon.bslot_aphy[i] = NULL;
1793 }
1794
1795 /* setup channels and rates */
1796
1797 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
1798 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1799 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1800 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1801 ARRAY_SIZE(ath9k_2ghz_chantable);
1802 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
1803 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
1804 ARRAY_SIZE(ath9k_legacy_rates);
1805 }
1806
1807 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1808 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1809 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1810 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1811 ARRAY_SIZE(ath9k_5ghz_chantable);
1812 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1813 ath9k_legacy_rates + 4;
1814 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
1815 ARRAY_SIZE(ath9k_legacy_rates) - 4;
1816 }
1817
1818 switch (ah->btcoex_hw.scheme) {
1819 case ATH_BTCOEX_CFG_NONE:
1820 break;
1821 case ATH_BTCOEX_CFG_2WIRE:
1822 ath9k_hw_btcoex_init_2wire(ah);
1823 break;
1824 case ATH_BTCOEX_CFG_3WIRE:
1825 ath9k_hw_btcoex_init_3wire(ah);
1826 r = ath_init_btcoex_timer(sc);
1827 if (r)
1828 goto bad2;
1829 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1830 ath9k_hw_init_btcoex_hw(ah, qnum);
1831 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1832 break;
1833 default:
1834 WARN_ON(1);
1835 break;
1836 }
1837
1838 return 0;
1839 bad2:
1840 /* cleanup tx queues */
1841 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1842 if (ATH_TXQ_SETUP(sc, i))
1843 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1844
1845 bad_free_hw:
1846 ath9k_uninit_hw(sc);
1847 return r;
1848 }
1849
1850 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1851 {
1852 struct ath_hw *ah = sc->sc_ah;
1853
1854 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1855 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1856 IEEE80211_HW_SIGNAL_DBM |
1857 IEEE80211_HW_SUPPORTS_PS |
1858 IEEE80211_HW_PS_NULLFUNC_STACK |
1859 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
1860 IEEE80211_HW_SPECTRUM_MGMT;
1861
1862 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1863 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
1864
1865 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1866 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1867
1868 hw->wiphy->interface_modes =
1869 BIT(NL80211_IFTYPE_AP) |
1870 BIT(NL80211_IFTYPE_STATION) |
1871 BIT(NL80211_IFTYPE_ADHOC) |
1872 BIT(NL80211_IFTYPE_MESH_POINT);
1873
1874 if (AR_SREV_5416(ah))
1875 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1876
1877 hw->queues = 4;
1878 hw->max_rates = 4;
1879 hw->channel_change_time = 5000;
1880 hw->max_listen_interval = 10;
1881 /* Hardware supports 10 but we use 4 */
1882 hw->max_rate_tries = 4;
1883 hw->sta_data_size = sizeof(struct ath_node);
1884 hw->vif_data_size = sizeof(struct ath_vif);
1885
1886 hw->rate_control_algorithm = "ath9k_rate_control";
1887
1888 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
1889 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1890 &sc->sbands[IEEE80211_BAND_2GHZ];
1891 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1892 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1893 &sc->sbands[IEEE80211_BAND_5GHZ];
1894 }
1895
1896 /* Device driver core initialization */
1897 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1898 const struct ath_bus_ops *bus_ops)
1899 {
1900 struct ieee80211_hw *hw = sc->hw;
1901 struct ath_common *common;
1902 struct ath_hw *ah;
1903 int error = 0, i;
1904 struct ath_regulatory *reg;
1905
1906 dev_dbg(sc->dev, "Attach ATH hw\n");
1907
1908 error = ath_init_softc(devid, sc, subsysid, bus_ops);
1909 if (error != 0)
1910 return error;
1911
1912 ah = sc->sc_ah;
1913 common = ath9k_hw_common(ah);
1914
1915 /* get mac address from hardware and set in mac80211 */
1916
1917 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1918
1919 ath_set_hw_capab(sc, hw);
1920
1921 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1922 ath9k_reg_notifier);
1923 if (error)
1924 return error;
1925
1926 reg = &common->regulatory;
1927
1928 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1929 if (test_bit(ATH9K_MODE_11G, ah->caps.wireless_modes))
1930 setup_ht_cap(sc,
1931 &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1932 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1933 setup_ht_cap(sc,
1934 &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1935 }
1936
1937 /* initialize tx/rx engine */
1938 error = ath_tx_init(sc, ATH_TXBUF);
1939 if (error != 0)
1940 goto error_attach;
1941
1942 error = ath_rx_init(sc, ATH_RXBUF);
1943 if (error != 0)
1944 goto error_attach;
1945
1946 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1947 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1948 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1949
1950 error = ieee80211_register_hw(hw);
1951
1952 if (!ath_is_world_regd(reg)) {
1953 error = regulatory_hint(hw->wiphy, reg->alpha2);
1954 if (error)
1955 goto error_attach;
1956 }
1957
1958 /* Initialize LED control */
1959 ath_init_leds(sc);
1960
1961 ath_start_rfkill_poll(sc);
1962
1963 return 0;
1964
1965 error_attach:
1966 /* cleanup tx queues */
1967 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1968 if (ATH_TXQ_SETUP(sc, i))
1969 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1970
1971 ath9k_uninit_hw(sc);
1972
1973 return error;
1974 }
1975
1976 int ath_reset(struct ath_softc *sc, bool retry_tx)
1977 {
1978 struct ath_hw *ah = sc->sc_ah;
1979 struct ath_common *common = ath9k_hw_common(ah);
1980 struct ieee80211_hw *hw = sc->hw;
1981 int r;
1982
1983 /* Stop ANI */
1984 del_timer_sync(&common->ani.timer);
1985
1986 ath9k_hw_set_interrupts(ah, 0);
1987 ath_drain_all_txq(sc, retry_tx);
1988 ath_stoprecv(sc);
1989 ath_flushrecv(sc);
1990
1991 spin_lock_bh(&sc->sc_resetlock);
1992 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1993 if (r)
1994 ath_print(common, ATH_DBG_FATAL,
1995 "Unable to reset hardware; reset status %d\n", r);
1996 spin_unlock_bh(&sc->sc_resetlock);
1997
1998 if (ath_startrecv(sc) != 0)
1999 ath_print(common, ATH_DBG_FATAL,
2000 "Unable to start recv logic\n");
2001
2002 /*
2003 * We may be doing a reset in response to a request
2004 * that changes the channel so update any state that
2005 * might change as a result.
2006 */
2007 ath_cache_conf_rate(sc, &hw->conf);
2008
2009 ath_update_txpow(sc);
2010
2011 if (sc->sc_flags & SC_OP_BEACONS)
2012 ath_beacon_config(sc, NULL); /* restart beacons */
2013
2014 ath9k_hw_set_interrupts(ah, sc->imask);
2015
2016 if (retry_tx) {
2017 int i;
2018 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2019 if (ATH_TXQ_SETUP(sc, i)) {
2020 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2021 ath_txq_schedule(sc, &sc->tx.txq[i]);
2022 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
2023 }
2024 }
2025 }
2026
2027 /* Start ANI */
2028 ath_start_ani(common);
2029
2030 return r;
2031 }
2032
2033 /*
2034 * This function will allocate both the DMA descriptor structure, and the
2035 * buffers it contains. These are used to contain the descriptors used
2036 * by the system.
2037 */
2038 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2039 struct list_head *head, const char *name,
2040 int nbuf, int ndesc)
2041 {
2042 #define DS2PHYS(_dd, _ds) \
2043 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2044 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2045 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2046 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2047 struct ath_desc *ds;
2048 struct ath_buf *bf;
2049 int i, bsize, error;
2050
2051 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2052 name, nbuf, ndesc);
2053
2054 INIT_LIST_HEAD(head);
2055 /* ath_desc must be a multiple of DWORDs */
2056 if ((sizeof(struct ath_desc) % 4) != 0) {
2057 ath_print(common, ATH_DBG_FATAL,
2058 "ath_desc not DWORD aligned\n");
2059 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
2060 error = -ENOMEM;
2061 goto fail;
2062 }
2063
2064 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2065
2066 /*
2067 * Need additional DMA memory because we can't use
2068 * descriptors that cross the 4K page boundary. Assume
2069 * one skipped descriptor per 4K page.
2070 */
2071 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2072 u32 ndesc_skipped =
2073 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2074 u32 dma_len;
2075
2076 while (ndesc_skipped) {
2077 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2078 dd->dd_desc_len += dma_len;
2079
2080 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2081 };
2082 }
2083
2084 /* allocate descriptors */
2085 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2086 &dd->dd_desc_paddr, GFP_KERNEL);
2087 if (dd->dd_desc == NULL) {
2088 error = -ENOMEM;
2089 goto fail;
2090 }
2091 ds = dd->dd_desc;
2092 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2093 name, ds, (u32) dd->dd_desc_len,
2094 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2095
2096 /* allocate buffers */
2097 bsize = sizeof(struct ath_buf) * nbuf;
2098 bf = kzalloc(bsize, GFP_KERNEL);
2099 if (bf == NULL) {
2100 error = -ENOMEM;
2101 goto fail2;
2102 }
2103 dd->dd_bufptr = bf;
2104
2105 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2106 bf->bf_desc = ds;
2107 bf->bf_daddr = DS2PHYS(dd, ds);
2108
2109 if (!(sc->sc_ah->caps.hw_caps &
2110 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2111 /*
2112 * Skip descriptor addresses which can cause 4KB
2113 * boundary crossing (addr + length) with a 32 dword
2114 * descriptor fetch.
2115 */
2116 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2117 BUG_ON((caddr_t) bf->bf_desc >=
2118 ((caddr_t) dd->dd_desc +
2119 dd->dd_desc_len));
2120
2121 ds += ndesc;
2122 bf->bf_desc = ds;
2123 bf->bf_daddr = DS2PHYS(dd, ds);
2124 }
2125 }
2126 list_add_tail(&bf->list, head);
2127 }
2128 return 0;
2129 fail2:
2130 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2131 dd->dd_desc_paddr);
2132 fail:
2133 memset(dd, 0, sizeof(*dd));
2134 return error;
2135 #undef ATH_DESC_4KB_BOUND_CHECK
2136 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2137 #undef DS2PHYS
2138 }
2139
2140 void ath_descdma_cleanup(struct ath_softc *sc,
2141 struct ath_descdma *dd,
2142 struct list_head *head)
2143 {
2144 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2145 dd->dd_desc_paddr);
2146
2147 INIT_LIST_HEAD(head);
2148 kfree(dd->dd_bufptr);
2149 memset(dd, 0, sizeof(*dd));
2150 }
2151
2152 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2153 {
2154 int qnum;
2155
2156 switch (queue) {
2157 case 0:
2158 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2159 break;
2160 case 1:
2161 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2162 break;
2163 case 2:
2164 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2165 break;
2166 case 3:
2167 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2168 break;
2169 default:
2170 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2171 break;
2172 }
2173
2174 return qnum;
2175 }
2176
2177 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2178 {
2179 int qnum;
2180
2181 switch (queue) {
2182 case ATH9K_WME_AC_VO:
2183 qnum = 0;
2184 break;
2185 case ATH9K_WME_AC_VI:
2186 qnum = 1;
2187 break;
2188 case ATH9K_WME_AC_BE:
2189 qnum = 2;
2190 break;
2191 case ATH9K_WME_AC_BK:
2192 qnum = 3;
2193 break;
2194 default:
2195 qnum = -1;
2196 break;
2197 }
2198
2199 return qnum;
2200 }
2201
2202 /* XXX: Remove me once we don't depend on ath9k_channel for all
2203 * this redundant data */
2204 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2205 struct ath9k_channel *ichan)
2206 {
2207 struct ieee80211_channel *chan = hw->conf.channel;
2208 struct ieee80211_conf *conf = &hw->conf;
2209
2210 ichan->channel = chan->center_freq;
2211 ichan->chan = chan;
2212
2213 if (chan->band == IEEE80211_BAND_2GHZ) {
2214 ichan->chanmode = CHANNEL_G;
2215 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2216 } else {
2217 ichan->chanmode = CHANNEL_A;
2218 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2219 }
2220
2221 if (conf_is_ht(conf))
2222 ichan->chanmode = ath_get_extchanmode(sc, chan,
2223 conf->channel_type);
2224 }
2225
2226 /**********************/
2227 /* mac80211 callbacks */
2228 /**********************/
2229
2230 /*
2231 * (Re)start btcoex timers
2232 */
2233 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2234 {
2235 struct ath_btcoex *btcoex = &sc->btcoex;
2236 struct ath_hw *ah = sc->sc_ah;
2237
2238 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2239 "Starting btcoex timers");
2240
2241 /* make sure duty cycle timer is also stopped when resuming */
2242 if (btcoex->hw_timer_enabled)
2243 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2244
2245 btcoex->bt_priority_cnt = 0;
2246 btcoex->bt_priority_time = jiffies;
2247 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2248
2249 mod_timer(&btcoex->period_timer, jiffies);
2250 }
2251
2252 static int ath9k_start(struct ieee80211_hw *hw)
2253 {
2254 struct ath_wiphy *aphy = hw->priv;
2255 struct ath_softc *sc = aphy->sc;
2256 struct ath_hw *ah = sc->sc_ah;
2257 struct ath_common *common = ath9k_hw_common(ah);
2258 struct ieee80211_channel *curchan = hw->conf.channel;
2259 struct ath9k_channel *init_channel;
2260 int r;
2261
2262 ath_print(common, ATH_DBG_CONFIG,
2263 "Starting driver with initial channel: %d MHz\n",
2264 curchan->center_freq);
2265
2266 mutex_lock(&sc->mutex);
2267
2268 if (ath9k_wiphy_started(sc)) {
2269 if (sc->chan_idx == curchan->hw_value) {
2270 /*
2271 * Already on the operational channel, the new wiphy
2272 * can be marked active.
2273 */
2274 aphy->state = ATH_WIPHY_ACTIVE;
2275 ieee80211_wake_queues(hw);
2276 } else {
2277 /*
2278 * Another wiphy is on another channel, start the new
2279 * wiphy in paused state.
2280 */
2281 aphy->state = ATH_WIPHY_PAUSED;
2282 ieee80211_stop_queues(hw);
2283 }
2284 mutex_unlock(&sc->mutex);
2285 return 0;
2286 }
2287 aphy->state = ATH_WIPHY_ACTIVE;
2288
2289 /* setup initial channel */
2290
2291 sc->chan_idx = curchan->hw_value;
2292
2293 init_channel = ath_get_curchannel(sc, hw);
2294
2295 /* Reset SERDES registers */
2296 ath9k_hw_configpcipowersave(ah, 0, 0);
2297
2298 /*
2299 * The basic interface to setting the hardware in a good
2300 * state is ``reset''. On return the hardware is known to
2301 * be powered up and with interrupts disabled. This must
2302 * be followed by initialization of the appropriate bits
2303 * and then setup of the interrupt mask.
2304 */
2305 spin_lock_bh(&sc->sc_resetlock);
2306 r = ath9k_hw_reset(ah, init_channel, false);
2307 if (r) {
2308 ath_print(common, ATH_DBG_FATAL,
2309 "Unable to reset hardware; reset status %d "
2310 "(freq %u MHz)\n", r,
2311 curchan->center_freq);
2312 spin_unlock_bh(&sc->sc_resetlock);
2313 goto mutex_unlock;
2314 }
2315 spin_unlock_bh(&sc->sc_resetlock);
2316
2317 /*
2318 * This is needed only to setup initial state
2319 * but it's best done after a reset.
2320 */
2321 ath_update_txpow(sc);
2322
2323 /*
2324 * Setup the hardware after reset:
2325 * The receive engine is set going.
2326 * Frame transmit is handled entirely
2327 * in the frame output path; there's nothing to do
2328 * here except setup the interrupt mask.
2329 */
2330 if (ath_startrecv(sc) != 0) {
2331 ath_print(common, ATH_DBG_FATAL,
2332 "Unable to start recv logic\n");
2333 r = -EIO;
2334 goto mutex_unlock;
2335 }
2336
2337 /* Setup our intr mask. */
2338 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2339 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2340 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2341
2342 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2343 sc->imask |= ATH9K_INT_GTT;
2344
2345 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2346 sc->imask |= ATH9K_INT_CST;
2347
2348 ath_cache_conf_rate(sc, &hw->conf);
2349
2350 sc->sc_flags &= ~SC_OP_INVALID;
2351
2352 /* Disable BMISS interrupt when we're not associated */
2353 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2354 ath9k_hw_set_interrupts(ah, sc->imask);
2355
2356 ieee80211_wake_queues(hw);
2357
2358 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2359
2360 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2361 !ah->btcoex_hw.enabled) {
2362 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2363 AR_STOMP_LOW_WLAN_WGHT);
2364 ath9k_hw_btcoex_enable(ah);
2365
2366 if (common->bus_ops->bt_coex_prep)
2367 common->bus_ops->bt_coex_prep(common);
2368 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2369 ath9k_btcoex_timer_resume(sc);
2370 }
2371
2372 mutex_unlock:
2373 mutex_unlock(&sc->mutex);
2374
2375 return r;
2376 }
2377
2378 static int ath9k_tx(struct ieee80211_hw *hw,
2379 struct sk_buff *skb)
2380 {
2381 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2382 struct ath_wiphy *aphy = hw->priv;
2383 struct ath_softc *sc = aphy->sc;
2384 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2385 struct ath_tx_control txctl;
2386 int padpos, padsize;
2387 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2388
2389 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2390 ath_print(common, ATH_DBG_XMIT,
2391 "ath9k: %s: TX in unexpected wiphy state "
2392 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2393 goto exit;
2394 }
2395
2396 if (sc->ps_enabled) {
2397 /*
2398 * mac80211 does not set PM field for normal data frames, so we
2399 * need to update that based on the current PS mode.
2400 */
2401 if (ieee80211_is_data(hdr->frame_control) &&
2402 !ieee80211_is_nullfunc(hdr->frame_control) &&
2403 !ieee80211_has_pm(hdr->frame_control)) {
2404 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2405 "while in PS mode\n");
2406 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2407 }
2408 }
2409
2410 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2411 /*
2412 * We are using PS-Poll and mac80211 can request TX while in
2413 * power save mode. Need to wake up hardware for the TX to be
2414 * completed and if needed, also for RX of buffered frames.
2415 */
2416 ath9k_ps_wakeup(sc);
2417 ath9k_hw_setrxabort(sc->sc_ah, 0);
2418 if (ieee80211_is_pspoll(hdr->frame_control)) {
2419 ath_print(common, ATH_DBG_PS,
2420 "Sending PS-Poll to pick a buffered frame\n");
2421 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2422 } else {
2423 ath_print(common, ATH_DBG_PS,
2424 "Wake up to complete TX\n");
2425 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2426 }
2427 /*
2428 * The actual restore operation will happen only after
2429 * the sc_flags bit is cleared. We are just dropping
2430 * the ps_usecount here.
2431 */
2432 ath9k_ps_restore(sc);
2433 }
2434
2435 memset(&txctl, 0, sizeof(struct ath_tx_control));
2436
2437 /*
2438 * As a temporary workaround, assign seq# here; this will likely need
2439 * to be cleaned up to work better with Beacon transmission and virtual
2440 * BSSes.
2441 */
2442 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2443 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2444 sc->tx.seq_no += 0x10;
2445 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2446 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2447 }
2448
2449 /* Add the padding after the header if this is not already done */
2450 padpos = ath9k_cmn_padpos(hdr->frame_control);
2451 padsize = padpos & 3;
2452 if (padsize && skb->len>padpos) {
2453 if (skb_headroom(skb) < padsize)
2454 return -1;
2455 skb_push(skb, padsize);
2456 memmove(skb->data, skb->data + padsize, padpos);
2457 }
2458
2459 /* Check if a tx queue is available */
2460
2461 txctl.txq = ath_test_get_txq(sc, skb);
2462 if (!txctl.txq)
2463 goto exit;
2464
2465 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2466
2467 if (ath_tx_start(hw, skb, &txctl) != 0) {
2468 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2469 goto exit;
2470 }
2471
2472 return 0;
2473 exit:
2474 dev_kfree_skb_any(skb);
2475 return 0;
2476 }
2477
2478 /*
2479 * Pause btcoex timer and bt duty cycle timer
2480 */
2481 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2482 {
2483 struct ath_btcoex *btcoex = &sc->btcoex;
2484 struct ath_hw *ah = sc->sc_ah;
2485
2486 del_timer_sync(&btcoex->period_timer);
2487
2488 if (btcoex->hw_timer_enabled)
2489 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2490
2491 btcoex->hw_timer_enabled = false;
2492 }
2493
2494 static void ath9k_stop(struct ieee80211_hw *hw)
2495 {
2496 struct ath_wiphy *aphy = hw->priv;
2497 struct ath_softc *sc = aphy->sc;
2498 struct ath_hw *ah = sc->sc_ah;
2499 struct ath_common *common = ath9k_hw_common(ah);
2500
2501 mutex_lock(&sc->mutex);
2502
2503 aphy->state = ATH_WIPHY_INACTIVE;
2504
2505 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2506 cancel_delayed_work_sync(&sc->tx_complete_work);
2507
2508 if (!sc->num_sec_wiphy) {
2509 cancel_delayed_work_sync(&sc->wiphy_work);
2510 cancel_work_sync(&sc->chan_work);
2511 }
2512
2513 if (sc->sc_flags & SC_OP_INVALID) {
2514 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2515 mutex_unlock(&sc->mutex);
2516 return;
2517 }
2518
2519 if (ath9k_wiphy_started(sc)) {
2520 mutex_unlock(&sc->mutex);
2521 return; /* another wiphy still in use */
2522 }
2523
2524 /* Ensure HW is awake when we try to shut it down. */
2525 ath9k_ps_wakeup(sc);
2526
2527 if (ah->btcoex_hw.enabled) {
2528 ath9k_hw_btcoex_disable(ah);
2529 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2530 ath9k_btcoex_timer_pause(sc);
2531 }
2532
2533 /* make sure h/w will not generate any interrupt
2534 * before setting the invalid flag. */
2535 ath9k_hw_set_interrupts(ah, 0);
2536
2537 if (!(sc->sc_flags & SC_OP_INVALID)) {
2538 ath_drain_all_txq(sc, false);
2539 ath_stoprecv(sc);
2540 ath9k_hw_phy_disable(ah);
2541 } else
2542 sc->rx.rxlink = NULL;
2543
2544 /* disable HAL and put h/w to sleep */
2545 ath9k_hw_disable(ah);
2546 ath9k_hw_configpcipowersave(ah, 1, 1);
2547 ath9k_ps_restore(sc);
2548
2549 /* Finally, put the chip in FULL SLEEP mode */
2550 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2551
2552 sc->sc_flags |= SC_OP_INVALID;
2553
2554 mutex_unlock(&sc->mutex);
2555
2556 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2557 }
2558
2559 static int ath9k_add_interface(struct ieee80211_hw *hw,
2560 struct ieee80211_if_init_conf *conf)
2561 {
2562 struct ath_wiphy *aphy = hw->priv;
2563 struct ath_softc *sc = aphy->sc;
2564 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2565 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2566 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2567 int ret = 0;
2568
2569 mutex_lock(&sc->mutex);
2570
2571 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2572 sc->nvifs > 0) {
2573 ret = -ENOBUFS;
2574 goto out;
2575 }
2576
2577 switch (conf->type) {
2578 case NL80211_IFTYPE_STATION:
2579 ic_opmode = NL80211_IFTYPE_STATION;
2580 break;
2581 case NL80211_IFTYPE_ADHOC:
2582 case NL80211_IFTYPE_AP:
2583 case NL80211_IFTYPE_MESH_POINT:
2584 if (sc->nbcnvifs >= ATH_BCBUF) {
2585 ret = -ENOBUFS;
2586 goto out;
2587 }
2588 ic_opmode = conf->type;
2589 break;
2590 default:
2591 ath_print(common, ATH_DBG_FATAL,
2592 "Interface type %d not yet supported\n", conf->type);
2593 ret = -EOPNOTSUPP;
2594 goto out;
2595 }
2596
2597 ath_print(common, ATH_DBG_CONFIG,
2598 "Attach a VIF of type: %d\n", ic_opmode);
2599
2600 /* Set the VIF opmode */
2601 avp->av_opmode = ic_opmode;
2602 avp->av_bslot = -1;
2603
2604 sc->nvifs++;
2605
2606 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2607 ath9k_set_bssid_mask(hw);
2608
2609 if (sc->nvifs > 1)
2610 goto out; /* skip global settings for secondary vif */
2611
2612 if (ic_opmode == NL80211_IFTYPE_AP) {
2613 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2614 sc->sc_flags |= SC_OP_TSF_RESET;
2615 }
2616
2617 /* Set the device opmode */
2618 sc->sc_ah->opmode = ic_opmode;
2619
2620 /*
2621 * Enable MIB interrupts when there are hardware phy counters.
2622 * Note we only do this (at the moment) for station mode.
2623 */
2624 if ((conf->type == NL80211_IFTYPE_STATION) ||
2625 (conf->type == NL80211_IFTYPE_ADHOC) ||
2626 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2627 sc->imask |= ATH9K_INT_MIB;
2628 sc->imask |= ATH9K_INT_TSFOOR;
2629 }
2630
2631 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2632
2633 if (conf->type == NL80211_IFTYPE_AP ||
2634 conf->type == NL80211_IFTYPE_ADHOC ||
2635 conf->type == NL80211_IFTYPE_MONITOR)
2636 ath_start_ani(common);
2637
2638 out:
2639 mutex_unlock(&sc->mutex);
2640 return ret;
2641 }
2642
2643 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2644 struct ieee80211_if_init_conf *conf)
2645 {
2646 struct ath_wiphy *aphy = hw->priv;
2647 struct ath_softc *sc = aphy->sc;
2648 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2649 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2650 int i;
2651
2652 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2653
2654 mutex_lock(&sc->mutex);
2655
2656 /* Stop ANI */
2657 del_timer_sync(&common->ani.timer);
2658
2659 /* Reclaim beacon resources */
2660 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2661 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2662 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2663 ath9k_ps_wakeup(sc);
2664 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2665 ath9k_ps_restore(sc);
2666 }
2667
2668 ath_beacon_return(sc, avp);
2669 sc->sc_flags &= ~SC_OP_BEACONS;
2670
2671 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2672 if (sc->beacon.bslot[i] == conf->vif) {
2673 printk(KERN_DEBUG "%s: vif had allocated beacon "
2674 "slot\n", __func__);
2675 sc->beacon.bslot[i] = NULL;
2676 sc->beacon.bslot_aphy[i] = NULL;
2677 }
2678 }
2679
2680 sc->nvifs--;
2681
2682 mutex_unlock(&sc->mutex);
2683 }
2684
2685 void ath9k_enable_ps(struct ath_softc *sc)
2686 {
2687 sc->ps_enabled = true;
2688 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2689 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2690 sc->imask |= ATH9K_INT_TIM_TIMER;
2691 ath9k_hw_set_interrupts(sc->sc_ah,
2692 sc->imask);
2693 }
2694 }
2695 ath9k_hw_setrxabort(sc->sc_ah, 1);
2696 }
2697
2698 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2699 {
2700 struct ath_wiphy *aphy = hw->priv;
2701 struct ath_softc *sc = aphy->sc;
2702 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2703 struct ieee80211_conf *conf = &hw->conf;
2704 struct ath_hw *ah = sc->sc_ah;
2705 bool disable_radio;
2706
2707 mutex_lock(&sc->mutex);
2708
2709 /*
2710 * Leave this as the first check because we need to turn on the
2711 * radio if it was disabled before prior to processing the rest
2712 * of the changes. Likewise we must only disable the radio towards
2713 * the end.
2714 */
2715 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2716 bool enable_radio;
2717 bool all_wiphys_idle;
2718 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
2719
2720 spin_lock_bh(&sc->wiphy_lock);
2721 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2722 ath9k_set_wiphy_idle(aphy, idle);
2723
2724 enable_radio = (!idle && all_wiphys_idle);
2725
2726 /*
2727 * After we unlock here its possible another wiphy
2728 * can be re-renabled so to account for that we will
2729 * only disable the radio toward the end of this routine
2730 * if by then all wiphys are still idle.
2731 */
2732 spin_unlock_bh(&sc->wiphy_lock);
2733
2734 if (enable_radio) {
2735 ath_radio_enable(sc, hw);
2736 ath_print(common, ATH_DBG_CONFIG,
2737 "not-idle: enabling radio\n");
2738 }
2739 }
2740
2741 /*
2742 * We just prepare to enable PS. We have to wait until our AP has
2743 * ACK'd our null data frame to disable RX otherwise we'll ignore
2744 * those ACKs and end up retransmitting the same null data frames.
2745 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
2746 */
2747 if (changed & IEEE80211_CONF_CHANGE_PS) {
2748 if (conf->flags & IEEE80211_CONF_PS) {
2749 sc->sc_flags |= SC_OP_PS_ENABLED;
2750 /*
2751 * At this point we know hardware has received an ACK
2752 * of a previously sent null data frame.
2753 */
2754 if ((sc->sc_flags & SC_OP_NULLFUNC_COMPLETED)) {
2755 sc->sc_flags &= ~SC_OP_NULLFUNC_COMPLETED;
2756 ath9k_enable_ps(sc);
2757 }
2758 } else {
2759 sc->ps_enabled = false;
2760 sc->sc_flags &= ~(SC_OP_PS_ENABLED |
2761 SC_OP_NULLFUNC_COMPLETED);
2762 ath9k_setpower(sc, ATH9K_PM_AWAKE);
2763 if (!(ah->caps.hw_caps &
2764 ATH9K_HW_CAP_AUTOSLEEP)) {
2765 ath9k_hw_setrxabort(sc->sc_ah, 0);
2766 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2767 SC_OP_WAIT_FOR_CAB |
2768 SC_OP_WAIT_FOR_PSPOLL_DATA |
2769 SC_OP_WAIT_FOR_TX_ACK);
2770 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2771 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2772 ath9k_hw_set_interrupts(sc->sc_ah,
2773 sc->imask);
2774 }
2775 }
2776 }
2777 }
2778
2779 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2780 struct ieee80211_channel *curchan = hw->conf.channel;
2781 int pos = curchan->hw_value;
2782
2783 aphy->chan_idx = pos;
2784 aphy->chan_is_ht = conf_is_ht(conf);
2785
2786 if (aphy->state == ATH_WIPHY_SCAN ||
2787 aphy->state == ATH_WIPHY_ACTIVE)
2788 ath9k_wiphy_pause_all_forced(sc, aphy);
2789 else {
2790 /*
2791 * Do not change operational channel based on a paused
2792 * wiphy changes.
2793 */
2794 goto skip_chan_change;
2795 }
2796
2797 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2798 curchan->center_freq);
2799
2800 /* XXX: remove me eventualy */
2801 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2802
2803 ath_update_chainmask(sc, conf_is_ht(conf));
2804
2805 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2806 ath_print(common, ATH_DBG_FATAL,
2807 "Unable to set channel\n");
2808 mutex_unlock(&sc->mutex);
2809 return -EINVAL;
2810 }
2811 }
2812
2813 skip_chan_change:
2814 if (changed & IEEE80211_CONF_CHANGE_POWER)
2815 sc->config.txpowlimit = 2 * conf->power_level;
2816
2817 spin_lock_bh(&sc->wiphy_lock);
2818 disable_radio = ath9k_all_wiphys_idle(sc);
2819 spin_unlock_bh(&sc->wiphy_lock);
2820
2821 if (disable_radio) {
2822 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2823 ath_radio_disable(sc, hw);
2824 }
2825
2826 mutex_unlock(&sc->mutex);
2827
2828 return 0;
2829 }
2830
2831 #define SUPPORTED_FILTERS \
2832 (FIF_PROMISC_IN_BSS | \
2833 FIF_ALLMULTI | \
2834 FIF_CONTROL | \
2835 FIF_PSPOLL | \
2836 FIF_OTHER_BSS | \
2837 FIF_BCN_PRBRESP_PROMISC | \
2838 FIF_FCSFAIL)
2839
2840 /* FIXME: sc->sc_full_reset ? */
2841 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2842 unsigned int changed_flags,
2843 unsigned int *total_flags,
2844 u64 multicast)
2845 {
2846 struct ath_wiphy *aphy = hw->priv;
2847 struct ath_softc *sc = aphy->sc;
2848 u32 rfilt;
2849
2850 changed_flags &= SUPPORTED_FILTERS;
2851 *total_flags &= SUPPORTED_FILTERS;
2852
2853 sc->rx.rxfilter = *total_flags;
2854 ath9k_ps_wakeup(sc);
2855 rfilt = ath_calcrxfilter(sc);
2856 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2857 ath9k_ps_restore(sc);
2858
2859 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2860 "Set HW RX filter: 0x%x\n", rfilt);
2861 }
2862
2863 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2864 struct ieee80211_vif *vif,
2865 enum sta_notify_cmd cmd,
2866 struct ieee80211_sta *sta)
2867 {
2868 struct ath_wiphy *aphy = hw->priv;
2869 struct ath_softc *sc = aphy->sc;
2870
2871 switch (cmd) {
2872 case STA_NOTIFY_ADD:
2873 ath_node_attach(sc, sta);
2874 break;
2875 case STA_NOTIFY_REMOVE:
2876 ath_node_detach(sc, sta);
2877 break;
2878 default:
2879 break;
2880 }
2881 }
2882
2883 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2884 const struct ieee80211_tx_queue_params *params)
2885 {
2886 struct ath_wiphy *aphy = hw->priv;
2887 struct ath_softc *sc = aphy->sc;
2888 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2889 struct ath9k_tx_queue_info qi;
2890 int ret = 0, qnum;
2891
2892 if (queue >= WME_NUM_AC)
2893 return 0;
2894
2895 mutex_lock(&sc->mutex);
2896
2897 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2898
2899 qi.tqi_aifs = params->aifs;
2900 qi.tqi_cwmin = params->cw_min;
2901 qi.tqi_cwmax = params->cw_max;
2902 qi.tqi_burstTime = params->txop;
2903 qnum = ath_get_hal_qnum(queue, sc);
2904
2905 ath_print(common, ATH_DBG_CONFIG,
2906 "Configure tx [queue/halq] [%d/%d], "
2907 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2908 queue, qnum, params->aifs, params->cw_min,
2909 params->cw_max, params->txop);
2910
2911 ret = ath_txq_update(sc, qnum, &qi);
2912 if (ret)
2913 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2914
2915 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
2916 if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
2917 ath_beaconq_config(sc);
2918
2919 mutex_unlock(&sc->mutex);
2920
2921 return ret;
2922 }
2923
2924 static int ath9k_set_key(struct ieee80211_hw *hw,
2925 enum set_key_cmd cmd,
2926 struct ieee80211_vif *vif,
2927 struct ieee80211_sta *sta,
2928 struct ieee80211_key_conf *key)
2929 {
2930 struct ath_wiphy *aphy = hw->priv;
2931 struct ath_softc *sc = aphy->sc;
2932 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2933 int ret = 0;
2934
2935 if (modparam_nohwcrypt)
2936 return -ENOSPC;
2937
2938 mutex_lock(&sc->mutex);
2939 ath9k_ps_wakeup(sc);
2940 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2941
2942 switch (cmd) {
2943 case SET_KEY:
2944 ret = ath_key_config(common, vif, sta, key);
2945 if (ret >= 0) {
2946 key->hw_key_idx = ret;
2947 /* push IV and Michael MIC generation to stack */
2948 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2949 if (key->alg == ALG_TKIP)
2950 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2951 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2952 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2953 ret = 0;
2954 }
2955 break;
2956 case DISABLE_KEY:
2957 ath_key_delete(common, key);
2958 break;
2959 default:
2960 ret = -EINVAL;
2961 }
2962
2963 ath9k_ps_restore(sc);
2964 mutex_unlock(&sc->mutex);
2965
2966 return ret;
2967 }
2968
2969 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2970 struct ieee80211_vif *vif,
2971 struct ieee80211_bss_conf *bss_conf,
2972 u32 changed)
2973 {
2974 struct ath_wiphy *aphy = hw->priv;
2975 struct ath_softc *sc = aphy->sc;
2976 struct ath_hw *ah = sc->sc_ah;
2977 struct ath_common *common = ath9k_hw_common(ah);
2978 struct ath_vif *avp = (void *)vif->drv_priv;
2979 int error;
2980
2981 mutex_lock(&sc->mutex);
2982
2983 if (changed & BSS_CHANGED_BSSID) {
2984 /* Set BSSID */
2985 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2986 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2987 common->curaid = 0;
2988 ath9k_hw_write_associd(ah);
2989
2990 /* Set aggregation protection mode parameters */
2991 sc->config.ath_aggr_prot = 0;
2992
2993 /* Only legacy IBSS for now */
2994 if (vif->type == NL80211_IFTYPE_ADHOC)
2995 ath_update_chainmask(sc, 0);
2996
2997 ath_print(common, ATH_DBG_CONFIG,
2998 "BSSID: %pM aid: 0x%x\n",
2999 common->curbssid, common->curaid);
3000
3001 /* need to reconfigure the beacon */
3002 sc->sc_flags &= ~SC_OP_BEACONS ;
3003 }
3004
3005 /* Enable transmission of beacons (AP, IBSS, MESH) */
3006 if ((changed & BSS_CHANGED_BEACON) ||
3007 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
3008 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
3009 error = ath_beacon_alloc(aphy, vif);
3010 if (!error)
3011 ath_beacon_config(sc, vif);
3012 }
3013
3014 /* Disable transmission of beacons */
3015 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
3016 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
3017
3018 if (changed & BSS_CHANGED_BEACON_INT) {
3019 sc->beacon_interval = bss_conf->beacon_int;
3020 /*
3021 * In case of AP mode, the HW TSF has to be reset
3022 * when the beacon interval changes.
3023 */
3024 if (vif->type == NL80211_IFTYPE_AP) {
3025 sc->sc_flags |= SC_OP_TSF_RESET;
3026 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
3027 error = ath_beacon_alloc(aphy, vif);
3028 if (!error)
3029 ath_beacon_config(sc, vif);
3030 } else {
3031 ath_beacon_config(sc, vif);
3032 }
3033 }
3034
3035 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3036 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3037 bss_conf->use_short_preamble);
3038 if (bss_conf->use_short_preamble)
3039 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3040 else
3041 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3042 }
3043
3044 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
3045 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3046 bss_conf->use_cts_prot);
3047 if (bss_conf->use_cts_prot &&
3048 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3049 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3050 else
3051 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3052 }
3053
3054 if (changed & BSS_CHANGED_ASSOC) {
3055 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3056 bss_conf->assoc);
3057 ath9k_bss_assoc_info(sc, vif, bss_conf);
3058 }
3059
3060 mutex_unlock(&sc->mutex);
3061 }
3062
3063 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3064 {
3065 u64 tsf;
3066 struct ath_wiphy *aphy = hw->priv;
3067 struct ath_softc *sc = aphy->sc;
3068
3069 mutex_lock(&sc->mutex);
3070 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3071 mutex_unlock(&sc->mutex);
3072
3073 return tsf;
3074 }
3075
3076 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3077 {
3078 struct ath_wiphy *aphy = hw->priv;
3079 struct ath_softc *sc = aphy->sc;
3080
3081 mutex_lock(&sc->mutex);
3082 ath9k_hw_settsf64(sc->sc_ah, tsf);
3083 mutex_unlock(&sc->mutex);
3084 }
3085
3086 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3087 {
3088 struct ath_wiphy *aphy = hw->priv;
3089 struct ath_softc *sc = aphy->sc;
3090
3091 mutex_lock(&sc->mutex);
3092
3093 ath9k_ps_wakeup(sc);
3094 ath9k_hw_reset_tsf(sc->sc_ah);
3095 ath9k_ps_restore(sc);
3096
3097 mutex_unlock(&sc->mutex);
3098 }
3099
3100 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3101 struct ieee80211_vif *vif,
3102 enum ieee80211_ampdu_mlme_action action,
3103 struct ieee80211_sta *sta,
3104 u16 tid, u16 *ssn)
3105 {
3106 struct ath_wiphy *aphy = hw->priv;
3107 struct ath_softc *sc = aphy->sc;
3108 int ret = 0;
3109
3110 switch (action) {
3111 case IEEE80211_AMPDU_RX_START:
3112 if (!(sc->sc_flags & SC_OP_RXAGGR))
3113 ret = -ENOTSUPP;
3114 break;
3115 case IEEE80211_AMPDU_RX_STOP:
3116 break;
3117 case IEEE80211_AMPDU_TX_START:
3118 ath9k_ps_wakeup(sc);
3119 ath_tx_aggr_start(sc, sta, tid, ssn);
3120 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3121 ath9k_ps_restore(sc);
3122 break;
3123 case IEEE80211_AMPDU_TX_STOP:
3124 ath9k_ps_wakeup(sc);
3125 ath_tx_aggr_stop(sc, sta, tid);
3126 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3127 ath9k_ps_restore(sc);
3128 break;
3129 case IEEE80211_AMPDU_TX_OPERATIONAL:
3130 ath9k_ps_wakeup(sc);
3131 ath_tx_aggr_resume(sc, sta, tid);
3132 ath9k_ps_restore(sc);
3133 break;
3134 default:
3135 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3136 "Unknown AMPDU action\n");
3137 }
3138
3139 return ret;
3140 }
3141
3142 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3143 {
3144 struct ath_wiphy *aphy = hw->priv;
3145 struct ath_softc *sc = aphy->sc;
3146
3147 mutex_lock(&sc->mutex);
3148 if (ath9k_wiphy_scanning(sc)) {
3149 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3150 "same time\n");
3151 /*
3152 * Do not allow the concurrent scanning state for now. This
3153 * could be improved with scanning control moved into ath9k.
3154 */
3155 mutex_unlock(&sc->mutex);
3156 return;
3157 }
3158
3159 aphy->state = ATH_WIPHY_SCAN;
3160 ath9k_wiphy_pause_all_forced(sc, aphy);
3161
3162 spin_lock_bh(&sc->ani_lock);
3163 sc->sc_flags |= SC_OP_SCANNING;
3164 spin_unlock_bh(&sc->ani_lock);
3165 mutex_unlock(&sc->mutex);
3166 }
3167
3168 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3169 {
3170 struct ath_wiphy *aphy = hw->priv;
3171 struct ath_softc *sc = aphy->sc;
3172
3173 mutex_lock(&sc->mutex);
3174 spin_lock_bh(&sc->ani_lock);
3175 aphy->state = ATH_WIPHY_ACTIVE;
3176 sc->sc_flags &= ~SC_OP_SCANNING;
3177 sc->sc_flags |= SC_OP_FULL_RESET;
3178 spin_unlock_bh(&sc->ani_lock);
3179 ath_beacon_config(sc, NULL);
3180 mutex_unlock(&sc->mutex);
3181 }
3182
3183 struct ieee80211_ops ath9k_ops = {
3184 .tx = ath9k_tx,
3185 .start = ath9k_start,
3186 .stop = ath9k_stop,
3187 .add_interface = ath9k_add_interface,
3188 .remove_interface = ath9k_remove_interface,
3189 .config = ath9k_config,
3190 .configure_filter = ath9k_configure_filter,
3191 .sta_notify = ath9k_sta_notify,
3192 .conf_tx = ath9k_conf_tx,
3193 .bss_info_changed = ath9k_bss_info_changed,
3194 .set_key = ath9k_set_key,
3195 .get_tsf = ath9k_get_tsf,
3196 .set_tsf = ath9k_set_tsf,
3197 .reset_tsf = ath9k_reset_tsf,
3198 .ampdu_action = ath9k_ampdu_action,
3199 .sw_scan_start = ath9k_sw_scan_start,
3200 .sw_scan_complete = ath9k_sw_scan_complete,
3201 .rfkill_poll = ath9k_rfkill_poll_state,
3202 };
3203
3204 static int __init ath9k_init(void)
3205 {
3206 int error;
3207
3208 /* Register rate control algorithm */
3209 error = ath_rate_control_register();
3210 if (error != 0) {
3211 printk(KERN_ERR
3212 "ath9k: Unable to register rate control "
3213 "algorithm: %d\n",
3214 error);
3215 goto err_out;
3216 }
3217
3218 error = ath9k_debug_create_root();
3219 if (error) {
3220 printk(KERN_ERR
3221 "ath9k: Unable to create debugfs root: %d\n",
3222 error);
3223 goto err_rate_unregister;
3224 }
3225
3226 error = ath_pci_init();
3227 if (error < 0) {
3228 printk(KERN_ERR
3229 "ath9k: No PCI devices found, driver not installed.\n");
3230 error = -ENODEV;
3231 goto err_remove_root;
3232 }
3233
3234 error = ath_ahb_init();
3235 if (error < 0) {
3236 error = -ENODEV;
3237 goto err_pci_exit;
3238 }
3239
3240 return 0;
3241
3242 err_pci_exit:
3243 ath_pci_exit();
3244
3245 err_remove_root:
3246 ath9k_debug_remove_root();
3247 err_rate_unregister:
3248 ath_rate_control_unregister();
3249 err_out:
3250 return error;
3251 }
3252 module_init(ath9k_init);
3253
3254 static void __exit ath9k_exit(void)
3255 {
3256 ath_ahb_exit();
3257 ath_pci_exit();
3258 ath9k_debug_remove_root();
3259 ath_rate_control_unregister();
3260 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3261 }
3262 module_exit(ath9k_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree