arch/arm/include/asm/pmu.h

   1 /*
   2  *  linux/arch/arm/include/asm/pmu.h
   3  *
   4  *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #ifndef __ARM_PMU_H__
  13 #define __ARM_PMU_H__
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/perf_event.h>
  17
  18 /*
  19  * Types of PMUs that can be accessed directly and require mutual
  20  * exclusion between profiling tools.
  21  */
  22 enum arm_pmu_type {
  23         ARM_PMU_DEVICE_CPU      = 0,
  24         ARM_NUM_PMU_DEVICES,
  25 };
  26
  27 /*
  28  * struct arm_pmu_platdata - ARM PMU platform data
  29  *
  30  * @handle_irq: an optional handler which will be called from the interrupt and
  31  * passed the address of the low level handler, and can be used to implement
  32  * any platform specific handling before or after calling it.
  33  */
  34 struct arm_pmu_platdata {
  35         irqreturn_t (*handle_irq)(int irq, void *dev,
  36                                   irq_handler_t pmu_handler);
  37 };
  38
  39 #ifdef CONFIG_CPU_HAS_PMU
  40
  41 /**
  42  * reserve_pmu() - reserve the hardware performance counters
  43  *
  44  * Reserve the hardware performance counters in the system for exclusive use.
  45  * Returns 0 on success or -EBUSY if the lock is already held.
  46  */
  47 extern int
  48 reserve_pmu(enum arm_pmu_type type);
  49
  50 /**
  51  * release_pmu() - Relinquish control of the performance counters
  52  *
  53  * Release the performance counters and allow someone else to use them.
  54  */
  55 extern void
  56 release_pmu(enum arm_pmu_type type);
  57
  58 /**
  59  * init_pmu() - Initialise the PMU.
  60  *
  61  * Initialise the system ready for PMU enabling. This should typically set the
  62  * IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
  63  * the actual hardware initialisation.
  64  */
  65 extern int
  66 init_pmu(enum arm_pmu_type type);
  67
  68 #else /* CONFIG_CPU_HAS_PMU */
  69
  70 #include <linux/err.h>
  71
  72 static inline int
  73 reserve_pmu(enum arm_pmu_type type)
  74 {
  75         return -ENODEV;
  76 }
  77
  78 static inline void
  79 release_pmu(enum arm_pmu_type type)     { }
  80
  81 #endif /* CONFIG_CPU_HAS_PMU */
  82
  83 #ifdef CONFIG_HW_PERF_EVENTS
  84
  85 /* The events for a given PMU register set. */
  86 struct pmu_hw_events {
  87         /*
  88          * The events that are active on the PMU for the given index.
  89          */
  90         struct perf_event       **events;
  91
  92         /*
  93          * A 1 bit for an index indicates that the counter is being used for
  94          * an event. A 0 means that the counter can be used.
  95          */
  96         unsigned long           *used_mask;
  97
  98         /*
  99          * Hardware lock to serialize accesses to PMU registers. Needed for the
 100          * read/modify/write sequences.
 101          */
 102         raw_spinlock_t          pmu_lock;
 103 };
 104
 105 struct arm_pmu {
 106         struct pmu      pmu;
 107         enum arm_perf_pmu_ids id;
 108         enum arm_pmu_type type;
 109         cpumask_t       active_irqs;
 110         const char      *name;
 111         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
 112         void            (*enable)(struct hw_perf_event *evt, int idx);
 113         void            (*disable)(struct hw_perf_event *evt, int idx);
 114         int             (*get_event_idx)(struct pmu_hw_events *hw_events,
 115                                          struct hw_perf_event *hwc);
 116         int             (*set_event_filter)(struct hw_perf_event *evt,
 117                                             struct perf_event_attr *attr);
 118         u32             (*read_counter)(int idx);
 119         void            (*write_counter)(int idx, u32 val);
 120         void            (*start)(void);
 121         void            (*stop)(void);
 122         void            (*reset)(void *);
 123         int             (*map_event)(struct perf_event *event);
 124         int             num_events;
 125         atomic_t        active_events;
 126         struct mutex    reserve_mutex;
 127         u64             max_period;
 128         struct platform_device  *plat_device;
 129         struct pmu_hw_events    *(*get_hw_events)(void);
 130 };
 131
 132 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 133
 134 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
 135
 136 u64 armpmu_event_update(struct perf_event *event,
 137                         struct hw_perf_event *hwc,
 138                         int idx, int overflow);
 139
 140 int armpmu_event_set_period(struct perf_event *event,
 141                             struct hw_perf_event *hwc,
 142                             int idx);
 143
 144 #endif /* CONFIG_HW_PERF_EVENTS */
 145
 146 #endif /* __ARM_PMU_H__ */