arch/blackfin/mach-bf548/include/mach/bf548.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf548/bf548.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:  System MMR register and memory map for ADSP-BF548
   8  *
   9  * Modified:
  10  *               Copyright 2004-2007 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #ifndef __MACH_BF548_H__
  31 #define __MACH_BF548_H__
  32
  33 #define OFFSET_(x) ((x) & 0x0000FFFF)
  34
  35 /*some misc defines*/
  36 #define IMASK_IVG15             0x8000
  37 #define IMASK_IVG14             0x4000
  38 #define IMASK_IVG13             0x2000
  39 #define IMASK_IVG12             0x1000
  40
  41 #define IMASK_IVG11             0x0800
  42 #define IMASK_IVG10             0x0400
  43 #define IMASK_IVG9              0x0200
  44 #define IMASK_IVG8              0x0100
  45
  46 #define IMASK_IVG7              0x0080
  47 #define IMASK_IVGTMR    0x0040
  48 #define IMASK_IVGHW             0x0020
  49
  50 /***************************/
  51
  52
  53 #define BFIN_DSUBBANKS  4
  54 #define BFIN_DWAYS              2
  55 #define BFIN_DLINES             64
  56 #define BFIN_ISUBBANKS  4
  57 #define BFIN_IWAYS              4
  58 #define BFIN_ILINES             32
  59
  60 #define WAY0_L                  0x1
  61 #define WAY1_L                  0x2
  62 #define WAY01_L                 0x3
  63 #define WAY2_L                  0x4
  64 #define WAY02_L                 0x5
  65 #define WAY12_L                 0x6
  66 #define WAY012_L                0x7
  67
  68 #define WAY3_L                  0x8
  69 #define WAY03_L                 0x9
  70 #define WAY13_L                 0xA
  71 #define WAY013_L                0xB
  72
  73 #define WAY32_L                 0xC
  74 #define WAY320_L                0xD
  75 #define WAY321_L                0xE
  76 #define WAYALL_L                0xF
  77
  78 #define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
  79
  80 /********************************* EBIU Settings ************************************/
  81 #define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
  82 #define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
  83
  84 #ifdef CONFIG_C_AMBEN_ALL
  85 #define V_AMBEN AMBEN_ALL
  86 #endif
  87 #ifdef CONFIG_C_AMBEN
  88 #define V_AMBEN 0x0
  89 #endif
  90 #ifdef CONFIG_C_AMBEN_B0
  91 #define V_AMBEN AMBEN_B0
  92 #endif
  93 #ifdef CONFIG_C_AMBEN_B0_B1
  94 #define V_AMBEN AMBEN_B0_B1
  95 #endif
  96 #ifdef CONFIG_C_AMBEN_B0_B1_B2
  97 #define V_AMBEN AMBEN_B0_B1_B2
  98 #endif
  99 #ifdef CONFIG_C_AMCKEN
 100 #define V_AMCKEN AMCKEN
 101 #else
 102 #define V_AMCKEN 0x0
 103 #endif
 104
 105 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
 106
 107 #if defined(CONFIG_BF542)
 108 # define CPU   "BF542"
 109 # define CPUID 0x027c8000
 110 #elif defined(CONFIG_BF544)
 111 # define CPU "BF544"
 112 # define CPUID 0x027c8000
 113 #elif defined(CONFIG_BF547)
 114 # define CPU "BF547"
 115 #elif defined(CONFIG_BF548)
 116 # define CPU "BF548"
 117 # define CPUID 0x027c6000
 118 #elif defined(CONFIG_BF549)
 119 # define CPU "BF549"
 120 #else
 121 # define CPU "UNKNOWN"
 122 # define CPUID 0x0
 123 #endif
 124
 125 #endif  /* __MACH_BF48_H__  */