1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
3 Written 1998-2001 by Donald Becker.
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
32 #define DRV_NAME "via-rhine"
33 #define DRV_VERSION "1.4.3"
34 #define DRV_RELDATE "2007-03-06"
37 /* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
40 static int debug
= 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41 static int max_interrupt_work
= 20;
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
45 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
46 || defined(CONFIG_SPARC) || defined(__ia64__) \
47 || defined(__sh__) || defined(__mips__)
48 static int rx_copybreak
= 1518;
50 static int rx_copybreak
;
53 /* Work-around for broken BIOSes: they are unable to get the chip back out of
54 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
58 * In case you are looking for 'options[]' or 'full_duplex[]', they
59 * are gone. Use ethtool(8) instead.
62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63 The Rhine has a 64 element 8390-like hash table. */
64 static const int multicast_filter_limit
= 32;
67 /* Operational parameters that are set at compile time. */
69 /* Keep the ring sizes a power of two for compile efficiency.
70 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
71 Making the Tx ring too large decreases the effectiveness of channel
72 bonding and packet priority.
73 There are no ill effects from too-large receive rings. */
74 #define TX_RING_SIZE 16
75 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
76 #define RX_RING_SIZE 64
78 /* Operational parameters that usually are not changed. */
80 /* Time in jiffies before concluding the transmitter is hung. */
81 #define TX_TIMEOUT (2*HZ)
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
85 #include <linux/module.h>
86 #include <linux/moduleparam.h>
87 #include <linux/kernel.h>
88 #include <linux/string.h>
89 #include <linux/timer.h>
90 #include <linux/errno.h>
91 #include <linux/ioport.h>
92 #include <linux/slab.h>
93 #include <linux/interrupt.h>
94 #include <linux/pci.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/netdevice.h>
97 #include <linux/etherdevice.h>
98 #include <linux/skbuff.h>
99 #include <linux/init.h>
100 #include <linux/delay.h>
101 #include <linux/mii.h>
102 #include <linux/ethtool.h>
103 #include <linux/crc32.h>
104 #include <linux/bitops.h>
105 #include <asm/processor.h> /* Processor type for cache alignment. */
108 #include <asm/uaccess.h>
109 #include <linux/dmi.h>
111 /* These identify the driver base version and may not be removed. */
112 static char version
[] __devinitdata
=
113 KERN_INFO DRV_NAME
".c:v1.10-LK" DRV_VERSION
" " DRV_RELDATE
" Written by Donald Becker\n";
115 /* This driver was written to use PCI memory space. Some early versions
116 of the Rhine may only work correctly with I/O space accesses. */
117 #ifdef CONFIG_VIA_RHINE_MMIO
122 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
123 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
124 MODULE_LICENSE("GPL");
126 module_param(max_interrupt_work
, int, 0);
127 module_param(debug
, int, 0);
128 module_param(rx_copybreak
, int, 0);
129 module_param(avoid_D3
, bool, 0);
130 MODULE_PARM_DESC(max_interrupt_work
, "VIA Rhine maximum events handled per interrupt");
131 MODULE_PARM_DESC(debug
, "VIA Rhine debug level (0-7)");
132 MODULE_PARM_DESC(rx_copybreak
, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
133 MODULE_PARM_DESC(avoid_D3
, "Avoid power state D3 (work-around for broken BIOSes)");
138 I. Board Compatibility
140 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
143 II. Board-specific settings
145 Boards with this chip are functional only in a bus-master PCI slot.
147 Many operational settings are loaded from the EEPROM to the Config word at
148 offset 0x78. For most of these settings, this driver assumes that they are
150 If this driver is compiled to use PCI memory space operations the EEPROM
151 must be configured to enable memory ops.
153 III. Driver operation
157 This driver uses two statically allocated fixed-size descriptor lists
158 formed into rings by a branch from the final descriptor to the beginning of
159 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
161 IIIb/c. Transmit/Receive Structure
163 This driver attempts to use a zero-copy receive and transmit scheme.
165 Alas, all data buffers are required to start on a 32 bit boundary, so
166 the driver must often copy transmit packets into bounce buffers.
168 The driver allocates full frame size skbuffs for the Rx ring buffers at
169 open() time and passes the skb->data field to the chip as receive data
170 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
171 a fresh skbuff is allocated and the frame is copied to the new skbuff.
172 When the incoming frame is larger, the skbuff is passed directly up the
173 protocol stack. Buffers consumed this way are replaced by newly allocated
174 skbuffs in the last phase of rhine_rx().
176 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
177 using a full-sized skbuff for small frames vs. the copying costs of larger
178 frames. New boards are typically used in generously configured machines
179 and the underfilled buffers have negligible impact compared to the benefit of
180 a single allocation size, so the default value of zero results in never
181 copying packets. When copying is done, the cost is usually mitigated by using
182 a combined copy/checksum routine. Copying also preloads the cache, which is
183 most useful with small frames.
185 Since the VIA chips are only able to transfer data to buffers on 32 bit
186 boundaries, the IP header at offset 14 in an ethernet frame isn't
187 longword aligned for further processing. Copying these unaligned buffers
188 has the beneficial effect of 16-byte aligning the IP header.
190 IIId. Synchronization
192 The driver runs as two independent, single-threaded flows of control. One
193 is the send-packet routine, which enforces single-threaded use by the
194 dev->priv->lock spinlock. The other thread is the interrupt handler, which
195 is single threaded by the hardware and interrupt handling software.
197 The send packet thread has partial control over the Tx ring. It locks the
198 dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
199 is not available it stops the transmit queue by calling netif_stop_queue.
201 The interrupt handler has exclusive control over the Rx ring and records stats
202 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
203 empty by incrementing the dirty_tx mark. If at least half of the entries in
204 the Rx ring are available the transmit queue is woken up if it was stopped.
210 Preliminary VT86C100A manual from http://www.via.com.tw/
211 http://www.scyld.com/expert/100mbps.html
212 http://www.scyld.com/expert/NWay.html
213 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
214 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
219 The VT86C100A manual is not reliable information.
220 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
221 in significant performance degradation for bounce buffer copies on transmit
222 and unaligned IP headers on receive.
223 The chip does not pad to minimum transmit length.
228 /* This table drives the PCI probe routines. It's mostly boilerplate in all
229 of the drivers, and will likely be provided by some future kernel.
230 Note the matching code -- the first table entry matchs all 56** cards but
231 second only the 1234 card.
238 VT8231
= 0x50, /* Integrated MAC */
239 VT8233
= 0x60, /* Integrated MAC */
240 VT8235
= 0x74, /* Integrated MAC */
241 VT8237
= 0x78, /* Integrated MAC */
248 VT6105M
= 0x90, /* Management adapter */
252 rqWOL
= 0x0001, /* Wake-On-LAN support */
253 rqForceReset
= 0x0002,
254 rq6patterns
= 0x0040, /* 6 instead of 4 patterns for WOL */
255 rqStatusWBRace
= 0x0080, /* Tx Status Writeback Error possible */
256 rqRhineI
= 0x0100, /* See comment below */
259 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
260 * MMIO as well as for the collision counter and the Tx FIFO underflow
261 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
264 /* Beware of PCI posted writes */
265 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
267 static const struct pci_device_id rhine_pci_tbl
[] = {
268 { 0x1106, 0x3043, PCI_ANY_ID
, PCI_ANY_ID
, }, /* VT86C100A */
269 { 0x1106, 0x3065, PCI_ANY_ID
, PCI_ANY_ID
, }, /* VT6102 */
270 { 0x1106, 0x3106, PCI_ANY_ID
, PCI_ANY_ID
, }, /* 6105{,L,LOM} */
271 { 0x1106, 0x3053, PCI_ANY_ID
, PCI_ANY_ID
, }, /* VT6105M */
272 { } /* terminate list */
274 MODULE_DEVICE_TABLE(pci
, rhine_pci_tbl
);
277 /* Offsets to the device registers. */
278 enum register_offsets
{
279 StationAddr
=0x00, RxConfig
=0x06, TxConfig
=0x07, ChipCmd
=0x08,
281 IntrStatus
=0x0C, IntrEnable
=0x0E,
282 MulticastFilter0
=0x10, MulticastFilter1
=0x14,
283 RxRingPtr
=0x18, TxRingPtr
=0x1C, GFIFOTest
=0x54,
284 MIIPhyAddr
=0x6C, MIIStatus
=0x6D, PCIBusConfig
=0x6E,
285 MIICmd
=0x70, MIIRegAddr
=0x71, MIIData
=0x72, MACRegEEcsr
=0x74,
286 ConfigA
=0x78, ConfigB
=0x79, ConfigC
=0x7A, ConfigD
=0x7B,
287 RxMissed
=0x7C, RxCRCErrs
=0x7E, MiscCmd
=0x81,
288 StickyHW
=0x83, IntrStatus2
=0x84,
289 WOLcrSet
=0xA0, PwcfgSet
=0xA1, WOLcgSet
=0xA3, WOLcrClr
=0xA4,
290 WOLcrClr1
=0xA6, WOLcgClr
=0xA7,
291 PwrcsrSet
=0xA8, PwrcsrSet1
=0xA9, PwrcsrClr
=0xAC, PwrcsrClr1
=0xAD,
294 /* Bits in ConfigD */
296 BackOptional
=0x01, BackModify
=0x02,
297 BackCaptureEffect
=0x04, BackRandom
=0x08
301 /* Registers we check that mmio and reg are the same. */
302 static const int mmio_verify_registers
[] = {
303 RxConfig
, TxConfig
, IntrEnable
, ConfigA
, ConfigB
, ConfigC
, ConfigD
,
308 /* Bits in the interrupt status/mask registers. */
309 enum intr_status_bits
{
310 IntrRxDone
=0x0001, IntrRxErr
=0x0004, IntrRxEmpty
=0x0020,
311 IntrTxDone
=0x0002, IntrTxError
=0x0008, IntrTxUnderrun
=0x0210,
313 IntrStatsMax
=0x0080, IntrRxEarly
=0x0100,
314 IntrRxOverflow
=0x0400, IntrRxDropped
=0x0800, IntrRxNoBuf
=0x1000,
315 IntrTxAborted
=0x2000, IntrLinkChange
=0x4000,
317 IntrNormalSummary
=0x0003, IntrAbnormalSummary
=0xC260,
318 IntrTxDescRace
=0x080000, /* mapped from IntrStatus2 */
319 IntrTxErrSummary
=0x082218,
322 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
331 /* The Rx and Tx buffer descriptors. */
334 __le32 desc_length
; /* Chain flag, Buffer/frame length */
340 __le32 desc_length
; /* Chain flag, Tx Config, Frame length */
345 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
346 #define TXDESC 0x00e08000
348 enum rx_status_bits
{
349 RxOK
=0x8000, RxWholePkt
=0x0300, RxErr
=0x008F
352 /* Bits in *_desc.*_status */
353 enum desc_status_bits
{
357 /* Bits in ChipCmd. */
359 CmdInit
=0x01, CmdStart
=0x02, CmdStop
=0x04, CmdRxOn
=0x08,
360 CmdTxOn
=0x10, Cmd1TxDemand
=0x20, CmdRxDemand
=0x40,
361 Cmd1EarlyRx
=0x01, Cmd1EarlyTx
=0x02, Cmd1FDuplex
=0x04,
362 Cmd1NoTxPoll
=0x08, Cmd1Reset
=0x80,
365 struct rhine_private
{
366 /* Descriptor rings */
367 struct rx_desc
*rx_ring
;
368 struct tx_desc
*tx_ring
;
369 dma_addr_t rx_ring_dma
;
370 dma_addr_t tx_ring_dma
;
372 /* The addresses of receive-in-place skbuffs. */
373 struct sk_buff
*rx_skbuff
[RX_RING_SIZE
];
374 dma_addr_t rx_skbuff_dma
[RX_RING_SIZE
];
376 /* The saved address of a sent-in-place packet/buffer, for later free(). */
377 struct sk_buff
*tx_skbuff
[TX_RING_SIZE
];
378 dma_addr_t tx_skbuff_dma
[TX_RING_SIZE
];
380 /* Tx bounce buffers (Rhine-I only) */
381 unsigned char *tx_buf
[TX_RING_SIZE
];
382 unsigned char *tx_bufs
;
383 dma_addr_t tx_bufs_dma
;
385 struct pci_dev
*pdev
;
387 struct net_device
*dev
;
388 struct napi_struct napi
;
389 struct net_device_stats stats
;
392 /* Frequently used values: keep some adjacent for cache effect. */
394 struct rx_desc
*rx_head_desc
;
395 unsigned int cur_rx
, dirty_rx
; /* Producer/consumer ring indices */
396 unsigned int cur_tx
, dirty_tx
;
397 unsigned int rx_buf_sz
; /* Based on MTU+slack. */
400 u8 tx_thresh
, rx_thresh
;
402 struct mii_if_info mii_if
;
406 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
);
407 static void mdio_write(struct net_device
*dev
, int phy_id
, int location
, int value
);
408 static int rhine_open(struct net_device
*dev
);
409 static void rhine_tx_timeout(struct net_device
*dev
);
410 static int rhine_start_tx(struct sk_buff
*skb
, struct net_device
*dev
);
411 static irqreturn_t
rhine_interrupt(int irq
, void *dev_instance
);
412 static void rhine_tx(struct net_device
*dev
);
413 static int rhine_rx(struct net_device
*dev
, int limit
);
414 static void rhine_error(struct net_device
*dev
, int intr_status
);
415 static void rhine_set_rx_mode(struct net_device
*dev
);
416 static struct net_device_stats
*rhine_get_stats(struct net_device
*dev
);
417 static int netdev_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
418 static const struct ethtool_ops netdev_ethtool_ops
;
419 static int rhine_close(struct net_device
*dev
);
420 static void rhine_shutdown (struct pci_dev
*pdev
);
422 #define RHINE_WAIT_FOR(condition) do { \
424 while (!(condition) && --i) \
426 if (debug > 1 && i < 512) \
427 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
428 DRV_NAME, 1024-i, __func__, __LINE__); \
431 static inline u32
get_intr_status(struct net_device
*dev
)
433 struct rhine_private
*rp
= netdev_priv(dev
);
434 void __iomem
*ioaddr
= rp
->base
;
437 intr_status
= ioread16(ioaddr
+ IntrStatus
);
438 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
439 if (rp
->quirks
& rqStatusWBRace
)
440 intr_status
|= ioread8(ioaddr
+ IntrStatus2
) << 16;
445 * Get power related registers into sane state.
446 * Notify user about past WOL event.
448 static void rhine_power_init(struct net_device
*dev
)
450 struct rhine_private
*rp
= netdev_priv(dev
);
451 void __iomem
*ioaddr
= rp
->base
;
454 if (rp
->quirks
& rqWOL
) {
455 /* Make sure chip is in power state D0 */
456 iowrite8(ioread8(ioaddr
+ StickyHW
) & 0xFC, ioaddr
+ StickyHW
);
458 /* Disable "force PME-enable" */
459 iowrite8(0x80, ioaddr
+ WOLcgClr
);
461 /* Clear power-event config bits (WOL) */
462 iowrite8(0xFF, ioaddr
+ WOLcrClr
);
463 /* More recent cards can manage two additional patterns */
464 if (rp
->quirks
& rq6patterns
)
465 iowrite8(0x03, ioaddr
+ WOLcrClr1
);
467 /* Save power-event status bits */
468 wolstat
= ioread8(ioaddr
+ PwrcsrSet
);
469 if (rp
->quirks
& rq6patterns
)
470 wolstat
|= (ioread8(ioaddr
+ PwrcsrSet1
) & 0x03) << 8;
472 /* Clear power-event status bits */
473 iowrite8(0xFF, ioaddr
+ PwrcsrClr
);
474 if (rp
->quirks
& rq6patterns
)
475 iowrite8(0x03, ioaddr
+ PwrcsrClr1
);
481 reason
= "Magic packet";
484 reason
= "Link went up";
487 reason
= "Link went down";
490 reason
= "Unicast packet";
493 reason
= "Multicast/broadcast packet";
498 printk(KERN_INFO
"%s: Woke system up. Reason: %s.\n",
504 static void rhine_chip_reset(struct net_device
*dev
)
506 struct rhine_private
*rp
= netdev_priv(dev
);
507 void __iomem
*ioaddr
= rp
->base
;
509 iowrite8(Cmd1Reset
, ioaddr
+ ChipCmd1
);
512 if (ioread8(ioaddr
+ ChipCmd1
) & Cmd1Reset
) {
513 printk(KERN_INFO
"%s: Reset not complete yet. "
514 "Trying harder.\n", DRV_NAME
);
517 if (rp
->quirks
& rqForceReset
)
518 iowrite8(0x40, ioaddr
+ MiscCmd
);
520 /* Reset can take somewhat longer (rare) */
521 RHINE_WAIT_FOR(!(ioread8(ioaddr
+ ChipCmd1
) & Cmd1Reset
));
525 printk(KERN_INFO
"%s: Reset %s.\n", dev
->name
,
526 (ioread8(ioaddr
+ ChipCmd1
) & Cmd1Reset
) ?
527 "failed" : "succeeded");
531 static void enable_mmio(long pioaddr
, u32 quirks
)
534 if (quirks
& rqRhineI
) {
535 /* More recent docs say that this bit is reserved ... */
536 n
= inb(pioaddr
+ ConfigA
) | 0x20;
537 outb(n
, pioaddr
+ ConfigA
);
539 n
= inb(pioaddr
+ ConfigD
) | 0x80;
540 outb(n
, pioaddr
+ ConfigD
);
546 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
547 * (plus 0x6C for Rhine-I/II)
549 static void __devinit
rhine_reload_eeprom(long pioaddr
, struct net_device
*dev
)
551 struct rhine_private
*rp
= netdev_priv(dev
);
552 void __iomem
*ioaddr
= rp
->base
;
554 outb(0x20, pioaddr
+ MACRegEEcsr
);
555 RHINE_WAIT_FOR(!(inb(pioaddr
+ MACRegEEcsr
) & 0x20));
559 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
560 * MMIO. If reloading EEPROM was done first this could be avoided, but
561 * it is not known if that still works with the "win98-reboot" problem.
563 enable_mmio(pioaddr
, rp
->quirks
);
566 /* Turn off EEPROM-controlled wake-up (magic packet) */
567 if (rp
->quirks
& rqWOL
)
568 iowrite8(ioread8(ioaddr
+ ConfigA
) & 0xFC, ioaddr
+ ConfigA
);
572 #ifdef CONFIG_NET_POLL_CONTROLLER
573 static void rhine_poll(struct net_device
*dev
)
575 disable_irq(dev
->irq
);
576 rhine_interrupt(dev
->irq
, (void *)dev
);
577 enable_irq(dev
->irq
);
581 static int rhine_napipoll(struct napi_struct
*napi
, int budget
)
583 struct rhine_private
*rp
= container_of(napi
, struct rhine_private
, napi
);
584 struct net_device
*dev
= rp
->dev
;
585 void __iomem
*ioaddr
= rp
->base
;
588 work_done
= rhine_rx(dev
, budget
);
590 if (work_done
< budget
) {
591 netif_rx_complete(dev
, napi
);
593 iowrite16(IntrRxDone
| IntrRxErr
| IntrRxEmpty
| IntrRxOverflow
|
594 IntrRxDropped
| IntrRxNoBuf
| IntrTxAborted
|
595 IntrTxDone
| IntrTxError
| IntrTxUnderrun
|
596 IntrPCIErr
| IntrStatsMax
| IntrLinkChange
,
597 ioaddr
+ IntrEnable
);
602 static void __devinit
rhine_hw_init(struct net_device
*dev
, long pioaddr
)
604 struct rhine_private
*rp
= netdev_priv(dev
);
606 /* Reset the chip to erase previous misconfiguration. */
607 rhine_chip_reset(dev
);
609 /* Rhine-I needs extra time to recuperate before EEPROM reload */
610 if (rp
->quirks
& rqRhineI
)
613 /* Reload EEPROM controlled bytes cleared by soft reset */
614 rhine_reload_eeprom(pioaddr
, dev
);
617 static int __devinit
rhine_init_one(struct pci_dev
*pdev
,
618 const struct pci_device_id
*ent
)
620 struct net_device
*dev
;
621 struct rhine_private
*rp
;
626 void __iomem
*ioaddr
;
635 /* when built into the kernel, we only print version if device is found */
637 static int printed_version
;
638 if (!printed_version
++)
646 if (pdev
->revision
< VTunknown0
) {
650 else if (pdev
->revision
>= VT6102
) {
651 quirks
= rqWOL
| rqForceReset
;
652 if (pdev
->revision
< VT6105
) {
654 quirks
|= rqStatusWBRace
; /* Rhine-II exclusive */
657 phy_id
= 1; /* Integrated PHY, phy_id fixed to 1 */
658 if (pdev
->revision
>= VT6105_B0
)
659 quirks
|= rq6patterns
;
660 if (pdev
->revision
< VT6105M
)
663 name
= "Rhine III (Management Adapter)";
667 rc
= pci_enable_device(pdev
);
671 /* this should always be supported */
672 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
674 printk(KERN_ERR
"32-bit PCI DMA addresses not supported by "
680 if ((pci_resource_len(pdev
, 0) < io_size
) ||
681 (pci_resource_len(pdev
, 1) < io_size
)) {
683 printk(KERN_ERR
"Insufficient PCI resources, aborting\n");
687 pioaddr
= pci_resource_start(pdev
, 0);
688 memaddr
= pci_resource_start(pdev
, 1);
690 pci_set_master(pdev
);
692 dev
= alloc_etherdev(sizeof(struct rhine_private
));
695 printk(KERN_ERR
"alloc_etherdev failed\n");
698 SET_NETDEV_DEV(dev
, &pdev
->dev
);
700 rp
= netdev_priv(dev
);
703 rp
->pioaddr
= pioaddr
;
706 rc
= pci_request_regions(pdev
, DRV_NAME
);
708 goto err_out_free_netdev
;
710 ioaddr
= pci_iomap(pdev
, bar
, io_size
);
713 printk(KERN_ERR
"ioremap failed for device %s, region 0x%X "
714 "@ 0x%lX\n", pci_name(pdev
), io_size
, memaddr
);
715 goto err_out_free_res
;
719 enable_mmio(pioaddr
, quirks
);
721 /* Check that selected MMIO registers match the PIO ones */
723 while (mmio_verify_registers
[i
]) {
724 int reg
= mmio_verify_registers
[i
++];
725 unsigned char a
= inb(pioaddr
+reg
);
726 unsigned char b
= readb(ioaddr
+reg
);
729 printk(KERN_ERR
"MMIO do not match PIO [%02x] "
730 "(%02x != %02x)\n", reg
, a
, b
);
734 #endif /* USE_MMIO */
736 dev
->base_addr
= (unsigned long)ioaddr
;
739 /* Get chip registers into a sane state */
740 rhine_power_init(dev
);
741 rhine_hw_init(dev
, pioaddr
);
743 for (i
= 0; i
< 6; i
++)
744 dev
->dev_addr
[i
] = ioread8(ioaddr
+ StationAddr
+ i
);
745 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
747 if (!is_valid_ether_addr(dev
->perm_addr
)) {
749 printk(KERN_ERR
"Invalid MAC address\n");
753 /* For Rhine-I/II, phy_id is loaded from EEPROM */
755 phy_id
= ioread8(ioaddr
+ 0x6C);
757 dev
->irq
= pdev
->irq
;
759 spin_lock_init(&rp
->lock
);
760 rp
->mii_if
.dev
= dev
;
761 rp
->mii_if
.mdio_read
= mdio_read
;
762 rp
->mii_if
.mdio_write
= mdio_write
;
763 rp
->mii_if
.phy_id_mask
= 0x1f;
764 rp
->mii_if
.reg_num_mask
= 0x1f;
766 /* The chip-specific entries in the device structure. */
767 dev
->open
= rhine_open
;
768 dev
->hard_start_xmit
= rhine_start_tx
;
769 dev
->stop
= rhine_close
;
770 dev
->get_stats
= rhine_get_stats
;
771 dev
->set_multicast_list
= rhine_set_rx_mode
;
772 dev
->do_ioctl
= netdev_ioctl
;
773 dev
->ethtool_ops
= &netdev_ethtool_ops
;
774 dev
->tx_timeout
= rhine_tx_timeout
;
775 dev
->watchdog_timeo
= TX_TIMEOUT
;
776 #ifdef CONFIG_NET_POLL_CONTROLLER
777 dev
->poll_controller
= rhine_poll
;
779 netif_napi_add(dev
, &rp
->napi
, rhine_napipoll
, 64);
781 if (rp
->quirks
& rqRhineI
)
782 dev
->features
|= NETIF_F_SG
|NETIF_F_HW_CSUM
;
784 /* dev->name not defined before register_netdev()! */
785 rc
= register_netdev(dev
);
789 printk(KERN_INFO
"%s: VIA %s at 0x%lx, %pM, IRQ %d.\n",
796 dev
->dev_addr
, pdev
->irq
);
798 pci_set_drvdata(pdev
, dev
);
802 int mii_status
= mdio_read(dev
, phy_id
, 1);
803 mii_cmd
= mdio_read(dev
, phy_id
, MII_BMCR
) & ~BMCR_ISOLATE
;
804 mdio_write(dev
, phy_id
, MII_BMCR
, mii_cmd
);
805 if (mii_status
!= 0xffff && mii_status
!= 0x0000) {
806 rp
->mii_if
.advertising
= mdio_read(dev
, phy_id
, 4);
807 printk(KERN_INFO
"%s: MII PHY found at address "
808 "%d, status 0x%4.4x advertising %4.4x "
809 "Link %4.4x.\n", dev
->name
, phy_id
,
810 mii_status
, rp
->mii_if
.advertising
,
811 mdio_read(dev
, phy_id
, 5));
813 /* set IFF_RUNNING */
814 if (mii_status
& BMSR_LSTATUS
)
815 netif_carrier_on(dev
);
817 netif_carrier_off(dev
);
821 rp
->mii_if
.phy_id
= phy_id
;
822 if (debug
> 1 && avoid_D3
)
823 printk(KERN_INFO
"%s: No D3 power state at shutdown.\n",
829 pci_iounmap(pdev
, ioaddr
);
831 pci_release_regions(pdev
);
838 static int alloc_ring(struct net_device
* dev
)
840 struct rhine_private
*rp
= netdev_priv(dev
);
844 ring
= pci_alloc_consistent(rp
->pdev
,
845 RX_RING_SIZE
* sizeof(struct rx_desc
) +
846 TX_RING_SIZE
* sizeof(struct tx_desc
),
849 printk(KERN_ERR
"Could not allocate DMA memory.\n");
852 if (rp
->quirks
& rqRhineI
) {
853 rp
->tx_bufs
= pci_alloc_consistent(rp
->pdev
,
854 PKT_BUF_SZ
* TX_RING_SIZE
,
856 if (rp
->tx_bufs
== NULL
) {
857 pci_free_consistent(rp
->pdev
,
858 RX_RING_SIZE
* sizeof(struct rx_desc
) +
859 TX_RING_SIZE
* sizeof(struct tx_desc
),
866 rp
->tx_ring
= ring
+ RX_RING_SIZE
* sizeof(struct rx_desc
);
867 rp
->rx_ring_dma
= ring_dma
;
868 rp
->tx_ring_dma
= ring_dma
+ RX_RING_SIZE
* sizeof(struct rx_desc
);
873 static void free_ring(struct net_device
* dev
)
875 struct rhine_private
*rp
= netdev_priv(dev
);
877 pci_free_consistent(rp
->pdev
,
878 RX_RING_SIZE
* sizeof(struct rx_desc
) +
879 TX_RING_SIZE
* sizeof(struct tx_desc
),
880 rp
->rx_ring
, rp
->rx_ring_dma
);
884 pci_free_consistent(rp
->pdev
, PKT_BUF_SZ
* TX_RING_SIZE
,
885 rp
->tx_bufs
, rp
->tx_bufs_dma
);
891 static void alloc_rbufs(struct net_device
*dev
)
893 struct rhine_private
*rp
= netdev_priv(dev
);
897 rp
->dirty_rx
= rp
->cur_rx
= 0;
899 rp
->rx_buf_sz
= (dev
->mtu
<= 1500 ? PKT_BUF_SZ
: dev
->mtu
+ 32);
900 rp
->rx_head_desc
= &rp
->rx_ring
[0];
901 next
= rp
->rx_ring_dma
;
903 /* Init the ring entries */
904 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
905 rp
->rx_ring
[i
].rx_status
= 0;
906 rp
->rx_ring
[i
].desc_length
= cpu_to_le32(rp
->rx_buf_sz
);
907 next
+= sizeof(struct rx_desc
);
908 rp
->rx_ring
[i
].next_desc
= cpu_to_le32(next
);
909 rp
->rx_skbuff
[i
] = NULL
;
911 /* Mark the last entry as wrapping the ring. */
912 rp
->rx_ring
[i
-1].next_desc
= cpu_to_le32(rp
->rx_ring_dma
);
914 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
915 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
916 struct sk_buff
*skb
= netdev_alloc_skb(dev
, rp
->rx_buf_sz
);
917 rp
->rx_skbuff
[i
] = skb
;
920 skb
->dev
= dev
; /* Mark as being used by this device. */
922 rp
->rx_skbuff_dma
[i
] =
923 pci_map_single(rp
->pdev
, skb
->data
, rp
->rx_buf_sz
,
926 rp
->rx_ring
[i
].addr
= cpu_to_le32(rp
->rx_skbuff_dma
[i
]);
927 rp
->rx_ring
[i
].rx_status
= cpu_to_le32(DescOwn
);
929 rp
->dirty_rx
= (unsigned int)(i
- RX_RING_SIZE
);
932 static void free_rbufs(struct net_device
* dev
)
934 struct rhine_private
*rp
= netdev_priv(dev
);
937 /* Free all the skbuffs in the Rx queue. */
938 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
939 rp
->rx_ring
[i
].rx_status
= 0;
940 rp
->rx_ring
[i
].addr
= cpu_to_le32(0xBADF00D0); /* An invalid address. */
941 if (rp
->rx_skbuff
[i
]) {
942 pci_unmap_single(rp
->pdev
,
943 rp
->rx_skbuff_dma
[i
],
944 rp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
945 dev_kfree_skb(rp
->rx_skbuff
[i
]);
947 rp
->rx_skbuff
[i
] = NULL
;
951 static void alloc_tbufs(struct net_device
* dev
)
953 struct rhine_private
*rp
= netdev_priv(dev
);
957 rp
->dirty_tx
= rp
->cur_tx
= 0;
958 next
= rp
->tx_ring_dma
;
959 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
960 rp
->tx_skbuff
[i
] = NULL
;
961 rp
->tx_ring
[i
].tx_status
= 0;
962 rp
->tx_ring
[i
].desc_length
= cpu_to_le32(TXDESC
);
963 next
+= sizeof(struct tx_desc
);
964 rp
->tx_ring
[i
].next_desc
= cpu_to_le32(next
);
965 if (rp
->quirks
& rqRhineI
)
966 rp
->tx_buf
[i
] = &rp
->tx_bufs
[i
* PKT_BUF_SZ
];
968 rp
->tx_ring
[i
-1].next_desc
= cpu_to_le32(rp
->tx_ring_dma
);
972 static void free_tbufs(struct net_device
* dev
)
974 struct rhine_private
*rp
= netdev_priv(dev
);
977 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
978 rp
->tx_ring
[i
].tx_status
= 0;
979 rp
->tx_ring
[i
].desc_length
= cpu_to_le32(TXDESC
);
980 rp
->tx_ring
[i
].addr
= cpu_to_le32(0xBADF00D0); /* An invalid address. */
981 if (rp
->tx_skbuff
[i
]) {
982 if (rp
->tx_skbuff_dma
[i
]) {
983 pci_unmap_single(rp
->pdev
,
984 rp
->tx_skbuff_dma
[i
],
985 rp
->tx_skbuff
[i
]->len
,
988 dev_kfree_skb(rp
->tx_skbuff
[i
]);
990 rp
->tx_skbuff
[i
] = NULL
;
991 rp
->tx_buf
[i
] = NULL
;
995 static void rhine_check_media(struct net_device
*dev
, unsigned int init_media
)
997 struct rhine_private
*rp
= netdev_priv(dev
);
998 void __iomem
*ioaddr
= rp
->base
;
1000 mii_check_media(&rp
->mii_if
, debug
, init_media
);
1002 if (rp
->mii_if
.full_duplex
)
1003 iowrite8(ioread8(ioaddr
+ ChipCmd1
) | Cmd1FDuplex
,
1006 iowrite8(ioread8(ioaddr
+ ChipCmd1
) & ~Cmd1FDuplex
,
1009 printk(KERN_INFO
"%s: force_media %d, carrier %d\n", dev
->name
,
1010 rp
->mii_if
.force_media
, netif_carrier_ok(dev
));
1013 /* Called after status of force_media possibly changed */
1014 static void rhine_set_carrier(struct mii_if_info
*mii
)
1016 if (mii
->force_media
) {
1017 /* autoneg is off: Link is always assumed to be up */
1018 if (!netif_carrier_ok(mii
->dev
))
1019 netif_carrier_on(mii
->dev
);
1021 else /* Let MMI library update carrier status */
1022 rhine_check_media(mii
->dev
, 0);
1024 printk(KERN_INFO
"%s: force_media %d, carrier %d\n",
1025 mii
->dev
->name
, mii
->force_media
,
1026 netif_carrier_ok(mii
->dev
));
1029 static void init_registers(struct net_device
*dev
)
1031 struct rhine_private
*rp
= netdev_priv(dev
);
1032 void __iomem
*ioaddr
= rp
->base
;
1035 for (i
= 0; i
< 6; i
++)
1036 iowrite8(dev
->dev_addr
[i
], ioaddr
+ StationAddr
+ i
);
1038 /* Initialize other registers. */
1039 iowrite16(0x0006, ioaddr
+ PCIBusConfig
); /* Tune configuration??? */
1040 /* Configure initial FIFO thresholds. */
1041 iowrite8(0x20, ioaddr
+ TxConfig
);
1042 rp
->tx_thresh
= 0x20;
1043 rp
->rx_thresh
= 0x60; /* Written in rhine_set_rx_mode(). */
1045 iowrite32(rp
->rx_ring_dma
, ioaddr
+ RxRingPtr
);
1046 iowrite32(rp
->tx_ring_dma
, ioaddr
+ TxRingPtr
);
1048 rhine_set_rx_mode(dev
);
1050 napi_enable(&rp
->napi
);
1052 /* Enable interrupts by setting the interrupt mask. */
1053 iowrite16(IntrRxDone
| IntrRxErr
| IntrRxEmpty
| IntrRxOverflow
|
1054 IntrRxDropped
| IntrRxNoBuf
| IntrTxAborted
|
1055 IntrTxDone
| IntrTxError
| IntrTxUnderrun
|
1056 IntrPCIErr
| IntrStatsMax
| IntrLinkChange
,
1057 ioaddr
+ IntrEnable
);
1059 iowrite16(CmdStart
| CmdTxOn
| CmdRxOn
| (Cmd1NoTxPoll
<< 8),
1061 rhine_check_media(dev
, 1);
1064 /* Enable MII link status auto-polling (required for IntrLinkChange) */
1065 static void rhine_enable_linkmon(void __iomem
*ioaddr
)
1067 iowrite8(0, ioaddr
+ MIICmd
);
1068 iowrite8(MII_BMSR
, ioaddr
+ MIIRegAddr
);
1069 iowrite8(0x80, ioaddr
+ MIICmd
);
1071 RHINE_WAIT_FOR((ioread8(ioaddr
+ MIIRegAddr
) & 0x20));
1073 iowrite8(MII_BMSR
| 0x40, ioaddr
+ MIIRegAddr
);
1076 /* Disable MII link status auto-polling (required for MDIO access) */
1077 static void rhine_disable_linkmon(void __iomem
*ioaddr
, u32 quirks
)
1079 iowrite8(0, ioaddr
+ MIICmd
);
1081 if (quirks
& rqRhineI
) {
1082 iowrite8(0x01, ioaddr
+ MIIRegAddr
); // MII_BMSR
1084 /* Can be called from ISR. Evil. */
1087 /* 0x80 must be set immediately before turning it off */
1088 iowrite8(0x80, ioaddr
+ MIICmd
);
1090 RHINE_WAIT_FOR(ioread8(ioaddr
+ MIIRegAddr
) & 0x20);
1092 /* Heh. Now clear 0x80 again. */
1093 iowrite8(0, ioaddr
+ MIICmd
);
1096 RHINE_WAIT_FOR(ioread8(ioaddr
+ MIIRegAddr
) & 0x80);
1099 /* Read and write over the MII Management Data I/O (MDIO) interface. */
1101 static int mdio_read(struct net_device
*dev
, int phy_id
, int regnum
)
1103 struct rhine_private
*rp
= netdev_priv(dev
);
1104 void __iomem
*ioaddr
= rp
->base
;
1107 rhine_disable_linkmon(ioaddr
, rp
->quirks
);
1109 /* rhine_disable_linkmon already cleared MIICmd */
1110 iowrite8(phy_id
, ioaddr
+ MIIPhyAddr
);
1111 iowrite8(regnum
, ioaddr
+ MIIRegAddr
);
1112 iowrite8(0x40, ioaddr
+ MIICmd
); /* Trigger read */
1113 RHINE_WAIT_FOR(!(ioread8(ioaddr
+ MIICmd
) & 0x40));
1114 result
= ioread16(ioaddr
+ MIIData
);
1116 rhine_enable_linkmon(ioaddr
);
1120 static void mdio_write(struct net_device
*dev
, int phy_id
, int regnum
, int value
)
1122 struct rhine_private
*rp
= netdev_priv(dev
);
1123 void __iomem
*ioaddr
= rp
->base
;
1125 rhine_disable_linkmon(ioaddr
, rp
->quirks
);
1127 /* rhine_disable_linkmon already cleared MIICmd */
1128 iowrite8(phy_id
, ioaddr
+ MIIPhyAddr
);
1129 iowrite8(regnum
, ioaddr
+ MIIRegAddr
);
1130 iowrite16(value
, ioaddr
+ MIIData
);
1131 iowrite8(0x20, ioaddr
+ MIICmd
); /* Trigger write */
1132 RHINE_WAIT_FOR(!(ioread8(ioaddr
+ MIICmd
) & 0x20));
1134 rhine_enable_linkmon(ioaddr
);
1137 static int rhine_open(struct net_device
*dev
)
1139 struct rhine_private
*rp
= netdev_priv(dev
);
1140 void __iomem
*ioaddr
= rp
->base
;
1143 rc
= request_irq(rp
->pdev
->irq
, &rhine_interrupt
, IRQF_SHARED
, dev
->name
,
1149 printk(KERN_DEBUG
"%s: rhine_open() irq %d.\n",
1150 dev
->name
, rp
->pdev
->irq
);
1152 rc
= alloc_ring(dev
);
1154 free_irq(rp
->pdev
->irq
, dev
);
1159 rhine_chip_reset(dev
);
1160 init_registers(dev
);
1162 printk(KERN_DEBUG
"%s: Done rhine_open(), status %4.4x "
1163 "MII status: %4.4x.\n",
1164 dev
->name
, ioread16(ioaddr
+ ChipCmd
),
1165 mdio_read(dev
, rp
->mii_if
.phy_id
, MII_BMSR
));
1167 netif_start_queue(dev
);
1172 static void rhine_tx_timeout(struct net_device
*dev
)
1174 struct rhine_private
*rp
= netdev_priv(dev
);
1175 void __iomem
*ioaddr
= rp
->base
;
1177 printk(KERN_WARNING
"%s: Transmit timed out, status %4.4x, PHY status "
1178 "%4.4x, resetting...\n",
1179 dev
->name
, ioread16(ioaddr
+ IntrStatus
),
1180 mdio_read(dev
, rp
->mii_if
.phy_id
, MII_BMSR
));
1182 /* protect against concurrent rx interrupts */
1183 disable_irq(rp
->pdev
->irq
);
1185 napi_disable(&rp
->napi
);
1187 spin_lock(&rp
->lock
);
1189 /* clear all descriptors */
1195 /* Reinitialize the hardware. */
1196 rhine_chip_reset(dev
);
1197 init_registers(dev
);
1199 spin_unlock(&rp
->lock
);
1200 enable_irq(rp
->pdev
->irq
);
1202 dev
->trans_start
= jiffies
;
1203 rp
->stats
.tx_errors
++;
1204 netif_wake_queue(dev
);
1207 static int rhine_start_tx(struct sk_buff
*skb
, struct net_device
*dev
)
1209 struct rhine_private
*rp
= netdev_priv(dev
);
1210 void __iomem
*ioaddr
= rp
->base
;
1213 /* Caution: the write order is important here, set the field
1214 with the "ownership" bits last. */
1216 /* Calculate the next Tx descriptor entry. */
1217 entry
= rp
->cur_tx
% TX_RING_SIZE
;
1219 if (skb_padto(skb
, ETH_ZLEN
))
1222 rp
->tx_skbuff
[entry
] = skb
;
1224 if ((rp
->quirks
& rqRhineI
) &&
1225 (((unsigned long)skb
->data
& 3) || skb_shinfo(skb
)->nr_frags
!= 0 || skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
1226 /* Must use alignment buffer. */
1227 if (skb
->len
> PKT_BUF_SZ
) {
1228 /* packet too long, drop it */
1230 rp
->tx_skbuff
[entry
] = NULL
;
1231 rp
->stats
.tx_dropped
++;
1235 /* Padding is not copied and so must be redone. */
1236 skb_copy_and_csum_dev(skb
, rp
->tx_buf
[entry
]);
1237 if (skb
->len
< ETH_ZLEN
)
1238 memset(rp
->tx_buf
[entry
] + skb
->len
, 0,
1239 ETH_ZLEN
- skb
->len
);
1240 rp
->tx_skbuff_dma
[entry
] = 0;
1241 rp
->tx_ring
[entry
].addr
= cpu_to_le32(rp
->tx_bufs_dma
+
1242 (rp
->tx_buf
[entry
] -
1245 rp
->tx_skbuff_dma
[entry
] =
1246 pci_map_single(rp
->pdev
, skb
->data
, skb
->len
,
1248 rp
->tx_ring
[entry
].addr
= cpu_to_le32(rp
->tx_skbuff_dma
[entry
]);
1251 rp
->tx_ring
[entry
].desc_length
=
1252 cpu_to_le32(TXDESC
| (skb
->len
>= ETH_ZLEN
? skb
->len
: ETH_ZLEN
));
1255 spin_lock_irq(&rp
->lock
);
1257 rp
->tx_ring
[entry
].tx_status
= cpu_to_le32(DescOwn
);
1262 /* Non-x86 Todo: explicitly flush cache lines here. */
1264 /* Wake the potentially-idle transmit channel */
1265 iowrite8(ioread8(ioaddr
+ ChipCmd1
) | Cmd1TxDemand
,
1269 if (rp
->cur_tx
== rp
->dirty_tx
+ TX_QUEUE_LEN
)
1270 netif_stop_queue(dev
);
1272 dev
->trans_start
= jiffies
;
1274 spin_unlock_irq(&rp
->lock
);
1277 printk(KERN_DEBUG
"%s: Transmit frame #%d queued in slot %d.\n",
1278 dev
->name
, rp
->cur_tx
-1, entry
);
1283 /* The interrupt handler does all of the Rx thread work and cleans up
1284 after the Tx thread. */
1285 static irqreturn_t
rhine_interrupt(int irq
, void *dev_instance
)
1287 struct net_device
*dev
= dev_instance
;
1288 struct rhine_private
*rp
= netdev_priv(dev
);
1289 void __iomem
*ioaddr
= rp
->base
;
1291 int boguscnt
= max_interrupt_work
;
1294 while ((intr_status
= get_intr_status(dev
))) {
1297 /* Acknowledge all of the current interrupt sources ASAP. */
1298 if (intr_status
& IntrTxDescRace
)
1299 iowrite8(0x08, ioaddr
+ IntrStatus2
);
1300 iowrite16(intr_status
& 0xffff, ioaddr
+ IntrStatus
);
1304 printk(KERN_DEBUG
"%s: Interrupt, status %8.8x.\n",
1305 dev
->name
, intr_status
);
1307 if (intr_status
& (IntrRxDone
| IntrRxErr
| IntrRxDropped
|
1308 IntrRxWakeUp
| IntrRxEmpty
| IntrRxNoBuf
)) {
1309 iowrite16(IntrTxAborted
|
1310 IntrTxDone
| IntrTxError
| IntrTxUnderrun
|
1311 IntrPCIErr
| IntrStatsMax
| IntrLinkChange
,
1312 ioaddr
+ IntrEnable
);
1314 netif_rx_schedule(dev
, &rp
->napi
);
1317 if (intr_status
& (IntrTxErrSummary
| IntrTxDone
)) {
1318 if (intr_status
& IntrTxErrSummary
) {
1319 /* Avoid scavenging before Tx engine turned off */
1320 RHINE_WAIT_FOR(!(ioread8(ioaddr
+ChipCmd
) & CmdTxOn
));
1322 ioread8(ioaddr
+ChipCmd
) & CmdTxOn
)
1323 printk(KERN_WARNING
"%s: "
1324 "rhine_interrupt() Tx engine "
1325 "still on.\n", dev
->name
);
1330 /* Abnormal error summary/uncommon events handlers. */
1331 if (intr_status
& (IntrPCIErr
| IntrLinkChange
|
1332 IntrStatsMax
| IntrTxError
| IntrTxAborted
|
1333 IntrTxUnderrun
| IntrTxDescRace
))
1334 rhine_error(dev
, intr_status
);
1336 if (--boguscnt
< 0) {
1337 printk(KERN_WARNING
"%s: Too much work at interrupt, "
1339 dev
->name
, intr_status
);
1345 printk(KERN_DEBUG
"%s: exiting interrupt, status=%8.8x.\n",
1346 dev
->name
, ioread16(ioaddr
+ IntrStatus
));
1347 return IRQ_RETVAL(handled
);
1350 /* This routine is logically part of the interrupt handler, but isolated
1352 static void rhine_tx(struct net_device
*dev
)
1354 struct rhine_private
*rp
= netdev_priv(dev
);
1355 int txstatus
= 0, entry
= rp
->dirty_tx
% TX_RING_SIZE
;
1357 spin_lock(&rp
->lock
);
1359 /* find and cleanup dirty tx descriptors */
1360 while (rp
->dirty_tx
!= rp
->cur_tx
) {
1361 txstatus
= le32_to_cpu(rp
->tx_ring
[entry
].tx_status
);
1363 printk(KERN_DEBUG
"Tx scavenge %d status %8.8x.\n",
1365 if (txstatus
& DescOwn
)
1367 if (txstatus
& 0x8000) {
1369 printk(KERN_DEBUG
"%s: Transmit error, "
1370 "Tx status %8.8x.\n",
1371 dev
->name
, txstatus
);
1372 rp
->stats
.tx_errors
++;
1373 if (txstatus
& 0x0400) rp
->stats
.tx_carrier_errors
++;
1374 if (txstatus
& 0x0200) rp
->stats
.tx_window_errors
++;
1375 if (txstatus
& 0x0100) rp
->stats
.tx_aborted_errors
++;
1376 if (txstatus
& 0x0080) rp
->stats
.tx_heartbeat_errors
++;
1377 if (((rp
->quirks
& rqRhineI
) && txstatus
& 0x0002) ||
1378 (txstatus
& 0x0800) || (txstatus
& 0x1000)) {
1379 rp
->stats
.tx_fifo_errors
++;
1380 rp
->tx_ring
[entry
].tx_status
= cpu_to_le32(DescOwn
);
1381 break; /* Keep the skb - we try again */
1383 /* Transmitter restarted in 'abnormal' handler. */
1385 if (rp
->quirks
& rqRhineI
)
1386 rp
->stats
.collisions
+= (txstatus
>> 3) & 0x0F;
1388 rp
->stats
.collisions
+= txstatus
& 0x0F;
1390 printk(KERN_DEBUG
"collisions: %1.1x:%1.1x\n",
1391 (txstatus
>> 3) & 0xF,
1393 rp
->stats
.tx_bytes
+= rp
->tx_skbuff
[entry
]->len
;
1394 rp
->stats
.tx_packets
++;
1396 /* Free the original skb. */
1397 if (rp
->tx_skbuff_dma
[entry
]) {
1398 pci_unmap_single(rp
->pdev
,
1399 rp
->tx_skbuff_dma
[entry
],
1400 rp
->tx_skbuff
[entry
]->len
,
1403 dev_kfree_skb_irq(rp
->tx_skbuff
[entry
]);
1404 rp
->tx_skbuff
[entry
] = NULL
;
1405 entry
= (++rp
->dirty_tx
) % TX_RING_SIZE
;
1407 if ((rp
->cur_tx
- rp
->dirty_tx
) < TX_QUEUE_LEN
- 4)
1408 netif_wake_queue(dev
);
1410 spin_unlock(&rp
->lock
);
1413 /* Process up to limit frames from receive ring */
1414 static int rhine_rx(struct net_device
*dev
, int limit
)
1416 struct rhine_private
*rp
= netdev_priv(dev
);
1418 int entry
= rp
->cur_rx
% RX_RING_SIZE
;
1421 printk(KERN_DEBUG
"%s: rhine_rx(), entry %d status %8.8x.\n",
1423 le32_to_cpu(rp
->rx_head_desc
->rx_status
));
1426 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1427 for (count
= 0; count
< limit
; ++count
) {
1428 struct rx_desc
*desc
= rp
->rx_head_desc
;
1429 u32 desc_status
= le32_to_cpu(desc
->rx_status
);
1430 int data_size
= desc_status
>> 16;
1432 if (desc_status
& DescOwn
)
1436 printk(KERN_DEBUG
"rhine_rx() status is %8.8x.\n",
1439 if ((desc_status
& (RxWholePkt
| RxErr
)) != RxWholePkt
) {
1440 if ((desc_status
& RxWholePkt
) != RxWholePkt
) {
1441 printk(KERN_WARNING
"%s: Oversized Ethernet "
1442 "frame spanned multiple buffers, entry "
1443 "%#x length %d status %8.8x!\n",
1444 dev
->name
, entry
, data_size
,
1446 printk(KERN_WARNING
"%s: Oversized Ethernet "
1447 "frame %p vs %p.\n", dev
->name
,
1448 rp
->rx_head_desc
, &rp
->rx_ring
[entry
]);
1449 rp
->stats
.rx_length_errors
++;
1450 } else if (desc_status
& RxErr
) {
1451 /* There was a error. */
1453 printk(KERN_DEBUG
"rhine_rx() Rx "
1454 "error was %8.8x.\n",
1456 rp
->stats
.rx_errors
++;
1457 if (desc_status
& 0x0030) rp
->stats
.rx_length_errors
++;
1458 if (desc_status
& 0x0048) rp
->stats
.rx_fifo_errors
++;
1459 if (desc_status
& 0x0004) rp
->stats
.rx_frame_errors
++;
1460 if (desc_status
& 0x0002) {
1461 /* this can also be updated outside the interrupt handler */
1462 spin_lock(&rp
->lock
);
1463 rp
->stats
.rx_crc_errors
++;
1464 spin_unlock(&rp
->lock
);
1468 struct sk_buff
*skb
;
1469 /* Length should omit the CRC */
1470 int pkt_len
= data_size
- 4;
1472 /* Check if the packet is long enough to accept without
1473 copying to a minimally-sized skbuff. */
1474 if (pkt_len
< rx_copybreak
&&
1475 (skb
= netdev_alloc_skb(dev
, pkt_len
+ NET_IP_ALIGN
)) != NULL
) {
1476 skb_reserve(skb
, NET_IP_ALIGN
); /* 16 byte align the IP header */
1477 pci_dma_sync_single_for_cpu(rp
->pdev
,
1478 rp
->rx_skbuff_dma
[entry
],
1480 PCI_DMA_FROMDEVICE
);
1482 skb_copy_to_linear_data(skb
,
1483 rp
->rx_skbuff
[entry
]->data
,
1485 skb_put(skb
, pkt_len
);
1486 pci_dma_sync_single_for_device(rp
->pdev
,
1487 rp
->rx_skbuff_dma
[entry
],
1489 PCI_DMA_FROMDEVICE
);
1491 skb
= rp
->rx_skbuff
[entry
];
1493 printk(KERN_ERR
"%s: Inconsistent Rx "
1494 "descriptor chain.\n",
1498 rp
->rx_skbuff
[entry
] = NULL
;
1499 skb_put(skb
, pkt_len
);
1500 pci_unmap_single(rp
->pdev
,
1501 rp
->rx_skbuff_dma
[entry
],
1503 PCI_DMA_FROMDEVICE
);
1505 skb
->protocol
= eth_type_trans(skb
, dev
);
1506 netif_receive_skb(skb
);
1507 dev
->last_rx
= jiffies
;
1508 rp
->stats
.rx_bytes
+= pkt_len
;
1509 rp
->stats
.rx_packets
++;
1511 entry
= (++rp
->cur_rx
) % RX_RING_SIZE
;
1512 rp
->rx_head_desc
= &rp
->rx_ring
[entry
];
1515 /* Refill the Rx ring buffers. */
1516 for (; rp
->cur_rx
- rp
->dirty_rx
> 0; rp
->dirty_rx
++) {
1517 struct sk_buff
*skb
;
1518 entry
= rp
->dirty_rx
% RX_RING_SIZE
;
1519 if (rp
->rx_skbuff
[entry
] == NULL
) {
1520 skb
= netdev_alloc_skb(dev
, rp
->rx_buf_sz
);
1521 rp
->rx_skbuff
[entry
] = skb
;
1523 break; /* Better luck next round. */
1524 skb
->dev
= dev
; /* Mark as being used by this device. */
1525 rp
->rx_skbuff_dma
[entry
] =
1526 pci_map_single(rp
->pdev
, skb
->data
,
1528 PCI_DMA_FROMDEVICE
);
1529 rp
->rx_ring
[entry
].addr
= cpu_to_le32(rp
->rx_skbuff_dma
[entry
]);
1531 rp
->rx_ring
[entry
].rx_status
= cpu_to_le32(DescOwn
);
1538 * Clears the "tally counters" for CRC errors and missed frames(?).
1539 * It has been reported that some chips need a write of 0 to clear
1540 * these, for others the counters are set to 1 when written to and
1541 * instead cleared when read. So we clear them both ways ...
1543 static inline void clear_tally_counters(void __iomem
*ioaddr
)
1545 iowrite32(0, ioaddr
+ RxMissed
);
1546 ioread16(ioaddr
+ RxCRCErrs
);
1547 ioread16(ioaddr
+ RxMissed
);
1550 static void rhine_restart_tx(struct net_device
*dev
) {
1551 struct rhine_private
*rp
= netdev_priv(dev
);
1552 void __iomem
*ioaddr
= rp
->base
;
1553 int entry
= rp
->dirty_tx
% TX_RING_SIZE
;
1557 * If new errors occured, we need to sort them out before doing Tx.
1558 * In that case the ISR will be back here RSN anyway.
1560 intr_status
= get_intr_status(dev
);
1562 if ((intr_status
& IntrTxErrSummary
) == 0) {
1564 /* We know better than the chip where it should continue. */
1565 iowrite32(rp
->tx_ring_dma
+ entry
* sizeof(struct tx_desc
),
1566 ioaddr
+ TxRingPtr
);
1568 iowrite8(ioread8(ioaddr
+ ChipCmd
) | CmdTxOn
,
1570 iowrite8(ioread8(ioaddr
+ ChipCmd1
) | Cmd1TxDemand
,
1575 /* This should never happen */
1577 printk(KERN_WARNING
"%s: rhine_restart_tx() "
1578 "Another error occured %8.8x.\n",
1579 dev
->name
, intr_status
);
1584 static void rhine_error(struct net_device
*dev
, int intr_status
)
1586 struct rhine_private
*rp
= netdev_priv(dev
);
1587 void __iomem
*ioaddr
= rp
->base
;
1589 spin_lock(&rp
->lock
);
1591 if (intr_status
& IntrLinkChange
)
1592 rhine_check_media(dev
, 0);
1593 if (intr_status
& IntrStatsMax
) {
1594 rp
->stats
.rx_crc_errors
+= ioread16(ioaddr
+ RxCRCErrs
);
1595 rp
->stats
.rx_missed_errors
+= ioread16(ioaddr
+ RxMissed
);
1596 clear_tally_counters(ioaddr
);
1598 if (intr_status
& IntrTxAborted
) {
1600 printk(KERN_INFO
"%s: Abort %8.8x, frame dropped.\n",
1601 dev
->name
, intr_status
);
1603 if (intr_status
& IntrTxUnderrun
) {
1604 if (rp
->tx_thresh
< 0xE0)
1605 iowrite8(rp
->tx_thresh
+= 0x20, ioaddr
+ TxConfig
);
1607 printk(KERN_INFO
"%s: Transmitter underrun, Tx "
1608 "threshold now %2.2x.\n",
1609 dev
->name
, rp
->tx_thresh
);
1611 if (intr_status
& IntrTxDescRace
) {
1613 printk(KERN_INFO
"%s: Tx descriptor write-back race.\n",
1616 if ((intr_status
& IntrTxError
) &&
1617 (intr_status
& (IntrTxAborted
|
1618 IntrTxUnderrun
| IntrTxDescRace
)) == 0) {
1619 if (rp
->tx_thresh
< 0xE0) {
1620 iowrite8(rp
->tx_thresh
+= 0x20, ioaddr
+ TxConfig
);
1623 printk(KERN_INFO
"%s: Unspecified error. Tx "
1624 "threshold now %2.2x.\n",
1625 dev
->name
, rp
->tx_thresh
);
1627 if (intr_status
& (IntrTxAborted
| IntrTxUnderrun
| IntrTxDescRace
|
1629 rhine_restart_tx(dev
);
1631 if (intr_status
& ~(IntrLinkChange
| IntrStatsMax
| IntrTxUnderrun
|
1632 IntrTxError
| IntrTxAborted
| IntrNormalSummary
|
1635 printk(KERN_ERR
"%s: Something Wicked happened! "
1636 "%8.8x.\n", dev
->name
, intr_status
);
1639 spin_unlock(&rp
->lock
);
1642 static struct net_device_stats
*rhine_get_stats(struct net_device
*dev
)
1644 struct rhine_private
*rp
= netdev_priv(dev
);
1645 void __iomem
*ioaddr
= rp
->base
;
1646 unsigned long flags
;
1648 spin_lock_irqsave(&rp
->lock
, flags
);
1649 rp
->stats
.rx_crc_errors
+= ioread16(ioaddr
+ RxCRCErrs
);
1650 rp
->stats
.rx_missed_errors
+= ioread16(ioaddr
+ RxMissed
);
1651 clear_tally_counters(ioaddr
);
1652 spin_unlock_irqrestore(&rp
->lock
, flags
);
1657 static void rhine_set_rx_mode(struct net_device
*dev
)
1659 struct rhine_private
*rp
= netdev_priv(dev
);
1660 void __iomem
*ioaddr
= rp
->base
;
1661 u32 mc_filter
[2]; /* Multicast hash filter */
1662 u8 rx_mode
; /* Note: 0x02=accept runt, 0x01=accept errs */
1664 if (dev
->flags
& IFF_PROMISC
) { /* Set promiscuous. */
1666 iowrite32(0xffffffff, ioaddr
+ MulticastFilter0
);
1667 iowrite32(0xffffffff, ioaddr
+ MulticastFilter1
);
1668 } else if ((dev
->mc_count
> multicast_filter_limit
)
1669 || (dev
->flags
& IFF_ALLMULTI
)) {
1670 /* Too many to match, or accept all multicasts. */
1671 iowrite32(0xffffffff, ioaddr
+ MulticastFilter0
);
1672 iowrite32(0xffffffff, ioaddr
+ MulticastFilter1
);
1675 struct dev_mc_list
*mclist
;
1677 memset(mc_filter
, 0, sizeof(mc_filter
));
1678 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
1679 i
++, mclist
= mclist
->next
) {
1680 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
1682 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
1684 iowrite32(mc_filter
[0], ioaddr
+ MulticastFilter0
);
1685 iowrite32(mc_filter
[1], ioaddr
+ MulticastFilter1
);
1688 iowrite8(rp
->rx_thresh
| rx_mode
, ioaddr
+ RxConfig
);
1691 static void netdev_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1693 struct rhine_private
*rp
= netdev_priv(dev
);
1695 strcpy(info
->driver
, DRV_NAME
);
1696 strcpy(info
->version
, DRV_VERSION
);
1697 strcpy(info
->bus_info
, pci_name(rp
->pdev
));
1700 static int netdev_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1702 struct rhine_private
*rp
= netdev_priv(dev
);
1705 spin_lock_irq(&rp
->lock
);
1706 rc
= mii_ethtool_gset(&rp
->mii_if
, cmd
);
1707 spin_unlock_irq(&rp
->lock
);
1712 static int netdev_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1714 struct rhine_private
*rp
= netdev_priv(dev
);
1717 spin_lock_irq(&rp
->lock
);
1718 rc
= mii_ethtool_sset(&rp
->mii_if
, cmd
);
1719 spin_unlock_irq(&rp
->lock
);
1720 rhine_set_carrier(&rp
->mii_if
);
1725 static int netdev_nway_reset(struct net_device
*dev
)
1727 struct rhine_private
*rp
= netdev_priv(dev
);
1729 return mii_nway_restart(&rp
->mii_if
);
1732 static u32
netdev_get_link(struct net_device
*dev
)
1734 struct rhine_private
*rp
= netdev_priv(dev
);
1736 return mii_link_ok(&rp
->mii_if
);
1739 static u32
netdev_get_msglevel(struct net_device
*dev
)
1744 static void netdev_set_msglevel(struct net_device
*dev
, u32 value
)
1749 static void rhine_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1751 struct rhine_private
*rp
= netdev_priv(dev
);
1753 if (!(rp
->quirks
& rqWOL
))
1756 spin_lock_irq(&rp
->lock
);
1757 wol
->supported
= WAKE_PHY
| WAKE_MAGIC
|
1758 WAKE_UCAST
| WAKE_MCAST
| WAKE_BCAST
; /* Untested */
1759 wol
->wolopts
= rp
->wolopts
;
1760 spin_unlock_irq(&rp
->lock
);
1763 static int rhine_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1765 struct rhine_private
*rp
= netdev_priv(dev
);
1766 u32 support
= WAKE_PHY
| WAKE_MAGIC
|
1767 WAKE_UCAST
| WAKE_MCAST
| WAKE_BCAST
; /* Untested */
1769 if (!(rp
->quirks
& rqWOL
))
1772 if (wol
->wolopts
& ~support
)
1775 spin_lock_irq(&rp
->lock
);
1776 rp
->wolopts
= wol
->wolopts
;
1777 spin_unlock_irq(&rp
->lock
);
1782 static const struct ethtool_ops netdev_ethtool_ops
= {
1783 .get_drvinfo
= netdev_get_drvinfo
,
1784 .get_settings
= netdev_get_settings
,
1785 .set_settings
= netdev_set_settings
,
1786 .nway_reset
= netdev_nway_reset
,
1787 .get_link
= netdev_get_link
,
1788 .get_msglevel
= netdev_get_msglevel
,
1789 .set_msglevel
= netdev_set_msglevel
,
1790 .get_wol
= rhine_get_wol
,
1791 .set_wol
= rhine_set_wol
,
1794 static int netdev_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1796 struct rhine_private
*rp
= netdev_priv(dev
);
1799 if (!netif_running(dev
))
1802 spin_lock_irq(&rp
->lock
);
1803 rc
= generic_mii_ioctl(&rp
->mii_if
, if_mii(rq
), cmd
, NULL
);
1804 spin_unlock_irq(&rp
->lock
);
1805 rhine_set_carrier(&rp
->mii_if
);
1810 static int rhine_close(struct net_device
*dev
)
1812 struct rhine_private
*rp
= netdev_priv(dev
);
1813 void __iomem
*ioaddr
= rp
->base
;
1815 spin_lock_irq(&rp
->lock
);
1817 netif_stop_queue(dev
);
1818 napi_disable(&rp
->napi
);
1821 printk(KERN_DEBUG
"%s: Shutting down ethercard, "
1822 "status was %4.4x.\n",
1823 dev
->name
, ioread16(ioaddr
+ ChipCmd
));
1825 /* Switch to loopback mode to avoid hardware races. */
1826 iowrite8(rp
->tx_thresh
| 0x02, ioaddr
+ TxConfig
);
1828 /* Disable interrupts by clearing the interrupt mask. */
1829 iowrite16(0x0000, ioaddr
+ IntrEnable
);
1831 /* Stop the chip's Tx and Rx processes. */
1832 iowrite16(CmdStop
, ioaddr
+ ChipCmd
);
1834 spin_unlock_irq(&rp
->lock
);
1836 free_irq(rp
->pdev
->irq
, dev
);
1845 static void __devexit
rhine_remove_one(struct pci_dev
*pdev
)
1847 struct net_device
*dev
= pci_get_drvdata(pdev
);
1848 struct rhine_private
*rp
= netdev_priv(dev
);
1850 unregister_netdev(dev
);
1852 pci_iounmap(pdev
, rp
->base
);
1853 pci_release_regions(pdev
);
1856 pci_disable_device(pdev
);
1857 pci_set_drvdata(pdev
, NULL
);
1860 static void rhine_shutdown (struct pci_dev
*pdev
)
1862 struct net_device
*dev
= pci_get_drvdata(pdev
);
1863 struct rhine_private
*rp
= netdev_priv(dev
);
1864 void __iomem
*ioaddr
= rp
->base
;
1866 if (!(rp
->quirks
& rqWOL
))
1867 return; /* Nothing to do for non-WOL adapters */
1869 rhine_power_init(dev
);
1871 /* Make sure we use pattern 0, 1 and not 4, 5 */
1872 if (rp
->quirks
& rq6patterns
)
1873 iowrite8(0x04, ioaddr
+ WOLcgClr
);
1875 if (rp
->wolopts
& WAKE_MAGIC
) {
1876 iowrite8(WOLmagic
, ioaddr
+ WOLcrSet
);
1878 * Turn EEPROM-controlled wake-up back on -- some hardware may
1879 * not cooperate otherwise.
1881 iowrite8(ioread8(ioaddr
+ ConfigA
) | 0x03, ioaddr
+ ConfigA
);
1884 if (rp
->wolopts
& (WAKE_BCAST
|WAKE_MCAST
))
1885 iowrite8(WOLbmcast
, ioaddr
+ WOLcgSet
);
1887 if (rp
->wolopts
& WAKE_PHY
)
1888 iowrite8(WOLlnkon
| WOLlnkoff
, ioaddr
+ WOLcrSet
);
1890 if (rp
->wolopts
& WAKE_UCAST
)
1891 iowrite8(WOLucast
, ioaddr
+ WOLcrSet
);
1894 /* Enable legacy WOL (for old motherboards) */
1895 iowrite8(0x01, ioaddr
+ PwcfgSet
);
1896 iowrite8(ioread8(ioaddr
+ StickyHW
) | 0x04, ioaddr
+ StickyHW
);
1899 /* Hit power state D3 (sleep) */
1901 iowrite8(ioread8(ioaddr
+ StickyHW
) | 0x03, ioaddr
+ StickyHW
);
1903 /* TODO: Check use of pci_enable_wake() */
1908 static int rhine_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1910 struct net_device
*dev
= pci_get_drvdata(pdev
);
1911 struct rhine_private
*rp
= netdev_priv(dev
);
1912 unsigned long flags
;
1914 if (!netif_running(dev
))
1917 napi_disable(&rp
->napi
);
1919 netif_device_detach(dev
);
1920 pci_save_state(pdev
);
1922 spin_lock_irqsave(&rp
->lock
, flags
);
1923 rhine_shutdown(pdev
);
1924 spin_unlock_irqrestore(&rp
->lock
, flags
);
1926 free_irq(dev
->irq
, dev
);
1930 static int rhine_resume(struct pci_dev
*pdev
)
1932 struct net_device
*dev
= pci_get_drvdata(pdev
);
1933 struct rhine_private
*rp
= netdev_priv(dev
);
1934 unsigned long flags
;
1937 if (!netif_running(dev
))
1940 if (request_irq(dev
->irq
, rhine_interrupt
, IRQF_SHARED
, dev
->name
, dev
))
1941 printk(KERN_ERR
"via-rhine %s: request_irq failed\n", dev
->name
);
1943 ret
= pci_set_power_state(pdev
, PCI_D0
);
1945 printk(KERN_INFO
"%s: Entering power state D0 %s (%d).\n",
1946 dev
->name
, ret
? "failed" : "succeeded", ret
);
1948 pci_restore_state(pdev
);
1950 spin_lock_irqsave(&rp
->lock
, flags
);
1952 enable_mmio(rp
->pioaddr
, rp
->quirks
);
1954 rhine_power_init(dev
);
1959 init_registers(dev
);
1960 spin_unlock_irqrestore(&rp
->lock
, flags
);
1962 netif_device_attach(dev
);
1966 #endif /* CONFIG_PM */
1968 static struct pci_driver rhine_driver
= {
1970 .id_table
= rhine_pci_tbl
,
1971 .probe
= rhine_init_one
,
1972 .remove
= __devexit_p(rhine_remove_one
),
1974 .suspend
= rhine_suspend
,
1975 .resume
= rhine_resume
,
1976 #endif /* CONFIG_PM */
1977 .shutdown
= rhine_shutdown
,
1980 static struct dmi_system_id __initdata rhine_dmi_table
[] = {
1984 DMI_MATCH(DMI_BIOS_VENDOR
, "Award Software International, Inc."),
1985 DMI_MATCH(DMI_BIOS_VERSION
, "6.00 PG"),
1991 DMI_MATCH(DMI_BIOS_VENDOR
, "Phoenix Technologies, LTD"),
1992 DMI_MATCH(DMI_BIOS_VERSION
, "6.00 PG"),
1998 static int __init
rhine_init(void)
2000 /* when a module, this is printed whether or not devices are found in probe */
2004 if (dmi_check_system(rhine_dmi_table
)) {
2005 /* these BIOSes fail at PXE boot if chip is in D3 */
2007 printk(KERN_WARNING
"%s: Broken BIOS detected, avoid_D3 "
2012 printk(KERN_INFO
"%s: avoid_D3 set.\n", DRV_NAME
);
2014 return pci_register_driver(&rhine_driver
);
2018 static void __exit
rhine_cleanup(void)
2020 pci_unregister_driver(&rhine_driver
);
2024 module_init(rhine_init
);
2025 module_exit(rhine_cleanup
);