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ixgbe: add device support for 82598AT (copper 10GbE) adapters
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / mv643xx_eth.c
blob3a759d0a7d1a79c0d5cf14902dadd9d490fd11a0
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
54 #include <asm/io.h>
55 #include <asm/types.h>
56 #include <asm/system.h>
57
58 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
59 static char mv643xx_eth_driver_version[] = "1.4";
60
61
62 /*
63 * Registers shared between all ports.
64 */
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
79
80 /*
81 * Per-port registers.
82 */
83 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
84 #define UNICAST_PROMISCUOUS_MODE 0x00000001
85 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
91 #define TX_FIFO_EMPTY 0x00000400
92 #define TX_IN_PROGRESS 0x00000080
93 #define PORT_SPEED_MASK 0x00000030
94 #define PORT_SPEED_1000 0x00000010
95 #define PORT_SPEED_100 0x00000020
96 #define PORT_SPEED_10 0x00000000
97 #define FLOW_CONTROL_ENABLED 0x00000008
98 #define FULL_DUPLEX 0x00000004
99 #define LINK_UP 0x00000002
100 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
101 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
103 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
104 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
105 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
106 #define INT_TX_END 0x07f80000
107 #define INT_RX 0x000003fc
108 #define INT_EXT 0x00000002
109 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
110 #define INT_EXT_LINK_PHY 0x00110000
111 #define INT_EXT_TX 0x000000ff
112 #define INT_MASK(p) (0x0468 + ((p) << 10))
113 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
114 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
115 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
116 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
117 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
118 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
119 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
120 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
121 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
122 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
123 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
124 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
125 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
126 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
127 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
128 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
129
130
131 /*
132 * SDMA configuration register.
133 */
134 #define RX_BURST_SIZE_16_64BIT (4 << 1)
135 #define BLM_RX_NO_SWAP (1 << 4)
136 #define BLM_TX_NO_SWAP (1 << 5)
137 #define TX_BURST_SIZE_16_64BIT (4 << 22)
138
139 #if defined(__BIG_ENDIAN)
140 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
141 RX_BURST_SIZE_16_64BIT | \
142 TX_BURST_SIZE_16_64BIT
143 #elif defined(__LITTLE_ENDIAN)
144 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
145 RX_BURST_SIZE_16_64BIT | \
146 BLM_RX_NO_SWAP | \
147 BLM_TX_NO_SWAP | \
148 TX_BURST_SIZE_16_64BIT
149 #else
150 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
151 #endif
152
153
154 /*
155 * Port serial control register.
156 */
157 #define SET_MII_SPEED_TO_100 (1 << 24)
158 #define SET_GMII_SPEED_TO_1000 (1 << 23)
159 #define SET_FULL_DUPLEX_MODE (1 << 21)
160 #define MAX_RX_PACKET_9700BYTE (5 << 17)
161 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
162 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
163 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
164 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
165 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
166 #define FORCE_LINK_PASS (1 << 1)
167 #define SERIAL_PORT_ENABLE (1 << 0)
168
169 #define DEFAULT_RX_QUEUE_SIZE 128
170 #define DEFAULT_TX_QUEUE_SIZE 256
171
172
173 /*
174 * RX/TX descriptors.
175 */
176 #if defined(__BIG_ENDIAN)
177 struct rx_desc {
178 u16 byte_cnt; /* Descriptor buffer byte count */
179 u16 buf_size; /* Buffer size */
180 u32 cmd_sts; /* Descriptor command status */
181 u32 next_desc_ptr; /* Next descriptor pointer */
182 u32 buf_ptr; /* Descriptor buffer pointer */
183 };
184
185 struct tx_desc {
186 u16 byte_cnt; /* buffer byte count */
187 u16 l4i_chk; /* CPU provided TCP checksum */
188 u32 cmd_sts; /* Command/status field */
189 u32 next_desc_ptr; /* Pointer to next descriptor */
190 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 };
192 #elif defined(__LITTLE_ENDIAN)
193 struct rx_desc {
194 u32 cmd_sts; /* Descriptor command status */
195 u16 buf_size; /* Buffer size */
196 u16 byte_cnt; /* Descriptor buffer byte count */
197 u32 buf_ptr; /* Descriptor buffer pointer */
198 u32 next_desc_ptr; /* Next descriptor pointer */
199 };
200
201 struct tx_desc {
202 u32 cmd_sts; /* Command/status field */
203 u16 l4i_chk; /* CPU provided TCP checksum */
204 u16 byte_cnt; /* buffer byte count */
205 u32 buf_ptr; /* pointer to buffer for this descriptor*/
206 u32 next_desc_ptr; /* Pointer to next descriptor */
207 };
208 #else
209 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
210 #endif
211
212 /* RX & TX descriptor command */
213 #define BUFFER_OWNED_BY_DMA 0x80000000
214
215 /* RX & TX descriptor status */
216 #define ERROR_SUMMARY 0x00000001
217
218 /* RX descriptor status */
219 #define LAYER_4_CHECKSUM_OK 0x40000000
220 #define RX_ENABLE_INTERRUPT 0x20000000
221 #define RX_FIRST_DESC 0x08000000
222 #define RX_LAST_DESC 0x04000000
223
224 /* TX descriptor command */
225 #define TX_ENABLE_INTERRUPT 0x00800000
226 #define GEN_CRC 0x00400000
227 #define TX_FIRST_DESC 0x00200000
228 #define TX_LAST_DESC 0x00100000
229 #define ZERO_PADDING 0x00080000
230 #define GEN_IP_V4_CHECKSUM 0x00040000
231 #define GEN_TCP_UDP_CHECKSUM 0x00020000
232 #define UDP_FRAME 0x00010000
233 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
234 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
235
236 #define TX_IHL_SHIFT 11
237
238
239 /* global *******************************************************************/
240 struct mv643xx_eth_shared_private {
241 /*
242 * Ethernet controller base address.
243 */
244 void __iomem *base;
245
246 /*
247 * Points at the right SMI instance to use.
248 */
249 struct mv643xx_eth_shared_private *smi;
250
251 /*
252 * Provides access to local SMI interface.
253 */
254 struct mii_bus *smi_bus;
255
256 /*
257 * If we have access to the error interrupt pin (which is
258 * somewhat misnamed as it not only reflects internal errors
259 * but also reflects SMI completion), use that to wait for
260 * SMI access completion instead of polling the SMI busy bit.
261 */
262 int err_interrupt;
263 wait_queue_head_t smi_busy_wait;
264
265 /*
266 * Per-port MBUS window access register value.
267 */
268 u32 win_protect;
269
270 /*
271 * Hardware-specific parameters.
272 */
273 unsigned int t_clk;
274 int extended_rx_coal_limit;
275 int tx_bw_control;
276 };
277
278 #define TX_BW_CONTROL_ABSENT 0
279 #define TX_BW_CONTROL_OLD_LAYOUT 1
280 #define TX_BW_CONTROL_NEW_LAYOUT 2
281
282
283 /* per-port *****************************************************************/
284 struct mib_counters {
285 u64 good_octets_received;
286 u32 bad_octets_received;
287 u32 internal_mac_transmit_err;
288 u32 good_frames_received;
289 u32 bad_frames_received;
290 u32 broadcast_frames_received;
291 u32 multicast_frames_received;
292 u32 frames_64_octets;
293 u32 frames_65_to_127_octets;
294 u32 frames_128_to_255_octets;
295 u32 frames_256_to_511_octets;
296 u32 frames_512_to_1023_octets;
297 u32 frames_1024_to_max_octets;
298 u64 good_octets_sent;
299 u32 good_frames_sent;
300 u32 excessive_collision;
301 u32 multicast_frames_sent;
302 u32 broadcast_frames_sent;
303 u32 unrec_mac_control_received;
304 u32 fc_sent;
305 u32 good_fc_received;
306 u32 bad_fc_received;
307 u32 undersize_received;
308 u32 fragments_received;
309 u32 oversize_received;
310 u32 jabber_received;
311 u32 mac_receive_error;
312 u32 bad_crc_event;
313 u32 collision;
314 u32 late_collision;
315 };
316
317 struct rx_queue {
318 int index;
319
320 int rx_ring_size;
321
322 int rx_desc_count;
323 int rx_curr_desc;
324 int rx_used_desc;
325
326 struct rx_desc *rx_desc_area;
327 dma_addr_t rx_desc_dma;
328 int rx_desc_area_size;
329 struct sk_buff **rx_skb;
330 };
331
332 struct tx_queue {
333 int index;
334
335 int tx_ring_size;
336
337 int tx_desc_count;
338 int tx_curr_desc;
339 int tx_used_desc;
340
341 struct tx_desc *tx_desc_area;
342 dma_addr_t tx_desc_dma;
343 int tx_desc_area_size;
344
345 struct sk_buff_head tx_skb;
346
347 unsigned long tx_packets;
348 unsigned long tx_bytes;
349 unsigned long tx_dropped;
350 };
351
352 struct mv643xx_eth_private {
353 struct mv643xx_eth_shared_private *shared;
354 int port_num;
355
356 struct net_device *dev;
357
358 struct phy_device *phy;
359
360 struct timer_list mib_counters_timer;
361 spinlock_t mib_counters_lock;
362 struct mib_counters mib_counters;
363
364 struct work_struct tx_timeout_task;
365
366 struct napi_struct napi;
367 u8 work_link;
368 u8 work_tx;
369 u8 work_tx_end;
370 u8 work_rx;
371 u8 work_rx_refill;
372 u8 work_rx_oom;
373
374 int skb_size;
375 struct sk_buff_head rx_recycle;
376
377 /*
378 * RX state.
379 */
380 int default_rx_ring_size;
381 unsigned long rx_desc_sram_addr;
382 int rx_desc_sram_size;
383 int rxq_count;
384 struct timer_list rx_oom;
385 struct rx_queue rxq[8];
386
387 /*
388 * TX state.
389 */
390 int default_tx_ring_size;
391 unsigned long tx_desc_sram_addr;
392 int tx_desc_sram_size;
393 int txq_count;
394 struct tx_queue txq[8];
395 };
396
397
398 /* port register accessors **************************************************/
399 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
400 {
401 return readl(mp->shared->base + offset);
402 }
403
404 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
405 {
406 writel(data, mp->shared->base + offset);
407 }
408
409
410 /* rxq/txq helper functions *************************************************/
411 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
412 {
413 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
414 }
415
416 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
417 {
418 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
419 }
420
421 static void rxq_enable(struct rx_queue *rxq)
422 {
423 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
424 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
425 }
426
427 static void rxq_disable(struct rx_queue *rxq)
428 {
429 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
430 u8 mask = 1 << rxq->index;
431
432 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
433 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
434 udelay(10);
435 }
436
437 static void txq_reset_hw_ptr(struct tx_queue *txq)
438 {
439 struct mv643xx_eth_private *mp = txq_to_mp(txq);
440 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
441 u32 addr;
442
443 addr = (u32)txq->tx_desc_dma;
444 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
445 wrl(mp, off, addr);
446 }
447
448 static void txq_enable(struct tx_queue *txq)
449 {
450 struct mv643xx_eth_private *mp = txq_to_mp(txq);
451 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
452 }
453
454 static void txq_disable(struct tx_queue *txq)
455 {
456 struct mv643xx_eth_private *mp = txq_to_mp(txq);
457 u8 mask = 1 << txq->index;
458
459 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
460 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
461 udelay(10);
462 }
463
464 static void txq_maybe_wake(struct tx_queue *txq)
465 {
466 struct mv643xx_eth_private *mp = txq_to_mp(txq);
467 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
468
469 if (netif_tx_queue_stopped(nq)) {
470 __netif_tx_lock(nq, smp_processor_id());
471 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
472 netif_tx_wake_queue(nq);
473 __netif_tx_unlock(nq);
474 }
475 }
476
477
478 /* rx napi ******************************************************************/
479 static int rxq_process(struct rx_queue *rxq, int budget)
480 {
481 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
482 struct net_device_stats *stats = &mp->dev->stats;
483 int rx;
484
485 rx = 0;
486 while (rx < budget && rxq->rx_desc_count) {
487 struct rx_desc *rx_desc;
488 unsigned int cmd_sts;
489 struct sk_buff *skb;
490 u16 byte_cnt;
491
492 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
493
494 cmd_sts = rx_desc->cmd_sts;
495 if (cmd_sts & BUFFER_OWNED_BY_DMA)
496 break;
497 rmb();
498
499 skb = rxq->rx_skb[rxq->rx_curr_desc];
500 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
501
502 rxq->rx_curr_desc++;
503 if (rxq->rx_curr_desc == rxq->rx_ring_size)
504 rxq->rx_curr_desc = 0;
505
506 dma_unmap_single(NULL, rx_desc->buf_ptr,
507 rx_desc->buf_size, DMA_FROM_DEVICE);
508 rxq->rx_desc_count--;
509 rx++;
510
511 mp->work_rx_refill |= 1 << rxq->index;
512
513 byte_cnt = rx_desc->byte_cnt;
514
515 /*
516 * Update statistics.
517 *
518 * Note that the descriptor byte count includes 2 dummy
519 * bytes automatically inserted by the hardware at the
520 * start of the packet (which we don't count), and a 4
521 * byte CRC at the end of the packet (which we do count).
522 */
523 stats->rx_packets++;
524 stats->rx_bytes += byte_cnt - 2;
525
526 /*
527 * In case we received a packet without first / last bits
528 * on, or the error summary bit is set, the packet needs
529 * to be dropped.
530 */
531 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
532 (RX_FIRST_DESC | RX_LAST_DESC))
533 || (cmd_sts & ERROR_SUMMARY)) {
534 stats->rx_dropped++;
535
536 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
537 (RX_FIRST_DESC | RX_LAST_DESC)) {
538 if (net_ratelimit())
539 dev_printk(KERN_ERR, &mp->dev->dev,
540 "received packet spanning "
541 "multiple descriptors\n");
542 }
543
544 if (cmd_sts & ERROR_SUMMARY)
545 stats->rx_errors++;
546
547 dev_kfree_skb(skb);
548 } else {
549 /*
550 * The -4 is for the CRC in the trailer of the
551 * received packet
552 */
553 skb_put(skb, byte_cnt - 2 - 4);
554
555 if (cmd_sts & LAYER_4_CHECKSUM_OK)
556 skb->ip_summed = CHECKSUM_UNNECESSARY;
557 skb->protocol = eth_type_trans(skb, mp->dev);
558 netif_receive_skb(skb);
559 }
560
561 mp->dev->last_rx = jiffies;
562 }
563
564 if (rx < budget)
565 mp->work_rx &= ~(1 << rxq->index);
566
567 return rx;
568 }
569
570 static int rxq_refill(struct rx_queue *rxq, int budget)
571 {
572 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
573 int refilled;
574
575 refilled = 0;
576 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
577 struct sk_buff *skb;
578 int unaligned;
579 int rx;
580
581 skb = __skb_dequeue(&mp->rx_recycle);
582 if (skb == NULL)
583 skb = dev_alloc_skb(mp->skb_size +
584 dma_get_cache_alignment() - 1);
585
586 if (skb == NULL) {
587 mp->work_rx_oom |= 1 << rxq->index;
588 goto oom;
589 }
590
591 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
592 if (unaligned)
593 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
594
595 refilled++;
596 rxq->rx_desc_count++;
597
598 rx = rxq->rx_used_desc++;
599 if (rxq->rx_used_desc == rxq->rx_ring_size)
600 rxq->rx_used_desc = 0;
601
602 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
603 mp->skb_size, DMA_FROM_DEVICE);
604 rxq->rx_desc_area[rx].buf_size = mp->skb_size;
605 rxq->rx_skb[rx] = skb;
606 wmb();
607 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
608 RX_ENABLE_INTERRUPT;
609 wmb();
610
611 /*
612 * The hardware automatically prepends 2 bytes of
613 * dummy data to each received packet, so that the
614 * IP header ends up 16-byte aligned.
615 */
616 skb_reserve(skb, 2);
617 }
618
619 if (refilled < budget)
620 mp->work_rx_refill &= ~(1 << rxq->index);
621
622 oom:
623 return refilled;
624 }
625
626
627 /* tx ***********************************************************************/
628 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
629 {
630 int frag;
631
632 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
633 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
634 if (fragp->size <= 8 && fragp->page_offset & 7)
635 return 1;
636 }
637
638 return 0;
639 }
640
641 static int txq_alloc_desc_index(struct tx_queue *txq)
642 {
643 int tx_desc_curr;
644
645 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
646
647 tx_desc_curr = txq->tx_curr_desc++;
648 if (txq->tx_curr_desc == txq->tx_ring_size)
649 txq->tx_curr_desc = 0;
650
651 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
652
653 return tx_desc_curr;
654 }
655
656 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
657 {
658 int nr_frags = skb_shinfo(skb)->nr_frags;
659 int frag;
660
661 for (frag = 0; frag < nr_frags; frag++) {
662 skb_frag_t *this_frag;
663 int tx_index;
664 struct tx_desc *desc;
665
666 this_frag = &skb_shinfo(skb)->frags[frag];
667 tx_index = txq_alloc_desc_index(txq);
668 desc = &txq->tx_desc_area[tx_index];
669
670 /*
671 * The last fragment will generate an interrupt
672 * which will free the skb on TX completion.
673 */
674 if (frag == nr_frags - 1) {
675 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
676 ZERO_PADDING | TX_LAST_DESC |
677 TX_ENABLE_INTERRUPT;
678 } else {
679 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
680 }
681
682 desc->l4i_chk = 0;
683 desc->byte_cnt = this_frag->size;
684 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
685 this_frag->page_offset,
686 this_frag->size,
687 DMA_TO_DEVICE);
688 }
689 }
690
691 static inline __be16 sum16_as_be(__sum16 sum)
692 {
693 return (__force __be16)sum;
694 }
695
696 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
697 {
698 struct mv643xx_eth_private *mp = txq_to_mp(txq);
699 int nr_frags = skb_shinfo(skb)->nr_frags;
700 int tx_index;
701 struct tx_desc *desc;
702 u32 cmd_sts;
703 u16 l4i_chk;
704 int length;
705
706 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
707 l4i_chk = 0;
708
709 if (skb->ip_summed == CHECKSUM_PARTIAL) {
710 int tag_bytes;
711
712 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
713 skb->protocol != htons(ETH_P_8021Q));
714
715 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
716 if (unlikely(tag_bytes & ~12)) {
717 if (skb_checksum_help(skb) == 0)
718 goto no_csum;
719 kfree_skb(skb);
720 return 1;
721 }
722
723 if (tag_bytes & 4)
724 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
725 if (tag_bytes & 8)
726 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
727
728 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
729 GEN_IP_V4_CHECKSUM |
730 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
731
732 switch (ip_hdr(skb)->protocol) {
733 case IPPROTO_UDP:
734 cmd_sts |= UDP_FRAME;
735 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
736 break;
737 case IPPROTO_TCP:
738 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
739 break;
740 default:
741 BUG();
742 }
743 } else {
744 no_csum:
745 /* Errata BTS #50, IHL must be 5 if no HW checksum */
746 cmd_sts |= 5 << TX_IHL_SHIFT;
747 }
748
749 tx_index = txq_alloc_desc_index(txq);
750 desc = &txq->tx_desc_area[tx_index];
751
752 if (nr_frags) {
753 txq_submit_frag_skb(txq, skb);
754 length = skb_headlen(skb);
755 } else {
756 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
757 length = skb->len;
758 }
759
760 desc->l4i_chk = l4i_chk;
761 desc->byte_cnt = length;
762 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
763
764 __skb_queue_tail(&txq->tx_skb, skb);
765
766 /* ensure all other descriptors are written before first cmd_sts */
767 wmb();
768 desc->cmd_sts = cmd_sts;
769
770 /* clear TX_END status */
771 mp->work_tx_end &= ~(1 << txq->index);
772
773 /* ensure all descriptors are written before poking hardware */
774 wmb();
775 txq_enable(txq);
776
777 txq->tx_desc_count += nr_frags + 1;
778
779 return 0;
780 }
781
782 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
783 {
784 struct mv643xx_eth_private *mp = netdev_priv(dev);
785 int queue;
786 struct tx_queue *txq;
787 struct netdev_queue *nq;
788
789 queue = skb_get_queue_mapping(skb);
790 txq = mp->txq + queue;
791 nq = netdev_get_tx_queue(dev, queue);
792
793 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
794 txq->tx_dropped++;
795 dev_printk(KERN_DEBUG, &dev->dev,
796 "failed to linearize skb with tiny "
797 "unaligned fragment\n");
798 return NETDEV_TX_BUSY;
799 }
800
801 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
802 if (net_ratelimit())
803 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
804 kfree_skb(skb);
805 return NETDEV_TX_OK;
806 }
807
808 if (!txq_submit_skb(txq, skb)) {
809 int entries_left;
810
811 txq->tx_bytes += skb->len;
812 txq->tx_packets++;
813 dev->trans_start = jiffies;
814
815 entries_left = txq->tx_ring_size - txq->tx_desc_count;
816 if (entries_left < MAX_SKB_FRAGS + 1)
817 netif_tx_stop_queue(nq);
818 }
819
820 return NETDEV_TX_OK;
821 }
822
823
824 /* tx napi ******************************************************************/
825 static void txq_kick(struct tx_queue *txq)
826 {
827 struct mv643xx_eth_private *mp = txq_to_mp(txq);
828 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
829 u32 hw_desc_ptr;
830 u32 expected_ptr;
831
832 __netif_tx_lock(nq, smp_processor_id());
833
834 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
835 goto out;
836
837 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
838 expected_ptr = (u32)txq->tx_desc_dma +
839 txq->tx_curr_desc * sizeof(struct tx_desc);
840
841 if (hw_desc_ptr != expected_ptr)
842 txq_enable(txq);
843
844 out:
845 __netif_tx_unlock(nq);
846
847 mp->work_tx_end &= ~(1 << txq->index);
848 }
849
850 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
851 {
852 struct mv643xx_eth_private *mp = txq_to_mp(txq);
853 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
854 int reclaimed;
855
856 __netif_tx_lock(nq, smp_processor_id());
857
858 reclaimed = 0;
859 while (reclaimed < budget && txq->tx_desc_count > 0) {
860 int tx_index;
861 struct tx_desc *desc;
862 u32 cmd_sts;
863 struct sk_buff *skb;
864
865 tx_index = txq->tx_used_desc;
866 desc = &txq->tx_desc_area[tx_index];
867 cmd_sts = desc->cmd_sts;
868
869 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
870 if (!force)
871 break;
872 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
873 }
874
875 txq->tx_used_desc = tx_index + 1;
876 if (txq->tx_used_desc == txq->tx_ring_size)
877 txq->tx_used_desc = 0;
878
879 reclaimed++;
880 txq->tx_desc_count--;
881
882 skb = NULL;
883 if (cmd_sts & TX_LAST_DESC)
884 skb = __skb_dequeue(&txq->tx_skb);
885
886 if (cmd_sts & ERROR_SUMMARY) {
887 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
888 mp->dev->stats.tx_errors++;
889 }
890
891 if (cmd_sts & TX_FIRST_DESC) {
892 dma_unmap_single(NULL, desc->buf_ptr,
893 desc->byte_cnt, DMA_TO_DEVICE);
894 } else {
895 dma_unmap_page(NULL, desc->buf_ptr,
896 desc->byte_cnt, DMA_TO_DEVICE);
897 }
898
899 if (skb != NULL) {
900 if (skb_queue_len(&mp->rx_recycle) <
901 mp->default_rx_ring_size &&
902 skb_recycle_check(skb, mp->skb_size))
903 __skb_queue_head(&mp->rx_recycle, skb);
904 else
905 dev_kfree_skb(skb);
906 }
907 }
908
909 __netif_tx_unlock(nq);
910
911 if (reclaimed < budget)
912 mp->work_tx &= ~(1 << txq->index);
913
914 return reclaimed;
915 }
916
917
918 /* tx rate control **********************************************************/
919 /*
920 * Set total maximum TX rate (shared by all TX queues for this port)
921 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
922 */
923 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
924 {
925 int token_rate;
926 int mtu;
927 int bucket_size;
928
929 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
930 if (token_rate > 1023)
931 token_rate = 1023;
932
933 mtu = (mp->dev->mtu + 255) >> 8;
934 if (mtu > 63)
935 mtu = 63;
936
937 bucket_size = (burst + 255) >> 8;
938 if (bucket_size > 65535)
939 bucket_size = 65535;
940
941 switch (mp->shared->tx_bw_control) {
942 case TX_BW_CONTROL_OLD_LAYOUT:
943 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
944 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
945 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
946 break;
947 case TX_BW_CONTROL_NEW_LAYOUT:
948 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
949 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
950 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
951 break;
952 }
953 }
954
955 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
956 {
957 struct mv643xx_eth_private *mp = txq_to_mp(txq);
958 int token_rate;
959 int bucket_size;
960
961 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
962 if (token_rate > 1023)
963 token_rate = 1023;
964
965 bucket_size = (burst + 255) >> 8;
966 if (bucket_size > 65535)
967 bucket_size = 65535;
968
969 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
970 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
971 (bucket_size << 10) | token_rate);
972 }
973
974 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
975 {
976 struct mv643xx_eth_private *mp = txq_to_mp(txq);
977 int off;
978 u32 val;
979
980 /*
981 * Turn on fixed priority mode.
982 */
983 off = 0;
984 switch (mp->shared->tx_bw_control) {
985 case TX_BW_CONTROL_OLD_LAYOUT:
986 off = TXQ_FIX_PRIO_CONF(mp->port_num);
987 break;
988 case TX_BW_CONTROL_NEW_LAYOUT:
989 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
990 break;
991 }
992
993 if (off) {
994 val = rdl(mp, off);
995 val |= 1 << txq->index;
996 wrl(mp, off, val);
997 }
998 }
999
1000 static void txq_set_wrr(struct tx_queue *txq, int weight)
1001 {
1002 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1003 int off;
1004 u32 val;
1005
1006 /*
1007 * Turn off fixed priority mode.
1008 */
1009 off = 0;
1010 switch (mp->shared->tx_bw_control) {
1011 case TX_BW_CONTROL_OLD_LAYOUT:
1012 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1013 break;
1014 case TX_BW_CONTROL_NEW_LAYOUT:
1015 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1016 break;
1017 }
1018
1019 if (off) {
1020 val = rdl(mp, off);
1021 val &= ~(1 << txq->index);
1022 wrl(mp, off, val);
1023
1024 /*
1025 * Configure WRR weight for this queue.
1026 */
1027 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1028
1029 val = rdl(mp, off);
1030 val = (val & ~0xff) | (weight & 0xff);
1031 wrl(mp, off, val);
1032 }
1033 }
1034
1035
1036 /* mii management interface *************************************************/
1037 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1038 {
1039 struct mv643xx_eth_shared_private *msp = dev_id;
1040
1041 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1042 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1043 wake_up(&msp->smi_busy_wait);
1044 return IRQ_HANDLED;
1045 }
1046
1047 return IRQ_NONE;
1048 }
1049
1050 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1051 {
1052 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1053 }
1054
1055 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1056 {
1057 if (msp->err_interrupt == NO_IRQ) {
1058 int i;
1059
1060 for (i = 0; !smi_is_done(msp); i++) {
1061 if (i == 10)
1062 return -ETIMEDOUT;
1063 msleep(10);
1064 }
1065
1066 return 0;
1067 }
1068
1069 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1070 msecs_to_jiffies(100)))
1071 return -ETIMEDOUT;
1072
1073 return 0;
1074 }
1075
1076 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1077 {
1078 struct mv643xx_eth_shared_private *msp = bus->priv;
1079 void __iomem *smi_reg = msp->base + SMI_REG;
1080 int ret;
1081
1082 if (smi_wait_ready(msp)) {
1083 printk("mv643xx_eth: SMI bus busy timeout\n");
1084 return -ETIMEDOUT;
1085 }
1086
1087 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1088
1089 if (smi_wait_ready(msp)) {
1090 printk("mv643xx_eth: SMI bus busy timeout\n");
1091 return -ETIMEDOUT;
1092 }
1093
1094 ret = readl(smi_reg);
1095 if (!(ret & SMI_READ_VALID)) {
1096 printk("mv643xx_eth: SMI bus read not valid\n");
1097 return -ENODEV;
1098 }
1099
1100 return ret & 0xffff;
1101 }
1102
1103 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1104 {
1105 struct mv643xx_eth_shared_private *msp = bus->priv;
1106 void __iomem *smi_reg = msp->base + SMI_REG;
1107
1108 if (smi_wait_ready(msp)) {
1109 printk("mv643xx_eth: SMI bus busy timeout\n");
1110 return -ETIMEDOUT;
1111 }
1112
1113 writel(SMI_OPCODE_WRITE | (reg << 21) |
1114 (addr << 16) | (val & 0xffff), smi_reg);
1115
1116 if (smi_wait_ready(msp)) {
1117 printk("mv643xx_eth: SMI bus busy timeout\n");
1118 return -ETIMEDOUT;
1119 }
1120
1121 return 0;
1122 }
1123
1124
1125 /* statistics ***************************************************************/
1126 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1127 {
1128 struct mv643xx_eth_private *mp = netdev_priv(dev);
1129 struct net_device_stats *stats = &dev->stats;
1130 unsigned long tx_packets = 0;
1131 unsigned long tx_bytes = 0;
1132 unsigned long tx_dropped = 0;
1133 int i;
1134
1135 for (i = 0; i < mp->txq_count; i++) {
1136 struct tx_queue *txq = mp->txq + i;
1137
1138 tx_packets += txq->tx_packets;
1139 tx_bytes += txq->tx_bytes;
1140 tx_dropped += txq->tx_dropped;
1141 }
1142
1143 stats->tx_packets = tx_packets;
1144 stats->tx_bytes = tx_bytes;
1145 stats->tx_dropped = tx_dropped;
1146
1147 return stats;
1148 }
1149
1150 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1151 {
1152 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1153 }
1154
1155 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1156 {
1157 int i;
1158
1159 for (i = 0; i < 0x80; i += 4)
1160 mib_read(mp, i);
1161 }
1162
1163 static void mib_counters_update(struct mv643xx_eth_private *mp)
1164 {
1165 struct mib_counters *p = &mp->mib_counters;
1166
1167 spin_lock(&mp->mib_counters_lock);
1168 p->good_octets_received += mib_read(mp, 0x00);
1169 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1170 p->bad_octets_received += mib_read(mp, 0x08);
1171 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1172 p->good_frames_received += mib_read(mp, 0x10);
1173 p->bad_frames_received += mib_read(mp, 0x14);
1174 p->broadcast_frames_received += mib_read(mp, 0x18);
1175 p->multicast_frames_received += mib_read(mp, 0x1c);
1176 p->frames_64_octets += mib_read(mp, 0x20);
1177 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1178 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1179 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1180 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1181 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1182 p->good_octets_sent += mib_read(mp, 0x38);
1183 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1184 p->good_frames_sent += mib_read(mp, 0x40);
1185 p->excessive_collision += mib_read(mp, 0x44);
1186 p->multicast_frames_sent += mib_read(mp, 0x48);
1187 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1188 p->unrec_mac_control_received += mib_read(mp, 0x50);
1189 p->fc_sent += mib_read(mp, 0x54);
1190 p->good_fc_received += mib_read(mp, 0x58);
1191 p->bad_fc_received += mib_read(mp, 0x5c);
1192 p->undersize_received += mib_read(mp, 0x60);
1193 p->fragments_received += mib_read(mp, 0x64);
1194 p->oversize_received += mib_read(mp, 0x68);
1195 p->jabber_received += mib_read(mp, 0x6c);
1196 p->mac_receive_error += mib_read(mp, 0x70);
1197 p->bad_crc_event += mib_read(mp, 0x74);
1198 p->collision += mib_read(mp, 0x78);
1199 p->late_collision += mib_read(mp, 0x7c);
1200 spin_unlock(&mp->mib_counters_lock);
1201
1202 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1203 }
1204
1205 static void mib_counters_timer_wrapper(unsigned long _mp)
1206 {
1207 struct mv643xx_eth_private *mp = (void *)_mp;
1208
1209 mib_counters_update(mp);
1210 }
1211
1212
1213 /* ethtool ******************************************************************/
1214 struct mv643xx_eth_stats {
1215 char stat_string[ETH_GSTRING_LEN];
1216 int sizeof_stat;
1217 int netdev_off;
1218 int mp_off;
1219 };
1220
1221 #define SSTAT(m) \
1222 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1223 offsetof(struct net_device, stats.m), -1 }
1224
1225 #define MIBSTAT(m) \
1226 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1227 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1228
1229 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1230 SSTAT(rx_packets),
1231 SSTAT(tx_packets),
1232 SSTAT(rx_bytes),
1233 SSTAT(tx_bytes),
1234 SSTAT(rx_errors),
1235 SSTAT(tx_errors),
1236 SSTAT(rx_dropped),
1237 SSTAT(tx_dropped),
1238 MIBSTAT(good_octets_received),
1239 MIBSTAT(bad_octets_received),
1240 MIBSTAT(internal_mac_transmit_err),
1241 MIBSTAT(good_frames_received),
1242 MIBSTAT(bad_frames_received),
1243 MIBSTAT(broadcast_frames_received),
1244 MIBSTAT(multicast_frames_received),
1245 MIBSTAT(frames_64_octets),
1246 MIBSTAT(frames_65_to_127_octets),
1247 MIBSTAT(frames_128_to_255_octets),
1248 MIBSTAT(frames_256_to_511_octets),
1249 MIBSTAT(frames_512_to_1023_octets),
1250 MIBSTAT(frames_1024_to_max_octets),
1251 MIBSTAT(good_octets_sent),
1252 MIBSTAT(good_frames_sent),
1253 MIBSTAT(excessive_collision),
1254 MIBSTAT(multicast_frames_sent),
1255 MIBSTAT(broadcast_frames_sent),
1256 MIBSTAT(unrec_mac_control_received),
1257 MIBSTAT(fc_sent),
1258 MIBSTAT(good_fc_received),
1259 MIBSTAT(bad_fc_received),
1260 MIBSTAT(undersize_received),
1261 MIBSTAT(fragments_received),
1262 MIBSTAT(oversize_received),
1263 MIBSTAT(jabber_received),
1264 MIBSTAT(mac_receive_error),
1265 MIBSTAT(bad_crc_event),
1266 MIBSTAT(collision),
1267 MIBSTAT(late_collision),
1268 };
1269
1270 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1271 {
1272 struct mv643xx_eth_private *mp = netdev_priv(dev);
1273 int err;
1274
1275 err = phy_read_status(mp->phy);
1276 if (err == 0)
1277 err = phy_ethtool_gset(mp->phy, cmd);
1278
1279 /*
1280 * The MAC does not support 1000baseT_Half.
1281 */
1282 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1283 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1284
1285 return err;
1286 }
1287
1288 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1289 {
1290 struct mv643xx_eth_private *mp = netdev_priv(dev);
1291 u32 port_status;
1292
1293 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1294
1295 cmd->supported = SUPPORTED_MII;
1296 cmd->advertising = ADVERTISED_MII;
1297 switch (port_status & PORT_SPEED_MASK) {
1298 case PORT_SPEED_10:
1299 cmd->speed = SPEED_10;
1300 break;
1301 case PORT_SPEED_100:
1302 cmd->speed = SPEED_100;
1303 break;
1304 case PORT_SPEED_1000:
1305 cmd->speed = SPEED_1000;
1306 break;
1307 default:
1308 cmd->speed = -1;
1309 break;
1310 }
1311 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1312 cmd->port = PORT_MII;
1313 cmd->phy_address = 0;
1314 cmd->transceiver = XCVR_INTERNAL;
1315 cmd->autoneg = AUTONEG_DISABLE;
1316 cmd->maxtxpkt = 1;
1317 cmd->maxrxpkt = 1;
1318
1319 return 0;
1320 }
1321
1322 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1323 {
1324 struct mv643xx_eth_private *mp = netdev_priv(dev);
1325
1326 /*
1327 * The MAC does not support 1000baseT_Half.
1328 */
1329 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1330
1331 return phy_ethtool_sset(mp->phy, cmd);
1332 }
1333
1334 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1335 {
1336 return -EINVAL;
1337 }
1338
1339 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1340 struct ethtool_drvinfo *drvinfo)
1341 {
1342 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1343 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1344 strncpy(drvinfo->fw_version, "N/A", 32);
1345 strncpy(drvinfo->bus_info, "platform", 32);
1346 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1347 }
1348
1349 static int mv643xx_eth_nway_reset(struct net_device *dev)
1350 {
1351 struct mv643xx_eth_private *mp = netdev_priv(dev);
1352
1353 return genphy_restart_aneg(mp->phy);
1354 }
1355
1356 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1357 {
1358 return -EINVAL;
1359 }
1360
1361 static u32 mv643xx_eth_get_link(struct net_device *dev)
1362 {
1363 return !!netif_carrier_ok(dev);
1364 }
1365
1366 static void mv643xx_eth_get_strings(struct net_device *dev,
1367 uint32_t stringset, uint8_t *data)
1368 {
1369 int i;
1370
1371 if (stringset == ETH_SS_STATS) {
1372 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1373 memcpy(data + i * ETH_GSTRING_LEN,
1374 mv643xx_eth_stats[i].stat_string,
1375 ETH_GSTRING_LEN);
1376 }
1377 }
1378 }
1379
1380 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1381 struct ethtool_stats *stats,
1382 uint64_t *data)
1383 {
1384 struct mv643xx_eth_private *mp = netdev_priv(dev);
1385 int i;
1386
1387 mv643xx_eth_get_stats(dev);
1388 mib_counters_update(mp);
1389
1390 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1391 const struct mv643xx_eth_stats *stat;
1392 void *p;
1393
1394 stat = mv643xx_eth_stats + i;
1395
1396 if (stat->netdev_off >= 0)
1397 p = ((void *)mp->dev) + stat->netdev_off;
1398 else
1399 p = ((void *)mp) + stat->mp_off;
1400
1401 data[i] = (stat->sizeof_stat == 8) ?
1402 *(uint64_t *)p : *(uint32_t *)p;
1403 }
1404 }
1405
1406 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1407 {
1408 if (sset == ETH_SS_STATS)
1409 return ARRAY_SIZE(mv643xx_eth_stats);
1410
1411 return -EOPNOTSUPP;
1412 }
1413
1414 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1415 .get_settings = mv643xx_eth_get_settings,
1416 .set_settings = mv643xx_eth_set_settings,
1417 .get_drvinfo = mv643xx_eth_get_drvinfo,
1418 .nway_reset = mv643xx_eth_nway_reset,
1419 .get_link = mv643xx_eth_get_link,
1420 .set_sg = ethtool_op_set_sg,
1421 .get_strings = mv643xx_eth_get_strings,
1422 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1423 .get_sset_count = mv643xx_eth_get_sset_count,
1424 };
1425
1426 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1427 .get_settings = mv643xx_eth_get_settings_phyless,
1428 .set_settings = mv643xx_eth_set_settings_phyless,
1429 .get_drvinfo = mv643xx_eth_get_drvinfo,
1430 .nway_reset = mv643xx_eth_nway_reset_phyless,
1431 .get_link = mv643xx_eth_get_link,
1432 .set_sg = ethtool_op_set_sg,
1433 .get_strings = mv643xx_eth_get_strings,
1434 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1435 .get_sset_count = mv643xx_eth_get_sset_count,
1436 };
1437
1438
1439 /* address handling *********************************************************/
1440 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1441 {
1442 unsigned int mac_h;
1443 unsigned int mac_l;
1444
1445 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1446 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1447
1448 addr[0] = (mac_h >> 24) & 0xff;
1449 addr[1] = (mac_h >> 16) & 0xff;
1450 addr[2] = (mac_h >> 8) & 0xff;
1451 addr[3] = mac_h & 0xff;
1452 addr[4] = (mac_l >> 8) & 0xff;
1453 addr[5] = mac_l & 0xff;
1454 }
1455
1456 static void init_mac_tables(struct mv643xx_eth_private *mp)
1457 {
1458 int i;
1459
1460 for (i = 0; i < 0x100; i += 4) {
1461 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1462 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1463 }
1464
1465 for (i = 0; i < 0x10; i += 4)
1466 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1467 }
1468
1469 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1470 int table, unsigned char entry)
1471 {
1472 unsigned int table_reg;
1473
1474 /* Set "accepts frame bit" at specified table entry */
1475 table_reg = rdl(mp, table + (entry & 0xfc));
1476 table_reg |= 0x01 << (8 * (entry & 3));
1477 wrl(mp, table + (entry & 0xfc), table_reg);
1478 }
1479
1480 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1481 {
1482 unsigned int mac_h;
1483 unsigned int mac_l;
1484 int table;
1485
1486 mac_l = (addr[4] << 8) | addr[5];
1487 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1488
1489 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1490 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1491
1492 table = UNICAST_TABLE(mp->port_num);
1493 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1494 }
1495
1496 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1497 {
1498 struct mv643xx_eth_private *mp = netdev_priv(dev);
1499
1500 /* +2 is for the offset of the HW addr type */
1501 memcpy(dev->dev_addr, addr + 2, 6);
1502
1503 init_mac_tables(mp);
1504 uc_addr_set(mp, dev->dev_addr);
1505
1506 return 0;
1507 }
1508
1509 static int addr_crc(unsigned char *addr)
1510 {
1511 int crc = 0;
1512 int i;
1513
1514 for (i = 0; i < 6; i++) {
1515 int j;
1516
1517 crc = (crc ^ addr[i]) << 8;
1518 for (j = 7; j >= 0; j--) {
1519 if (crc & (0x100 << j))
1520 crc ^= 0x107 << j;
1521 }
1522 }
1523
1524 return crc;
1525 }
1526
1527 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1528 {
1529 struct mv643xx_eth_private *mp = netdev_priv(dev);
1530 u32 port_config;
1531 struct dev_addr_list *addr;
1532 int i;
1533
1534 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1535 if (dev->flags & IFF_PROMISC)
1536 port_config |= UNICAST_PROMISCUOUS_MODE;
1537 else
1538 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1539 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1540
1541 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1542 int port_num = mp->port_num;
1543 u32 accept = 0x01010101;
1544
1545 for (i = 0; i < 0x100; i += 4) {
1546 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1547 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1548 }
1549 return;
1550 }
1551
1552 for (i = 0; i < 0x100; i += 4) {
1553 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1554 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1555 }
1556
1557 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1558 u8 *a = addr->da_addr;
1559 int table;
1560
1561 if (addr->da_addrlen != 6)
1562 continue;
1563
1564 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1565 table = SPECIAL_MCAST_TABLE(mp->port_num);
1566 set_filter_table_entry(mp, table, a[5]);
1567 } else {
1568 int crc = addr_crc(a);
1569
1570 table = OTHER_MCAST_TABLE(mp->port_num);
1571 set_filter_table_entry(mp, table, crc);
1572 }
1573 }
1574 }
1575
1576
1577 /* rx/tx queue initialisation ***********************************************/
1578 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1579 {
1580 struct rx_queue *rxq = mp->rxq + index;
1581 struct rx_desc *rx_desc;
1582 int size;
1583 int i;
1584
1585 rxq->index = index;
1586
1587 rxq->rx_ring_size = mp->default_rx_ring_size;
1588
1589 rxq->rx_desc_count = 0;
1590 rxq->rx_curr_desc = 0;
1591 rxq->rx_used_desc = 0;
1592
1593 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1594
1595 if (index == 0 && size <= mp->rx_desc_sram_size) {
1596 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1597 mp->rx_desc_sram_size);
1598 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1599 } else {
1600 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1601 &rxq->rx_desc_dma,
1602 GFP_KERNEL);
1603 }
1604
1605 if (rxq->rx_desc_area == NULL) {
1606 dev_printk(KERN_ERR, &mp->dev->dev,
1607 "can't allocate rx ring (%d bytes)\n", size);
1608 goto out;
1609 }
1610 memset(rxq->rx_desc_area, 0, size);
1611
1612 rxq->rx_desc_area_size = size;
1613 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1614 GFP_KERNEL);
1615 if (rxq->rx_skb == NULL) {
1616 dev_printk(KERN_ERR, &mp->dev->dev,
1617 "can't allocate rx skb ring\n");
1618 goto out_free;
1619 }
1620
1621 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1622 for (i = 0; i < rxq->rx_ring_size; i++) {
1623 int nexti;
1624
1625 nexti = i + 1;
1626 if (nexti == rxq->rx_ring_size)
1627 nexti = 0;
1628
1629 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1630 nexti * sizeof(struct rx_desc);
1631 }
1632
1633 return 0;
1634
1635
1636 out_free:
1637 if (index == 0 && size <= mp->rx_desc_sram_size)
1638 iounmap(rxq->rx_desc_area);
1639 else
1640 dma_free_coherent(NULL, size,
1641 rxq->rx_desc_area,
1642 rxq->rx_desc_dma);
1643
1644 out:
1645 return -ENOMEM;
1646 }
1647
1648 static void rxq_deinit(struct rx_queue *rxq)
1649 {
1650 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1651 int i;
1652
1653 rxq_disable(rxq);
1654
1655 for (i = 0; i < rxq->rx_ring_size; i++) {
1656 if (rxq->rx_skb[i]) {
1657 dev_kfree_skb(rxq->rx_skb[i]);
1658 rxq->rx_desc_count--;
1659 }
1660 }
1661
1662 if (rxq->rx_desc_count) {
1663 dev_printk(KERN_ERR, &mp->dev->dev,
1664 "error freeing rx ring -- %d skbs stuck\n",
1665 rxq->rx_desc_count);
1666 }
1667
1668 if (rxq->index == 0 &&
1669 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1670 iounmap(rxq->rx_desc_area);
1671 else
1672 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1673 rxq->rx_desc_area, rxq->rx_desc_dma);
1674
1675 kfree(rxq->rx_skb);
1676 }
1677
1678 static int txq_init(struct mv643xx_eth_private *mp, int index)
1679 {
1680 struct tx_queue *txq = mp->txq + index;
1681 struct tx_desc *tx_desc;
1682 int size;
1683 int i;
1684
1685 txq->index = index;
1686
1687 txq->tx_ring_size = mp->default_tx_ring_size;
1688
1689 txq->tx_desc_count = 0;
1690 txq->tx_curr_desc = 0;
1691 txq->tx_used_desc = 0;
1692
1693 size = txq->tx_ring_size * sizeof(struct tx_desc);
1694
1695 if (index == 0 && size <= mp->tx_desc_sram_size) {
1696 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1697 mp->tx_desc_sram_size);
1698 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1699 } else {
1700 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1701 &txq->tx_desc_dma,
1702 GFP_KERNEL);
1703 }
1704
1705 if (txq->tx_desc_area == NULL) {
1706 dev_printk(KERN_ERR, &mp->dev->dev,
1707 "can't allocate tx ring (%d bytes)\n", size);
1708 return -ENOMEM;
1709 }
1710 memset(txq->tx_desc_area, 0, size);
1711
1712 txq->tx_desc_area_size = size;
1713
1714 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1715 for (i = 0; i < txq->tx_ring_size; i++) {
1716 struct tx_desc *txd = tx_desc + i;
1717 int nexti;
1718
1719 nexti = i + 1;
1720 if (nexti == txq->tx_ring_size)
1721 nexti = 0;
1722
1723 txd->cmd_sts = 0;
1724 txd->next_desc_ptr = txq->tx_desc_dma +
1725 nexti * sizeof(struct tx_desc);
1726 }
1727
1728 skb_queue_head_init(&txq->tx_skb);
1729
1730 return 0;
1731 }
1732
1733 static void txq_deinit(struct tx_queue *txq)
1734 {
1735 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1736
1737 txq_disable(txq);
1738 txq_reclaim(txq, txq->tx_ring_size, 1);
1739
1740 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1741
1742 if (txq->index == 0 &&
1743 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1744 iounmap(txq->tx_desc_area);
1745 else
1746 dma_free_coherent(NULL, txq->tx_desc_area_size,
1747 txq->tx_desc_area, txq->tx_desc_dma);
1748 }
1749
1750
1751 /* netdev ops and related ***************************************************/
1752 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1753 {
1754 u32 int_cause;
1755 u32 int_cause_ext;
1756
1757 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1758 (INT_TX_END | INT_RX | INT_EXT);
1759 if (int_cause == 0)
1760 return 0;
1761
1762 int_cause_ext = 0;
1763 if (int_cause & INT_EXT)
1764 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1765
1766 int_cause &= INT_TX_END | INT_RX;
1767 if (int_cause) {
1768 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1769 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1770 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1771 mp->work_rx |= (int_cause & INT_RX) >> 2;
1772 }
1773
1774 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1775 if (int_cause_ext) {
1776 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1777 if (int_cause_ext & INT_EXT_LINK_PHY)
1778 mp->work_link = 1;
1779 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1780 }
1781
1782 return 1;
1783 }
1784
1785 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1786 {
1787 struct net_device *dev = (struct net_device *)dev_id;
1788 struct mv643xx_eth_private *mp = netdev_priv(dev);
1789
1790 if (unlikely(!mv643xx_eth_collect_events(mp)))
1791 return IRQ_NONE;
1792
1793 wrl(mp, INT_MASK(mp->port_num), 0);
1794 napi_schedule(&mp->napi);
1795
1796 return IRQ_HANDLED;
1797 }
1798
1799 static void handle_link_event(struct mv643xx_eth_private *mp)
1800 {
1801 struct net_device *dev = mp->dev;
1802 u32 port_status;
1803 int speed;
1804 int duplex;
1805 int fc;
1806
1807 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1808 if (!(port_status & LINK_UP)) {
1809 if (netif_carrier_ok(dev)) {
1810 int i;
1811
1812 printk(KERN_INFO "%s: link down\n", dev->name);
1813
1814 netif_carrier_off(dev);
1815
1816 for (i = 0; i < mp->txq_count; i++) {
1817 struct tx_queue *txq = mp->txq + i;
1818
1819 txq_reclaim(txq, txq->tx_ring_size, 1);
1820 txq_reset_hw_ptr(txq);
1821 }
1822 }
1823 return;
1824 }
1825
1826 switch (port_status & PORT_SPEED_MASK) {
1827 case PORT_SPEED_10:
1828 speed = 10;
1829 break;
1830 case PORT_SPEED_100:
1831 speed = 100;
1832 break;
1833 case PORT_SPEED_1000:
1834 speed = 1000;
1835 break;
1836 default:
1837 speed = -1;
1838 break;
1839 }
1840 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1841 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1842
1843 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1844 "flow control %sabled\n", dev->name,
1845 speed, duplex ? "full" : "half",
1846 fc ? "en" : "dis");
1847
1848 if (!netif_carrier_ok(dev))
1849 netif_carrier_on(dev);
1850 }
1851
1852 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1853 {
1854 struct mv643xx_eth_private *mp;
1855 int work_done;
1856
1857 mp = container_of(napi, struct mv643xx_eth_private, napi);
1858
1859 mp->work_rx_refill |= mp->work_rx_oom;
1860 mp->work_rx_oom = 0;
1861
1862 work_done = 0;
1863 while (work_done < budget) {
1864 u8 queue_mask;
1865 int queue;
1866 int work_tbd;
1867
1868 if (mp->work_link) {
1869 mp->work_link = 0;
1870 handle_link_event(mp);
1871 continue;
1872 }
1873
1874 queue_mask = mp->work_tx | mp->work_tx_end |
1875 mp->work_rx | mp->work_rx_refill;
1876 if (!queue_mask) {
1877 if (mv643xx_eth_collect_events(mp))
1878 continue;
1879 break;
1880 }
1881
1882 queue = fls(queue_mask) - 1;
1883 queue_mask = 1 << queue;
1884
1885 work_tbd = budget - work_done;
1886 if (work_tbd > 16)
1887 work_tbd = 16;
1888
1889 if (mp->work_tx_end & queue_mask) {
1890 txq_kick(mp->txq + queue);
1891 } else if (mp->work_tx & queue_mask) {
1892 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1893 txq_maybe_wake(mp->txq + queue);
1894 } else if (mp->work_rx & queue_mask) {
1895 work_done += rxq_process(mp->rxq + queue, work_tbd);
1896 } else if (mp->work_rx_refill & queue_mask) {
1897 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1898 } else {
1899 BUG();
1900 }
1901 }
1902
1903 if (work_done < budget) {
1904 if (mp->work_rx_oom)
1905 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1906 napi_complete(napi);
1907 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1908 }
1909
1910 return work_done;
1911 }
1912
1913 static inline void oom_timer_wrapper(unsigned long data)
1914 {
1915 struct mv643xx_eth_private *mp = (void *)data;
1916
1917 napi_schedule(&mp->napi);
1918 }
1919
1920 static void phy_reset(struct mv643xx_eth_private *mp)
1921 {
1922 int data;
1923
1924 data = phy_read(mp->phy, MII_BMCR);
1925 if (data < 0)
1926 return;
1927
1928 data |= BMCR_RESET;
1929 if (phy_write(mp->phy, MII_BMCR, data) < 0)
1930 return;
1931
1932 do {
1933 data = phy_read(mp->phy, MII_BMCR);
1934 } while (data >= 0 && data & BMCR_RESET);
1935 }
1936
1937 static void port_start(struct mv643xx_eth_private *mp)
1938 {
1939 u32 pscr;
1940 int i;
1941
1942 /*
1943 * Perform PHY reset, if there is a PHY.
1944 */
1945 if (mp->phy != NULL) {
1946 struct ethtool_cmd cmd;
1947
1948 mv643xx_eth_get_settings(mp->dev, &cmd);
1949 phy_reset(mp);
1950 mv643xx_eth_set_settings(mp->dev, &cmd);
1951 }
1952
1953 /*
1954 * Configure basic link parameters.
1955 */
1956 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1957
1958 pscr |= SERIAL_PORT_ENABLE;
1959 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1960
1961 pscr |= DO_NOT_FORCE_LINK_FAIL;
1962 if (mp->phy == NULL)
1963 pscr |= FORCE_LINK_PASS;
1964 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1965
1966 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1967
1968 /*
1969 * Configure TX path and queues.
1970 */
1971 tx_set_rate(mp, 1000000000, 16777216);
1972 for (i = 0; i < mp->txq_count; i++) {
1973 struct tx_queue *txq = mp->txq + i;
1974
1975 txq_reset_hw_ptr(txq);
1976 txq_set_rate(txq, 1000000000, 16777216);
1977 txq_set_fixed_prio_mode(txq);
1978 }
1979
1980 /*
1981 * Add configured unicast address to address filter table.
1982 */
1983 uc_addr_set(mp, mp->dev->dev_addr);
1984
1985 /*
1986 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1987 * frames to RX queue #0, and include the pseudo-header when
1988 * calculating receive checksums.
1989 */
1990 wrl(mp, PORT_CONFIG(mp->port_num), 0x02000000);
1991
1992 /*
1993 * Treat BPDUs as normal multicasts, and disable partition mode.
1994 */
1995 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1996
1997 /*
1998 * Enable the receive queues.
1999 */
2000 for (i = 0; i < mp->rxq_count; i++) {
2001 struct rx_queue *rxq = mp->rxq + i;
2002 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2003 u32 addr;
2004
2005 addr = (u32)rxq->rx_desc_dma;
2006 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2007 wrl(mp, off, addr);
2008
2009 rxq_enable(rxq);
2010 }
2011 }
2012
2013 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2014 {
2015 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2016 u32 val;
2017
2018 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2019 if (mp->shared->extended_rx_coal_limit) {
2020 if (coal > 0xffff)
2021 coal = 0xffff;
2022 val &= ~0x023fff80;
2023 val |= (coal & 0x8000) << 10;
2024 val |= (coal & 0x7fff) << 7;
2025 } else {
2026 if (coal > 0x3fff)
2027 coal = 0x3fff;
2028 val &= ~0x003fff00;
2029 val |= (coal & 0x3fff) << 8;
2030 }
2031 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2032 }
2033
2034 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2035 {
2036 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2037
2038 if (coal > 0x3fff)
2039 coal = 0x3fff;
2040 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2041 }
2042
2043 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2044 {
2045 int skb_size;
2046
2047 /*
2048 * Reserve 2+14 bytes for an ethernet header (the hardware
2049 * automatically prepends 2 bytes of dummy data to each
2050 * received packet), 16 bytes for up to four VLAN tags, and
2051 * 4 bytes for the trailing FCS -- 36 bytes total.
2052 */
2053 skb_size = mp->dev->mtu + 36;
2054
2055 /*
2056 * Make sure that the skb size is a multiple of 8 bytes, as
2057 * the lower three bits of the receive descriptor's buffer
2058 * size field are ignored by the hardware.
2059 */
2060 mp->skb_size = (skb_size + 7) & ~7;
2061 }
2062
2063 static int mv643xx_eth_open(struct net_device *dev)
2064 {
2065 struct mv643xx_eth_private *mp = netdev_priv(dev);
2066 int err;
2067 int i;
2068
2069 wrl(mp, INT_CAUSE(mp->port_num), 0);
2070 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2071 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2072
2073 err = request_irq(dev->irq, mv643xx_eth_irq,
2074 IRQF_SHARED, dev->name, dev);
2075 if (err) {
2076 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2077 return -EAGAIN;
2078 }
2079
2080 init_mac_tables(mp);
2081
2082 mv643xx_eth_recalc_skb_size(mp);
2083
2084 napi_enable(&mp->napi);
2085
2086 skb_queue_head_init(&mp->rx_recycle);
2087
2088 for (i = 0; i < mp->rxq_count; i++) {
2089 err = rxq_init(mp, i);
2090 if (err) {
2091 while (--i >= 0)
2092 rxq_deinit(mp->rxq + i);
2093 goto out;
2094 }
2095
2096 rxq_refill(mp->rxq + i, INT_MAX);
2097 }
2098
2099 if (mp->work_rx_oom) {
2100 mp->rx_oom.expires = jiffies + (HZ / 10);
2101 add_timer(&mp->rx_oom);
2102 }
2103
2104 for (i = 0; i < mp->txq_count; i++) {
2105 err = txq_init(mp, i);
2106 if (err) {
2107 while (--i >= 0)
2108 txq_deinit(mp->txq + i);
2109 goto out_free;
2110 }
2111 }
2112
2113 netif_carrier_off(dev);
2114
2115 port_start(mp);
2116
2117 set_rx_coal(mp, 0);
2118 set_tx_coal(mp, 0);
2119
2120 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
2121 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2122
2123 return 0;
2124
2125
2126 out_free:
2127 for (i = 0; i < mp->rxq_count; i++)
2128 rxq_deinit(mp->rxq + i);
2129 out:
2130 free_irq(dev->irq, dev);
2131
2132 return err;
2133 }
2134
2135 static void port_reset(struct mv643xx_eth_private *mp)
2136 {
2137 unsigned int data;
2138 int i;
2139
2140 for (i = 0; i < mp->rxq_count; i++)
2141 rxq_disable(mp->rxq + i);
2142 for (i = 0; i < mp->txq_count; i++)
2143 txq_disable(mp->txq + i);
2144
2145 while (1) {
2146 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2147
2148 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2149 break;
2150 udelay(10);
2151 }
2152
2153 /* Reset the Enable bit in the Configuration Register */
2154 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2155 data &= ~(SERIAL_PORT_ENABLE |
2156 DO_NOT_FORCE_LINK_FAIL |
2157 FORCE_LINK_PASS);
2158 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2159 }
2160
2161 static int mv643xx_eth_stop(struct net_device *dev)
2162 {
2163 struct mv643xx_eth_private *mp = netdev_priv(dev);
2164 int i;
2165
2166 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2167 rdl(mp, INT_MASK(mp->port_num));
2168
2169 del_timer_sync(&mp->mib_counters_timer);
2170
2171 napi_disable(&mp->napi);
2172
2173 del_timer_sync(&mp->rx_oom);
2174
2175 netif_carrier_off(dev);
2176
2177 free_irq(dev->irq, dev);
2178
2179 port_reset(mp);
2180 mv643xx_eth_get_stats(dev);
2181 mib_counters_update(mp);
2182
2183 skb_queue_purge(&mp->rx_recycle);
2184
2185 for (i = 0; i < mp->rxq_count; i++)
2186 rxq_deinit(mp->rxq + i);
2187 for (i = 0; i < mp->txq_count; i++)
2188 txq_deinit(mp->txq + i);
2189
2190 return 0;
2191 }
2192
2193 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2194 {
2195 struct mv643xx_eth_private *mp = netdev_priv(dev);
2196
2197 if (mp->phy != NULL)
2198 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2199
2200 return -EOPNOTSUPP;
2201 }
2202
2203 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2204 {
2205 struct mv643xx_eth_private *mp = netdev_priv(dev);
2206
2207 if (new_mtu < 64 || new_mtu > 9500)
2208 return -EINVAL;
2209
2210 dev->mtu = new_mtu;
2211 mv643xx_eth_recalc_skb_size(mp);
2212 tx_set_rate(mp, 1000000000, 16777216);
2213
2214 if (!netif_running(dev))
2215 return 0;
2216
2217 /*
2218 * Stop and then re-open the interface. This will allocate RX
2219 * skbs of the new MTU.
2220 * There is a possible danger that the open will not succeed,
2221 * due to memory being full.
2222 */
2223 mv643xx_eth_stop(dev);
2224 if (mv643xx_eth_open(dev)) {
2225 dev_printk(KERN_ERR, &dev->dev,
2226 "fatal error on re-opening device after "
2227 "MTU change\n");
2228 }
2229
2230 return 0;
2231 }
2232
2233 static void tx_timeout_task(struct work_struct *ugly)
2234 {
2235 struct mv643xx_eth_private *mp;
2236
2237 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2238 if (netif_running(mp->dev)) {
2239 netif_tx_stop_all_queues(mp->dev);
2240 port_reset(mp);
2241 port_start(mp);
2242 netif_tx_wake_all_queues(mp->dev);
2243 }
2244 }
2245
2246 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2247 {
2248 struct mv643xx_eth_private *mp = netdev_priv(dev);
2249
2250 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2251
2252 schedule_work(&mp->tx_timeout_task);
2253 }
2254
2255 #ifdef CONFIG_NET_POLL_CONTROLLER
2256 static void mv643xx_eth_netpoll(struct net_device *dev)
2257 {
2258 struct mv643xx_eth_private *mp = netdev_priv(dev);
2259
2260 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2261 rdl(mp, INT_MASK(mp->port_num));
2262
2263 mv643xx_eth_irq(dev->irq, dev);
2264
2265 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2266 }
2267 #endif
2268
2269
2270 /* platform glue ************************************************************/
2271 static void
2272 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2273 struct mbus_dram_target_info *dram)
2274 {
2275 void __iomem *base = msp->base;
2276 u32 win_enable;
2277 u32 win_protect;
2278 int i;
2279
2280 for (i = 0; i < 6; i++) {
2281 writel(0, base + WINDOW_BASE(i));
2282 writel(0, base + WINDOW_SIZE(i));
2283 if (i < 4)
2284 writel(0, base + WINDOW_REMAP_HIGH(i));
2285 }
2286
2287 win_enable = 0x3f;
2288 win_protect = 0;
2289
2290 for (i = 0; i < dram->num_cs; i++) {
2291 struct mbus_dram_window *cs = dram->cs + i;
2292
2293 writel((cs->base & 0xffff0000) |
2294 (cs->mbus_attr << 8) |
2295 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2296 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2297
2298 win_enable &= ~(1 << i);
2299 win_protect |= 3 << (2 * i);
2300 }
2301
2302 writel(win_enable, base + WINDOW_BAR_ENABLE);
2303 msp->win_protect = win_protect;
2304 }
2305
2306 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2307 {
2308 /*
2309 * Check whether we have a 14-bit coal limit field in bits
2310 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2311 * SDMA config register.
2312 */
2313 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2314 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2315 msp->extended_rx_coal_limit = 1;
2316 else
2317 msp->extended_rx_coal_limit = 0;
2318
2319 /*
2320 * Check whether the MAC supports TX rate control, and if
2321 * yes, whether its associated registers are in the old or
2322 * the new place.
2323 */
2324 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2325 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) {
2326 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2327 } else {
2328 writel(7, msp->base + TX_BW_RATE(0));
2329 if (readl(msp->base + TX_BW_RATE(0)) & 7)
2330 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2331 else
2332 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2333 }
2334 }
2335
2336 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2337 {
2338 static int mv643xx_eth_version_printed = 0;
2339 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2340 struct mv643xx_eth_shared_private *msp;
2341 struct resource *res;
2342 int ret;
2343
2344 if (!mv643xx_eth_version_printed++)
2345 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2346 "driver version %s\n", mv643xx_eth_driver_version);
2347
2348 ret = -EINVAL;
2349 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2350 if (res == NULL)
2351 goto out;
2352
2353 ret = -ENOMEM;
2354 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2355 if (msp == NULL)
2356 goto out;
2357 memset(msp, 0, sizeof(*msp));
2358
2359 msp->base = ioremap(res->start, res->end - res->start + 1);
2360 if (msp->base == NULL)
2361 goto out_free;
2362
2363 /*
2364 * Set up and register SMI bus.
2365 */
2366 if (pd == NULL || pd->shared_smi == NULL) {
2367 msp->smi_bus = mdiobus_alloc();
2368 if (msp->smi_bus == NULL)
2369 goto out_unmap;
2370
2371 msp->smi_bus->priv = msp;
2372 msp->smi_bus->name = "mv643xx_eth smi";
2373 msp->smi_bus->read = smi_bus_read;
2374 msp->smi_bus->write = smi_bus_write,
2375 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2376 msp->smi_bus->parent = &pdev->dev;
2377 msp->smi_bus->phy_mask = 0xffffffff;
2378 if (mdiobus_register(msp->smi_bus) < 0)
2379 goto out_free_mii_bus;
2380 msp->smi = msp;
2381 } else {
2382 msp->smi = platform_get_drvdata(pd->shared_smi);
2383 }
2384
2385 msp->err_interrupt = NO_IRQ;
2386 init_waitqueue_head(&msp->smi_busy_wait);
2387
2388 /*
2389 * Check whether the error interrupt is hooked up.
2390 */
2391 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2392 if (res != NULL) {
2393 int err;
2394
2395 err = request_irq(res->start, mv643xx_eth_err_irq,
2396 IRQF_SHARED, "mv643xx_eth", msp);
2397 if (!err) {
2398 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2399 msp->err_interrupt = res->start;
2400 }
2401 }
2402
2403 /*
2404 * (Re-)program MBUS remapping windows if we are asked to.
2405 */
2406 if (pd != NULL && pd->dram != NULL)
2407 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2408
2409 /*
2410 * Detect hardware parameters.
2411 */
2412 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2413 infer_hw_params(msp);
2414
2415 platform_set_drvdata(pdev, msp);
2416
2417 return 0;
2418
2419 out_free_mii_bus:
2420 mdiobus_free(msp->smi_bus);
2421 out_unmap:
2422 iounmap(msp->base);
2423 out_free:
2424 kfree(msp);
2425 out:
2426 return ret;
2427 }
2428
2429 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2430 {
2431 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2432 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2433
2434 if (pd == NULL || pd->shared_smi == NULL) {
2435 mdiobus_free(msp->smi_bus);
2436 mdiobus_unregister(msp->smi_bus);
2437 }
2438 if (msp->err_interrupt != NO_IRQ)
2439 free_irq(msp->err_interrupt, msp);
2440 iounmap(msp->base);
2441 kfree(msp);
2442
2443 return 0;
2444 }
2445
2446 static struct platform_driver mv643xx_eth_shared_driver = {
2447 .probe = mv643xx_eth_shared_probe,
2448 .remove = mv643xx_eth_shared_remove,
2449 .driver = {
2450 .name = MV643XX_ETH_SHARED_NAME,
2451 .owner = THIS_MODULE,
2452 },
2453 };
2454
2455 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2456 {
2457 int addr_shift = 5 * mp->port_num;
2458 u32 data;
2459
2460 data = rdl(mp, PHY_ADDR);
2461 data &= ~(0x1f << addr_shift);
2462 data |= (phy_addr & 0x1f) << addr_shift;
2463 wrl(mp, PHY_ADDR, data);
2464 }
2465
2466 static int phy_addr_get(struct mv643xx_eth_private *mp)
2467 {
2468 unsigned int data;
2469
2470 data = rdl(mp, PHY_ADDR);
2471
2472 return (data >> (5 * mp->port_num)) & 0x1f;
2473 }
2474
2475 static void set_params(struct mv643xx_eth_private *mp,
2476 struct mv643xx_eth_platform_data *pd)
2477 {
2478 struct net_device *dev = mp->dev;
2479
2480 if (is_valid_ether_addr(pd->mac_addr))
2481 memcpy(dev->dev_addr, pd->mac_addr, 6);
2482 else
2483 uc_addr_get(mp, dev->dev_addr);
2484
2485 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2486 if (pd->rx_queue_size)
2487 mp->default_rx_ring_size = pd->rx_queue_size;
2488 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2489 mp->rx_desc_sram_size = pd->rx_sram_size;
2490
2491 mp->rxq_count = pd->rx_queue_count ? : 1;
2492
2493 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2494 if (pd->tx_queue_size)
2495 mp->default_tx_ring_size = pd->tx_queue_size;
2496 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2497 mp->tx_desc_sram_size = pd->tx_sram_size;
2498
2499 mp->txq_count = pd->tx_queue_count ? : 1;
2500 }
2501
2502 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2503 int phy_addr)
2504 {
2505 struct mii_bus *bus = mp->shared->smi->smi_bus;
2506 struct phy_device *phydev;
2507 int start;
2508 int num;
2509 int i;
2510
2511 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2512 start = phy_addr_get(mp) & 0x1f;
2513 num = 32;
2514 } else {
2515 start = phy_addr & 0x1f;
2516 num = 1;
2517 }
2518
2519 phydev = NULL;
2520 for (i = 0; i < num; i++) {
2521 int addr = (start + i) & 0x1f;
2522
2523 if (bus->phy_map[addr] == NULL)
2524 mdiobus_scan(bus, addr);
2525
2526 if (phydev == NULL) {
2527 phydev = bus->phy_map[addr];
2528 if (phydev != NULL)
2529 phy_addr_set(mp, addr);
2530 }
2531 }
2532
2533 return phydev;
2534 }
2535
2536 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2537 {
2538 struct phy_device *phy = mp->phy;
2539
2540 phy_reset(mp);
2541
2542 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2543
2544 if (speed == 0) {
2545 phy->autoneg = AUTONEG_ENABLE;
2546 phy->speed = 0;
2547 phy->duplex = 0;
2548 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2549 } else {
2550 phy->autoneg = AUTONEG_DISABLE;
2551 phy->advertising = 0;
2552 phy->speed = speed;
2553 phy->duplex = duplex;
2554 }
2555 phy_start_aneg(phy);
2556 }
2557
2558 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2559 {
2560 u32 pscr;
2561
2562 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2563 if (pscr & SERIAL_PORT_ENABLE) {
2564 pscr &= ~SERIAL_PORT_ENABLE;
2565 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2566 }
2567
2568 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2569 if (mp->phy == NULL) {
2570 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2571 if (speed == SPEED_1000)
2572 pscr |= SET_GMII_SPEED_TO_1000;
2573 else if (speed == SPEED_100)
2574 pscr |= SET_MII_SPEED_TO_100;
2575
2576 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2577
2578 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2579 if (duplex == DUPLEX_FULL)
2580 pscr |= SET_FULL_DUPLEX_MODE;
2581 }
2582
2583 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2584 }
2585
2586 static int mv643xx_eth_probe(struct platform_device *pdev)
2587 {
2588 struct mv643xx_eth_platform_data *pd;
2589 struct mv643xx_eth_private *mp;
2590 struct net_device *dev;
2591 struct resource *res;
2592 int err;
2593
2594 pd = pdev->dev.platform_data;
2595 if (pd == NULL) {
2596 dev_printk(KERN_ERR, &pdev->dev,
2597 "no mv643xx_eth_platform_data\n");
2598 return -ENODEV;
2599 }
2600
2601 if (pd->shared == NULL) {
2602 dev_printk(KERN_ERR, &pdev->dev,
2603 "no mv643xx_eth_platform_data->shared\n");
2604 return -ENODEV;
2605 }
2606
2607 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2608 if (!dev)
2609 return -ENOMEM;
2610
2611 mp = netdev_priv(dev);
2612 platform_set_drvdata(pdev, mp);
2613
2614 mp->shared = platform_get_drvdata(pd->shared);
2615 mp->port_num = pd->port_number;
2616
2617 mp->dev = dev;
2618
2619 set_params(mp, pd);
2620 dev->real_num_tx_queues = mp->txq_count;
2621
2622 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2623 mp->phy = phy_scan(mp, pd->phy_addr);
2624
2625 if (mp->phy != NULL) {
2626 phy_init(mp, pd->speed, pd->duplex);
2627 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2628 } else {
2629 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2630 }
2631
2632 init_pscr(mp, pd->speed, pd->duplex);
2633
2634
2635 mib_counters_clear(mp);
2636
2637 init_timer(&mp->mib_counters_timer);
2638 mp->mib_counters_timer.data = (unsigned long)mp;
2639 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2640 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2641 add_timer(&mp->mib_counters_timer);
2642
2643 spin_lock_init(&mp->mib_counters_lock);
2644
2645 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2646
2647 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2648
2649 init_timer(&mp->rx_oom);
2650 mp->rx_oom.data = (unsigned long)mp;
2651 mp->rx_oom.function = oom_timer_wrapper;
2652
2653
2654 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2655 BUG_ON(!res);
2656 dev->irq = res->start;
2657
2658 dev->get_stats = mv643xx_eth_get_stats;
2659 dev->hard_start_xmit = mv643xx_eth_xmit;
2660 dev->open = mv643xx_eth_open;
2661 dev->stop = mv643xx_eth_stop;
2662 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2663 dev->set_mac_address = mv643xx_eth_set_mac_address;
2664 dev->do_ioctl = mv643xx_eth_ioctl;
2665 dev->change_mtu = mv643xx_eth_change_mtu;
2666 dev->tx_timeout = mv643xx_eth_tx_timeout;
2667 #ifdef CONFIG_NET_POLL_CONTROLLER
2668 dev->poll_controller = mv643xx_eth_netpoll;
2669 #endif
2670 dev->watchdog_timeo = 2 * HZ;
2671 dev->base_addr = 0;
2672
2673 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2674 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2675
2676 SET_NETDEV_DEV(dev, &pdev->dev);
2677
2678 if (mp->shared->win_protect)
2679 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2680
2681 err = register_netdev(dev);
2682 if (err)
2683 goto out;
2684
2685 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2686 mp->port_num, dev->dev_addr);
2687
2688 if (mp->tx_desc_sram_size > 0)
2689 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2690
2691 return 0;
2692
2693 out:
2694 free_netdev(dev);
2695
2696 return err;
2697 }
2698
2699 static int mv643xx_eth_remove(struct platform_device *pdev)
2700 {
2701 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2702
2703 unregister_netdev(mp->dev);
2704 if (mp->phy != NULL)
2705 phy_detach(mp->phy);
2706 flush_scheduled_work();
2707 free_netdev(mp->dev);
2708
2709 platform_set_drvdata(pdev, NULL);
2710
2711 return 0;
2712 }
2713
2714 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2715 {
2716 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2717
2718 /* Mask all interrupts on ethernet port */
2719 wrl(mp, INT_MASK(mp->port_num), 0);
2720 rdl(mp, INT_MASK(mp->port_num));
2721
2722 if (netif_running(mp->dev))
2723 port_reset(mp);
2724 }
2725
2726 static struct platform_driver mv643xx_eth_driver = {
2727 .probe = mv643xx_eth_probe,
2728 .remove = mv643xx_eth_remove,
2729 .shutdown = mv643xx_eth_shutdown,
2730 .driver = {
2731 .name = MV643XX_ETH_NAME,
2732 .owner = THIS_MODULE,
2733 },
2734 };
2735
2736 static int __init mv643xx_eth_init_module(void)
2737 {
2738 int rc;
2739
2740 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2741 if (!rc) {
2742 rc = platform_driver_register(&mv643xx_eth_driver);
2743 if (rc)
2744 platform_driver_unregister(&mv643xx_eth_shared_driver);
2745 }
2746
2747 return rc;
2748 }
2749 module_init(mv643xx_eth_init_module);
2750
2751 static void __exit mv643xx_eth_cleanup_module(void)
2752 {
2753 platform_driver_unregister(&mv643xx_eth_driver);
2754 platform_driver_unregister(&mv643xx_eth_shared_driver);
2755 }
2756 module_exit(mv643xx_eth_cleanup_module);
2757
2758 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2759 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2760 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2761 MODULE_LICENSE("GPL");
2762 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2763 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree