drivers/staging/et131x/et1310_address_map.h

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_address_map.h - Contains the register mapping for the ET1310
  12  *
  13  *------------------------------------------------------------------------------
  14  *
  15  * SOFTWARE LICENSE
  16  *
  17  * This software is provided subject to the following terms and conditions,
  18  * which you should read carefully before using the software.  Using this
  19  * software indicates your acceptance of these terms and conditions.  If you do
  20  * not agree with these terms and conditions, do not use the software.
  21  *
  22  * Copyright © 2005 Agere Systems Inc.
  23  * All rights reserved.
  24  *
  25  * Redistribution and use in source or binary forms, with or without
  26  * modifications, are permitted provided that the following conditions are met:
  27  *
  28  * . Redistributions of source code must retain the above copyright notice, this
  29  *    list of conditions and the following Disclaimer as comments in the code as
  30  *    well as in the documentation and/or other materials provided with the
  31  *    distribution.
  32  *
  33  * . Redistributions in binary form must reproduce the above copyright notice,
  34  *    this list of conditions and the following Disclaimer in the documentation
  35  *    and/or other materials provided with the distribution.
  36  *
  37  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38  *    may be used to endorse or promote products derived from this software
  39  *    without specific prior written permission.
  40  *
  41  * Disclaimer
  42  *
  43  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54  * DAMAGE.
  55  *
  56  */
  57
  58 #ifndef _ET1310_ADDRESS_MAP_H_
  59 #define _ET1310_ADDRESS_MAP_H_
  60
  61
  62 /* START OF GLOBAL REGISTER ADDRESS MAP */
  63
  64 /*
  65  * 10bit registers
  66  *
  67  * Tx queue start address reg in global address map at address 0x0000
  68  * tx queue end address reg in global address map at address 0x0004
  69  * rx queue start address reg in global address map at address 0x0008
  70  * rx queue end address reg in global address map at address 0x000C
  71  */
  72
  73 /*
  74  * structure for power management control status reg in global address map
  75  * located at address 0x0010
  76  *      jagcore_rx_rdy  bit 9
  77  *      jagcore_tx_rdy  bit 8
  78  *      phy_lped_en     bit 7
  79  *      phy_sw_coma     bit 6
  80  *      rxclk_gate      bit 5
  81  *      txclk_gate      bit 4
  82  *      sysclk_gate     bit 3
  83  *      jagcore_rx_en   bit 2
  84  *      jagcore_tx_en   bit 1
  85  *      gigephy_en      bit 0
  86  */
  87
  88 #define ET_PM_PHY_SW_COMA               0x40
  89 #define ET_PMCSR_INIT                   0x38
  90
  91 /*
  92  * Interrupt status reg at address 0x0018
  93  */
  94
  95 #define ET_INTR_TXDMA_ISR       0x00000008
  96 #define ET_INTR_TXDMA_ERR       0x00000010
  97 #define ET_INTR_RXDMA_XFR_DONE  0x00000020
  98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
  99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
 100 #define ET_INTR_RXDMA_STAT_LOW  0x00000100
 101 #define ET_INTR_RXDMA_ERR       0x00000200
 102 #define ET_INTR_WATCHDOG        0x00004000
 103 #define ET_INTR_WOL             0x00008000
 104 #define ET_INTR_PHY             0x00010000
 105 #define ET_INTR_TXMAC           0x00020000
 106 #define ET_INTR_RXMAC           0x00040000
 107 #define ET_INTR_MAC_STAT        0x00080000
 108 #define ET_INTR_SLV_TIMEOUT     0x00100000
 109
 110 /*
 111  * Interrupt mask register at address 0x001C
 112  * Interrupt alias clear mask reg at address 0x0020
 113  * Interrupt status alias reg at address 0x0024
 114  *
 115  * Same masks as above
 116  */
 117
 118 /*
 119  * Software reset reg at address 0x0028
 120  * 0:   txdma_sw_reset
 121  * 1:   rxdma_sw_reset
 122  * 2:   txmac_sw_reset
 123  * 3:   rxmac_sw_reset
 124  * 4:   mac_sw_reset
 125  * 5:   mac_stat_sw_reset
 126  * 6:   mmc_sw_reset
 127  *31:   selfclr_disable
 128  */
 129
 130 /*
 131  * SLV Timer reg at address 0x002C (low 24 bits)
 132  */
 133
 134 /*
 135  * MSI Configuration reg at address 0x0030
 136  */
 137
 138 #define ET_MSI_VECTOR   0x0000001F
 139 #define ET_MSI_TC       0x00070000
 140
 141 /*
 142  * Loopback reg located at address 0x0034
 143  */
 144
 145 #define ET_LOOP_MAC     0x00000001
 146 #define ET_LOOP_DMA     0x00000002
 147
 148 /*
 149  * GLOBAL Module of JAGCore Address Mapping
 150  * Located at address 0x0000
 151  */
 152 struct global_regs {                    /* Location: */
 153         u32 txq_start_addr;                     /*  0x0000 */
 154         u32 txq_end_addr;                       /*  0x0004 */
 155         u32 rxq_start_addr;                     /*  0x0008 */
 156         u32 rxq_end_addr;                       /*  0x000C */
 157         u32 pm_csr;                             /*  0x0010 */
 158         u32 unused;                             /*  0x0014 */
 159         u32 int_status;                         /*  0x0018 */
 160         u32 int_mask;                           /*  0x001C */
 161         u32 int_alias_clr_en;                   /*  0x0020 */
 162         u32 int_status_alias;                   /*  0x0024 */
 163         u32 sw_reset;                           /*  0x0028 */
 164         u32 slv_timer;                          /*  0x002C */
 165         u32 msi_config;                         /*  0x0030 */
 166         u32 loopback;                   /*  0x0034 */
 167         u32 watchdog_timer;                     /*  0x0038 */
 168 };
 169
 170
 171 /* START OF TXDMA REGISTER ADDRESS MAP */
 172
 173 /*
 174  * txdma control status reg at address 0x1000
 175  */
 176
 177 #define ET_TXDMA_CSR_HALT       0x00000001
 178 #define ET_TXDMA_DROP_TLP       0x00000002
 179 #define ET_TXDMA_CACHE_THRS     0x000000F0
 180 #define ET_TXDMA_CACHE_SHIFT    4
 181 #define ET_TXDMA_SNGL_EPKT      0x00000100
 182 #define ET_TXDMA_CLASS          0x00001E00
 183
 184 /*
 185  * structure for txdma packet ring base address hi reg in txdma address map
 186  * located at address 0x1004
 187  * Defined earlier (u32)
 188  */
 189
 190 /*
 191  * structure for txdma packet ring base address low reg in txdma address map
 192  * located at address 0x1008
 193  * Defined earlier (u32)
 194  */
 195
 196 /*
 197  * structure for txdma packet ring number of descriptor reg in txdma address
 198  * map.  Located at address 0x100C
 199  *
 200  * 31-10: unused
 201  * 9-0: pr ndes
 202  */
 203
 204 #define ET_DMA12_MASK           0x0FFF  /* 12 bit mask for DMA12W types */
 205 #define ET_DMA12_WRAP           0x1000
 206 #define ET_DMA10_MASK           0x03FF  /* 10 bit mask for DMA10W types */
 207 #define ET_DMA10_WRAP           0x0400
 208 #define ET_DMA4_MASK            0x000F  /* 4 bit mask for DMA4W types */
 209 #define ET_DMA4_WRAP            0x0010
 210
 211 #define INDEX12(x)      ((x) & ET_DMA12_MASK)
 212 #define INDEX10(x)      ((x) & ET_DMA10_MASK)
 213 #define INDEX4(x)       ((x) & ET_DMA4_MASK)
 214
 215 extern inline void add_10bit(u32 *v, int n)
 216 {
 217         *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
 218 }
 219
 220 extern inline void add_12bit(u32 *v, int n)
 221 {
 222         *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
 223 }
 224
 225 /*
 226  * 10bit DMA with wrap
 227  * txdma tx queue write address reg in txdma address map at 0x1010
 228  * txdma tx queue write address external reg in txdma address map at 0x1014
 229  * txdma tx queue read address reg in txdma address map at 0x1018
 230  *
 231  * u32
 232  * txdma status writeback address hi reg in txdma address map at0x101C
 233  * txdma status writeback address lo reg in txdma address map at 0x1020
 234  *
 235  * 10bit DMA with wrap
 236  * txdma service request reg in txdma address map at 0x1024
 237  * structure for txdma service complete reg in txdma address map at 0x1028
 238  *
 239  * 4bit DMA with wrap
 240  * txdma tx descriptor cache read index reg in txdma address map at 0x102C
 241  * txdma tx descriptor cache write index reg in txdma address map at 0x1030
 242  *
 243  * txdma error reg in txdma address map at address 0x1034
 244  * 0: PyldResend
 245  * 1: PyldRewind
 246  * 4: DescrResend
 247  * 5: DescrRewind
 248  * 8: WrbkResend
 249  * 9: WrbkRewind
 250  */
 251
 252 /*
 253  * Tx DMA Module of JAGCore Address Mapping
 254  * Located at address 0x1000
 255  */
 256 struct txdma_regs {                     /* Location: */
 257         u32 csr;                        /*  0x1000 */
 258         u32 pr_base_hi;                 /*  0x1004 */
 259         u32 pr_base_lo;                 /*  0x1008 */
 260         u32 pr_num_des;                 /*  0x100C */
 261         u32 txq_wr_addr;                /*  0x1010 */
 262         u32 txq_wr_addr_ext;            /*  0x1014 */
 263         u32 txq_rd_addr;                /*  0x1018 */
 264         u32 dma_wb_base_hi;             /*  0x101C */
 265         u32 dma_wb_base_lo;             /*  0x1020 */
 266         u32 service_request;            /*  0x1024 */
 267         u32 service_complete;           /*  0x1028 */
 268         u32 cache_rd_index;             /*  0x102C */
 269         u32 cache_wr_index;             /*  0x1030 */
 270         u32 TxDmaError;                 /*  0x1034 */
 271         u32 DescAbortCount;             /*  0x1038 */
 272         u32 PayloadAbortCnt;            /*  0x103c */
 273         u32 WriteBackAbortCnt;          /*  0x1040 */
 274         u32 DescTimeoutCnt;             /*  0x1044 */
 275         u32 PayloadTimeoutCnt;          /*  0x1048 */
 276         u32 WriteBackTimeoutCnt;        /*  0x104c */
 277         u32 DescErrorCount;             /*  0x1050 */
 278         u32 PayloadErrorCnt;            /*  0x1054 */
 279         u32 WriteBackErrorCnt;          /*  0x1058 */
 280         u32 DroppedTLPCount;            /*  0x105c */
 281         u32 NewServiceComplete;         /*  0x1060 */
 282         u32 EthernetPacketCount;        /*  0x1064 */
 283 };
 284
 285 /* END OF TXDMA REGISTER ADDRESS MAP */
 286
 287
 288 /* START OF RXDMA REGISTER ADDRESS MAP */
 289
 290 /*
 291  * structure for control status reg in rxdma address map
 292  * Located at address 0x2000
 293  *
 294  * CSR
 295  * 0: halt
 296  * 1-3: tc
 297  * 4: fbr_big_endian
 298  * 5: psr_big_endian
 299  * 6: pkt_big_endian
 300  * 7: dma_big_endian
 301  * 8-9: fbr0_size
 302  * 10: fbr0_enable
 303  * 11-12: fbr1_size
 304  * 13: fbr1_enable
 305  * 14: unused
 306  * 15: pkt_drop_disable
 307  * 16: pkt_done_flush
 308  * 17: halt_status
 309  * 18-31: unused
 310  */
 311
 312
 313 /*
 314  * structure for dma writeback lo reg in rxdma address map
 315  * located at address 0x2004
 316  * Defined earlier (u32)
 317  */
 318
 319 /*
 320  * structure for dma writeback hi reg in rxdma address map
 321  * located at address 0x2008
 322  * Defined earlier (u32)
 323  */
 324
 325 /*
 326  * structure for number of packets done reg in rxdma address map
 327  * located at address 0x200C
 328  *
 329  * 31-8: unused
 330  * 7-0: num done
 331  */
 332
 333 /*
 334  * structure for max packet time reg in rxdma address map
 335  * located at address 0x2010
 336  *
 337  * 31-18: unused
 338  * 17-0: time done
 339  */
 340
 341 /*
 342  * structure for rx queue read address reg in rxdma address map
 343  * located at address 0x2014
 344  * Defined earlier (u32)
 345  */
 346
 347 /*
 348  * structure for rx queue read address external reg in rxdma address map
 349  * located at address 0x2018
 350  * Defined earlier (u32)
 351  */
 352
 353 /*
 354  * structure for rx queue write address reg in rxdma address map
 355  * located at address 0x201C
 356  * Defined earlier (u32)
 357  */
 358
 359 /*
 360  * structure for packet status ring base address lo reg in rxdma address map
 361  * located at address 0x2020
 362  * Defined earlier (u32)
 363  */
 364
 365 /*
 366  * structure for packet status ring base address hi reg in rxdma address map
 367  * located at address 0x2024
 368  * Defined earlier (u32)
 369  */
 370
 371 /*
 372  * structure for packet status ring number of descriptors reg in rxdma address
 373  * map.  Located at address 0x2028
 374  *
 375  * 31-12: unused
 376  * 11-0: psr ndes
 377  */
 378
 379 /*
 380  * structure for packet status ring available offset reg in rxdma address map
 381  * located at address 0x202C
 382  *
 383  * 31-13: unused
 384  * 12: psr avail wrap
 385  * 11-0: psr avail
 386  */
 387
 388 /*
 389  * structure for packet status ring full offset reg in rxdma address map
 390  * located at address 0x2030
 391  *
 392  * 31-13: unused
 393  * 12: psr full wrap
 394  * 11-0: psr full
 395  */
 396
 397 /*
 398  * structure for packet status ring access index reg in rxdma address map
 399  * located at address 0x2034
 400  *
 401  * 31-5: unused
 402  * 4-0: psr_ai
 403  */
 404
 405 /*
 406  * structure for packet status ring minimum descriptors reg in rxdma address
 407  * map.  Located at address 0x2038
 408  *
 409  * 31-12: unused
 410  * 11-0: psr_min
 411  */
 412
 413 /*
 414  * structure for free buffer ring base lo address reg in rxdma address map
 415  * located at address 0x203C
 416  * Defined earlier (u32)
 417  */
 418
 419 /*
 420  * structure for free buffer ring base hi address reg in rxdma address map
 421  * located at address 0x2040
 422  * Defined earlier (u32)
 423  */
 424
 425 /*
 426  * structure for free buffer ring number of descriptors reg in rxdma address
 427  * map.  Located at address 0x2044
 428  *
 429  * 31-10: unused
 430  * 9-0: fbr ndesc
 431  */
 432
 433 /*
 434  * structure for free buffer ring 0 available offset reg in rxdma address map
 435  * located at address 0x2048
 436  * Defined earlier (u32)
 437  */
 438
 439 /*
 440  * structure for free buffer ring 0 full offset reg in rxdma address map
 441  * located at address 0x204C
 442  * Defined earlier (u32)
 443  */
 444
 445 /*
 446  * structure for free buffer cache 0 full offset reg in rxdma address map
 447  * located at address 0x2050
 448  *
 449  * 31-5: unused
 450  * 4-0: fbc rdi
 451  */
 452
 453 /*
 454  * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
 455  * located at address 0x2054
 456  *
 457  * 31-10: unused
 458  * 9-0: fbr min
 459  */
 460
 461 /*
 462  * structure for free buffer ring 1 base address lo reg in rxdma address map
 463  * located at address 0x2058 - 0x205C
 464  * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
 465  */
 466
 467 /*
 468  * structure for free buffer ring 1 number of descriptors reg in rxdma address
 469  * map.  Located at address 0x2060
 470  * Defined earlier (RXDMA_FBR_NUM_DES_t)
 471  */
 472
 473 /*
 474  * structure for free buffer ring 1 available offset reg in rxdma address map
 475  * located at address 0x2064
 476  * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
 477  */
 478
 479 /*
 480  * structure for free buffer ring 1 full offset reg in rxdma address map
 481  * located at address 0x2068
 482  * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
 483  */
 484
 485 /*
 486  * structure for free buffer cache 1 read index reg in rxdma address map
 487  * located at address 0x206C
 488  * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
 489  */
 490
 491 /*
 492  * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
 493  * located at address 0x2070
 494  * Defined Earlier (RXDMA_FBR_MIN_DES_t)
 495  */
 496
 497 /*
 498  * Rx DMA Module of JAGCore Address Mapping
 499  * Located at address 0x2000
 500  */
 501 struct rxdma_regs {                                     /* Location: */
 502         u32 csr;                                        /*  0x2000 */
 503         u32 dma_wb_base_lo;                             /*  0x2004 */
 504         u32 dma_wb_base_hi;                             /*  0x2008 */
 505         u32 num_pkt_done;                               /*  0x200C */
 506         u32 max_pkt_time;                               /*  0x2010 */
 507         u32 rxq_rd_addr;                                /*  0x2014 */
 508         u32 rxq_rd_addr_ext;                            /*  0x2018 */
 509         u32 rxq_wr_addr;                                /*  0x201C */
 510         u32 psr_base_lo;                                /*  0x2020 */
 511         u32 psr_base_hi;                                /*  0x2024 */
 512         u32 psr_num_des;                                /*  0x2028 */
 513         u32 psr_avail_offset;                           /*  0x202C */
 514         u32 psr_full_offset;                            /*  0x2030 */
 515         u32 psr_access_index;                           /*  0x2034 */
 516         u32 psr_min_des;                                /*  0x2038 */
 517         u32 fbr0_base_lo;                               /*  0x203C */
 518         u32 fbr0_base_hi;                               /*  0x2040 */
 519         u32 fbr0_num_des;                               /*  0x2044 */
 520         u32 fbr0_avail_offset;                          /*  0x2048 */
 521         u32 fbr0_full_offset;                           /*  0x204C */
 522         u32 fbr0_rd_index;                              /*  0x2050 */
 523         u32 fbr0_min_des;                               /*  0x2054 */
 524         u32 fbr1_base_lo;                               /*  0x2058 */
 525         u32 fbr1_base_hi;                               /*  0x205C */
 526         u32 fbr1_num_des;                               /*  0x2060 */
 527         u32 fbr1_avail_offset;                          /*  0x2064 */
 528         u32 fbr1_full_offset;                           /*  0x2068 */
 529         u32 fbr1_rd_index;                              /*  0x206C */
 530         u32 fbr1_min_des;                               /*  0x2070 */
 531 };
 532
 533 /* END OF RXDMA REGISTER ADDRESS MAP */
 534
 535
 536 /* START OF TXMAC REGISTER ADDRESS MAP */
 537
 538 /*
 539  * structure for control reg in txmac address map
 540  * located at address 0x3000
 541  *
 542  * bits
 543  * 31-8: unused
 544  * 7: cklseg_disable
 545  * 6: ckbcnt_disable
 546  * 5: cksegnum
 547  * 4: async_disable
 548  * 3: fc_disable
 549  * 2: mcif_disable
 550  * 1: mif_disable
 551  * 0: txmac_en
 552  */
 553
 554 /*
 555  * structure for shadow pointer reg in txmac address map
 556  * located at address 0x3004
 557  * 31-27: reserved
 558  * 26-16: txq rd ptr
 559  * 15-11: reserved
 560  * 10-0: txq wr ptr
 561  */
 562
 563 /*
 564  * structure for error count reg in txmac address map
 565  * located at address 0x3008
 566  *
 567  * 31-12: unused
 568  * 11-8: reserved
 569  * 7-4: txq_underrun
 570  * 3-0: fifo_underrun
 571  */
 572
 573 /*
 574  * structure for max fill reg in txmac address map
 575  * located at address 0x300C
 576  * 31-12: unused
 577  * 11-0: max fill
 578  */
 579
 580 /*
 581  * structure for cf parameter reg in txmac address map
 582  * located at address 0x3010
 583  * 31-16: cfep
 584  * 15-0: cfpt
 585  */
 586
 587 /*
 588  * structure for tx test reg in txmac address map
 589  * located at address 0x3014
 590  * 31-17: unused
 591  * 16: reserved1
 592  * 15: txtest_en
 593  * 14-11: unused
 594  * 10-0: txq test pointer
 595  */
 596
 597 /*
 598  * structure for error reg in txmac address map
 599  * located at address 0x3018
 600  *
 601  * 31-9: unused
 602  * 8: fifo_underrun
 603  * 7-6: unused
 604  * 5: ctrl2_err
 605  * 4: txq_underrun
 606  * 3: bcnt_err
 607  * 2: lseg_err
 608  * 1: segnum_err
 609  * 0: seg0_err
 610  */
 611
 612 /*
 613  * structure for error interrupt reg in txmac address map
 614  * located at address 0x301C
 615  *
 616  * 31-9: unused
 617  * 8: fifo_underrun
 618  * 7-6: unused
 619  * 5: ctrl2_err
 620  * 4: txq_underrun
 621  * 3: bcnt_err
 622  * 2: lseg_err
 623  * 1: segnum_err
 624  * 0: seg0_err
 625  */
 626
 627 /*
 628  * structure for error interrupt reg in txmac address map
 629  * located at address 0x3020
 630  *
 631  * 31-2: unused
 632  * 1: bp_req
 633  * 0: bp_xonxoff
 634  */
 635
 636 /*
 637  * Tx MAC Module of JAGCore Address Mapping
 638  */
 639 struct txmac_regs {                     /* Location: */
 640         u32 ctl;                        /*  0x3000 */
 641         u32 shadow_ptr;                 /*  0x3004 */
 642         u32 err_cnt;                    /*  0x3008 */
 643         u32 max_fill;                   /*  0x300C */
 644         u32 cf_param;                   /*  0x3010 */
 645         u32 tx_test;                    /*  0x3014 */
 646         u32 err;                        /*  0x3018 */
 647         u32 err_int;                    /*  0x301C */
 648         u32 bp_ctrl;                    /*  0x3020 */
 649 };
 650
 651 /* END OF TXMAC REGISTER ADDRESS MAP */
 652
 653 /* START OF RXMAC REGISTER ADDRESS MAP */
 654
 655 /*
 656  * structure for rxmac control reg in rxmac address map
 657  * located at address 0x4000
 658  *
 659  * 31-7: reserved
 660  * 6: rxmac_int_disable
 661  * 5: async_disable
 662  * 4: mif_disable
 663  * 3: wol_disable
 664  * 2: pkt_filter_disable
 665  * 1: mcif_disable
 666  * 0: rxmac_en
 667  */
 668
 669 /*
 670  * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
 671  * located at address 0x4004
 672  * 31-16: crc
 673  * 15-12: reserved
 674  * 11: ignore_pp
 675  * 10: ignore_mp
 676  * 9: clr_intr
 677  * 8: ignore_link_chg
 678  * 7: ignore_uni
 679  * 6: ignore_multi
 680  * 5: ignore_broad
 681  * 4-0: valid_crc 4-0
 682  */
 683
 684 /*
 685  * structure for CRC 1 and CRC 2 reg in rxmac address map
 686  * located at address 0x4008
 687  *
 688  * 31-16: crc2
 689  * 15-0: crc1
 690  */
 691
 692 /*
 693  * structure for CRC 3 and CRC 4 reg in rxmac address map
 694  * located at address 0x400C
 695  *
 696  * 31-16: crc4
 697  * 15-0: crc3
 698  */
 699
 700 /*
 701  * structure for Wake On Lan Source Address Lo reg in rxmac address map
 702  * located at address 0x4010
 703  *
 704  * 31-24: sa3
 705  * 23-16: sa4
 706  * 15-8: sa5
 707  * 7-0: sa6
 708  */
 709
 710 #define ET_WOL_LO_SA3_SHIFT 24
 711 #define ET_WOL_LO_SA4_SHIFT 16
 712 #define ET_WOL_LO_SA5_SHIFT 8
 713
 714 /*
 715  * structure for Wake On Lan Source Address Hi reg in rxmac address map
 716  * located at address 0x4014
 717  *
 718  * 31-16: reserved
 719  * 15-8: sa1
 720  * 7-0: sa2
 721  */
 722
 723 #define ET_WOL_HI_SA1_SHIFT 8
 724
 725 /*
 726  * structure for Wake On Lan mask reg in rxmac address map
 727  * located at address 0x4018 - 0x4064
 728  * Defined earlier (u32)
 729  */
 730
 731 /*
 732  * structure for Unicast Paket Filter Address 1 reg in rxmac address map
 733  * located at address 0x4068
 734  *
 735  * 31-24: addr1_3
 736  * 23-16: addr1_4
 737  * 15-8: addr1_5
 738  * 7-0: addr1_6
 739  */
 740
 741 #define ET_UNI_PF_ADDR1_3_SHIFT 24
 742 #define ET_UNI_PF_ADDR1_4_SHIFT 16
 743 #define ET_UNI_PF_ADDR1_5_SHIFT 8
 744
 745 /*
 746  * structure for Unicast Paket Filter Address 2 reg in rxmac address map
 747  * located at address 0x406C
 748  *
 749  * 31-24: addr2_3
 750  * 23-16: addr2_4
 751  * 15-8: addr2_5
 752  * 7-0: addr2_6
 753  */
 754
 755 #define ET_UNI_PF_ADDR2_3_SHIFT 24
 756 #define ET_UNI_PF_ADDR2_4_SHIFT 16
 757 #define ET_UNI_PF_ADDR2_5_SHIFT 8
 758
 759 /*
 760  * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
 761  * located at address 0x4070
 762  *
 763  * 31-24: addr2_1
 764  * 23-16: addr2_2
 765  * 15-8: addr1_1
 766  * 7-0: addr1_2
 767  */
 768
 769 #define ET_UNI_PF_ADDR2_1_SHIFT 24
 770 #define ET_UNI_PF_ADDR2_2_SHIFT 16
 771 #define ET_UNI_PF_ADDR1_1_SHIFT 8
 772
 773
 774 /*
 775  * structure for Multicast Hash reg in rxmac address map
 776  * located at address 0x4074 - 0x4080
 777  * Defined earlier (u32)
 778  */
 779
 780 /*
 781  * structure for Packet Filter Control reg in rxmac address map
 782  * located at address 0x4084
 783  *
 784  * 31-23: unused
 785  * 22-16: min_pkt_size
 786  * 15-4: unused
 787  * 3: filter_frag_en
 788  * 2: filter_uni_en
 789  * 1: filter_multi_en
 790  * 0: filter_broad_en
 791  */
 792
 793 /*
 794  * structure for Memory Controller Interface Control Max Segment reg in rxmac
 795  * address map.  Located at address 0x4088
 796  *
 797  * 31-10: reserved
 798  * 9-2: max_size
 799  * 1: fc_en
 800  * 0: seg_en
 801  */
 802
 803 /*
 804  * structure for Memory Controller Interface Water Mark reg in rxmac address
 805  * map.  Located at address 0x408C
 806  *
 807  * 31-26: unused
 808  * 25-16: mark_hi
 809  * 15-10: unused
 810  * 9-0: mark_lo
 811  */
 812
 813 /*
 814  * structure for Rx Queue Dialog reg in rxmac address map.
 815  * located at address 0x4090
 816  *
 817  * 31-26: reserved
 818  * 25-16: rd_ptr
 819  * 15-10: reserved
 820  * 9-0: wr_ptr
 821  */
 822
 823 /*
 824  * structure for space available reg in rxmac address map.
 825  * located at address 0x4094
 826  *
 827  * 31-17: reserved
 828  * 16: space_avail_en
 829  * 15-10: reserved
 830  * 9-0: space_avail
 831  */
 832
 833 /*
 834  * structure for management interface reg in rxmac address map.
 835  * located at address 0x4098
 836  *
 837  * 31-18: reserved
 838  * 17: drop_pkt_en
 839  * 16-0: drop_pkt_mask
 840  */
 841
 842 /*
 843  * structure for Error reg in rxmac address map.
 844  * located at address 0x409C
 845  *
 846  * 31-4: unused
 847  * 3: mif
 848  * 2: async
 849  * 1: pkt_filter
 850  * 0: mcif
 851  */
 852
 853 /*
 854  * Rx MAC Module of JAGCore Address Mapping
 855  */
 856 struct rxmac_regs {                                     /* Location: */
 857         u32 ctrl;                                       /*  0x4000 */
 858         u32 crc0;                                       /*  0x4004 */
 859         u32 crc12;                                      /*  0x4008 */
 860         u32 crc34;                                      /*  0x400C */
 861         u32 sa_lo;                                      /*  0x4010 */
 862         u32 sa_hi;                                      /*  0x4014 */
 863         u32 mask0_word0;                                /*  0x4018 */
 864         u32 mask0_word1;                                /*  0x401C */
 865         u32 mask0_word2;                                /*  0x4020 */
 866         u32 mask0_word3;                                /*  0x4024 */
 867         u32 mask1_word0;                                /*  0x4028 */
 868         u32 mask1_word1;                                /*  0x402C */
 869         u32 mask1_word2;                                /*  0x4030 */
 870         u32 mask1_word3;                                /*  0x4034 */
 871         u32 mask2_word0;                                /*  0x4038 */
 872         u32 mask2_word1;                                /*  0x403C */
 873         u32 mask2_word2;                                /*  0x4040 */
 874         u32 mask2_word3;                                /*  0x4044 */
 875         u32 mask3_word0;                                /*  0x4048 */
 876         u32 mask3_word1;                                /*  0x404C */
 877         u32 mask3_word2;                                /*  0x4050 */
 878         u32 mask3_word3;                                /*  0x4054 */
 879         u32 mask4_word0;                                /*  0x4058 */
 880         u32 mask4_word1;                                /*  0x405C */
 881         u32 mask4_word2;                                /*  0x4060 */
 882         u32 mask4_word3;                                /*  0x4064 */
 883         u32 uni_pf_addr1;                               /*  0x4068 */
 884         u32 uni_pf_addr2;                               /*  0x406C */
 885         u32 uni_pf_addr3;                               /*  0x4070 */
 886         u32 multi_hash1;                                /*  0x4074 */
 887         u32 multi_hash2;                                /*  0x4078 */
 888         u32 multi_hash3;                                /*  0x407C */
 889         u32 multi_hash4;                                /*  0x4080 */
 890         u32 pf_ctrl;                                    /*  0x4084 */
 891         u32 mcif_ctrl_max_seg;                          /*  0x4088 */
 892         u32 mcif_water_mark;                            /*  0x408C */
 893         u32 rxq_diag;                                   /*  0x4090 */
 894         u32 space_avail;                                /*  0x4094 */
 895
 896         u32 mif_ctrl;                                   /*  0x4098 */
 897         u32 err_reg;                                    /*  0x409C */
 898 };
 899
 900 /* END OF RXMAC REGISTER ADDRESS MAP */
 901
 902
 903 /* START OF MAC REGISTER ADDRESS MAP */
 904
 905 /*
 906  * structure for configuration #1 reg in mac address map.
 907  * located at address 0x5000
 908  *
 909  * 31: soft reset
 910  * 30: sim reset
 911  * 29-20: reserved
 912  * 19: reset rx mc
 913  * 18: reset tx mc
 914  * 17: reset rx func
 915  * 16: reset tx fnc
 916  * 15-9: reserved
 917  * 8: loopback
 918  * 7-6: reserved
 919  * 5: rx flow
 920  * 4: tx flow
 921  * 3: syncd rx en
 922  * 2: rx enable
 923  * 1: syncd tx en
 924  * 0: tx enable
 925  */
 926
 927 #define CFG1_LOOPBACK   0x00000100
 928 #define CFG1_RX_FLOW    0x00000020
 929 #define CFG1_TX_FLOW    0x00000010
 930 #define CFG1_RX_ENABLE  0x00000004
 931 #define CFG1_TX_ENABLE  0x00000001
 932 #define CFG1_WAIT       0x0000000A      /* RX & TX syncd */
 933
 934 /*
 935  * structure for configuration #2 reg in mac address map.
 936  * located at address 0x5004
 937  * 31-16: reserved
 938  * 15-12: preamble
 939  * 11-10: reserved
 940  * 9-8: if mode
 941  * 7-6: reserved
 942  * 5: huge frame
 943  * 4: length check
 944  * 3: undefined
 945  * 2: pad crc
 946  * 1: crc enable
 947  * 0: full duplex
 948  */
 949
 950
 951 /*
 952  * structure for Interpacket gap reg in mac address map.
 953  * located at address 0x5008
 954  *
 955  * 31: reserved
 956  * 30-24: non B2B ipg 1
 957  * 23: undefined
 958  * 22-16: non B2B ipg 2
 959  * 15-8: Min ifg enforce
 960  * 7-0: B2B ipg
 961  *
 962  * structure for half duplex reg in mac address map.
 963  * located at address 0x500C
 964  * 31-24: reserved
 965  * 23-20: Alt BEB trunc
 966  * 19: Alt BEB enable
 967  * 18: BP no backoff
 968  * 17: no backoff
 969  * 16: excess defer
 970  * 15-12: re-xmit max
 971  * 11-10: reserved
 972  * 9-0: collision window
 973  */
 974
 975 /*
 976  * structure for Maximum Frame Length reg in mac address map.
 977  * located at address 0x5010: bits 0-15 hold the length.
 978  */
 979
 980 /*
 981  * structure for Reserve 1 reg in mac address map.
 982  * located at address 0x5014 - 0x5018
 983  * Defined earlier (u32)
 984  */
 985
 986 /*
 987  * structure for Test reg in mac address map.
 988  * located at address 0x501C
 989  * test: bits 0-2, rest unused
 990  */
 991
 992 /*
 993  * structure for MII Management Configuration reg in mac address map.
 994  * located at address 0x5020
 995  *
 996  * 31: reset MII mgmt
 997  * 30-6: unused
 998  * 5: scan auto increment
 999  * 4: preamble suppress
1000  * 3: undefined
1001  * 2-0: mgmt clock reset
1002  */
1003
1004 /*
1005  * structure for MII Management Command reg in mac address map.
1006  * located at address 0x5024
1007  * bit 1: scan cycle
1008  * bit 0: read cycle
1009  */
1010
1011 /*
1012  * structure for MII Management Address reg in mac address map.
1013  * located at address 0x5028
1014  * 31-13: reserved
1015  * 12-8: phy addr
1016  * 7-5: reserved
1017  * 4-0: register
1018  */
1019
1020 #define MII_ADDR(phy, reg)      ((phy) << 8 | (reg))
1021
1022 /*
1023  * structure for MII Management Control reg in mac address map.
1024  * located at address 0x502C
1025  * 31-16: reserved
1026  * 15-0: phy control
1027  */
1028
1029 /*
1030  * structure for MII Management Status reg in mac address map.
1031  * located at address 0x5030
1032  * 31-16: reserved
1033  * 15-0: phy control
1034  */
1035
1036 /*
1037  * structure for MII Management Indicators reg in mac address map.
1038  * located at address 0x5034
1039  * 31-3: reserved
1040  * 2: not valid
1041  * 1: scanning
1042  * 0: busy
1043  */
1044
1045 #define MGMT_BUSY       0x00000001      /* busy */
1046 #define MGMT_WAIT       0x00000005      /* busy | not valid */
1047
1048 /*
1049  * structure for Interface Control reg in mac address map.
1050  * located at address 0x5038
1051  *
1052  * 31: reset if module
1053  * 30-28: reserved
1054  * 27: tbi mode
1055  * 26: ghd mode
1056  * 25: lhd mode
1057  * 24: phy mode
1058  * 23: reset per mii
1059  * 22-17: reserved
1060  * 16: speed
1061  * 15: reset pe100x
1062  * 14-11: reserved
1063  * 10: force quiet
1064  * 9: no cipher
1065  * 8: disable link fail
1066  * 7: reset gpsi
1067  * 6-1: reserved
1068  * 0: enable jabber protection
1069  */
1070
1071 /*
1072  * structure for Interface Status reg in mac address map.
1073  * located at address 0x503C
1074  *
1075  * 31-10: reserved
1076  * 9: excess_defer
1077  * 8: clash
1078  * 7: phy_jabber
1079  * 6: phy_link_ok
1080  * 5: phy_full_duplex
1081  * 4: phy_speed
1082  * 3: pe100x_link_fail
1083  * 2: pe10t_loss_carrier
1084  * 1: pe10t_sqe_error
1085  * 0: pe10t_jabber
1086  */
1087
1088 /*
1089  * structure for Mac Station Address, Part 1 reg in mac address map.
1090  * located at address 0x5040
1091  *
1092  * 31-24: Octet6
1093  * 23-16: Octet5
1094  * 15-8: Octet4
1095  * 7-0: Octet3
1096  */
1097
1098 #define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
1099 #define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
1100 #define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
1101
1102 /*
1103  * structure for Mac Station Address, Part 2 reg in mac address map.
1104  * located at address 0x5044
1105  *
1106  * 31-24: Octet2
1107  * 23-16: Octet1
1108  * 15-0: reserved
1109  */
1110
1111 #define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
1112 #define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
1113
1114 /*
1115  * MAC Module of JAGCore Address Mapping
1116  */
1117 struct mac_regs {                                       /* Location: */
1118         u32 cfg1;                                       /*  0x5000 */
1119         u32 cfg2;                                       /*  0x5004 */
1120         u32 ipg;                                        /*  0x5008 */
1121         u32 hfdp;                                       /*  0x500C */
1122         u32 max_fm_len;                                 /*  0x5010 */
1123         u32 rsv1;                                       /*  0x5014 */
1124         u32 rsv2;                                       /*  0x5018 */
1125         u32 mac_test;                                   /*  0x501C */
1126         u32 mii_mgmt_cfg;                               /*  0x5020 */
1127         u32 mii_mgmt_cmd;                               /*  0x5024 */
1128         u32 mii_mgmt_addr;                              /*  0x5028 */
1129         u32 mii_mgmt_ctrl;                              /*  0x502C */
1130         u32 mii_mgmt_stat;                              /*  0x5030 */
1131         u32 mii_mgmt_indicator;                         /*  0x5034 */
1132         u32 if_ctrl;                                    /*  0x5038 */
1133         u32 if_stat;                                    /*  0x503C */
1134         u32 station_addr_1;                             /*  0x5040 */
1135         u32 station_addr_2;                             /*  0x5044 */
1136 };
1137
1138 /* END OF MAC REGISTER ADDRESS MAP */
1139
1140 /* START OF MAC STAT REGISTER ADDRESS MAP */
1141
1142 /*
1143  * structure for Carry Register One and it's Mask Register reg located in mac
1144  * stat address map address 0x6130 and 0x6138.
1145  *
1146  * 31: tr64
1147  * 30: tr127
1148  * 29: tr255
1149  * 28: tr511
1150  * 27: tr1k
1151  * 26: trmax
1152  * 25: trmgv
1153  * 24-17: unused
1154  * 16: rbyt
1155  * 15: rpkt
1156  * 14: rfcs
1157  * 13: rmca
1158  * 12: rbca
1159  * 11: rxcf
1160  * 10: rxpf
1161  * 9: rxuo
1162  * 8: raln
1163  * 7: rflr
1164  * 6: rcde
1165  * 5: rcse
1166  * 4: rund
1167  * 3: rovr
1168  * 2: rfrg
1169  * 1: rjbr
1170  * 0: rdrp
1171  */
1172
1173 /*
1174  * structure for Carry Register Two Mask Register reg in mac stat address map.
1175  * located at address 0x613C
1176  *
1177  * 31-20: unused
1178  * 19: tjbr
1179  * 18: tfcs
1180  * 17: txcf
1181  * 16: tovr
1182  * 15: tund
1183  * 14: trfg
1184  * 13: tbyt
1185  * 12: tpkt
1186  * 11: tmca
1187  * 10: tbca
1188  * 9: txpf
1189  * 8: tdfr
1190  * 7: tedf
1191  * 6: tscl
1192  * 5: tmcl
1193  * 4: tlcl
1194  * 3: txcl
1195  * 2: tncl
1196  * 1: tpfh
1197  * 0: tdrp
1198  */
1199
1200 /*
1201  * MAC STATS Module of JAGCore Address Mapping
1202  */
1203 struct macstat_regs {                   /* Location: */
1204         u32 pad[32];                    /*  0x6000 - 607C */
1205
1206         /* Tx/Rx 0-64 Byte Frame Counter */
1207         u32 TR64;                       /*  0x6080 */
1208
1209         /* Tx/Rx 65-127 Byte Frame Counter */
1210         u32 TR127;                      /*  0x6084 */
1211
1212         /* Tx/Rx 128-255 Byte Frame Counter */
1213         u32 TR255;                      /*  0x6088 */
1214
1215         /* Tx/Rx 256-511 Byte Frame Counter */
1216         u32 TR511;                      /*  0x608C */
1217
1218         /* Tx/Rx 512-1023 Byte Frame Counter */
1219         u32 TR1K;                       /*  0x6090 */
1220
1221         /* Tx/Rx 1024-1518 Byte Frame Counter */
1222         u32 TRMax;                      /*  0x6094 */
1223
1224         /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1225         u32 TRMgv;                      /*  0x6098 */
1226
1227         /* Rx Byte Counter */
1228         u32 RByt;                       /*  0x609C */
1229
1230         /* Rx Packet Counter */
1231         u32 RPkt;                       /*  0x60A0 */
1232
1233         /* Rx FCS Error Counter */
1234         u32 RFcs;                       /*  0x60A4 */
1235
1236         /* Rx Multicast Packet Counter */
1237         u32 RMca;                       /*  0x60A8 */
1238
1239         /* Rx Broadcast Packet Counter */
1240         u32 RBca;                       /*  0x60AC */
1241
1242         /* Rx Control Frame Packet Counter */
1243         u32 RxCf;                       /*  0x60B0 */
1244
1245         /* Rx Pause Frame Packet Counter */
1246         u32 RxPf;                       /*  0x60B4 */
1247
1248         /* Rx Unknown OP Code Counter */
1249         u32 RxUo;                       /*  0x60B8 */
1250
1251         /* Rx Alignment Error Counter */
1252         u32 RAln;                       /*  0x60BC */
1253
1254         /* Rx Frame Length Error Counter */
1255         u32 RFlr;                       /*  0x60C0 */
1256
1257         /* Rx Code Error Counter */
1258         u32 RCde;                       /*  0x60C4 */
1259
1260         /* Rx Carrier Sense Error Counter */
1261         u32 RCse;                       /*  0x60C8 */
1262
1263         /* Rx Undersize Packet Counter */
1264         u32 RUnd;                       /*  0x60CC */
1265
1266         /* Rx Oversize Packet Counter */
1267         u32 ROvr;                       /*  0x60D0 */
1268
1269         /* Rx Fragment Counter */
1270         u32 RFrg;                       /*  0x60D4 */
1271
1272         /* Rx Jabber Counter */
1273         u32 RJbr;                       /*  0x60D8 */
1274
1275         /* Rx Drop */
1276         u32 RDrp;                       /*  0x60DC */
1277
1278         /* Tx Byte Counter */
1279         u32 TByt;                       /*  0x60E0 */
1280
1281         /* Tx Packet Counter */
1282         u32 TPkt;                       /*  0x60E4 */
1283
1284         /* Tx Multicast Packet Counter */
1285         u32 TMca;                       /*  0x60E8 */
1286
1287         /* Tx Broadcast Packet Counter */
1288         u32 TBca;                       /*  0x60EC */
1289
1290         /* Tx Pause Control Frame Counter */
1291         u32 TxPf;                       /*  0x60F0 */
1292
1293         /* Tx Deferral Packet Counter */
1294         u32 TDfr;                       /*  0x60F4 */
1295
1296         /* Tx Excessive Deferral Packet Counter */
1297         u32 TEdf;                       /*  0x60F8 */
1298
1299         /* Tx Single Collision Packet Counter */
1300         u32 TScl;                       /*  0x60FC */
1301
1302         /* Tx Multiple Collision Packet Counter */
1303         u32 TMcl;                       /*  0x6100 */
1304
1305         /* Tx Late Collision Packet Counter */
1306         u32 TLcl;                       /*  0x6104 */
1307
1308         /* Tx Excessive Collision Packet Counter */
1309         u32 TXcl;                       /*  0x6108 */
1310
1311         /* Tx Total Collision Packet Counter */
1312         u32 TNcl;                       /*  0x610C */
1313
1314         /* Tx Pause Frame Honored Counter */
1315         u32 TPfh;                       /*  0x6110 */
1316
1317         /* Tx Drop Frame Counter */
1318         u32 TDrp;                       /*  0x6114 */
1319
1320         /* Tx Jabber Frame Counter */
1321         u32 TJbr;                       /*  0x6118 */
1322
1323         /* Tx FCS Error Counter */
1324         u32 TFcs;                       /*  0x611C */
1325
1326         /* Tx Control Frame Counter */
1327         u32 TxCf;                       /*  0x6120 */
1328
1329         /* Tx Oversize Frame Counter */
1330         u32 TOvr;                       /*  0x6124 */
1331
1332         /* Tx Undersize Frame Counter */
1333         u32 TUnd;                       /*  0x6128 */
1334
1335         /* Tx Fragments Frame Counter */
1336         u32 TFrg;                       /*  0x612C */
1337
1338         /* Carry Register One Register */
1339         u32 Carry1;                     /*  0x6130 */
1340
1341         /* Carry Register Two Register */
1342         u32 Carry2;                     /*  0x6134 */
1343
1344         /* Carry Register One Mask Register */
1345         u32 Carry1M;                    /*  0x6138 */
1346
1347         /* Carry Register Two Mask Register */
1348         u32 Carry2M;                    /*  0x613C */
1349 };
1350
1351 /* END OF MAC STAT REGISTER ADDRESS MAP */
1352
1353
1354 /* START OF MMC REGISTER ADDRESS MAP */
1355
1356 /*
1357  * Main Memory Controller Control reg in mmc address map.
1358  * located at address 0x7000
1359  */
1360
1361 #define ET_MMC_ENABLE           1
1362 #define ET_MMC_ARB_DISABLE      2
1363 #define ET_MMC_RXMAC_DISABLE    4
1364 #define ET_MMC_TXMAC_DISABLE    8
1365 #define ET_MMC_TXDMA_DISABLE    16
1366 #define ET_MMC_RXDMA_DISABLE    32
1367 #define ET_MMC_FORCE_CE         64
1368
1369 /*
1370  * Main Memory Controller Host Memory Access Address reg in mmc
1371  * address map.  Located at address 0x7004. Top 16 bits hold the address bits
1372  */
1373
1374 #define ET_SRAM_REQ_ACCESS      1
1375 #define ET_SRAM_WR_ACCESS       2
1376 #define ET_SRAM_IS_CTRL         4
1377
1378 /*
1379  * structure for Main Memory Controller Host Memory Access Data reg in mmc
1380  * address map.  Located at address 0x7008 - 0x7014
1381  * Defined earlier (u32)
1382  */
1383
1384 /*
1385  * Memory Control Module of JAGCore Address Mapping
1386  */
1387 struct mmc_regs {               /* Location: */
1388         u32 mmc_ctrl;           /*  0x7000 */
1389         u32 sram_access;        /*  0x7004 */
1390         u32 sram_word1;         /*  0x7008 */
1391         u32 sram_word2;         /*  0x700C */
1392         u32 sram_word3;         /*  0x7010 */
1393         u32 sram_word4;         /*  0x7014 */
1394 };
1395
1396 /* END OF MMC REGISTER ADDRESS MAP */
1397
1398
1399 /*
1400  * JAGCore Address Mapping
1401  */
1402 struct address_map {
1403         struct global_regs global;
1404         /* unused section of global address map */
1405         u8 unused_global[4096 - sizeof(struct global_regs)];
1406         struct txdma_regs txdma;
1407         /* unused section of txdma address map */
1408         u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1409         struct rxdma_regs rxdma;
1410         /* unused section of rxdma address map */
1411         u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1412         struct txmac_regs txmac;
1413         /* unused section of txmac address map */
1414         u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1415         struct rxmac_regs rxmac;
1416         /* unused section of rxmac address map */
1417         u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
1418         struct mac_regs mac;
1419         /* unused section of mac address map */
1420         u8 unused_mac[4096 - sizeof(struct mac_regs)];
1421         struct macstat_regs macstat;
1422         /* unused section of mac stat address map */
1423         u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1424         struct mmc_regs mmc;
1425         /* unused section of mmc address map */
1426         u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1427         /* unused section of address map */
1428         u8 unused_[1015808];
1429
1430         u8 unused_exp_rom[4096];        /* MGS-size TBD */
1431         u8 unused__[524288];    /* unused section of address map */
1432 };
1433
1434 #endif /* _ET1310_ADDRESS_MAP_H_ */