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kbuild: call make once for all targets when O=.. is used
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / pci / hda / hda_intel.c
blob92bc8b3fa2a0b7b198f03b8d4c3d53f73b0cd469
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 *
24 * CONTACTS:
25 *
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
29 *
30 * CHANGES:
31 *
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
33 *
34 */
35
36 #include <sound/driver.h>
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
50
51
52 static int index = SNDRV_DEFAULT_IDX1;
53 static char *id = SNDRV_DEFAULT_STR1;
54 static char *model;
55 static int position_fix;
56 static int probe_mask = -1;
57 static int single_cmd;
58 static int enable_msi;
59
60 module_param(index, int, 0444);
61 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
62 module_param(id, charp, 0444);
63 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
64 module_param(model, charp, 0444);
65 MODULE_PARM_DESC(model, "Use the given board model.");
66 module_param(position_fix, int, 0444);
67 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
68 module_param(probe_mask, int, 0444);
69 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
70 module_param(single_cmd, bool, 0444);
71 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only).");
72 module_param(enable_msi, int, 0);
73 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
74
75
76 /* just for backward compatibility */
77 static int enable;
78 module_param(enable, bool, 0444);
79
80 MODULE_LICENSE("GPL");
81 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
82 "{Intel, ICH6M},"
83 "{Intel, ICH7},"
84 "{Intel, ESB2},"
85 "{Intel, ICH8},"
86 "{Intel, ICH9},"
87 "{ATI, SB450},"
88 "{ATI, SB600},"
89 "{ATI, RS600},"
90 "{ATI, RS690},"
91 "{ATI, RS780},"
92 "{ATI, R600},"
93 "{VIA, VT8251},"
94 "{VIA, VT8237A},"
95 "{SiS, SIS966},"
96 "{ULI, M5461}}");
97 MODULE_DESCRIPTION("Intel HDA driver");
98
99 #define SFX "hda-intel: "
100
101 /*
102 * registers
103 */
104 #define ICH6_REG_GCAP 0x00
105 #define ICH6_REG_VMIN 0x02
106 #define ICH6_REG_VMAJ 0x03
107 #define ICH6_REG_OUTPAY 0x04
108 #define ICH6_REG_INPAY 0x06
109 #define ICH6_REG_GCTL 0x08
110 #define ICH6_REG_WAKEEN 0x0c
111 #define ICH6_REG_STATESTS 0x0e
112 #define ICH6_REG_GSTS 0x10
113 #define ICH6_REG_INTCTL 0x20
114 #define ICH6_REG_INTSTS 0x24
115 #define ICH6_REG_WALCLK 0x30
116 #define ICH6_REG_SYNC 0x34
117 #define ICH6_REG_CORBLBASE 0x40
118 #define ICH6_REG_CORBUBASE 0x44
119 #define ICH6_REG_CORBWP 0x48
120 #define ICH6_REG_CORBRP 0x4A
121 #define ICH6_REG_CORBCTL 0x4c
122 #define ICH6_REG_CORBSTS 0x4d
123 #define ICH6_REG_CORBSIZE 0x4e
124
125 #define ICH6_REG_RIRBLBASE 0x50
126 #define ICH6_REG_RIRBUBASE 0x54
127 #define ICH6_REG_RIRBWP 0x58
128 #define ICH6_REG_RINTCNT 0x5a
129 #define ICH6_REG_RIRBCTL 0x5c
130 #define ICH6_REG_RIRBSTS 0x5d
131 #define ICH6_REG_RIRBSIZE 0x5e
132
133 #define ICH6_REG_IC 0x60
134 #define ICH6_REG_IR 0x64
135 #define ICH6_REG_IRS 0x68
136 #define ICH6_IRS_VALID (1<<1)
137 #define ICH6_IRS_BUSY (1<<0)
138
139 #define ICH6_REG_DPLBASE 0x70
140 #define ICH6_REG_DPUBASE 0x74
141 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
142
143 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
144 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
145
146 /* stream register offsets from stream base */
147 #define ICH6_REG_SD_CTL 0x00
148 #define ICH6_REG_SD_STS 0x03
149 #define ICH6_REG_SD_LPIB 0x04
150 #define ICH6_REG_SD_CBL 0x08
151 #define ICH6_REG_SD_LVI 0x0c
152 #define ICH6_REG_SD_FIFOW 0x0e
153 #define ICH6_REG_SD_FIFOSIZE 0x10
154 #define ICH6_REG_SD_FORMAT 0x12
155 #define ICH6_REG_SD_BDLPL 0x18
156 #define ICH6_REG_SD_BDLPU 0x1c
157
158 /* PCI space */
159 #define ICH6_PCIREG_TCSEL 0x44
160
161 /*
162 * other constants
163 */
164
165 /* max number of SDs */
166 /* ICH, ATI and VIA have 4 playback and 4 capture */
167 #define ICH6_CAPTURE_INDEX 0
168 #define ICH6_NUM_CAPTURE 4
169 #define ICH6_PLAYBACK_INDEX 4
170 #define ICH6_NUM_PLAYBACK 4
171
172 /* ULI has 6 playback and 5 capture */
173 #define ULI_CAPTURE_INDEX 0
174 #define ULI_NUM_CAPTURE 5
175 #define ULI_PLAYBACK_INDEX 5
176 #define ULI_NUM_PLAYBACK 6
177
178 /* ATI HDMI has 1 playback and 0 capture */
179 #define ATIHDMI_CAPTURE_INDEX 0
180 #define ATIHDMI_NUM_CAPTURE 0
181 #define ATIHDMI_PLAYBACK_INDEX 0
182 #define ATIHDMI_NUM_PLAYBACK 1
183
184 /* this number is statically defined for simplicity */
185 #define MAX_AZX_DEV 16
186
187 /* max number of fragments - we may use more if allocating more pages for BDL */
188 #define BDL_SIZE PAGE_ALIGN(8192)
189 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
190 /* max buffer size - no h/w limit, you can increase as you like */
191 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
192 /* max number of PCM devics per card */
193 #define AZX_MAX_AUDIO_PCMS 6
194 #define AZX_MAX_MODEM_PCMS 2
195 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
196
197 /* RIRB int mask: overrun[2], response[0] */
198 #define RIRB_INT_RESPONSE 0x01
199 #define RIRB_INT_OVERRUN 0x04
200 #define RIRB_INT_MASK 0x05
201
202 /* STATESTS int mask: SD2,SD1,SD0 */
203 #define AZX_MAX_CODECS 3
204 #define STATESTS_INT_MASK 0x07
205
206 /* SD_CTL bits */
207 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
208 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
209 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
210 #define SD_CTL_STREAM_TAG_SHIFT 20
211
212 /* SD_CTL and SD_STS */
213 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
214 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
215 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
216 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
217
218 /* SD_STS */
219 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
220
221 /* INTCTL and INTSTS */
222 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
223 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
224 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
225
226 /* GCTL unsolicited response enable bit */
227 #define ICH6_GCTL_UREN (1<<8)
228
229 /* GCTL reset bit */
230 #define ICH6_GCTL_RESET (1<<0)
231
232 /* CORB/RIRB control, read/write pointer */
233 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
234 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
235 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
236 /* below are so far hardcoded - should read registers in future */
237 #define ICH6_MAX_CORB_ENTRIES 256
238 #define ICH6_MAX_RIRB_ENTRIES 256
239
240 /* position fix mode */
241 enum {
242 POS_FIX_AUTO,
243 POS_FIX_NONE,
244 POS_FIX_POSBUF,
245 POS_FIX_FIFO,
246 };
247
248 /* Defines for ATI HD Audio support in SB450 south bridge */
249 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
250 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
251
252 /* Defines for Nvidia HDA support */
253 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
254 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
255
256 /*
257 */
258
259 struct azx_dev {
260 u32 *bdl; /* virtual address of the BDL */
261 dma_addr_t bdl_addr; /* physical address of the BDL */
262 u32 *posbuf; /* position buffer pointer */
263
264 unsigned int bufsize; /* size of the play buffer in bytes */
265 unsigned int fragsize; /* size of each period in bytes */
266 unsigned int frags; /* number for period in the play buffer */
267 unsigned int fifo_size; /* FIFO size */
268
269 void __iomem *sd_addr; /* stream descriptor pointer */
270
271 u32 sd_int_sta_mask; /* stream int status mask */
272
273 /* pcm support */
274 struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */
275 unsigned int format_val; /* format value to be set in the controller and the codec */
276 unsigned char stream_tag; /* assigned stream */
277 unsigned char index; /* stream index */
278 /* for sanity check of position buffer */
279 unsigned int period_intr;
280
281 unsigned int opened :1;
282 unsigned int running :1;
283 };
284
285 /* CORB/RIRB */
286 struct azx_rb {
287 u32 *buf; /* CORB/RIRB buffer
288 * Each CORB entry is 4byte, RIRB is 8byte
289 */
290 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
291 /* for RIRB */
292 unsigned short rp, wp; /* read/write pointers */
293 int cmds; /* number of pending requests */
294 u32 res; /* last read value */
295 };
296
297 struct azx {
298 struct snd_card *card;
299 struct pci_dev *pci;
300
301 /* chip type specific */
302 int driver_type;
303 int playback_streams;
304 int playback_index_offset;
305 int capture_streams;
306 int capture_index_offset;
307 int num_streams;
308
309 /* pci resources */
310 unsigned long addr;
311 void __iomem *remap_addr;
312 int irq;
313
314 /* locks */
315 spinlock_t reg_lock;
316 struct mutex open_mutex;
317
318 /* streams (x num_streams) */
319 struct azx_dev *azx_dev;
320
321 /* PCM */
322 unsigned int pcm_devs;
323 struct snd_pcm *pcm[AZX_MAX_PCMS];
324
325 /* HD codec */
326 unsigned short codec_mask;
327 struct hda_bus *bus;
328
329 /* CORB/RIRB */
330 struct azx_rb corb;
331 struct azx_rb rirb;
332
333 /* BDL, CORB/RIRB and position buffers */
334 struct snd_dma_buffer bdl;
335 struct snd_dma_buffer rb;
336 struct snd_dma_buffer posbuf;
337
338 /* flags */
339 int position_fix;
340 unsigned int initialized :1;
341 unsigned int single_cmd :1;
342 unsigned int polling_mode :1;
343 unsigned int msi :1;
344
345 /* for debugging */
346 unsigned int last_cmd; /* last issued command (to sync) */
347 };
348
349 /* driver types */
350 enum {
351 AZX_DRIVER_ICH,
352 AZX_DRIVER_ATI,
353 AZX_DRIVER_ATIHDMI,
354 AZX_DRIVER_VIA,
355 AZX_DRIVER_SIS,
356 AZX_DRIVER_ULI,
357 AZX_DRIVER_NVIDIA,
358 };
359
360 static char *driver_short_names[] __devinitdata = {
361 [AZX_DRIVER_ICH] = "HDA Intel",
362 [AZX_DRIVER_ATI] = "HDA ATI SB",
363 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
364 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
365 [AZX_DRIVER_SIS] = "HDA SIS966",
366 [AZX_DRIVER_ULI] = "HDA ULI M5461",
367 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
368 };
369
370 /*
371 * macros for easy use
372 */
373 #define azx_writel(chip,reg,value) \
374 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
375 #define azx_readl(chip,reg) \
376 readl((chip)->remap_addr + ICH6_REG_##reg)
377 #define azx_writew(chip,reg,value) \
378 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
379 #define azx_readw(chip,reg) \
380 readw((chip)->remap_addr + ICH6_REG_##reg)
381 #define azx_writeb(chip,reg,value) \
382 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
383 #define azx_readb(chip,reg) \
384 readb((chip)->remap_addr + ICH6_REG_##reg)
385
386 #define azx_sd_writel(dev,reg,value) \
387 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
388 #define azx_sd_readl(dev,reg) \
389 readl((dev)->sd_addr + ICH6_REG_##reg)
390 #define azx_sd_writew(dev,reg,value) \
391 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
392 #define azx_sd_readw(dev,reg) \
393 readw((dev)->sd_addr + ICH6_REG_##reg)
394 #define azx_sd_writeb(dev,reg,value) \
395 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
396 #define azx_sd_readb(dev,reg) \
397 readb((dev)->sd_addr + ICH6_REG_##reg)
398
399 /* for pcm support */
400 #define get_azx_dev(substream) (substream->runtime->private_data)
401
402 /* Get the upper 32bit of the given dma_addr_t
403 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
404 */
405 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
406
407 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
408
409 /*
410 * Interface for HD codec
411 */
412
413 /*
414 * CORB / RIRB interface
415 */
416 static int azx_alloc_cmd_io(struct azx *chip)
417 {
418 int err;
419
420 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
421 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
422 PAGE_SIZE, &chip->rb);
423 if (err < 0) {
424 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
425 return err;
426 }
427 return 0;
428 }
429
430 static void azx_init_cmd_io(struct azx *chip)
431 {
432 /* CORB set up */
433 chip->corb.addr = chip->rb.addr;
434 chip->corb.buf = (u32 *)chip->rb.area;
435 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
436 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
437
438 /* set the corb size to 256 entries (ULI requires explicitly) */
439 azx_writeb(chip, CORBSIZE, 0x02);
440 /* set the corb write pointer to 0 */
441 azx_writew(chip, CORBWP, 0);
442 /* reset the corb hw read pointer */
443 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
444 /* enable corb dma */
445 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
446
447 /* RIRB set up */
448 chip->rirb.addr = chip->rb.addr + 2048;
449 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
450 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
451 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
452
453 /* set the rirb size to 256 entries (ULI requires explicitly) */
454 azx_writeb(chip, RIRBSIZE, 0x02);
455 /* reset the rirb hw write pointer */
456 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
457 /* set N=1, get RIRB response interrupt for new entry */
458 azx_writew(chip, RINTCNT, 1);
459 /* enable rirb dma and response irq */
460 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
461 chip->rirb.rp = chip->rirb.cmds = 0;
462 }
463
464 static void azx_free_cmd_io(struct azx *chip)
465 {
466 /* disable ringbuffer DMAs */
467 azx_writeb(chip, RIRBCTL, 0);
468 azx_writeb(chip, CORBCTL, 0);
469 }
470
471 /* send a command */
472 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
473 {
474 struct azx *chip = codec->bus->private_data;
475 unsigned int wp;
476
477 /* add command to corb */
478 wp = azx_readb(chip, CORBWP);
479 wp++;
480 wp %= ICH6_MAX_CORB_ENTRIES;
481
482 spin_lock_irq(&chip->reg_lock);
483 chip->rirb.cmds++;
484 chip->corb.buf[wp] = cpu_to_le32(val);
485 azx_writel(chip, CORBWP, wp);
486 spin_unlock_irq(&chip->reg_lock);
487
488 return 0;
489 }
490
491 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
492
493 /* retrieve RIRB entry - called from interrupt handler */
494 static void azx_update_rirb(struct azx *chip)
495 {
496 unsigned int rp, wp;
497 u32 res, res_ex;
498
499 wp = azx_readb(chip, RIRBWP);
500 if (wp == chip->rirb.wp)
501 return;
502 chip->rirb.wp = wp;
503
504 while (chip->rirb.rp != wp) {
505 chip->rirb.rp++;
506 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
507
508 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
509 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
510 res = le32_to_cpu(chip->rirb.buf[rp]);
511 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
512 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
513 else if (chip->rirb.cmds) {
514 chip->rirb.cmds--;
515 chip->rirb.res = res;
516 }
517 }
518 }
519
520 /* receive a response */
521 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
522 {
523 struct azx *chip = codec->bus->private_data;
524 unsigned long timeout;
525
526 again:
527 timeout = jiffies + msecs_to_jiffies(1000);
528 do {
529 if (chip->polling_mode) {
530 spin_lock_irq(&chip->reg_lock);
531 azx_update_rirb(chip);
532 spin_unlock_irq(&chip->reg_lock);
533 }
534 if (! chip->rirb.cmds)
535 return chip->rirb.res; /* the last value */
536 schedule_timeout(1);
537 } while (time_after_eq(timeout, jiffies));
538
539 if (chip->msi) {
540 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
541 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
542 free_irq(chip->irq, chip);
543 chip->irq = -1;
544 pci_disable_msi(chip->pci);
545 chip->msi = 0;
546 if (azx_acquire_irq(chip, 1) < 0)
547 return -1;
548 goto again;
549 }
550
551 if (!chip->polling_mode) {
552 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
553 "switching to polling mode: last cmd=0x%08x\n",
554 chip->last_cmd);
555 chip->polling_mode = 1;
556 goto again;
557 }
558
559 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
560 "switching to single_cmd mode: last cmd=0x%08x\n",
561 chip->last_cmd);
562 chip->rirb.rp = azx_readb(chip, RIRBWP);
563 chip->rirb.cmds = 0;
564 /* switch to single_cmd mode */
565 chip->single_cmd = 1;
566 azx_free_cmd_io(chip);
567 return -1;
568 }
569
570 /*
571 * Use the single immediate command instead of CORB/RIRB for simplicity
572 *
573 * Note: according to Intel, this is not preferred use. The command was
574 * intended for the BIOS only, and may get confused with unsolicited
575 * responses. So, we shouldn't use it for normal operation from the
576 * driver.
577 * I left the codes, however, for debugging/testing purposes.
578 */
579
580 /* send a command */
581 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
582 {
583 struct azx *chip = codec->bus->private_data;
584 int timeout = 50;
585
586 while (timeout--) {
587 /* check ICB busy bit */
588 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
589 /* Clear IRV valid bit */
590 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
591 azx_writel(chip, IC, val);
592 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
593 return 0;
594 }
595 udelay(1);
596 }
597 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
598 return -EIO;
599 }
600
601 /* receive a response */
602 static unsigned int azx_single_get_response(struct hda_codec *codec)
603 {
604 struct azx *chip = codec->bus->private_data;
605 int timeout = 50;
606
607 while (timeout--) {
608 /* check IRV busy bit */
609 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
610 return azx_readl(chip, IR);
611 udelay(1);
612 }
613 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
614 return (unsigned int)-1;
615 }
616
617 /*
618 * The below are the main callbacks from hda_codec.
619 *
620 * They are just the skeleton to call sub-callbacks according to the
621 * current setting of chip->single_cmd.
622 */
623
624 /* send a command */
625 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
626 int direct, unsigned int verb,
627 unsigned int para)
628 {
629 struct azx *chip = codec->bus->private_data;
630 u32 val;
631
632 val = (u32)(codec->addr & 0x0f) << 28;
633 val |= (u32)direct << 27;
634 val |= (u32)nid << 20;
635 val |= verb << 8;
636 val |= para;
637 chip->last_cmd = val;
638
639 if (chip->single_cmd)
640 return azx_single_send_cmd(codec, val);
641 else
642 return azx_corb_send_cmd(codec, val);
643 }
644
645 /* get a response */
646 static unsigned int azx_get_response(struct hda_codec *codec)
647 {
648 struct azx *chip = codec->bus->private_data;
649 if (chip->single_cmd)
650 return azx_single_get_response(codec);
651 else
652 return azx_rirb_get_response(codec);
653 }
654
655
656 /* reset codec link */
657 static int azx_reset(struct azx *chip)
658 {
659 int count;
660
661 /* reset controller */
662 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
663
664 count = 50;
665 while (azx_readb(chip, GCTL) && --count)
666 msleep(1);
667
668 /* delay for >= 100us for codec PLL to settle per spec
669 * Rev 0.9 section 5.5.1
670 */
671 msleep(1);
672
673 /* Bring controller out of reset */
674 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
675
676 count = 50;
677 while (!azx_readb(chip, GCTL) && --count)
678 msleep(1);
679
680 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
681 msleep(1);
682
683 /* check to see if controller is ready */
684 if (!azx_readb(chip, GCTL)) {
685 snd_printd("azx_reset: controller not ready!\n");
686 return -EBUSY;
687 }
688
689 /* Accept unsolicited responses */
690 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
691
692 /* detect codecs */
693 if (!chip->codec_mask) {
694 chip->codec_mask = azx_readw(chip, STATESTS);
695 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
696 }
697
698 return 0;
699 }
700
701
702 /*
703 * Lowlevel interface
704 */
705
706 /* enable interrupts */
707 static void azx_int_enable(struct azx *chip)
708 {
709 /* enable controller CIE and GIE */
710 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
711 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
712 }
713
714 /* disable interrupts */
715 static void azx_int_disable(struct azx *chip)
716 {
717 int i;
718
719 /* disable interrupts in stream descriptor */
720 for (i = 0; i < chip->num_streams; i++) {
721 struct azx_dev *azx_dev = &chip->azx_dev[i];
722 azx_sd_writeb(azx_dev, SD_CTL,
723 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
724 }
725
726 /* disable SIE for all streams */
727 azx_writeb(chip, INTCTL, 0);
728
729 /* disable controller CIE and GIE */
730 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
731 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
732 }
733
734 /* clear interrupts */
735 static void azx_int_clear(struct azx *chip)
736 {
737 int i;
738
739 /* clear stream status */
740 for (i = 0; i < chip->num_streams; i++) {
741 struct azx_dev *azx_dev = &chip->azx_dev[i];
742 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
743 }
744
745 /* clear STATESTS */
746 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
747
748 /* clear rirb status */
749 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
750
751 /* clear int status */
752 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
753 }
754
755 /* start a stream */
756 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
757 {
758 /* enable SIE */
759 azx_writeb(chip, INTCTL,
760 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
761 /* set DMA start and interrupt mask */
762 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
763 SD_CTL_DMA_START | SD_INT_MASK);
764 }
765
766 /* stop a stream */
767 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
768 {
769 /* stop DMA */
770 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
771 ~(SD_CTL_DMA_START | SD_INT_MASK));
772 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
773 /* disable SIE */
774 azx_writeb(chip, INTCTL,
775 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
776 }
777
778
779 /*
780 * initialize the chip
781 */
782 static void azx_init_chip(struct azx *chip)
783 {
784 unsigned char reg;
785
786 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
787 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
788 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
789 */
790 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &reg);
791 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8);
792
793 /* reset controller */
794 azx_reset(chip);
795
796 /* initialize interrupts */
797 azx_int_clear(chip);
798 azx_int_enable(chip);
799
800 /* initialize the codec command I/O */
801 if (!chip->single_cmd)
802 azx_init_cmd_io(chip);
803
804 /* program the position buffer */
805 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
806 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
807
808 switch (chip->driver_type) {
809 case AZX_DRIVER_ATI:
810 /* For ATI SB450 azalia HD audio, we need to enable snoop */
811 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
812 &reg);
813 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
814 (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
815 break;
816 case AZX_DRIVER_NVIDIA:
817 /* For NVIDIA HDA, enable snoop */
818 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, &reg);
819 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR,
820 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS);
821 break;
822 }
823 }
824
825
826 /*
827 * interrupt handler
828 */
829 static irqreturn_t azx_interrupt(int irq, void *dev_id)
830 {
831 struct azx *chip = dev_id;
832 struct azx_dev *azx_dev;
833 u32 status;
834 int i;
835
836 spin_lock(&chip->reg_lock);
837
838 status = azx_readl(chip, INTSTS);
839 if (status == 0) {
840 spin_unlock(&chip->reg_lock);
841 return IRQ_NONE;
842 }
843
844 for (i = 0; i < chip->num_streams; i++) {
845 azx_dev = &chip->azx_dev[i];
846 if (status & azx_dev->sd_int_sta_mask) {
847 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
848 if (azx_dev->substream && azx_dev->running) {
849 azx_dev->period_intr++;
850 spin_unlock(&chip->reg_lock);
851 snd_pcm_period_elapsed(azx_dev->substream);
852 spin_lock(&chip->reg_lock);
853 }
854 }
855 }
856
857 /* clear rirb int */
858 status = azx_readb(chip, RIRBSTS);
859 if (status & RIRB_INT_MASK) {
860 if (! chip->single_cmd && (status & RIRB_INT_RESPONSE))
861 azx_update_rirb(chip);
862 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
863 }
864
865 #if 0
866 /* clear state status int */
867 if (azx_readb(chip, STATESTS) & 0x04)
868 azx_writeb(chip, STATESTS, 0x04);
869 #endif
870 spin_unlock(&chip->reg_lock);
871
872 return IRQ_HANDLED;
873 }
874
875
876 /*
877 * set up BDL entries
878 */
879 static void azx_setup_periods(struct azx_dev *azx_dev)
880 {
881 u32 *bdl = azx_dev->bdl;
882 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
883 int idx;
884
885 /* reset BDL address */
886 azx_sd_writel(azx_dev, SD_BDLPL, 0);
887 azx_sd_writel(azx_dev, SD_BDLPU, 0);
888
889 /* program the initial BDL entries */
890 for (idx = 0; idx < azx_dev->frags; idx++) {
891 unsigned int off = idx << 2; /* 4 dword step */
892 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
893 /* program the address field of the BDL entry */
894 bdl[off] = cpu_to_le32((u32)addr);
895 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
896
897 /* program the size field of the BDL entry */
898 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
899
900 /* program the IOC to enable interrupt when buffer completes */
901 bdl[off+3] = cpu_to_le32(0x01);
902 }
903 }
904
905 /*
906 * set up the SD for streaming
907 */
908 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
909 {
910 unsigned char val;
911 int timeout;
912
913 /* make sure the run bit is zero for SD */
914 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
915 /* reset stream */
916 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
917 udelay(3);
918 timeout = 300;
919 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
920 --timeout)
921 ;
922 val &= ~SD_CTL_STREAM_RESET;
923 azx_sd_writeb(azx_dev, SD_CTL, val);
924 udelay(3);
925
926 timeout = 300;
927 /* waiting for hardware to report that the stream is out of reset */
928 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
929 --timeout)
930 ;
931
932 /* program the stream_tag */
933 azx_sd_writel(azx_dev, SD_CTL,
934 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
935 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
936
937 /* program the length of samples in cyclic buffer */
938 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
939
940 /* program the stream format */
941 /* this value needs to be the same as the one programmed */
942 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
943
944 /* program the stream LVI (last valid index) of the BDL */
945 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
946
947 /* program the BDL address */
948 /* lower BDL address */
949 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
950 /* upper BDL address */
951 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
952
953 /* enable the position buffer */
954 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
955 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
956
957 /* set the interrupt enable bits in the descriptor control register */
958 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
959
960 return 0;
961 }
962
963
964 /*
965 * Codec initialization
966 */
967
968 static unsigned int azx_max_codecs[] __devinitdata = {
969 [AZX_DRIVER_ICH] = 3,
970 [AZX_DRIVER_ATI] = 4,
971 [AZX_DRIVER_ATIHDMI] = 4,
972 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
973 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
974 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
975 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
976 };
977
978 static int __devinit azx_codec_create(struct azx *chip, const char *model)
979 {
980 struct hda_bus_template bus_temp;
981 int c, codecs, audio_codecs, err;
982
983 memset(&bus_temp, 0, sizeof(bus_temp));
984 bus_temp.private_data = chip;
985 bus_temp.modelname = model;
986 bus_temp.pci = chip->pci;
987 bus_temp.ops.command = azx_send_cmd;
988 bus_temp.ops.get_response = azx_get_response;
989
990 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
991 return err;
992
993 codecs = audio_codecs = 0;
994 for (c = 0; c < AZX_MAX_CODECS; c++) {
995 if ((chip->codec_mask & (1 << c)) & probe_mask) {
996 struct hda_codec *codec;
997 err = snd_hda_codec_new(chip->bus, c, &codec);
998 if (err < 0)
999 continue;
1000 codecs++;
1001 if (codec->afg)
1002 audio_codecs++;
1003 }
1004 }
1005 if (!audio_codecs) {
1006 /* probe additional slots if no codec is found */
1007 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1008 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1009 err = snd_hda_codec_new(chip->bus, c, NULL);
1010 if (err < 0)
1011 continue;
1012 codecs++;
1013 }
1014 }
1015 }
1016 if (!codecs) {
1017 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1018 return -ENXIO;
1019 }
1020
1021 return 0;
1022 }
1023
1024
1025 /*
1026 * PCM support
1027 */
1028
1029 /* assign a stream for the PCM */
1030 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1031 {
1032 int dev, i, nums;
1033 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1034 dev = chip->playback_index_offset;
1035 nums = chip->playback_streams;
1036 } else {
1037 dev = chip->capture_index_offset;
1038 nums = chip->capture_streams;
1039 }
1040 for (i = 0; i < nums; i++, dev++)
1041 if (! chip->azx_dev[dev].opened) {
1042 chip->azx_dev[dev].opened = 1;
1043 return &chip->azx_dev[dev];
1044 }
1045 return NULL;
1046 }
1047
1048 /* release the assigned stream */
1049 static inline void azx_release_device(struct azx_dev *azx_dev)
1050 {
1051 azx_dev->opened = 0;
1052 }
1053
1054 static struct snd_pcm_hardware azx_pcm_hw = {
1055 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1056 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1057 SNDRV_PCM_INFO_MMAP_VALID |
1058 /* No full-resume yet implemented */
1059 /* SNDRV_PCM_INFO_RESUME |*/
1060 SNDRV_PCM_INFO_PAUSE),
1061 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1062 .rates = SNDRV_PCM_RATE_48000,
1063 .rate_min = 48000,
1064 .rate_max = 48000,
1065 .channels_min = 2,
1066 .channels_max = 2,
1067 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1068 .period_bytes_min = 128,
1069 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1070 .periods_min = 2,
1071 .periods_max = AZX_MAX_FRAG,
1072 .fifo_size = 0,
1073 };
1074
1075 struct azx_pcm {
1076 struct azx *chip;
1077 struct hda_codec *codec;
1078 struct hda_pcm_stream *hinfo[2];
1079 };
1080
1081 static int azx_pcm_open(struct snd_pcm_substream *substream)
1082 {
1083 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1084 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1085 struct azx *chip = apcm->chip;
1086 struct azx_dev *azx_dev;
1087 struct snd_pcm_runtime *runtime = substream->runtime;
1088 unsigned long flags;
1089 int err;
1090
1091 mutex_lock(&chip->open_mutex);
1092 azx_dev = azx_assign_device(chip, substream->stream);
1093 if (azx_dev == NULL) {
1094 mutex_unlock(&chip->open_mutex);
1095 return -EBUSY;
1096 }
1097 runtime->hw = azx_pcm_hw;
1098 runtime->hw.channels_min = hinfo->channels_min;
1099 runtime->hw.channels_max = hinfo->channels_max;
1100 runtime->hw.formats = hinfo->formats;
1101 runtime->hw.rates = hinfo->rates;
1102 snd_pcm_limit_hw_rates(runtime);
1103 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1104 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1105 128);
1106 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1107 128);
1108 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
1109 azx_release_device(azx_dev);
1110 mutex_unlock(&chip->open_mutex);
1111 return err;
1112 }
1113 spin_lock_irqsave(&chip->reg_lock, flags);
1114 azx_dev->substream = substream;
1115 azx_dev->running = 0;
1116 spin_unlock_irqrestore(&chip->reg_lock, flags);
1117
1118 runtime->private_data = azx_dev;
1119 mutex_unlock(&chip->open_mutex);
1120 return 0;
1121 }
1122
1123 static int azx_pcm_close(struct snd_pcm_substream *substream)
1124 {
1125 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1126 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1127 struct azx *chip = apcm->chip;
1128 struct azx_dev *azx_dev = get_azx_dev(substream);
1129 unsigned long flags;
1130
1131 mutex_lock(&chip->open_mutex);
1132 spin_lock_irqsave(&chip->reg_lock, flags);
1133 azx_dev->substream = NULL;
1134 azx_dev->running = 0;
1135 spin_unlock_irqrestore(&chip->reg_lock, flags);
1136 azx_release_device(azx_dev);
1137 hinfo->ops.close(hinfo, apcm->codec, substream);
1138 mutex_unlock(&chip->open_mutex);
1139 return 0;
1140 }
1141
1142 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params)
1143 {
1144 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1145 }
1146
1147 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1148 {
1149 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1150 struct azx_dev *azx_dev = get_azx_dev(substream);
1151 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1152
1153 /* reset BDL address */
1154 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1155 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1156 azx_sd_writel(azx_dev, SD_CTL, 0);
1157
1158 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1159
1160 return snd_pcm_lib_free_pages(substream);
1161 }
1162
1163 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1164 {
1165 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1166 struct azx *chip = apcm->chip;
1167 struct azx_dev *azx_dev = get_azx_dev(substream);
1168 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1169 struct snd_pcm_runtime *runtime = substream->runtime;
1170
1171 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1172 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1173 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1174 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1175 runtime->channels,
1176 runtime->format,
1177 hinfo->maxbps);
1178 if (! azx_dev->format_val) {
1179 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1180 runtime->rate, runtime->channels, runtime->format);
1181 return -EINVAL;
1182 }
1183
1184 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1185 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1186 azx_setup_periods(azx_dev);
1187 azx_setup_controller(chip, azx_dev);
1188 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1189 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1190 else
1191 azx_dev->fifo_size = 0;
1192
1193 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1194 azx_dev->format_val, substream);
1195 }
1196
1197 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1198 {
1199 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1200 struct azx_dev *azx_dev = get_azx_dev(substream);
1201 struct azx *chip = apcm->chip;
1202 int err = 0;
1203
1204 spin_lock(&chip->reg_lock);
1205 switch (cmd) {
1206 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1207 case SNDRV_PCM_TRIGGER_RESUME:
1208 case SNDRV_PCM_TRIGGER_START:
1209 azx_stream_start(chip, azx_dev);
1210 azx_dev->running = 1;
1211 break;
1212 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1213 case SNDRV_PCM_TRIGGER_SUSPEND:
1214 case SNDRV_PCM_TRIGGER_STOP:
1215 azx_stream_stop(chip, azx_dev);
1216 azx_dev->running = 0;
1217 break;
1218 default:
1219 err = -EINVAL;
1220 }
1221 spin_unlock(&chip->reg_lock);
1222 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1223 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1224 cmd == SNDRV_PCM_TRIGGER_STOP) {
1225 int timeout = 5000;
1226 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1227 ;
1228 }
1229 return err;
1230 }
1231
1232 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1233 {
1234 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1235 struct azx *chip = apcm->chip;
1236 struct azx_dev *azx_dev = get_azx_dev(substream);
1237 unsigned int pos;
1238
1239 if (chip->position_fix == POS_FIX_POSBUF ||
1240 chip->position_fix == POS_FIX_AUTO) {
1241 /* use the position buffer */
1242 pos = le32_to_cpu(*azx_dev->posbuf);
1243 if (chip->position_fix == POS_FIX_AUTO &&
1244 azx_dev->period_intr == 1 && ! pos) {
1245 printk(KERN_WARNING
1246 "hda-intel: Invalid position buffer, "
1247 "using LPIB read method instead.\n");
1248 chip->position_fix = POS_FIX_NONE;
1249 goto read_lpib;
1250 }
1251 } else {
1252 read_lpib:
1253 /* read LPIB */
1254 pos = azx_sd_readl(azx_dev, SD_LPIB);
1255 if (chip->position_fix == POS_FIX_FIFO)
1256 pos += azx_dev->fifo_size;
1257 }
1258 if (pos >= azx_dev->bufsize)
1259 pos = 0;
1260 return bytes_to_frames(substream->runtime, pos);
1261 }
1262
1263 static struct snd_pcm_ops azx_pcm_ops = {
1264 .open = azx_pcm_open,
1265 .close = azx_pcm_close,
1266 .ioctl = snd_pcm_lib_ioctl,
1267 .hw_params = azx_pcm_hw_params,
1268 .hw_free = azx_pcm_hw_free,
1269 .prepare = azx_pcm_prepare,
1270 .trigger = azx_pcm_trigger,
1271 .pointer = azx_pcm_pointer,
1272 };
1273
1274 static void azx_pcm_free(struct snd_pcm *pcm)
1275 {
1276 kfree(pcm->private_data);
1277 }
1278
1279 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1280 struct hda_pcm *cpcm, int pcm_dev)
1281 {
1282 int err;
1283 struct snd_pcm *pcm;
1284 struct azx_pcm *apcm;
1285
1286 /* if no substreams are defined for both playback and capture,
1287 * it's just a placeholder. ignore it.
1288 */
1289 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1290 return 0;
1291
1292 snd_assert(cpcm->name, return -EINVAL);
1293
1294 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1295 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1296 &pcm);
1297 if (err < 0)
1298 return err;
1299 strcpy(pcm->name, cpcm->name);
1300 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1301 if (apcm == NULL)
1302 return -ENOMEM;
1303 apcm->chip = chip;
1304 apcm->codec = codec;
1305 apcm->hinfo[0] = &cpcm->stream[0];
1306 apcm->hinfo[1] = &cpcm->stream[1];
1307 pcm->private_data = apcm;
1308 pcm->private_free = azx_pcm_free;
1309 if (cpcm->stream[0].substreams)
1310 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1311 if (cpcm->stream[1].substreams)
1312 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1313 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1314 snd_dma_pci_data(chip->pci),
1315 1024 * 64, 1024 * 1024);
1316 chip->pcm[pcm_dev] = pcm;
1317 if (chip->pcm_devs < pcm_dev + 1)
1318 chip->pcm_devs = pcm_dev + 1;
1319
1320 return 0;
1321 }
1322
1323 static int __devinit azx_pcm_create(struct azx *chip)
1324 {
1325 struct list_head *p;
1326 struct hda_codec *codec;
1327 int c, err;
1328 int pcm_dev;
1329
1330 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1331 return err;
1332
1333 /* create audio PCMs */
1334 pcm_dev = 0;
1335 list_for_each(p, &chip->bus->codec_list) {
1336 codec = list_entry(p, struct hda_codec, list);
1337 for (c = 0; c < codec->num_pcms; c++) {
1338 if (codec->pcm_info[c].is_modem)
1339 continue; /* create later */
1340 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1341 snd_printk(KERN_ERR SFX "Too many audio PCMs\n");
1342 return -EINVAL;
1343 }
1344 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1345 if (err < 0)
1346 return err;
1347 pcm_dev++;
1348 }
1349 }
1350
1351 /* create modem PCMs */
1352 pcm_dev = AZX_MAX_AUDIO_PCMS;
1353 list_for_each(p, &chip->bus->codec_list) {
1354 codec = list_entry(p, struct hda_codec, list);
1355 for (c = 0; c < codec->num_pcms; c++) {
1356 if (! codec->pcm_info[c].is_modem)
1357 continue; /* already created */
1358 if (pcm_dev >= AZX_MAX_PCMS) {
1359 snd_printk(KERN_ERR SFX "Too many modem PCMs\n");
1360 return -EINVAL;
1361 }
1362 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1363 if (err < 0)
1364 return err;
1365 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1366 pcm_dev++;
1367 }
1368 }
1369 return 0;
1370 }
1371
1372 /*
1373 * mixer creation - all stuff is implemented in hda module
1374 */
1375 static int __devinit azx_mixer_create(struct azx *chip)
1376 {
1377 return snd_hda_build_controls(chip->bus);
1378 }
1379
1380
1381 /*
1382 * initialize SD streams
1383 */
1384 static int __devinit azx_init_stream(struct azx *chip)
1385 {
1386 int i;
1387
1388 /* initialize each stream (aka device)
1389 * assign the starting bdl address to each stream (device) and initialize
1390 */
1391 for (i = 0; i < chip->num_streams; i++) {
1392 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1393 struct azx_dev *azx_dev = &chip->azx_dev[i];
1394 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1395 azx_dev->bdl_addr = chip->bdl.addr + off;
1396 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1397 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1398 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1399 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1400 azx_dev->sd_int_sta_mask = 1 << i;
1401 /* stream tag: must be non-zero and unique */
1402 azx_dev->index = i;
1403 azx_dev->stream_tag = i + 1;
1404 }
1405
1406 return 0;
1407 }
1408
1409 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1410 {
1411 if (request_irq(chip->pci->irq, azx_interrupt,
1412 chip->msi ? 0 : IRQF_SHARED,
1413 "HDA Intel", chip)) {
1414 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1415 "disabling device\n", chip->pci->irq);
1416 if (do_disconnect)
1417 snd_card_disconnect(chip->card);
1418 return -1;
1419 }
1420 chip->irq = chip->pci->irq;
1421 pci_intx(chip->pci, !chip->msi);
1422 return 0;
1423 }
1424
1425
1426 #ifdef CONFIG_PM
1427 /*
1428 * power management
1429 */
1430 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1431 {
1432 struct snd_card *card = pci_get_drvdata(pci);
1433 struct azx *chip = card->private_data;
1434 int i;
1435
1436 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1437 for (i = 0; i < chip->pcm_devs; i++)
1438 snd_pcm_suspend_all(chip->pcm[i]);
1439 snd_hda_suspend(chip->bus, state);
1440 azx_free_cmd_io(chip);
1441 if (chip->irq >= 0) {
1442 synchronize_irq(chip->irq);
1443 free_irq(chip->irq, chip);
1444 chip->irq = -1;
1445 }
1446 if (chip->msi)
1447 pci_disable_msi(chip->pci);
1448 pci_disable_device(pci);
1449 pci_save_state(pci);
1450 pci_set_power_state(pci, pci_choose_state(pci, state));
1451 return 0;
1452 }
1453
1454 static int azx_resume(struct pci_dev *pci)
1455 {
1456 struct snd_card *card = pci_get_drvdata(pci);
1457 struct azx *chip = card->private_data;
1458
1459 pci_set_power_state(pci, PCI_D0);
1460 pci_restore_state(pci);
1461 if (pci_enable_device(pci) < 0) {
1462 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1463 "disabling device\n");
1464 snd_card_disconnect(card);
1465 return -EIO;
1466 }
1467 pci_set_master(pci);
1468 if (chip->msi)
1469 if (pci_enable_msi(pci) < 0)
1470 chip->msi = 0;
1471 if (azx_acquire_irq(chip, 1) < 0)
1472 return -EIO;
1473 azx_init_chip(chip);
1474 snd_hda_resume(chip->bus);
1475 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1476 return 0;
1477 }
1478 #endif /* CONFIG_PM */
1479
1480
1481 /*
1482 * destructor
1483 */
1484 static int azx_free(struct azx *chip)
1485 {
1486 if (chip->initialized) {
1487 int i;
1488
1489 for (i = 0; i < chip->num_streams; i++)
1490 azx_stream_stop(chip, &chip->azx_dev[i]);
1491
1492 /* disable interrupts */
1493 azx_int_disable(chip);
1494 azx_int_clear(chip);
1495
1496 /* disable CORB/RIRB */
1497 azx_free_cmd_io(chip);
1498
1499 /* disable position buffer */
1500 azx_writel(chip, DPLBASE, 0);
1501 azx_writel(chip, DPUBASE, 0);
1502 }
1503
1504 if (chip->irq >= 0) {
1505 synchronize_irq(chip->irq);
1506 free_irq(chip->irq, (void*)chip);
1507 }
1508 if (chip->msi)
1509 pci_disable_msi(chip->pci);
1510 if (chip->remap_addr)
1511 iounmap(chip->remap_addr);
1512
1513 if (chip->bdl.area)
1514 snd_dma_free_pages(&chip->bdl);
1515 if (chip->rb.area)
1516 snd_dma_free_pages(&chip->rb);
1517 if (chip->posbuf.area)
1518 snd_dma_free_pages(&chip->posbuf);
1519 pci_release_regions(chip->pci);
1520 pci_disable_device(chip->pci);
1521 kfree(chip->azx_dev);
1522 kfree(chip);
1523
1524 return 0;
1525 }
1526
1527 static int azx_dev_free(struct snd_device *device)
1528 {
1529 return azx_free(device->device_data);
1530 }
1531
1532 /*
1533 * white/black-listing for position_fix
1534 */
1535 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1536 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1537 {}
1538 };
1539
1540 static int __devinit check_position_fix(struct azx *chip, int fix)
1541 {
1542 const struct snd_pci_quirk *q;
1543
1544 if (fix == POS_FIX_AUTO) {
1545 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1546 if (q) {
1547 snd_printdd(KERN_INFO
1548 "hda_intel: position_fix set to %d "
1549 "for device %04x:%04x\n",
1550 q->value, q->subvendor, q->subdevice);
1551 return q->value;
1552 }
1553 }
1554 return fix;
1555 }
1556
1557 /*
1558 * constructor
1559 */
1560 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1561 int driver_type,
1562 struct azx **rchip)
1563 {
1564 struct azx *chip;
1565 int err;
1566 static struct snd_device_ops ops = {
1567 .dev_free = azx_dev_free,
1568 };
1569
1570 *rchip = NULL;
1571
1572 err = pci_enable_device(pci);
1573 if (err < 0)
1574 return err;
1575
1576 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1577 if (!chip) {
1578 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1579 pci_disable_device(pci);
1580 return -ENOMEM;
1581 }
1582
1583 spin_lock_init(&chip->reg_lock);
1584 mutex_init(&chip->open_mutex);
1585 chip->card = card;
1586 chip->pci = pci;
1587 chip->irq = -1;
1588 chip->driver_type = driver_type;
1589 chip->msi = enable_msi;
1590
1591 chip->position_fix = check_position_fix(chip, position_fix);
1592
1593 chip->single_cmd = single_cmd;
1594
1595 #if BITS_PER_LONG != 64
1596 /* Fix up base address on ULI M5461 */
1597 if (chip->driver_type == AZX_DRIVER_ULI) {
1598 u16 tmp3;
1599 pci_read_config_word(pci, 0x40, &tmp3);
1600 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1601 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1602 }
1603 #endif
1604
1605 err = pci_request_regions(pci, "ICH HD audio");
1606 if (err < 0) {
1607 kfree(chip);
1608 pci_disable_device(pci);
1609 return err;
1610 }
1611
1612 chip->addr = pci_resource_start(pci, 0);
1613 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1614 if (chip->remap_addr == NULL) {
1615 snd_printk(KERN_ERR SFX "ioremap error\n");
1616 err = -ENXIO;
1617 goto errout;
1618 }
1619
1620 if (chip->msi)
1621 if (pci_enable_msi(pci) < 0)
1622 chip->msi = 0;
1623
1624 if (azx_acquire_irq(chip, 0) < 0) {
1625 err = -EBUSY;
1626 goto errout;
1627 }
1628
1629 pci_set_master(pci);
1630 synchronize_irq(chip->irq);
1631
1632 switch (chip->driver_type) {
1633 case AZX_DRIVER_ULI:
1634 chip->playback_streams = ULI_NUM_PLAYBACK;
1635 chip->capture_streams = ULI_NUM_CAPTURE;
1636 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1637 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1638 break;
1639 case AZX_DRIVER_ATIHDMI:
1640 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1641 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1642 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1643 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1644 break;
1645 default:
1646 chip->playback_streams = ICH6_NUM_PLAYBACK;
1647 chip->capture_streams = ICH6_NUM_CAPTURE;
1648 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1649 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1650 break;
1651 }
1652 chip->num_streams = chip->playback_streams + chip->capture_streams;
1653 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
1654 if (!chip->azx_dev) {
1655 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1656 goto errout;
1657 }
1658
1659 /* allocate memory for the BDL for each stream */
1660 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1661 BDL_SIZE, &chip->bdl)) < 0) {
1662 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1663 goto errout;
1664 }
1665 /* allocate memory for the position buffer */
1666 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1667 chip->num_streams * 8, &chip->posbuf)) < 0) {
1668 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1669 goto errout;
1670 }
1671 /* allocate CORB/RIRB */
1672 if (! chip->single_cmd)
1673 if ((err = azx_alloc_cmd_io(chip)) < 0)
1674 goto errout;
1675
1676 /* initialize streams */
1677 azx_init_stream(chip);
1678
1679 /* initialize chip */
1680 azx_init_chip(chip);
1681
1682 chip->initialized = 1;
1683
1684 /* codec detection */
1685 if (!chip->codec_mask) {
1686 snd_printk(KERN_ERR SFX "no codecs found!\n");
1687 err = -ENODEV;
1688 goto errout;
1689 }
1690
1691 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1692 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1693 goto errout;
1694 }
1695
1696 strcpy(card->driver, "HDA-Intel");
1697 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1698 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1699
1700 *rchip = chip;
1701 return 0;
1702
1703 errout:
1704 azx_free(chip);
1705 return err;
1706 }
1707
1708 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1709 {
1710 struct snd_card *card;
1711 struct azx *chip;
1712 int err;
1713
1714 card = snd_card_new(index, id, THIS_MODULE, 0);
1715 if (!card) {
1716 snd_printk(KERN_ERR SFX "Error creating card!\n");
1717 return -ENOMEM;
1718 }
1719
1720 err = azx_create(card, pci, pci_id->driver_data, &chip);
1721 if (err < 0) {
1722 snd_card_free(card);
1723 return err;
1724 }
1725 card->private_data = chip;
1726
1727 /* create codec instances */
1728 if ((err = azx_codec_create(chip, model)) < 0) {
1729 snd_card_free(card);
1730 return err;
1731 }
1732
1733 /* create PCM streams */
1734 if ((err = azx_pcm_create(chip)) < 0) {
1735 snd_card_free(card);
1736 return err;
1737 }
1738
1739 /* create mixer controls */
1740 if ((err = azx_mixer_create(chip)) < 0) {
1741 snd_card_free(card);
1742 return err;
1743 }
1744
1745 snd_card_set_dev(card, &pci->dev);
1746
1747 if ((err = snd_card_register(card)) < 0) {
1748 snd_card_free(card);
1749 return err;
1750 }
1751
1752 pci_set_drvdata(pci, card);
1753
1754 return err;
1755 }
1756
1757 static void __devexit azx_remove(struct pci_dev *pci)
1758 {
1759 snd_card_free(pci_get_drvdata(pci));
1760 pci_set_drvdata(pci, NULL);
1761 }
1762
1763 /* PCI IDs */
1764 static struct pci_device_id azx_ids[] = {
1765 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1766 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1767 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1768 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1769 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1770 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1771 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1772 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1773 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1774 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
1775 { 0x1002, 0x960c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1776 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
1777 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1778 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1779 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1780 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1781 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1782 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1783 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1784 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1785 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1786 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1787 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1788 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1789 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1790 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1791 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1792 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1793 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1794 { 0, }
1795 };
1796 MODULE_DEVICE_TABLE(pci, azx_ids);
1797
1798 /* pci_driver definition */
1799 static struct pci_driver driver = {
1800 .name = "HDA Intel",
1801 .id_table = azx_ids,
1802 .probe = azx_probe,
1803 .remove = __devexit_p(azx_remove),
1804 #ifdef CONFIG_PM
1805 .suspend = azx_suspend,
1806 .resume = azx_resume,
1807 #endif
1808 };
1809
1810 static int __init alsa_card_azx_init(void)
1811 {
1812 return pci_register_driver(&driver);
1813 }
1814
1815 static void __exit alsa_card_azx_exit(void)
1816 {
1817 pci_unregister_driver(&driver);
1818 }
1819
1820 module_init(alsa_card_azx_init)
1821 module_exit(alsa_card_azx_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree