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Merge branch 'ioat' into dmaengine
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / atmel-mci.c
blobc293ac4ee150c1b4f1692795a27951571a2e32a8
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/scatterlist.h>
24 #include <linux/seq_file.h>
25 #include <linux/slab.h>
26 #include <linux/stat.h>
27
28 #include <linux/mmc/host.h>
29
30 #include <mach/atmel-mci.h>
31 #include <linux/atmel-mci.h>
32
33 #include <asm/io.h>
34 #include <asm/unaligned.h>
35
36 #include <mach/cpu.h>
37 #include <mach/board.h>
38
39 #include "atmel-mci-regs.h"
40
41 #define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE)
42 #define ATMCI_DMA_THRESHOLD 16
43
44 enum {
45 EVENT_CMD_COMPLETE = 0,
46 EVENT_XFER_COMPLETE,
47 EVENT_DATA_COMPLETE,
48 EVENT_DATA_ERROR,
49 };
50
51 enum atmel_mci_state {
52 STATE_IDLE = 0,
53 STATE_SENDING_CMD,
54 STATE_SENDING_DATA,
55 STATE_DATA_BUSY,
56 STATE_SENDING_STOP,
57 STATE_DATA_ERROR,
58 };
59
60 struct atmel_mci_dma {
61 #ifdef CONFIG_MMC_ATMELMCI_DMA
62 struct dma_chan *chan;
63 struct dma_async_tx_descriptor *data_desc;
64 #endif
65 };
66
67 /**
68 * struct atmel_mci - MMC controller state shared between all slots
69 * @lock: Spinlock protecting the queue and associated data.
70 * @regs: Pointer to MMIO registers.
71 * @sg: Scatterlist entry currently being processed by PIO code, if any.
72 * @pio_offset: Offset into the current scatterlist entry.
73 * @cur_slot: The slot which is currently using the controller.
74 * @mrq: The request currently being processed on @cur_slot,
75 * or NULL if the controller is idle.
76 * @cmd: The command currently being sent to the card, or NULL.
77 * @data: The data currently being transferred, or NULL if no data
78 * transfer is in progress.
79 * @dma: DMA client state.
80 * @data_chan: DMA channel being used for the current data transfer.
81 * @cmd_status: Snapshot of SR taken upon completion of the current
82 * command. Only valid when EVENT_CMD_COMPLETE is pending.
83 * @data_status: Snapshot of SR taken upon completion of the current
84 * data transfer. Only valid when EVENT_DATA_COMPLETE or
85 * EVENT_DATA_ERROR is pending.
86 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
87 * to be sent.
88 * @tasklet: Tasklet running the request state machine.
89 * @pending_events: Bitmask of events flagged by the interrupt handler
90 * to be processed by the tasklet.
91 * @completed_events: Bitmask of events which the state machine has
92 * processed.
93 * @state: Tasklet state.
94 * @queue: List of slots waiting for access to the controller.
95 * @need_clock_update: Update the clock rate before the next request.
96 * @need_reset: Reset controller before next request.
97 * @mode_reg: Value of the MR register.
98 * @cfg_reg: Value of the CFG register.
99 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
100 * rate and timeout calculations.
101 * @mapbase: Physical address of the MMIO registers.
102 * @mck: The peripheral bus clock hooked up to the MMC controller.
103 * @pdev: Platform device associated with the MMC controller.
104 * @slot: Slots sharing this MMC controller.
105 *
106 * Locking
107 * =======
108 *
109 * @lock is a softirq-safe spinlock protecting @queue as well as
110 * @cur_slot, @mrq and @state. These must always be updated
111 * at the same time while holding @lock.
112 *
113 * @lock also protects mode_reg and need_clock_update since these are
114 * used to synchronize mode register updates with the queue
115 * processing.
116 *
117 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
118 * and must always be written at the same time as the slot is added to
119 * @queue.
120 *
121 * @pending_events and @completed_events are accessed using atomic bit
122 * operations, so they don't need any locking.
123 *
124 * None of the fields touched by the interrupt handler need any
125 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
126 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
127 * interrupts must be disabled and @data_status updated with a
128 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
129 * CMDRDY interupt must be disabled and @cmd_status updated with a
130 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
131 * bytes_xfered field of @data must be written. This is ensured by
132 * using barriers.
133 */
134 struct atmel_mci {
135 spinlock_t lock;
136 void __iomem *regs;
137
138 struct scatterlist *sg;
139 unsigned int pio_offset;
140
141 struct atmel_mci_slot *cur_slot;
142 struct mmc_request *mrq;
143 struct mmc_command *cmd;
144 struct mmc_data *data;
145
146 struct atmel_mci_dma dma;
147 struct dma_chan *data_chan;
148
149 u32 cmd_status;
150 u32 data_status;
151 u32 stop_cmdr;
152
153 struct tasklet_struct tasklet;
154 unsigned long pending_events;
155 unsigned long completed_events;
156 enum atmel_mci_state state;
157 struct list_head queue;
158
159 bool need_clock_update;
160 bool need_reset;
161 u32 mode_reg;
162 u32 cfg_reg;
163 unsigned long bus_hz;
164 unsigned long mapbase;
165 struct clk *mck;
166 struct platform_device *pdev;
167
168 struct atmel_mci_slot *slot[ATMEL_MCI_MAX_NR_SLOTS];
169 };
170
171 /**
172 * struct atmel_mci_slot - MMC slot state
173 * @mmc: The mmc_host representing this slot.
174 * @host: The MMC controller this slot is using.
175 * @sdc_reg: Value of SDCR to be written before using this slot.
176 * @mrq: mmc_request currently being processed or waiting to be
177 * processed, or NULL when the slot is idle.
178 * @queue_node: List node for placing this node in the @queue list of
179 * &struct atmel_mci.
180 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
181 * @flags: Random state bits associated with the slot.
182 * @detect_pin: GPIO pin used for card detection, or negative if not
183 * available.
184 * @wp_pin: GPIO pin used for card write protect sending, or negative
185 * if not available.
186 * @detect_is_active_high: The state of the detect pin when it is active.
187 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
188 */
189 struct atmel_mci_slot {
190 struct mmc_host *mmc;
191 struct atmel_mci *host;
192
193 u32 sdc_reg;
194
195 struct mmc_request *mrq;
196 struct list_head queue_node;
197
198 unsigned int clock;
199 unsigned long flags;
200 #define ATMCI_CARD_PRESENT 0
201 #define ATMCI_CARD_NEED_INIT 1
202 #define ATMCI_SHUTDOWN 2
203
204 int detect_pin;
205 int wp_pin;
206 bool detect_is_active_high;
207
208 struct timer_list detect_timer;
209 };
210
211 #define atmci_test_and_clear_pending(host, event) \
212 test_and_clear_bit(event, &host->pending_events)
213 #define atmci_set_completed(host, event) \
214 set_bit(event, &host->completed_events)
215 #define atmci_set_pending(host, event) \
216 set_bit(event, &host->pending_events)
217
218 /*
219 * Enable or disable features/registers based on
220 * whether the processor supports them
221 */
222 static bool mci_has_rwproof(void)
223 {
224 if (cpu_is_at91sam9261() || cpu_is_at91rm9200())
225 return false;
226 else
227 return true;
228 }
229
230 /*
231 * The new MCI2 module isn't 100% compatible with the old MCI module,
232 * and it has a few nice features which we want to use...
233 */
234 static inline bool atmci_is_mci2(void)
235 {
236 if (cpu_is_at91sam9g45())
237 return true;
238
239 return false;
240 }
241
242
243 /*
244 * The debugfs stuff below is mostly optimized away when
245 * CONFIG_DEBUG_FS is not set.
246 */
247 static int atmci_req_show(struct seq_file *s, void *v)
248 {
249 struct atmel_mci_slot *slot = s->private;
250 struct mmc_request *mrq;
251 struct mmc_command *cmd;
252 struct mmc_command *stop;
253 struct mmc_data *data;
254
255 /* Make sure we get a consistent snapshot */
256 spin_lock_bh(&slot->host->lock);
257 mrq = slot->mrq;
258
259 if (mrq) {
260 cmd = mrq->cmd;
261 data = mrq->data;
262 stop = mrq->stop;
263
264 if (cmd)
265 seq_printf(s,
266 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
267 cmd->opcode, cmd->arg, cmd->flags,
268 cmd->resp[0], cmd->resp[1], cmd->resp[2],
269 cmd->resp[2], cmd->error);
270 if (data)
271 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
272 data->bytes_xfered, data->blocks,
273 data->blksz, data->flags, data->error);
274 if (stop)
275 seq_printf(s,
276 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
277 stop->opcode, stop->arg, stop->flags,
278 stop->resp[0], stop->resp[1], stop->resp[2],
279 stop->resp[2], stop->error);
280 }
281
282 spin_unlock_bh(&slot->host->lock);
283
284 return 0;
285 }
286
287 static int atmci_req_open(struct inode *inode, struct file *file)
288 {
289 return single_open(file, atmci_req_show, inode->i_private);
290 }
291
292 static const struct file_operations atmci_req_fops = {
293 .owner = THIS_MODULE,
294 .open = atmci_req_open,
295 .read = seq_read,
296 .llseek = seq_lseek,
297 .release = single_release,
298 };
299
300 static void atmci_show_status_reg(struct seq_file *s,
301 const char *regname, u32 value)
302 {
303 static const char *sr_bit[] = {
304 [0] = "CMDRDY",
305 [1] = "RXRDY",
306 [2] = "TXRDY",
307 [3] = "BLKE",
308 [4] = "DTIP",
309 [5] = "NOTBUSY",
310 [6] = "ENDRX",
311 [7] = "ENDTX",
312 [8] = "SDIOIRQA",
313 [9] = "SDIOIRQB",
314 [12] = "SDIOWAIT",
315 [14] = "RXBUFF",
316 [15] = "TXBUFE",
317 [16] = "RINDE",
318 [17] = "RDIRE",
319 [18] = "RCRCE",
320 [19] = "RENDE",
321 [20] = "RTOE",
322 [21] = "DCRCE",
323 [22] = "DTOE",
324 [23] = "CSTOE",
325 [24] = "BLKOVRE",
326 [25] = "DMADONE",
327 [26] = "FIFOEMPTY",
328 [27] = "XFRDONE",
329 [30] = "OVRE",
330 [31] = "UNRE",
331 };
332 unsigned int i;
333
334 seq_printf(s, "%s:\t0x%08x", regname, value);
335 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
336 if (value & (1 << i)) {
337 if (sr_bit[i])
338 seq_printf(s, " %s", sr_bit[i]);
339 else
340 seq_puts(s, " UNKNOWN");
341 }
342 }
343 seq_putc(s, '\n');
344 }
345
346 static int atmci_regs_show(struct seq_file *s, void *v)
347 {
348 struct atmel_mci *host = s->private;
349 u32 *buf;
350
351 buf = kmalloc(MCI_REGS_SIZE, GFP_KERNEL);
352 if (!buf)
353 return -ENOMEM;
354
355 /*
356 * Grab a more or less consistent snapshot. Note that we're
357 * not disabling interrupts, so IMR and SR may not be
358 * consistent.
359 */
360 spin_lock_bh(&host->lock);
361 clk_enable(host->mck);
362 memcpy_fromio(buf, host->regs, MCI_REGS_SIZE);
363 clk_disable(host->mck);
364 spin_unlock_bh(&host->lock);
365
366 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
367 buf[MCI_MR / 4],
368 buf[MCI_MR / 4] & MCI_MR_RDPROOF ? " RDPROOF" : "",
369 buf[MCI_MR / 4] & MCI_MR_WRPROOF ? " WRPROOF" : "",
370 buf[MCI_MR / 4] & 0xff);
371 seq_printf(s, "DTOR:\t0x%08x\n", buf[MCI_DTOR / 4]);
372 seq_printf(s, "SDCR:\t0x%08x\n", buf[MCI_SDCR / 4]);
373 seq_printf(s, "ARGR:\t0x%08x\n", buf[MCI_ARGR / 4]);
374 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
375 buf[MCI_BLKR / 4],
376 buf[MCI_BLKR / 4] & 0xffff,
377 (buf[MCI_BLKR / 4] >> 16) & 0xffff);
378 if (atmci_is_mci2())
379 seq_printf(s, "CSTOR:\t0x%08x\n", buf[MCI_CSTOR / 4]);
380
381 /* Don't read RSPR and RDR; it will consume the data there */
382
383 atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]);
384 atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]);
385
386 if (atmci_is_mci2()) {
387 u32 val;
388
389 val = buf[MCI_DMA / 4];
390 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
391 val, val & 3,
392 ((val >> 4) & 3) ?
393 1 << (((val >> 4) & 3) + 1) : 1,
394 val & MCI_DMAEN ? " DMAEN" : "");
395
396 val = buf[MCI_CFG / 4];
397 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
398 val,
399 val & MCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
400 val & MCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
401 val & MCI_CFG_HSMODE ? " HSMODE" : "",
402 val & MCI_CFG_LSYNC ? " LSYNC" : "");
403 }
404
405 kfree(buf);
406
407 return 0;
408 }
409
410 static int atmci_regs_open(struct inode *inode, struct file *file)
411 {
412 return single_open(file, atmci_regs_show, inode->i_private);
413 }
414
415 static const struct file_operations atmci_regs_fops = {
416 .owner = THIS_MODULE,
417 .open = atmci_regs_open,
418 .read = seq_read,
419 .llseek = seq_lseek,
420 .release = single_release,
421 };
422
423 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
424 {
425 struct mmc_host *mmc = slot->mmc;
426 struct atmel_mci *host = slot->host;
427 struct dentry *root;
428 struct dentry *node;
429
430 root = mmc->debugfs_root;
431 if (!root)
432 return;
433
434 node = debugfs_create_file("regs", S_IRUSR, root, host,
435 &atmci_regs_fops);
436 if (IS_ERR(node))
437 return;
438 if (!node)
439 goto err;
440
441 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
442 if (!node)
443 goto err;
444
445 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
446 if (!node)
447 goto err;
448
449 node = debugfs_create_x32("pending_events", S_IRUSR, root,
450 (u32 *)&host->pending_events);
451 if (!node)
452 goto err;
453
454 node = debugfs_create_x32("completed_events", S_IRUSR, root,
455 (u32 *)&host->completed_events);
456 if (!node)
457 goto err;
458
459 return;
460
461 err:
462 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
463 }
464
465 static inline unsigned int ns_to_clocks(struct atmel_mci *host,
466 unsigned int ns)
467 {
468 return (ns * (host->bus_hz / 1000000) + 999) / 1000;
469 }
470
471 static void atmci_set_timeout(struct atmel_mci *host,
472 struct atmel_mci_slot *slot, struct mmc_data *data)
473 {
474 static unsigned dtomul_to_shift[] = {
475 0, 4, 7, 8, 10, 12, 16, 20
476 };
477 unsigned timeout;
478 unsigned dtocyc;
479 unsigned dtomul;
480
481 timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
482
483 for (dtomul = 0; dtomul < 8; dtomul++) {
484 unsigned shift = dtomul_to_shift[dtomul];
485 dtocyc = (timeout + (1 << shift) - 1) >> shift;
486 if (dtocyc < 15)
487 break;
488 }
489
490 if (dtomul >= 8) {
491 dtomul = 7;
492 dtocyc = 15;
493 }
494
495 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
496 dtocyc << dtomul_to_shift[dtomul]);
497 mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc)));
498 }
499
500 /*
501 * Return mask with command flags to be enabled for this command.
502 */
503 static u32 atmci_prepare_command(struct mmc_host *mmc,
504 struct mmc_command *cmd)
505 {
506 struct mmc_data *data;
507 u32 cmdr;
508
509 cmd->error = -EINPROGRESS;
510
511 cmdr = MCI_CMDR_CMDNB(cmd->opcode);
512
513 if (cmd->flags & MMC_RSP_PRESENT) {
514 if (cmd->flags & MMC_RSP_136)
515 cmdr |= MCI_CMDR_RSPTYP_136BIT;
516 else
517 cmdr |= MCI_CMDR_RSPTYP_48BIT;
518 }
519
520 /*
521 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
522 * it's too difficult to determine whether this is an ACMD or
523 * not. Better make it 64.
524 */
525 cmdr |= MCI_CMDR_MAXLAT_64CYC;
526
527 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
528 cmdr |= MCI_CMDR_OPDCMD;
529
530 data = cmd->data;
531 if (data) {
532 cmdr |= MCI_CMDR_START_XFER;
533 if (data->flags & MMC_DATA_STREAM)
534 cmdr |= MCI_CMDR_STREAM;
535 else if (data->blocks > 1)
536 cmdr |= MCI_CMDR_MULTI_BLOCK;
537 else
538 cmdr |= MCI_CMDR_BLOCK;
539
540 if (data->flags & MMC_DATA_READ)
541 cmdr |= MCI_CMDR_TRDIR_READ;
542 }
543
544 return cmdr;
545 }
546
547 static void atmci_start_command(struct atmel_mci *host,
548 struct mmc_command *cmd, u32 cmd_flags)
549 {
550 WARN_ON(host->cmd);
551 host->cmd = cmd;
552
553 dev_vdbg(&host->pdev->dev,
554 "start command: ARGR=0x%08x CMDR=0x%08x\n",
555 cmd->arg, cmd_flags);
556
557 mci_writel(host, ARGR, cmd->arg);
558 mci_writel(host, CMDR, cmd_flags);
559 }
560
561 static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
562 {
563 atmci_start_command(host, data->stop, host->stop_cmdr);
564 mci_writel(host, IER, MCI_CMDRDY);
565 }
566
567 #ifdef CONFIG_MMC_ATMELMCI_DMA
568 static void atmci_dma_cleanup(struct atmel_mci *host)
569 {
570 struct mmc_data *data = host->data;
571
572 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
573 ((data->flags & MMC_DATA_WRITE)
574 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
575 }
576
577 static void atmci_stop_dma(struct atmel_mci *host)
578 {
579 struct dma_chan *chan = host->data_chan;
580
581 if (chan) {
582 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
583 atmci_dma_cleanup(host);
584 } else {
585 /* Data transfer was stopped by the interrupt handler */
586 atmci_set_pending(host, EVENT_XFER_COMPLETE);
587 mci_writel(host, IER, MCI_NOTBUSY);
588 }
589 }
590
591 /* This function is called by the DMA driver from tasklet context. */
592 static void atmci_dma_complete(void *arg)
593 {
594 struct atmel_mci *host = arg;
595 struct mmc_data *data = host->data;
596
597 dev_vdbg(&host->pdev->dev, "DMA complete\n");
598
599 if (atmci_is_mci2())
600 /* Disable DMA hardware handshaking on MCI */
601 mci_writel(host, DMA, mci_readl(host, DMA) & ~MCI_DMAEN);
602
603 atmci_dma_cleanup(host);
604
605 /*
606 * If the card was removed, data will be NULL. No point trying
607 * to send the stop command or waiting for NBUSY in this case.
608 */
609 if (data) {
610 atmci_set_pending(host, EVENT_XFER_COMPLETE);
611 tasklet_schedule(&host->tasklet);
612
613 /*
614 * Regardless of what the documentation says, we have
615 * to wait for NOTBUSY even after block read
616 * operations.
617 *
618 * When the DMA transfer is complete, the controller
619 * may still be reading the CRC from the card, i.e.
620 * the data transfer is still in progress and we
621 * haven't seen all the potential error bits yet.
622 *
623 * The interrupt handler will schedule a different
624 * tasklet to finish things up when the data transfer
625 * is completely done.
626 *
627 * We may not complete the mmc request here anyway
628 * because the mmc layer may call back and cause us to
629 * violate the "don't submit new operations from the
630 * completion callback" rule of the dma engine
631 * framework.
632 */
633 mci_writel(host, IER, MCI_NOTBUSY);
634 }
635 }
636
637 static int
638 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
639 {
640 struct dma_chan *chan;
641 struct dma_async_tx_descriptor *desc;
642 struct scatterlist *sg;
643 unsigned int i;
644 enum dma_data_direction direction;
645 unsigned int sglen;
646
647 /*
648 * We don't do DMA on "complex" transfers, i.e. with
649 * non-word-aligned buffers or lengths. Also, we don't bother
650 * with all the DMA setup overhead for short transfers.
651 */
652 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
653 return -EINVAL;
654 if (data->blksz & 3)
655 return -EINVAL;
656
657 for_each_sg(data->sg, sg, data->sg_len, i) {
658 if (sg->offset & 3 || sg->length & 3)
659 return -EINVAL;
660 }
661
662 /* If we don't have a channel, we can't do DMA */
663 chan = host->dma.chan;
664 if (chan)
665 host->data_chan = chan;
666
667 if (!chan)
668 return -ENODEV;
669
670 if (atmci_is_mci2())
671 mci_writel(host, DMA, MCI_DMA_CHKSIZE(3) | MCI_DMAEN);
672
673 if (data->flags & MMC_DATA_READ)
674 direction = DMA_FROM_DEVICE;
675 else
676 direction = DMA_TO_DEVICE;
677
678 sglen = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, direction);
679 if (sglen != data->sg_len)
680 goto unmap_exit;
681 desc = chan->device->device_prep_slave_sg(chan,
682 data->sg, data->sg_len, direction,
683 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
684 if (!desc)
685 goto unmap_exit;
686
687 host->dma.data_desc = desc;
688 desc->callback = atmci_dma_complete;
689 desc->callback_param = host;
690
691 return 0;
692 unmap_exit:
693 dma_unmap_sg(&host->pdev->dev, data->sg, sglen, direction);
694 return -ENOMEM;
695 }
696
697 static void atmci_submit_data(struct atmel_mci *host)
698 {
699 struct dma_chan *chan = host->data_chan;
700 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
701
702 if (chan) {
703 desc->tx_submit(desc);
704 chan->device->device_issue_pending(chan);
705 }
706 }
707
708 #else /* CONFIG_MMC_ATMELMCI_DMA */
709
710 static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
711 {
712 return -ENOSYS;
713 }
714
715 static void atmci_submit_data(struct atmel_mci *host) {}
716
717 static void atmci_stop_dma(struct atmel_mci *host)
718 {
719 /* Data transfer was stopped by the interrupt handler */
720 atmci_set_pending(host, EVENT_XFER_COMPLETE);
721 mci_writel(host, IER, MCI_NOTBUSY);
722 }
723
724 #endif /* CONFIG_MMC_ATMELMCI_DMA */
725
726 /*
727 * Returns a mask of interrupt flags to be enabled after the whole
728 * request has been prepared.
729 */
730 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
731 {
732 u32 iflags;
733
734 data->error = -EINPROGRESS;
735
736 WARN_ON(host->data);
737 host->sg = NULL;
738 host->data = data;
739
740 iflags = ATMCI_DATA_ERROR_FLAGS;
741 if (atmci_prepare_data_dma(host, data)) {
742 host->data_chan = NULL;
743
744 /*
745 * Errata: MMC data write operation with less than 12
746 * bytes is impossible.
747 *
748 * Errata: MCI Transmit Data Register (TDR) FIFO
749 * corruption when length is not multiple of 4.
750 */
751 if (data->blocks * data->blksz < 12
752 || (data->blocks * data->blksz) & 3)
753 host->need_reset = true;
754
755 host->sg = data->sg;
756 host->pio_offset = 0;
757 if (data->flags & MMC_DATA_READ)
758 iflags |= MCI_RXRDY;
759 else
760 iflags |= MCI_TXRDY;
761 }
762
763 return iflags;
764 }
765
766 static void atmci_start_request(struct atmel_mci *host,
767 struct atmel_mci_slot *slot)
768 {
769 struct mmc_request *mrq;
770 struct mmc_command *cmd;
771 struct mmc_data *data;
772 u32 iflags;
773 u32 cmdflags;
774
775 mrq = slot->mrq;
776 host->cur_slot = slot;
777 host->mrq = mrq;
778
779 host->pending_events = 0;
780 host->completed_events = 0;
781 host->data_status = 0;
782
783 if (host->need_reset) {
784 mci_writel(host, CR, MCI_CR_SWRST);
785 mci_writel(host, CR, MCI_CR_MCIEN);
786 mci_writel(host, MR, host->mode_reg);
787 if (atmci_is_mci2())
788 mci_writel(host, CFG, host->cfg_reg);
789 host->need_reset = false;
790 }
791 mci_writel(host, SDCR, slot->sdc_reg);
792
793 iflags = mci_readl(host, IMR);
794 if (iflags)
795 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
796 iflags);
797
798 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
799 /* Send init sequence (74 clock cycles) */
800 mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT);
801 while (!(mci_readl(host, SR) & MCI_CMDRDY))
802 cpu_relax();
803 }
804 iflags = 0;
805 data = mrq->data;
806 if (data) {
807 atmci_set_timeout(host, slot, data);
808
809 /* Must set block count/size before sending command */
810 mci_writel(host, BLKR, MCI_BCNT(data->blocks)
811 | MCI_BLKLEN(data->blksz));
812 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
813 MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
814
815 iflags |= atmci_prepare_data(host, data);
816 }
817
818 iflags |= MCI_CMDRDY;
819 cmd = mrq->cmd;
820 cmdflags = atmci_prepare_command(slot->mmc, cmd);
821 atmci_start_command(host, cmd, cmdflags);
822
823 if (data)
824 atmci_submit_data(host);
825
826 if (mrq->stop) {
827 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
828 host->stop_cmdr |= MCI_CMDR_STOP_XFER;
829 if (!(data->flags & MMC_DATA_WRITE))
830 host->stop_cmdr |= MCI_CMDR_TRDIR_READ;
831 if (data->flags & MMC_DATA_STREAM)
832 host->stop_cmdr |= MCI_CMDR_STREAM;
833 else
834 host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK;
835 }
836
837 /*
838 * We could have enabled interrupts earlier, but I suspect
839 * that would open up a nice can of interesting race
840 * conditions (e.g. command and data complete, but stop not
841 * prepared yet.)
842 */
843 mci_writel(host, IER, iflags);
844 }
845
846 static void atmci_queue_request(struct atmel_mci *host,
847 struct atmel_mci_slot *slot, struct mmc_request *mrq)
848 {
849 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
850 host->state);
851
852 spin_lock_bh(&host->lock);
853 slot->mrq = mrq;
854 if (host->state == STATE_IDLE) {
855 host->state = STATE_SENDING_CMD;
856 atmci_start_request(host, slot);
857 } else {
858 list_add_tail(&slot->queue_node, &host->queue);
859 }
860 spin_unlock_bh(&host->lock);
861 }
862
863 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
864 {
865 struct atmel_mci_slot *slot = mmc_priv(mmc);
866 struct atmel_mci *host = slot->host;
867 struct mmc_data *data;
868
869 WARN_ON(slot->mrq);
870
871 /*
872 * We may "know" the card is gone even though there's still an
873 * electrical connection. If so, we really need to communicate
874 * this to the MMC core since there won't be any more
875 * interrupts as the card is completely removed. Otherwise,
876 * the MMC core might believe the card is still there even
877 * though the card was just removed very slowly.
878 */
879 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
880 mrq->cmd->error = -ENOMEDIUM;
881 mmc_request_done(mmc, mrq);
882 return;
883 }
884
885 /* We don't support multiple blocks of weird lengths. */
886 data = mrq->data;
887 if (data && data->blocks > 1 && data->blksz & 3) {
888 mrq->cmd->error = -EINVAL;
889 mmc_request_done(mmc, mrq);
890 }
891
892 atmci_queue_request(host, slot, mrq);
893 }
894
895 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
896 {
897 struct atmel_mci_slot *slot = mmc_priv(mmc);
898 struct atmel_mci *host = slot->host;
899 unsigned int i;
900
901 slot->sdc_reg &= ~MCI_SDCBUS_MASK;
902 switch (ios->bus_width) {
903 case MMC_BUS_WIDTH_1:
904 slot->sdc_reg |= MCI_SDCBUS_1BIT;
905 break;
906 case MMC_BUS_WIDTH_4:
907 slot->sdc_reg |= MCI_SDCBUS_4BIT;
908 break;
909 }
910
911 if (ios->clock) {
912 unsigned int clock_min = ~0U;
913 u32 clkdiv;
914
915 spin_lock_bh(&host->lock);
916 if (!host->mode_reg) {
917 clk_enable(host->mck);
918 mci_writel(host, CR, MCI_CR_SWRST);
919 mci_writel(host, CR, MCI_CR_MCIEN);
920 if (atmci_is_mci2())
921 mci_writel(host, CFG, host->cfg_reg);
922 }
923
924 /*
925 * Use mirror of ios->clock to prevent race with mmc
926 * core ios update when finding the minimum.
927 */
928 slot->clock = ios->clock;
929 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
930 if (host->slot[i] && host->slot[i]->clock
931 && host->slot[i]->clock < clock_min)
932 clock_min = host->slot[i]->clock;
933 }
934
935 /* Calculate clock divider */
936 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
937 if (clkdiv > 255) {
938 dev_warn(&mmc->class_dev,
939 "clock %u too slow; using %lu\n",
940 clock_min, host->bus_hz / (2 * 256));
941 clkdiv = 255;
942 }
943
944 host->mode_reg = MCI_MR_CLKDIV(clkdiv);
945
946 /*
947 * WRPROOF and RDPROOF prevent overruns/underruns by
948 * stopping the clock when the FIFO is full/empty.
949 * This state is not expected to last for long.
950 */
951 if (mci_has_rwproof())
952 host->mode_reg |= (MCI_MR_WRPROOF | MCI_MR_RDPROOF);
953
954 if (list_empty(&host->queue))
955 mci_writel(host, MR, host->mode_reg);
956 else
957 host->need_clock_update = true;
958
959 spin_unlock_bh(&host->lock);
960 } else {
961 bool any_slot_active = false;
962
963 spin_lock_bh(&host->lock);
964 slot->clock = 0;
965 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
966 if (host->slot[i] && host->slot[i]->clock) {
967 any_slot_active = true;
968 break;
969 }
970 }
971 if (!any_slot_active) {
972 mci_writel(host, CR, MCI_CR_MCIDIS);
973 if (host->mode_reg) {
974 mci_readl(host, MR);
975 clk_disable(host->mck);
976 }
977 host->mode_reg = 0;
978 }
979 spin_unlock_bh(&host->lock);
980 }
981
982 switch (ios->power_mode) {
983 case MMC_POWER_UP:
984 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
985 break;
986 default:
987 /*
988 * TODO: None of the currently available AVR32-based
989 * boards allow MMC power to be turned off. Implement
990 * power control when this can be tested properly.
991 *
992 * We also need to hook this into the clock management
993 * somehow so that newly inserted cards aren't
994 * subjected to a fast clock before we have a chance
995 * to figure out what the maximum rate is. Currently,
996 * there's no way to avoid this, and there never will
997 * be for boards that don't support power control.
998 */
999 break;
1000 }
1001 }
1002
1003 static int atmci_get_ro(struct mmc_host *mmc)
1004 {
1005 int read_only = -ENOSYS;
1006 struct atmel_mci_slot *slot = mmc_priv(mmc);
1007
1008 if (gpio_is_valid(slot->wp_pin)) {
1009 read_only = gpio_get_value(slot->wp_pin);
1010 dev_dbg(&mmc->class_dev, "card is %s\n",
1011 read_only ? "read-only" : "read-write");
1012 }
1013
1014 return read_only;
1015 }
1016
1017 static int atmci_get_cd(struct mmc_host *mmc)
1018 {
1019 int present = -ENOSYS;
1020 struct atmel_mci_slot *slot = mmc_priv(mmc);
1021
1022 if (gpio_is_valid(slot->detect_pin)) {
1023 present = !(gpio_get_value(slot->detect_pin) ^
1024 slot->detect_is_active_high);
1025 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1026 present ? "" : "not ");
1027 }
1028
1029 return present;
1030 }
1031
1032 static const struct mmc_host_ops atmci_ops = {
1033 .request = atmci_request,
1034 .set_ios = atmci_set_ios,
1035 .get_ro = atmci_get_ro,
1036 .get_cd = atmci_get_cd,
1037 };
1038
1039 /* Called with host->lock held */
1040 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1041 __releases(&host->lock)
1042 __acquires(&host->lock)
1043 {
1044 struct atmel_mci_slot *slot = NULL;
1045 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1046
1047 WARN_ON(host->cmd || host->data);
1048
1049 /*
1050 * Update the MMC clock rate if necessary. This may be
1051 * necessary if set_ios() is called when a different slot is
1052 * busy transfering data.
1053 */
1054 if (host->need_clock_update)
1055 mci_writel(host, MR, host->mode_reg);
1056
1057 host->cur_slot->mrq = NULL;
1058 host->mrq = NULL;
1059 if (!list_empty(&host->queue)) {
1060 slot = list_entry(host->queue.next,
1061 struct atmel_mci_slot, queue_node);
1062 list_del(&slot->queue_node);
1063 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1064 mmc_hostname(slot->mmc));
1065 host->state = STATE_SENDING_CMD;
1066 atmci_start_request(host, slot);
1067 } else {
1068 dev_vdbg(&host->pdev->dev, "list empty\n");
1069 host->state = STATE_IDLE;
1070 }
1071
1072 spin_unlock(&host->lock);
1073 mmc_request_done(prev_mmc, mrq);
1074 spin_lock(&host->lock);
1075 }
1076
1077 static void atmci_command_complete(struct atmel_mci *host,
1078 struct mmc_command *cmd)
1079 {
1080 u32 status = host->cmd_status;
1081
1082 /* Read the response from the card (up to 16 bytes) */
1083 cmd->resp[0] = mci_readl(host, RSPR);
1084 cmd->resp[1] = mci_readl(host, RSPR);
1085 cmd->resp[2] = mci_readl(host, RSPR);
1086 cmd->resp[3] = mci_readl(host, RSPR);
1087
1088 if (status & MCI_RTOE)
1089 cmd->error = -ETIMEDOUT;
1090 else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE))
1091 cmd->error = -EILSEQ;
1092 else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE))
1093 cmd->error = -EIO;
1094 else
1095 cmd->error = 0;
1096
1097 if (cmd->error) {
1098 dev_dbg(&host->pdev->dev,
1099 "command error: status=0x%08x\n", status);
1100
1101 if (cmd->data) {
1102 host->data = NULL;
1103 atmci_stop_dma(host);
1104 mci_writel(host, IDR, MCI_NOTBUSY
1105 | MCI_TXRDY | MCI_RXRDY
1106 | ATMCI_DATA_ERROR_FLAGS);
1107 }
1108 }
1109 }
1110
1111 static void atmci_detect_change(unsigned long data)
1112 {
1113 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1114 bool present;
1115 bool present_old;
1116
1117 /*
1118 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1119 * freeing the interrupt. We must not re-enable the interrupt
1120 * if it has been freed, and if we're shutting down, it
1121 * doesn't really matter whether the card is present or not.
1122 */
1123 smp_rmb();
1124 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1125 return;
1126
1127 enable_irq(gpio_to_irq(slot->detect_pin));
1128 present = !(gpio_get_value(slot->detect_pin) ^
1129 slot->detect_is_active_high);
1130 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1131
1132 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1133 present, present_old);
1134
1135 if (present != present_old) {
1136 struct atmel_mci *host = slot->host;
1137 struct mmc_request *mrq;
1138
1139 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1140 present ? "inserted" : "removed");
1141
1142 spin_lock(&host->lock);
1143
1144 if (!present)
1145 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1146 else
1147 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1148
1149 /* Clean up queue if present */
1150 mrq = slot->mrq;
1151 if (mrq) {
1152 if (mrq == host->mrq) {
1153 /*
1154 * Reset controller to terminate any ongoing
1155 * commands or data transfers.
1156 */
1157 mci_writel(host, CR, MCI_CR_SWRST);
1158 mci_writel(host, CR, MCI_CR_MCIEN);
1159 mci_writel(host, MR, host->mode_reg);
1160 if (atmci_is_mci2())
1161 mci_writel(host, CFG, host->cfg_reg);
1162
1163 host->data = NULL;
1164 host->cmd = NULL;
1165
1166 switch (host->state) {
1167 case STATE_IDLE:
1168 break;
1169 case STATE_SENDING_CMD:
1170 mrq->cmd->error = -ENOMEDIUM;
1171 if (!mrq->data)
1172 break;
1173 /* fall through */
1174 case STATE_SENDING_DATA:
1175 mrq->data->error = -ENOMEDIUM;
1176 atmci_stop_dma(host);
1177 break;
1178 case STATE_DATA_BUSY:
1179 case STATE_DATA_ERROR:
1180 if (mrq->data->error == -EINPROGRESS)
1181 mrq->data->error = -ENOMEDIUM;
1182 if (!mrq->stop)
1183 break;
1184 /* fall through */
1185 case STATE_SENDING_STOP:
1186 mrq->stop->error = -ENOMEDIUM;
1187 break;
1188 }
1189
1190 atmci_request_end(host, mrq);
1191 } else {
1192 list_del(&slot->queue_node);
1193 mrq->cmd->error = -ENOMEDIUM;
1194 if (mrq->data)
1195 mrq->data->error = -ENOMEDIUM;
1196 if (mrq->stop)
1197 mrq->stop->error = -ENOMEDIUM;
1198
1199 spin_unlock(&host->lock);
1200 mmc_request_done(slot->mmc, mrq);
1201 spin_lock(&host->lock);
1202 }
1203 }
1204 spin_unlock(&host->lock);
1205
1206 mmc_detect_change(slot->mmc, 0);
1207 }
1208 }
1209
1210 static void atmci_tasklet_func(unsigned long priv)
1211 {
1212 struct atmel_mci *host = (struct atmel_mci *)priv;
1213 struct mmc_request *mrq = host->mrq;
1214 struct mmc_data *data = host->data;
1215 struct mmc_command *cmd = host->cmd;
1216 enum atmel_mci_state state = host->state;
1217 enum atmel_mci_state prev_state;
1218 u32 status;
1219
1220 spin_lock(&host->lock);
1221
1222 state = host->state;
1223
1224 dev_vdbg(&host->pdev->dev,
1225 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1226 state, host->pending_events, host->completed_events,
1227 mci_readl(host, IMR));
1228
1229 do {
1230 prev_state = state;
1231
1232 switch (state) {
1233 case STATE_IDLE:
1234 break;
1235
1236 case STATE_SENDING_CMD:
1237 if (!atmci_test_and_clear_pending(host,
1238 EVENT_CMD_COMPLETE))
1239 break;
1240
1241 host->cmd = NULL;
1242 atmci_set_completed(host, EVENT_CMD_COMPLETE);
1243 atmci_command_complete(host, mrq->cmd);
1244 if (!mrq->data || cmd->error) {
1245 atmci_request_end(host, host->mrq);
1246 goto unlock;
1247 }
1248
1249 prev_state = state = STATE_SENDING_DATA;
1250 /* fall through */
1251
1252 case STATE_SENDING_DATA:
1253 if (atmci_test_and_clear_pending(host,
1254 EVENT_DATA_ERROR)) {
1255 atmci_stop_dma(host);
1256 if (data->stop)
1257 send_stop_cmd(host, data);
1258 state = STATE_DATA_ERROR;
1259 break;
1260 }
1261
1262 if (!atmci_test_and_clear_pending(host,
1263 EVENT_XFER_COMPLETE))
1264 break;
1265
1266 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1267 prev_state = state = STATE_DATA_BUSY;
1268 /* fall through */
1269
1270 case STATE_DATA_BUSY:
1271 if (!atmci_test_and_clear_pending(host,
1272 EVENT_DATA_COMPLETE))
1273 break;
1274
1275 host->data = NULL;
1276 atmci_set_completed(host, EVENT_DATA_COMPLETE);
1277 status = host->data_status;
1278 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
1279 if (status & MCI_DTOE) {
1280 dev_dbg(&host->pdev->dev,
1281 "data timeout error\n");
1282 data->error = -ETIMEDOUT;
1283 } else if (status & MCI_DCRCE) {
1284 dev_dbg(&host->pdev->dev,
1285 "data CRC error\n");
1286 data->error = -EILSEQ;
1287 } else {
1288 dev_dbg(&host->pdev->dev,
1289 "data FIFO error (status=%08x)\n",
1290 status);
1291 data->error = -EIO;
1292 }
1293 } else {
1294 data->bytes_xfered = data->blocks * data->blksz;
1295 data->error = 0;
1296 }
1297
1298 if (!data->stop) {
1299 atmci_request_end(host, host->mrq);
1300 goto unlock;
1301 }
1302
1303 prev_state = state = STATE_SENDING_STOP;
1304 if (!data->error)
1305 send_stop_cmd(host, data);
1306 /* fall through */
1307
1308 case STATE_SENDING_STOP:
1309 if (!atmci_test_and_clear_pending(host,
1310 EVENT_CMD_COMPLETE))
1311 break;
1312
1313 host->cmd = NULL;
1314 atmci_command_complete(host, mrq->stop);
1315 atmci_request_end(host, host->mrq);
1316 goto unlock;
1317
1318 case STATE_DATA_ERROR:
1319 if (!atmci_test_and_clear_pending(host,
1320 EVENT_XFER_COMPLETE))
1321 break;
1322
1323 state = STATE_DATA_BUSY;
1324 break;
1325 }
1326 } while (state != prev_state);
1327
1328 host->state = state;
1329
1330 unlock:
1331 spin_unlock(&host->lock);
1332 }
1333
1334 static void atmci_read_data_pio(struct atmel_mci *host)
1335 {
1336 struct scatterlist *sg = host->sg;
1337 void *buf = sg_virt(sg);
1338 unsigned int offset = host->pio_offset;
1339 struct mmc_data *data = host->data;
1340 u32 value;
1341 u32 status;
1342 unsigned int nbytes = 0;
1343
1344 do {
1345 value = mci_readl(host, RDR);
1346 if (likely(offset + 4 <= sg->length)) {
1347 put_unaligned(value, (u32 *)(buf + offset));
1348
1349 offset += 4;
1350 nbytes += 4;
1351
1352 if (offset == sg->length) {
1353 flush_dcache_page(sg_page(sg));
1354 host->sg = sg = sg_next(sg);
1355 if (!sg)
1356 goto done;
1357
1358 offset = 0;
1359 buf = sg_virt(sg);
1360 }
1361 } else {
1362 unsigned int remaining = sg->length - offset;
1363 memcpy(buf + offset, &value, remaining);
1364 nbytes += remaining;
1365
1366 flush_dcache_page(sg_page(sg));
1367 host->sg = sg = sg_next(sg);
1368 if (!sg)
1369 goto done;
1370
1371 offset = 4 - remaining;
1372 buf = sg_virt(sg);
1373 memcpy(buf, (u8 *)&value + remaining, offset);
1374 nbytes += offset;
1375 }
1376
1377 status = mci_readl(host, SR);
1378 if (status & ATMCI_DATA_ERROR_FLAGS) {
1379 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY
1380 | ATMCI_DATA_ERROR_FLAGS));
1381 host->data_status = status;
1382 data->bytes_xfered += nbytes;
1383 smp_wmb();
1384 atmci_set_pending(host, EVENT_DATA_ERROR);
1385 tasklet_schedule(&host->tasklet);
1386 return;
1387 }
1388 } while (status & MCI_RXRDY);
1389
1390 host->pio_offset = offset;
1391 data->bytes_xfered += nbytes;
1392
1393 return;
1394
1395 done:
1396 mci_writel(host, IDR, MCI_RXRDY);
1397 mci_writel(host, IER, MCI_NOTBUSY);
1398 data->bytes_xfered += nbytes;
1399 smp_wmb();
1400 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1401 }
1402
1403 static void atmci_write_data_pio(struct atmel_mci *host)
1404 {
1405 struct scatterlist *sg = host->sg;
1406 void *buf = sg_virt(sg);
1407 unsigned int offset = host->pio_offset;
1408 struct mmc_data *data = host->data;
1409 u32 value;
1410 u32 status;
1411 unsigned int nbytes = 0;
1412
1413 do {
1414 if (likely(offset + 4 <= sg->length)) {
1415 value = get_unaligned((u32 *)(buf + offset));
1416 mci_writel(host, TDR, value);
1417
1418 offset += 4;
1419 nbytes += 4;
1420 if (offset == sg->length) {
1421 host->sg = sg = sg_next(sg);
1422 if (!sg)
1423 goto done;
1424
1425 offset = 0;
1426 buf = sg_virt(sg);
1427 }
1428 } else {
1429 unsigned int remaining = sg->length - offset;
1430
1431 value = 0;
1432 memcpy(&value, buf + offset, remaining);
1433 nbytes += remaining;
1434
1435 host->sg = sg = sg_next(sg);
1436 if (!sg) {
1437 mci_writel(host, TDR, value);
1438 goto done;
1439 }
1440
1441 offset = 4 - remaining;
1442 buf = sg_virt(sg);
1443 memcpy((u8 *)&value + remaining, buf, offset);
1444 mci_writel(host, TDR, value);
1445 nbytes += offset;
1446 }
1447
1448 status = mci_readl(host, SR);
1449 if (status & ATMCI_DATA_ERROR_FLAGS) {
1450 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY
1451 | ATMCI_DATA_ERROR_FLAGS));
1452 host->data_status = status;
1453 data->bytes_xfered += nbytes;
1454 smp_wmb();
1455 atmci_set_pending(host, EVENT_DATA_ERROR);
1456 tasklet_schedule(&host->tasklet);
1457 return;
1458 }
1459 } while (status & MCI_TXRDY);
1460
1461 host->pio_offset = offset;
1462 data->bytes_xfered += nbytes;
1463
1464 return;
1465
1466 done:
1467 mci_writel(host, IDR, MCI_TXRDY);
1468 mci_writel(host, IER, MCI_NOTBUSY);
1469 data->bytes_xfered += nbytes;
1470 smp_wmb();
1471 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1472 }
1473
1474 static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
1475 {
1476 mci_writel(host, IDR, MCI_CMDRDY);
1477
1478 host->cmd_status = status;
1479 smp_wmb();
1480 atmci_set_pending(host, EVENT_CMD_COMPLETE);
1481 tasklet_schedule(&host->tasklet);
1482 }
1483
1484 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1485 {
1486 struct atmel_mci *host = dev_id;
1487 u32 status, mask, pending;
1488 unsigned int pass_count = 0;
1489
1490 do {
1491 status = mci_readl(host, SR);
1492 mask = mci_readl(host, IMR);
1493 pending = status & mask;
1494 if (!pending)
1495 break;
1496
1497 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1498 mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS
1499 | MCI_RXRDY | MCI_TXRDY);
1500 pending &= mci_readl(host, IMR);
1501
1502 host->data_status = status;
1503 smp_wmb();
1504 atmci_set_pending(host, EVENT_DATA_ERROR);
1505 tasklet_schedule(&host->tasklet);
1506 }
1507 if (pending & MCI_NOTBUSY) {
1508 mci_writel(host, IDR,
1509 ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY);
1510 if (!host->data_status)
1511 host->data_status = status;
1512 smp_wmb();
1513 atmci_set_pending(host, EVENT_DATA_COMPLETE);
1514 tasklet_schedule(&host->tasklet);
1515 }
1516 if (pending & MCI_RXRDY)
1517 atmci_read_data_pio(host);
1518 if (pending & MCI_TXRDY)
1519 atmci_write_data_pio(host);
1520
1521 if (pending & MCI_CMDRDY)
1522 atmci_cmd_interrupt(host, status);
1523 } while (pass_count++ < 5);
1524
1525 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1526 }
1527
1528 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1529 {
1530 struct atmel_mci_slot *slot = dev_id;
1531
1532 /*
1533 * Disable interrupts until the pin has stabilized and check
1534 * the state then. Use mod_timer() since we may be in the
1535 * middle of the timer routine when this interrupt triggers.
1536 */
1537 disable_irq_nosync(irq);
1538 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
1539
1540 return IRQ_HANDLED;
1541 }
1542
1543 static int __init atmci_init_slot(struct atmel_mci *host,
1544 struct mci_slot_pdata *slot_data, unsigned int id,
1545 u32 sdc_reg)
1546 {
1547 struct mmc_host *mmc;
1548 struct atmel_mci_slot *slot;
1549
1550 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1551 if (!mmc)
1552 return -ENOMEM;
1553
1554 slot = mmc_priv(mmc);
1555 slot->mmc = mmc;
1556 slot->host = host;
1557 slot->detect_pin = slot_data->detect_pin;
1558 slot->wp_pin = slot_data->wp_pin;
1559 slot->detect_is_active_high = slot_data->detect_is_active_high;
1560 slot->sdc_reg = sdc_reg;
1561
1562 mmc->ops = &atmci_ops;
1563 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1564 mmc->f_max = host->bus_hz / 2;
1565 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1566 if (slot_data->bus_width >= 4)
1567 mmc->caps |= MMC_CAP_4_BIT_DATA;
1568
1569 mmc->max_hw_segs = 64;
1570 mmc->max_phys_segs = 64;
1571 mmc->max_req_size = 32768 * 512;
1572 mmc->max_blk_size = 32768;
1573 mmc->max_blk_count = 512;
1574
1575 /* Assume card is present initially */
1576 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1577 if (gpio_is_valid(slot->detect_pin)) {
1578 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1579 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1580 slot->detect_pin = -EBUSY;
1581 } else if (gpio_get_value(slot->detect_pin) ^
1582 slot->detect_is_active_high) {
1583 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1584 }
1585 }
1586
1587 if (!gpio_is_valid(slot->detect_pin))
1588 mmc->caps |= MMC_CAP_NEEDS_POLL;
1589
1590 if (gpio_is_valid(slot->wp_pin)) {
1591 if (gpio_request(slot->wp_pin, "mmc_wp")) {
1592 dev_dbg(&mmc->class_dev, "no WP pin available\n");
1593 slot->wp_pin = -EBUSY;
1594 }
1595 }
1596
1597 host->slot[id] = slot;
1598 mmc_add_host(mmc);
1599
1600 if (gpio_is_valid(slot->detect_pin)) {
1601 int ret;
1602
1603 setup_timer(&slot->detect_timer, atmci_detect_change,
1604 (unsigned long)slot);
1605
1606 ret = request_irq(gpio_to_irq(slot->detect_pin),
1607 atmci_detect_interrupt,
1608 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1609 "mmc-detect", slot);
1610 if (ret) {
1611 dev_dbg(&mmc->class_dev,
1612 "could not request IRQ %d for detect pin\n",
1613 gpio_to_irq(slot->detect_pin));
1614 gpio_free(slot->detect_pin);
1615 slot->detect_pin = -EBUSY;
1616 }
1617 }
1618
1619 atmci_init_debugfs(slot);
1620
1621 return 0;
1622 }
1623
1624 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1625 unsigned int id)
1626 {
1627 /* Debugfs stuff is cleaned up by mmc core */
1628
1629 set_bit(ATMCI_SHUTDOWN, &slot->flags);
1630 smp_wmb();
1631
1632 mmc_remove_host(slot->mmc);
1633
1634 if (gpio_is_valid(slot->detect_pin)) {
1635 int pin = slot->detect_pin;
1636
1637 free_irq(gpio_to_irq(pin), slot);
1638 del_timer_sync(&slot->detect_timer);
1639 gpio_free(pin);
1640 }
1641 if (gpio_is_valid(slot->wp_pin))
1642 gpio_free(slot->wp_pin);
1643
1644 slot->host->slot[id] = NULL;
1645 mmc_free_host(slot->mmc);
1646 }
1647
1648 #ifdef CONFIG_MMC_ATMELMCI_DMA
1649 static bool filter(struct dma_chan *chan, void *slave)
1650 {
1651 struct mci_dma_data *sl = slave;
1652
1653 if (sl && find_slave_dev(sl) == chan->device->dev) {
1654 chan->private = slave_data_ptr(sl);
1655 return true;
1656 } else {
1657 return false;
1658 }
1659 }
1660
1661 static void atmci_configure_dma(struct atmel_mci *host)
1662 {
1663 struct mci_platform_data *pdata;
1664
1665 if (host == NULL)
1666 return;
1667
1668 pdata = host->pdev->dev.platform_data;
1669
1670 if (pdata && find_slave_dev(pdata->dma_slave)) {
1671 dma_cap_mask_t mask;
1672
1673 setup_dma_addr(pdata->dma_slave,
1674 host->mapbase + MCI_TDR,
1675 host->mapbase + MCI_RDR);
1676
1677 /* Try to grab a DMA channel */
1678 dma_cap_zero(mask);
1679 dma_cap_set(DMA_SLAVE, mask);
1680 host->dma.chan =
1681 dma_request_channel(mask, filter, pdata->dma_slave);
1682 }
1683 if (!host->dma.chan)
1684 dev_notice(&host->pdev->dev, "DMA not available, using PIO\n");
1685 else
1686 dev_info(&host->pdev->dev,
1687 "Using %s for DMA transfers\n",
1688 dma_chan_name(host->dma.chan));
1689 }
1690 #else
1691 static void atmci_configure_dma(struct atmel_mci *host) {}
1692 #endif
1693
1694 static int __init atmci_probe(struct platform_device *pdev)
1695 {
1696 struct mci_platform_data *pdata;
1697 struct atmel_mci *host;
1698 struct resource *regs;
1699 unsigned int nr_slots;
1700 int irq;
1701 int ret;
1702
1703 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1704 if (!regs)
1705 return -ENXIO;
1706 pdata = pdev->dev.platform_data;
1707 if (!pdata)
1708 return -ENXIO;
1709 irq = platform_get_irq(pdev, 0);
1710 if (irq < 0)
1711 return irq;
1712
1713 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
1714 if (!host)
1715 return -ENOMEM;
1716
1717 host->pdev = pdev;
1718 spin_lock_init(&host->lock);
1719 INIT_LIST_HEAD(&host->queue);
1720
1721 host->mck = clk_get(&pdev->dev, "mci_clk");
1722 if (IS_ERR(host->mck)) {
1723 ret = PTR_ERR(host->mck);
1724 goto err_clk_get;
1725 }
1726
1727 ret = -ENOMEM;
1728 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1729 if (!host->regs)
1730 goto err_ioremap;
1731
1732 clk_enable(host->mck);
1733 mci_writel(host, CR, MCI_CR_SWRST);
1734 host->bus_hz = clk_get_rate(host->mck);
1735 clk_disable(host->mck);
1736
1737 host->mapbase = regs->start;
1738
1739 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
1740
1741 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
1742 if (ret)
1743 goto err_request_irq;
1744
1745 atmci_configure_dma(host);
1746
1747 platform_set_drvdata(pdev, host);
1748
1749 /* We need at least one slot to succeed */
1750 nr_slots = 0;
1751 ret = -ENODEV;
1752 if (pdata->slot[0].bus_width) {
1753 ret = atmci_init_slot(host, &pdata->slot[0],
1754 MCI_SDCSEL_SLOT_A, 0);
1755 if (!ret)
1756 nr_slots++;
1757 }
1758 if (pdata->slot[1].bus_width) {
1759 ret = atmci_init_slot(host, &pdata->slot[1],
1760 MCI_SDCSEL_SLOT_B, 1);
1761 if (!ret)
1762 nr_slots++;
1763 }
1764
1765 if (!nr_slots) {
1766 dev_err(&pdev->dev, "init failed: no slot defined\n");
1767 goto err_init_slot;
1768 }
1769
1770 dev_info(&pdev->dev,
1771 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
1772 host->mapbase, irq, nr_slots);
1773
1774 return 0;
1775
1776 err_init_slot:
1777 #ifdef CONFIG_MMC_ATMELMCI_DMA
1778 if (host->dma.chan)
1779 dma_release_channel(host->dma.chan);
1780 #endif
1781 free_irq(irq, host);
1782 err_request_irq:
1783 iounmap(host->regs);
1784 err_ioremap:
1785 clk_put(host->mck);
1786 err_clk_get:
1787 kfree(host);
1788 return ret;
1789 }
1790
1791 static int __exit atmci_remove(struct platform_device *pdev)
1792 {
1793 struct atmel_mci *host = platform_get_drvdata(pdev);
1794 unsigned int i;
1795
1796 platform_set_drvdata(pdev, NULL);
1797
1798 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
1799 if (host->slot[i])
1800 atmci_cleanup_slot(host->slot[i], i);
1801 }
1802
1803 clk_enable(host->mck);
1804 mci_writel(host, IDR, ~0UL);
1805 mci_writel(host, CR, MCI_CR_MCIDIS);
1806 mci_readl(host, SR);
1807 clk_disable(host->mck);
1808
1809 #ifdef CONFIG_MMC_ATMELMCI_DMA
1810 if (host->dma.chan)
1811 dma_release_channel(host->dma.chan);
1812 #endif
1813
1814 free_irq(platform_get_irq(pdev, 0), host);
1815 iounmap(host->regs);
1816
1817 clk_put(host->mck);
1818 kfree(host);
1819
1820 return 0;
1821 }
1822
1823 static struct platform_driver atmci_driver = {
1824 .remove = __exit_p(atmci_remove),
1825 .driver = {
1826 .name = "atmel_mci",
1827 },
1828 };
1829
1830 static int __init atmci_init(void)
1831 {
1832 return platform_driver_probe(&atmci_driver, atmci_probe);
1833 }
1834
1835 static void __exit atmci_exit(void)
1836 {
1837 platform_driver_unregister(&atmci_driver);
1838 }
1839
1840 late_initcall(atmci_init); /* try to load after dma driver when built-in */
1841 module_exit(atmci_exit);
1842
1843 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
1844 MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
1845 MODULE_LICENSE("GPL v2");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree